ASF: minor, update copyright
upstream ASFv4 updated the copyright year.
somehow they don't know you should use the range instead of the
last year :/
this change is just so I can't continue diffing ASF files without
false positive.
Change-Id: Ic90e692815b30921bc8750c240ba0a5d3f4ccc70
diff --git a/sysmoOCTSIM/include/component/ac.h b/sysmoOCTSIM/include/component/ac.h
index 28714de..e8a9fc4 100644
--- a/sysmoOCTSIM/include/component/ac.h
+++ b/sysmoOCTSIM/include/component/ac.h
@@ -1,598 +1,598 @@
-/**
- * \file
- *
- * \brief Component description for AC
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_AC_COMPONENT_
-#define _SAME54_AC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR AC */
-/* ========================================================================== */
-/** \addtogroup SAME54_AC Analog Comparators */
-/*@{*/
-
-#define AC_U2501
-#define REV_AC 0x100
-
-/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */
-#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */
-
-#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */
-#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos)
-#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */
-#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos)
-#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */
-
-/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
- uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} AC_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */
-#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */
-
-#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
-#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos)
-#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
-#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos)
-#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */
-#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos)
-#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
-#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */
-
-/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
- uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */
- uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */
- uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} AC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */
-#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */
-
-#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
-#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos)
-#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
-#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos)
-#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
-#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos)
-#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
-#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
-#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos)
-#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */
-#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos)
-#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
-#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */
-#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos)
-#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */
-#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos)
-#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */
-#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos)
-#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
-#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */
-#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos)
-#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */
-#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos)
-#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */
-#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos)
-#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos))
-#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */
-
-/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
- uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} AC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
-#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
-#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos)
-#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
-#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos)
-#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
-#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos)
-#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
-#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
-#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos)
-#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
-#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos)
-#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
-#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */
-
-/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
- uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} AC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
-#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
-
-#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
-#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos)
-#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
-#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos)
-#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
-#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos)
-#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
-#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
-#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos)
-#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */
-#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos)
-#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
-#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */
-
-/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
- __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
- __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
- __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
- __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
- __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
- __I uint8_t WIN:1; /*!< bit: 4 Window x */
- __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} AC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */
-#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos)
-#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */
-#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos)
-#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */
-#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos)
-#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
-#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */
-#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos)
-#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */
-#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos)
-#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
-#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */
-
-/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
- uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} AC_STATUSA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */
-#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */
-
-#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */
-#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos)
-#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */
-#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos)
-#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */
-#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos)
-#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
-#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */
-#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos)
-#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
-#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */
-#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */
-#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */
-#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos)
-#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
-#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos)
-#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */
-
-/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
- uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} AC_STATUSB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */
-#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */
-
-#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */
-#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos)
-#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */
-#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos)
-#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */
-#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos)
-#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
-#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */
-
-/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */
-#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */
-
-#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */
-#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos)
-#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */
-
-/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
- uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AC_WINCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */
-#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */
-
-#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
-#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos)
-#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
-#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
-#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */
-#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
-#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */
-#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
-#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */
-
-/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AC_SCALER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */
-#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */
-
-#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */
-#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos)
-#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
-#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */
-
-/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */
- uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */
- uint32_t :1; /*!< bit: 5 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */
- uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
- uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */
- uint32_t :1; /*!< bit: 18 Reserved */
- uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */
- uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
- uint32_t :1; /*!< bit: 27 Reserved */
- uint32_t OUT:2; /*!< bit: 28..29 Output */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} AC_COMPCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */
-#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
-
-#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */
-#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos)
-#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */
-#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos)
-#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */
-#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
-#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
-#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
-#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
-#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
-#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */
-#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos)
-#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
-#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
-#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */
-#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */
-#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */
-#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */
-#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */
-#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */
-#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
-#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */
-#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
-#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
-#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */
-#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */
-#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */
-#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */
-#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */
-#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
-#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos)
-#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */
-#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos)
-#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
-#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */
-#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos)
-#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */
-#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos)
-#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */
-#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos)
-#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos))
-#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */
-#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 100mV */
-#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 150mV */
-#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos)
-#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos)
-#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos)
-#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */
-#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos)
-#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
-#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */
-#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
-#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
-#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos)
-#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos)
-#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos)
-#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */
-#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos)
-#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
-#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
-#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
-#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
-#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos)
-#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos)
-#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos)
-#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */
-
-/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
- uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */
- uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */
- uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */
- uint32_t :27; /*!< bit: 5..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :3; /*!< bit: 0.. 2 Reserved */
- uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */
- uint32_t :27; /*!< bit: 5..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} AC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */
-#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */
-
-#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */
-#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos)
-#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */
-#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos)
-#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */
-#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos)
-#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */
-#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos)
-#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */
-#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos)
-#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */
-#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos)
-#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos))
-#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */
-
-/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t BIAS0:2; /*!< bit: 0.. 1 COMP0/1 Bias Scaling */
- uint16_t :14; /*!< bit: 2..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} AC_CALIB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_CALIB_OFFSET 0x24 /**< \brief (AC_CALIB offset) Calibration */
-#define AC_CALIB_RESETVALUE _U_(0x0101) /**< \brief (AC_CALIB reset_value) Calibration */
-
-#define AC_CALIB_BIAS0_Pos 0 /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */
-#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos)
-#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos))
-#define AC_CALIB_MASK _U_(0x0003) /**< \brief (AC_CALIB) MASK Register */
-
-/** \brief AC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
- __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
- __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
- __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
- __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
- __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
- __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */
- __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */
- __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */
- __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */
- RoReg8 Reserved1[0x1];
- __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */
- RoReg8 Reserved2[0x2];
- __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
- RoReg8 Reserved3[0x8];
- __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */
- __IO AC_CALIB_Type CALIB; /**< \brief Offset: 0x24 (R/W 16) Calibration */
-} Ac;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_AC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for AC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_AC_COMPONENT_
+#define _SAME54_AC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR AC */
+/* ========================================================================== */
+/** \addtogroup SAME54_AC Analog Comparators */
+/*@{*/
+
+#define AC_U2501
+#define REV_AC 0x100
+
+/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */
+#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */
+
+#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */
+#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos)
+#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */
+#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos)
+#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */
+
+/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
+ uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */
+#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */
+
+#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
+#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos)
+#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
+#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos)
+#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */
+#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos)
+#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
+#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */
+
+/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
+ uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */
+ uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */
+ uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} AC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */
+#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */
+
+#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
+#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos)
+#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
+#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos)
+#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
+#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos)
+#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
+#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
+#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos)
+#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */
+#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos)
+#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
+#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */
+#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos)
+#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */
+#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos)
+#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */
+#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos)
+#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
+#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */
+#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos)
+#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */
+#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos)
+#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */
+#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos)
+#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos))
+#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */
+
+/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
+#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
+#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos)
+#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
+#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos)
+#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
+#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos)
+#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
+#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
+#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos)
+#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
+#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos)
+#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
+#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */
+
+/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
+#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
+
+#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
+#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos)
+#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
+#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos)
+#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
+#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos)
+#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
+#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
+#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos)
+#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */
+#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos)
+#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
+#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */
+
+/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
+ __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
+ __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
+ __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
+ __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint8_t WIN:1; /*!< bit: 4 Window x */
+ __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */
+#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos)
+#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */
+#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos)
+#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */
+#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos)
+#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
+#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */
+#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos)
+#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */
+#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos)
+#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
+#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */
+
+/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */
+#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */
+
+#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */
+#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos)
+#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */
+#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos)
+#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */
+#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos)
+#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
+#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */
+#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
+#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */
+#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */
+#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */
+#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */
+
+/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
+ uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */
+#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */
+
+#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */
+#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos)
+#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */
+#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos)
+#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */
+#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos)
+#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
+#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */
+
+/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */
+#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */
+
+#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */
+#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos)
+#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */
+
+/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
+ uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */
+#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */
+
+#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
+#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos)
+#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
+#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
+#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */
+#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
+#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */
+#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
+#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */
+
+/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_SCALER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */
+#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */
+
+#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */
+#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos)
+#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
+#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */
+
+/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */
+ uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */
+ uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
+ uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */
+ uint32_t :1; /*!< bit: 18 Reserved */
+ uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */
+ uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t OUT:2; /*!< bit: 28..29 Output */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} AC_COMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */
+#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
+
+#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */
+#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos)
+#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */
+#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos)
+#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */
+#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
+#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
+#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
+#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
+#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
+#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */
+#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos)
+#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
+#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
+#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */
+#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */
+#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
+#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */
+#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
+#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
+#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */
+#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
+#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos)
+#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */
+#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
+#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */
+#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */
+#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos)
+#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */
+#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos))
+#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */
+#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 100mV */
+#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 150mV */
+#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */
+#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
+#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */
+#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
+#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
+#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */
+#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
+#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */
+
+/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
+ uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */
+ uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */
+ uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :3; /*!< bit: 0.. 2 Reserved */
+ uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} AC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */
+#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */
+#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos)
+#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */
+#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos)
+#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */
+#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos)
+#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */
+#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos)
+#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */
+#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos)
+#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */
+#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos)
+#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos))
+#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */
+
+/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BIAS0:2; /*!< bit: 0.. 1 COMP0/1 Bias Scaling */
+ uint16_t :14; /*!< bit: 2..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} AC_CALIB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CALIB_OFFSET 0x24 /**< \brief (AC_CALIB offset) Calibration */
+#define AC_CALIB_RESETVALUE _U_(0x0101) /**< \brief (AC_CALIB reset_value) Calibration */
+
+#define AC_CALIB_BIAS0_Pos 0 /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */
+#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos)
+#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos))
+#define AC_CALIB_MASK _U_(0x0003) /**< \brief (AC_CALIB) MASK Register */
+
+/** \brief AC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
+ __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
+ __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
+ __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
+ __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
+ __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */
+ __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */
+ __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */
+ __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */
+ RoReg8 Reserved1[0x1];
+ __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */
+ RoReg8 Reserved2[0x2];
+ __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
+ RoReg8 Reserved3[0x8];
+ __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */
+ __IO AC_CALIB_Type CALIB; /**< \brief Offset: 0x24 (R/W 16) Calibration */
+} Ac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_AC_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/adc.h b/sysmoOCTSIM/include/component/adc.h
index 9d3c651..b2fee11 100644
--- a/sysmoOCTSIM/include/component/adc.h
+++ b/sysmoOCTSIM/include/component/adc.h
@@ -1,871 +1,871 @@
-/**
- * \file
- *
- * \brief Component description for ADC
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_ADC_COMPONENT_
-#define _SAME54_ADC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR ADC */
-/* ========================================================================== */
-/** \addtogroup SAME54_ADC Analog Digital Converter */
-/*@{*/
-
-#define ADC_U2500
-#define REV_ADC 0x100
-
-/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t :1; /*!< bit: 2 Reserved */
- uint16_t DUALSEL:2; /*!< bit: 3.. 4 Dual Mode Trigger Selection */
- uint16_t SLAVEEN:1; /*!< bit: 5 Slave Enable */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
- uint16_t :4; /*!< bit: 11..14 Reserved */
- uint16_t R2R:1; /*!< bit: 15 Rail to Rail Operation Enable */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */
-#define ADC_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLA reset_value) Control A */
-
-#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */
-#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos)
-#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */
-#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos)
-#define ADC_CTRLA_DUALSEL_Pos 3 /**< \brief (ADC_CTRLA) Dual Mode Trigger Selection */
-#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos)
-#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos))
-#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */
-#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */
-#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos)
-#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos)
-#define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */
-#define ADC_CTRLA_SLAVEEN (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos)
-#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run in Standby */
-#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos)
-#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */
-#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos)
-#define ADC_CTRLA_PRESCALER_Pos 8 /**< \brief (ADC_CTRLA) Prescaler Configuration */
-#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos))
-#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */
-#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */
-#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */
-#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */
-#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */
-#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */
-#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */
-#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */
-#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_R2R_Pos 15 /**< \brief (ADC_CTRLA) Rail to Rail Operation Enable */
-#define ADC_CTRLA_R2R (_U_(0x1) << ADC_CTRLA_R2R_Pos)
-#define ADC_CTRLA_MASK _U_(0x87FB) /**< \brief (ADC_CTRLA) MASK Register */
-
-/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */
- uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */
- uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */
- uint8_t STARTINV:1; /*!< bit: 3 Start Conversion Event Invert Enable */
- uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
- uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_EVCTRL_OFFSET 0x02 /**< \brief (ADC_EVCTRL offset) Event Control */
-#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */
-
-#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */
-#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos)
-#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */
-#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos)
-#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */
-#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos)
-#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Start Conversion Event Invert Enable */
-#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos)
-#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */
-#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos)
-#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
-#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos)
-#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */
-
-/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_DBGCTRL_OFFSET 0x03 /**< \brief (ADC_DBGCTRL offset) Debug Control */
-#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
-
-#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */
-#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos)
-#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */
-
-/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
- uint16_t :2; /*!< bit: 5.. 6 Reserved */
- uint16_t DIFFMODE:1; /*!< bit: 7 Differential Mode */
- uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
- uint16_t :2; /*!< bit: 13..14 Reserved */
- uint16_t DSEQSTOP:1; /*!< bit: 15 Stop DMA Sequencing */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_INPUTCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_INPUTCTRL_OFFSET 0x04 /**< \brief (ADC_INPUTCTRL offset) Input Control */
-#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
-
-#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
-#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
-#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */
-#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
-#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */
-#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
-#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
-#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */
-#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */
-#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< \brief (ADC_INPUTCTRL) DAC Output */
-#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */
-#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_DIFFMODE_Pos 7 /**< \brief (ADC_INPUTCTRL) Differential Mode */
-#define ADC_INPUTCTRL_DIFFMODE (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos)
-#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
-#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
-#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
-#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
-#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
-#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
-#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
-#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
-#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
-#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
-#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */
-#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_DSEQSTOP_Pos 15 /**< \brief (ADC_INPUTCTRL) Stop DMA Sequencing */
-#define ADC_INPUTCTRL_DSEQSTOP (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos)
-#define ADC_INPUTCTRL_MASK _U_(0x9F9F) /**< \brief (ADC_INPUTCTRL) MASK Register */
-
-/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t LEFTADJ:1; /*!< bit: 0 Left-Adjusted Result */
- uint16_t FREERUN:1; /*!< bit: 1 Free Running Mode */
- uint16_t CORREN:1; /*!< bit: 2 Digital Correction Logic Enable */
- uint16_t RESSEL:2; /*!< bit: 3.. 4 Conversion Result Resolution */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */
- uint16_t WINSS:1; /*!< bit: 11 Window Single Sample */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_CTRLB_OFFSET 0x06 /**< \brief (ADC_CTRLB offset) Control B */
-#define ADC_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */
-
-#define ADC_CTRLB_LEFTADJ_Pos 0 /**< \brief (ADC_CTRLB) Left-Adjusted Result */
-#define ADC_CTRLB_LEFTADJ (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos)
-#define ADC_CTRLB_FREERUN_Pos 1 /**< \brief (ADC_CTRLB) Free Running Mode */
-#define ADC_CTRLB_FREERUN (_U_(0x1) << ADC_CTRLB_FREERUN_Pos)
-#define ADC_CTRLB_CORREN_Pos 2 /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */
-#define ADC_CTRLB_CORREN (_U_(0x1) << ADC_CTRLB_CORREN_Pos)
-#define ADC_CTRLB_RESSEL_Pos 3 /**< \brief (ADC_CTRLB) Conversion Result Resolution */
-#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
-#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLB) 12-bit result */
-#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */
-#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLB) 10-bit result */
-#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLB) 8-bit result */
-#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_WINMODE_Pos 8 /**< \brief (ADC_CTRLB) Window Monitor Mode */
-#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos)
-#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos))
-#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLB) No window mode (default) */
-#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLB) RESULT > WINLT */
-#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLB) RESULT < WINUT */
-#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */
-#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */
-#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos)
-#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos)
-#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos)
-#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos)
-#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos)
-#define ADC_CTRLB_WINSS_Pos 11 /**< \brief (ADC_CTRLB) Window Single Sample */
-#define ADC_CTRLB_WINSS (_U_(0x1) << ADC_CTRLB_WINSS_Pos)
-#define ADC_CTRLB_MASK _U_(0x0F1F) /**< \brief (ADC_CTRLB) MASK Register */
-
-/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_REFCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_REFCTRL_OFFSET 0x08 /**< \brief (ADC_REFCTRL offset) Reference Control */
-#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */
-
-#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */
-#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
-#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */
-#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */
-#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< \brief (ADC_REFCTRL) VDDANA */
-#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */
-#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< \brief (ADC_REFCTRL) External Reference */
-#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */
-#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
-#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos)
-#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */
-
-/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
- uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_AVGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_AVGCTRL_OFFSET 0x0A /**< \brief (ADC_AVGCTRL offset) Average Control */
-#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */
-
-#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
-#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
-#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */
-#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */
-#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */
-#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */
-#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */
-#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */
-#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */
-#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */
-#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */
-#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */
-#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */
-#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
-#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos)
-#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
-#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */
-
-/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
- uint8_t :1; /*!< bit: 6 Reserved */
- uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_SAMPCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_SAMPCTRL_OFFSET 0x0B /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */
-#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */
-
-#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
-#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos)
-#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
-#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */
-#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos)
-#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */
-
-/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_WINLT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_WINLT_OFFSET 0x0C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
-#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
-
-#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */
-#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos)
-#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
-#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */
-
-/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_WINUT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_WINUT_OFFSET 0x0E /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
-#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
-
-#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */
-#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos)
-#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
-#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */
-
-/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_GAINCORR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_GAINCORR_OFFSET 0x10 /**< \brief (ADC_GAINCORR offset) Gain Correction */
-#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
-
-#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */
-#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos)
-#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
-#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */
-
-/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_OFFSETCORR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_OFFSETCORR_OFFSET 0x12 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
-#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
-
-#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
-#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos)
-#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
-#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */
-
-/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
- uint8_t START:1; /*!< bit: 1 Start ADC Conversion */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_SWTRIG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_SWTRIG_OFFSET 0x14 /**< \brief (ADC_SWTRIG offset) Software Trigger */
-#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
-
-#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
-#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos)
-#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */
-#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos)
-#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */
-
-/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */
- uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */
- uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_INTENCLR_OFFSET 0x2C /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
-#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */
-#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos)
-#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */
-#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos)
-#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */
-#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos)
-#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */
-
-/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
- uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
- uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_INTENSET_OFFSET 0x2D /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
-#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
-
-#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
-#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos)
-#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
-#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos)
-#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
-#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos)
-#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */
-
-/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */
- __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */
- __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */
- __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_INTFLAG_OFFSET 0x2E /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */
-#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos)
-#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */
-#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos)
-#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */
-#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos)
-#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */
-
-/* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/ 8) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t ADCBUSY:1; /*!< bit: 0 ADC Busy Status */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t WCC:6; /*!< bit: 2.. 7 Window Comparator Counter */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_STATUS_OFFSET 0x2F /**< \brief (ADC_STATUS offset) Status */
-#define ADC_STATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_STATUS reset_value) Status */
-
-#define ADC_STATUS_ADCBUSY_Pos 0 /**< \brief (ADC_STATUS) ADC Busy Status */
-#define ADC_STATUS_ADCBUSY (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos)
-#define ADC_STATUS_WCC_Pos 2 /**< \brief (ADC_STATUS) Window Comparator Counter */
-#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos)
-#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos))
-#define ADC_STATUS_MASK _U_(0xFD) /**< \brief (ADC_STATUS) MASK Register */
-
-/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/ 32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */
- uint32_t INPUTCTRL:1; /*!< bit: 2 Input Control Synchronization Busy */
- uint32_t CTRLB:1; /*!< bit: 3 Control B Synchronization Busy */
- uint32_t REFCTRL:1; /*!< bit: 4 Reference Control Synchronization Busy */
- uint32_t AVGCTRL:1; /*!< bit: 5 Average Control Synchronization Busy */
- uint32_t SAMPCTRL:1; /*!< bit: 6 Sampling Time Control Synchronization Busy */
- uint32_t WINLT:1; /*!< bit: 7 Window Monitor Lower Threshold Synchronization Busy */
- uint32_t WINUT:1; /*!< bit: 8 Window Monitor Upper Threshold Synchronization Busy */
- uint32_t GAINCORR:1; /*!< bit: 9 Gain Correction Synchronization Busy */
- uint32_t OFFSETCORR:1; /*!< bit: 10 Offset Correction Synchronization Busy */
- uint32_t SWTRIG:1; /*!< bit: 11 Software Trigger Synchronization Busy */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ADC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_SYNCBUSY_OFFSET 0x30 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */
-#define ADC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */
-
-#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */
-#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos)
-#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */
-#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos)
-#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) Input Control Synchronization Busy */
-#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos)
-#define ADC_SYNCBUSY_CTRLB_Pos 3 /**< \brief (ADC_SYNCBUSY) Control B Synchronization Busy */
-#define ADC_SYNCBUSY_CTRLB (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos)
-#define ADC_SYNCBUSY_REFCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) Reference Control Synchronization Busy */
-#define ADC_SYNCBUSY_REFCTRL (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos)
-#define ADC_SYNCBUSY_AVGCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) Average Control Synchronization Busy */
-#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos)
-#define ADC_SYNCBUSY_SAMPCTRL_Pos 6 /**< \brief (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy */
-#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos)
-#define ADC_SYNCBUSY_WINLT_Pos 7 /**< \brief (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy */
-#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos)
-#define ADC_SYNCBUSY_WINUT_Pos 8 /**< \brief (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy */
-#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos)
-#define ADC_SYNCBUSY_GAINCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) Gain Correction Synchronization Busy */
-#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos)
-#define ADC_SYNCBUSY_OFFSETCORR_Pos 10 /**< \brief (ADC_SYNCBUSY) Offset Correction Synchronization Busy */
-#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos)
-#define ADC_SYNCBUSY_SWTRIG_Pos 11 /**< \brief (ADC_SYNCBUSY) Software Trigger Synchronization Busy */
-#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos)
-#define ADC_SYNCBUSY_MASK _U_(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */
-
-/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 DMA Sequential Data */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ADC_DSEQDATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_DSEQDATA_OFFSET 0x34 /**< \brief (ADC_DSEQDATA offset) DMA Sequencial Data */
-#define ADC_DSEQDATA_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */
-
-#define ADC_DSEQDATA_DATA_Pos 0 /**< \brief (ADC_DSEQDATA) DMA Sequential Data */
-#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos)
-#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos))
-#define ADC_DSEQDATA_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */
-
-/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */
- uint32_t CTRLB:1; /*!< bit: 1 Control B */
- uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */
- uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */
- uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */
- uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */
- uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */
- uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */
- uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */
- uint32_t :22; /*!< bit: 9..30 Reserved */
- uint32_t AUTOSTART:1; /*!< bit: 31 ADC Auto-Start Conversion */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ADC_DSEQCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_DSEQCTRL_OFFSET 0x38 /**< \brief (ADC_DSEQCTRL offset) DMA Sequential Control */
-#define ADC_DSEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */
-
-#define ADC_DSEQCTRL_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQCTRL) Input Control */
-#define ADC_DSEQCTRL_INPUTCTRL (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos)
-#define ADC_DSEQCTRL_CTRLB_Pos 1 /**< \brief (ADC_DSEQCTRL) Control B */
-#define ADC_DSEQCTRL_CTRLB (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos)
-#define ADC_DSEQCTRL_REFCTRL_Pos 2 /**< \brief (ADC_DSEQCTRL) Reference Control */
-#define ADC_DSEQCTRL_REFCTRL (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos)
-#define ADC_DSEQCTRL_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQCTRL) Average Control */
-#define ADC_DSEQCTRL_AVGCTRL (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos)
-#define ADC_DSEQCTRL_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQCTRL) Sampling Time Control */
-#define ADC_DSEQCTRL_SAMPCTRL (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos)
-#define ADC_DSEQCTRL_WINLT_Pos 5 /**< \brief (ADC_DSEQCTRL) Window Monitor Lower Threshold */
-#define ADC_DSEQCTRL_WINLT (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos)
-#define ADC_DSEQCTRL_WINUT_Pos 6 /**< \brief (ADC_DSEQCTRL) Window Monitor Upper Threshold */
-#define ADC_DSEQCTRL_WINUT (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos)
-#define ADC_DSEQCTRL_GAINCORR_Pos 7 /**< \brief (ADC_DSEQCTRL) Gain Correction */
-#define ADC_DSEQCTRL_GAINCORR (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos)
-#define ADC_DSEQCTRL_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQCTRL) Offset Correction */
-#define ADC_DSEQCTRL_OFFSETCORR (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos)
-#define ADC_DSEQCTRL_AUTOSTART_Pos 31 /**< \brief (ADC_DSEQCTRL) ADC Auto-Start Conversion */
-#define ADC_DSEQCTRL_AUTOSTART (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos)
-#define ADC_DSEQCTRL_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */
-
-/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/ 32) DMA Sequencial Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */
- uint32_t CTRLB:1; /*!< bit: 1 Control B */
- uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */
- uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */
- uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */
- uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */
- uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */
- uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */
- uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */
- uint32_t :22; /*!< bit: 9..30 Reserved */
- uint32_t BUSY:1; /*!< bit: 31 DMA Sequencing Busy */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ADC_DSEQSTAT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_DSEQSTAT_OFFSET 0x3C /**< \brief (ADC_DSEQSTAT offset) DMA Sequencial Status */
-#define ADC_DSEQSTAT_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */
-
-#define ADC_DSEQSTAT_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQSTAT) Input Control */
-#define ADC_DSEQSTAT_INPUTCTRL (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos)
-#define ADC_DSEQSTAT_CTRLB_Pos 1 /**< \brief (ADC_DSEQSTAT) Control B */
-#define ADC_DSEQSTAT_CTRLB (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos)
-#define ADC_DSEQSTAT_REFCTRL_Pos 2 /**< \brief (ADC_DSEQSTAT) Reference Control */
-#define ADC_DSEQSTAT_REFCTRL (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos)
-#define ADC_DSEQSTAT_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQSTAT) Average Control */
-#define ADC_DSEQSTAT_AVGCTRL (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos)
-#define ADC_DSEQSTAT_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQSTAT) Sampling Time Control */
-#define ADC_DSEQSTAT_SAMPCTRL (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos)
-#define ADC_DSEQSTAT_WINLT_Pos 5 /**< \brief (ADC_DSEQSTAT) Window Monitor Lower Threshold */
-#define ADC_DSEQSTAT_WINLT (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos)
-#define ADC_DSEQSTAT_WINUT_Pos 6 /**< \brief (ADC_DSEQSTAT) Window Monitor Upper Threshold */
-#define ADC_DSEQSTAT_WINUT (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos)
-#define ADC_DSEQSTAT_GAINCORR_Pos 7 /**< \brief (ADC_DSEQSTAT) Gain Correction */
-#define ADC_DSEQSTAT_GAINCORR (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos)
-#define ADC_DSEQSTAT_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQSTAT) Offset Correction */
-#define ADC_DSEQSTAT_OFFSETCORR (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos)
-#define ADC_DSEQSTAT_BUSY_Pos 31 /**< \brief (ADC_DSEQSTAT) DMA Sequencing Busy */
-#define ADC_DSEQSTAT_BUSY (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos)
-#define ADC_DSEQSTAT_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */
-
-/* -------- ADC_RESULT : (ADC Offset: 0x40) (R/ 16) Result Conversion Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_RESULT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_RESULT_OFFSET 0x40 /**< \brief (ADC_RESULT offset) Result Conversion Value */
-#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result Conversion Value */
-
-#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */
-#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos)
-#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
-#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */
-
-/* -------- ADC_RESS : (ADC Offset: 0x44) (R/ 16) Last Sample Result -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t RESS:16; /*!< bit: 0..15 Last ADC conversion result */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_RESS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_RESS_OFFSET 0x44 /**< \brief (ADC_RESS offset) Last Sample Result */
-#define ADC_RESS_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESS reset_value) Last Sample Result */
-
-#define ADC_RESS_RESS_Pos 0 /**< \brief (ADC_RESS) Last ADC conversion result */
-#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos)
-#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos))
-#define ADC_RESS_MASK _U_(0xFFFF) /**< \brief (ADC_RESS) MASK Register */
-
-/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */
- uint16_t :1; /*!< bit: 3 Reserved */
- uint16_t BIASR2R:3; /*!< bit: 4.. 6 Bias R2R Ampli scaling */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_CALIB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_CALIB_OFFSET 0x48 /**< \brief (ADC_CALIB offset) Calibration */
-#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */
-
-#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */
-#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos)
-#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos))
-#define ADC_CALIB_BIASR2R_Pos 4 /**< \brief (ADC_CALIB) Bias R2R Ampli scaling */
-#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos)
-#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos))
-#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */
-#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos)
-#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos))
-#define ADC_CALIB_MASK _U_(0x0777) /**< \brief (ADC_CALIB) MASK Register */
-
-/** \brief ADC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
- __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */
- __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x03 (R/W 8) Debug Control */
- __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x04 (R/W 16) Input Control */
- __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x06 (R/W 16) Control B */
- __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x08 (R/W 8) Reference Control */
- RoReg8 Reserved1[0x1];
- __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0A (R/W 8) Average Control */
- __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0B (R/W 8) Sample Time Control */
- __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */
- __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */
- __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x10 (R/W 16) Gain Correction */
- __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x12 (R/W 16) Offset Correction */
- __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x14 (R/W 8) Software Trigger */
- RoReg8 Reserved2[0x17];
- __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x2C (R/W 8) Interrupt Enable Clear */
- __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x2D (R/W 8) Interrupt Enable Set */
- __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */
- __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x2F (R/ 8) Status */
- __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x30 (R/ 32) Synchronization Busy */
- __O ADC_DSEQDATA_Type DSEQDATA; /**< \brief Offset: 0x34 ( /W 32) DMA Sequencial Data */
- __IO ADC_DSEQCTRL_Type DSEQCTRL; /**< \brief Offset: 0x38 (R/W 32) DMA Sequential Control */
- __I ADC_DSEQSTAT_Type DSEQSTAT; /**< \brief Offset: 0x3C (R/ 32) DMA Sequencial Status */
- __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x40 (R/ 16) Result Conversion Value */
- RoReg8 Reserved3[0x2];
- __I ADC_RESS_Type RESS; /**< \brief Offset: 0x44 (R/ 16) Last Sample Result */
- RoReg8 Reserved4[0x2];
- __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x48 (R/W 16) Calibration */
-} Adc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_ADC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for ADC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_ADC_COMPONENT_
+#define _SAME54_ADC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR ADC */
+/* ========================================================================== */
+/** \addtogroup SAME54_ADC Analog Digital Converter */
+/*@{*/
+
+#define ADC_U2500
+#define REV_ADC 0x100
+
+/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t :1; /*!< bit: 2 Reserved */
+ uint16_t DUALSEL:2; /*!< bit: 3.. 4 Dual Mode Trigger Selection */
+ uint16_t SLAVEEN:1; /*!< bit: 5 Slave Enable */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
+ uint16_t :4; /*!< bit: 11..14 Reserved */
+ uint16_t R2R:1; /*!< bit: 15 Rail to Rail Operation Enable */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */
+#define ADC_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLA reset_value) Control A */
+
+#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */
+#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos)
+#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */
+#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos)
+#define ADC_CTRLA_DUALSEL_Pos 3 /**< \brief (ADC_CTRLA) Dual Mode Trigger Selection */
+#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos)
+#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos))
+#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */
+#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */
+#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos)
+#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos)
+#define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */
+#define ADC_CTRLA_SLAVEEN (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos)
+#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run in Standby */
+#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos)
+#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */
+#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos)
+#define ADC_CTRLA_PRESCALER_Pos 8 /**< \brief (ADC_CTRLA) Prescaler Configuration */
+#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos))
+#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */
+#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */
+#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */
+#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */
+#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */
+#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */
+#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */
+#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */
+#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_R2R_Pos 15 /**< \brief (ADC_CTRLA) Rail to Rail Operation Enable */
+#define ADC_CTRLA_R2R (_U_(0x1) << ADC_CTRLA_R2R_Pos)
+#define ADC_CTRLA_MASK _U_(0x87FB) /**< \brief (ADC_CTRLA) MASK Register */
+
+/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */
+ uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */
+ uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */
+ uint8_t STARTINV:1; /*!< bit: 3 Start Conversion Event Invert Enable */
+ uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
+ uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_EVCTRL_OFFSET 0x02 /**< \brief (ADC_EVCTRL offset) Event Control */
+#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */
+
+#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */
+#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos)
+#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */
+#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos)
+#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */
+#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos)
+#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Start Conversion Event Invert Enable */
+#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos)
+#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */
+#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos)
+#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
+#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos)
+#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */
+
+/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DBGCTRL_OFFSET 0x03 /**< \brief (ADC_DBGCTRL offset) Debug Control */
+#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
+
+#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */
+#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos)
+#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */
+
+/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
+ uint16_t :2; /*!< bit: 5.. 6 Reserved */
+ uint16_t DIFFMODE:1; /*!< bit: 7 Differential Mode */
+ uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
+ uint16_t :2; /*!< bit: 13..14 Reserved */
+ uint16_t DSEQSTOP:1; /*!< bit: 15 Stop DMA Sequencing */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_INPUTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INPUTCTRL_OFFSET 0x04 /**< \brief (ADC_INPUTCTRL offset) Input Control */
+#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
+
+#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
+#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
+#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
+#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
+#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */
+#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */
+#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< \brief (ADC_INPUTCTRL) DAC Output */
+#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */
+#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_DIFFMODE_Pos 7 /**< \brief (ADC_INPUTCTRL) Differential Mode */
+#define ADC_INPUTCTRL_DIFFMODE (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos)
+#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
+#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
+#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */
+#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_DSEQSTOP_Pos 15 /**< \brief (ADC_INPUTCTRL) Stop DMA Sequencing */
+#define ADC_INPUTCTRL_DSEQSTOP (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos)
+#define ADC_INPUTCTRL_MASK _U_(0x9F9F) /**< \brief (ADC_INPUTCTRL) MASK Register */
+
+/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t LEFTADJ:1; /*!< bit: 0 Left-Adjusted Result */
+ uint16_t FREERUN:1; /*!< bit: 1 Free Running Mode */
+ uint16_t CORREN:1; /*!< bit: 2 Digital Correction Logic Enable */
+ uint16_t RESSEL:2; /*!< bit: 3.. 4 Conversion Result Resolution */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */
+ uint16_t WINSS:1; /*!< bit: 11 Window Single Sample */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLB_OFFSET 0x06 /**< \brief (ADC_CTRLB offset) Control B */
+#define ADC_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */
+
+#define ADC_CTRLB_LEFTADJ_Pos 0 /**< \brief (ADC_CTRLB) Left-Adjusted Result */
+#define ADC_CTRLB_LEFTADJ (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos)
+#define ADC_CTRLB_FREERUN_Pos 1 /**< \brief (ADC_CTRLB) Free Running Mode */
+#define ADC_CTRLB_FREERUN (_U_(0x1) << ADC_CTRLB_FREERUN_Pos)
+#define ADC_CTRLB_CORREN_Pos 2 /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */
+#define ADC_CTRLB_CORREN (_U_(0x1) << ADC_CTRLB_CORREN_Pos)
+#define ADC_CTRLB_RESSEL_Pos 3 /**< \brief (ADC_CTRLB) Conversion Result Resolution */
+#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
+#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLB) 12-bit result */
+#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */
+#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLB) 10-bit result */
+#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLB) 8-bit result */
+#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_WINMODE_Pos 8 /**< \brief (ADC_CTRLB) Window Monitor Mode */
+#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos)
+#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos))
+#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLB) No window mode (default) */
+#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLB) RESULT > WINLT */
+#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLB) RESULT < WINUT */
+#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */
+#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */
+#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos)
+#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos)
+#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos)
+#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos)
+#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos)
+#define ADC_CTRLB_WINSS_Pos 11 /**< \brief (ADC_CTRLB) Window Single Sample */
+#define ADC_CTRLB_WINSS (_U_(0x1) << ADC_CTRLB_WINSS_Pos)
+#define ADC_CTRLB_MASK _U_(0x0F1F) /**< \brief (ADC_CTRLB) MASK Register */
+
+/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_REFCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_REFCTRL_OFFSET 0x08 /**< \brief (ADC_REFCTRL offset) Reference Control */
+#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */
+
+#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */
+#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
+#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */
+#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */
+#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< \brief (ADC_REFCTRL) VDDANA */
+#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */
+#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< \brief (ADC_REFCTRL) External Reference */
+#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */
+#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
+#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos)
+#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */
+
+/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
+ uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_AVGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_AVGCTRL_OFFSET 0x0A /**< \brief (ADC_AVGCTRL offset) Average Control */
+#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */
+
+#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
+#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
+#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */
+#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */
+#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */
+#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */
+#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */
+#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */
+#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */
+#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */
+#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */
+#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */
+#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */
+#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
+#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos)
+#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
+#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */
+
+/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_SAMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SAMPCTRL_OFFSET 0x0B /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */
+#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */
+
+#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
+#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos)
+#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
+#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */
+#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos)
+#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */
+
+/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_WINLT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINLT_OFFSET 0x0C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
+#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
+
+#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */
+#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos)
+#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
+#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */
+
+/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_WINUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINUT_OFFSET 0x0E /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
+#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
+
+#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */
+#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos)
+#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
+#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */
+
+/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_GAINCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_GAINCORR_OFFSET 0x10 /**< \brief (ADC_GAINCORR offset) Gain Correction */
+#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
+
+#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */
+#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos)
+#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
+#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */
+
+/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_OFFSETCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_OFFSETCORR_OFFSET 0x12 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
+#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
+
+#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
+#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos)
+#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
+#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */
+
+/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
+ uint8_t START:1; /*!< bit: 1 Start ADC Conversion */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_SWTRIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SWTRIG_OFFSET 0x14 /**< \brief (ADC_SWTRIG offset) Software Trigger */
+#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
+
+#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
+#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos)
+#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */
+#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos)
+#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */
+
+/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENCLR_OFFSET 0x2C /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
+#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */
+#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos)
+#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */
+#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos)
+#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */
+#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos)
+#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */
+
+/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENSET_OFFSET 0x2D /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
+#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
+
+#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
+#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos)
+#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
+#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos)
+#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
+#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos)
+#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */
+
+/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */
+ __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */
+ __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */
+ __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTFLAG_OFFSET 0x2E /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */
+#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos)
+#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */
+#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos)
+#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */
+#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos)
+#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */
+
+/* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ADCBUSY:1; /*!< bit: 0 ADC Busy Status */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t WCC:6; /*!< bit: 2.. 7 Window Comparator Counter */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_STATUS_OFFSET 0x2F /**< \brief (ADC_STATUS offset) Status */
+#define ADC_STATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_STATUS reset_value) Status */
+
+#define ADC_STATUS_ADCBUSY_Pos 0 /**< \brief (ADC_STATUS) ADC Busy Status */
+#define ADC_STATUS_ADCBUSY (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos)
+#define ADC_STATUS_WCC_Pos 2 /**< \brief (ADC_STATUS) Window Comparator Counter */
+#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos)
+#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos))
+#define ADC_STATUS_MASK _U_(0xFD) /**< \brief (ADC_STATUS) MASK Register */
+
+/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/ 32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */
+ uint32_t INPUTCTRL:1; /*!< bit: 2 Input Control Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 3 Control B Synchronization Busy */
+ uint32_t REFCTRL:1; /*!< bit: 4 Reference Control Synchronization Busy */
+ uint32_t AVGCTRL:1; /*!< bit: 5 Average Control Synchronization Busy */
+ uint32_t SAMPCTRL:1; /*!< bit: 6 Sampling Time Control Synchronization Busy */
+ uint32_t WINLT:1; /*!< bit: 7 Window Monitor Lower Threshold Synchronization Busy */
+ uint32_t WINUT:1; /*!< bit: 8 Window Monitor Upper Threshold Synchronization Busy */
+ uint32_t GAINCORR:1; /*!< bit: 9 Gain Correction Synchronization Busy */
+ uint32_t OFFSETCORR:1; /*!< bit: 10 Offset Correction Synchronization Busy */
+ uint32_t SWTRIG:1; /*!< bit: 11 Software Trigger Synchronization Busy */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ADC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SYNCBUSY_OFFSET 0x30 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */
+#define ADC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */
+#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos)
+#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */
+#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos)
+#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) Input Control Synchronization Busy */
+#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos)
+#define ADC_SYNCBUSY_CTRLB_Pos 3 /**< \brief (ADC_SYNCBUSY) Control B Synchronization Busy */
+#define ADC_SYNCBUSY_CTRLB (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos)
+#define ADC_SYNCBUSY_REFCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) Reference Control Synchronization Busy */
+#define ADC_SYNCBUSY_REFCTRL (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos)
+#define ADC_SYNCBUSY_AVGCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) Average Control Synchronization Busy */
+#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos)
+#define ADC_SYNCBUSY_SAMPCTRL_Pos 6 /**< \brief (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy */
+#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos)
+#define ADC_SYNCBUSY_WINLT_Pos 7 /**< \brief (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy */
+#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos)
+#define ADC_SYNCBUSY_WINUT_Pos 8 /**< \brief (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy */
+#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos)
+#define ADC_SYNCBUSY_GAINCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) Gain Correction Synchronization Busy */
+#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos)
+#define ADC_SYNCBUSY_OFFSETCORR_Pos 10 /**< \brief (ADC_SYNCBUSY) Offset Correction Synchronization Busy */
+#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos)
+#define ADC_SYNCBUSY_SWTRIG_Pos 11 /**< \brief (ADC_SYNCBUSY) Software Trigger Synchronization Busy */
+#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos)
+#define ADC_SYNCBUSY_MASK _U_(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */
+
+/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 DMA Sequential Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ADC_DSEQDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DSEQDATA_OFFSET 0x34 /**< \brief (ADC_DSEQDATA offset) DMA Sequencial Data */
+#define ADC_DSEQDATA_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */
+
+#define ADC_DSEQDATA_DATA_Pos 0 /**< \brief (ADC_DSEQDATA) DMA Sequential Data */
+#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos)
+#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos))
+#define ADC_DSEQDATA_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */
+
+/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */
+ uint32_t CTRLB:1; /*!< bit: 1 Control B */
+ uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */
+ uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */
+ uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */
+ uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */
+ uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */
+ uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */
+ uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */
+ uint32_t :22; /*!< bit: 9..30 Reserved */
+ uint32_t AUTOSTART:1; /*!< bit: 31 ADC Auto-Start Conversion */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ADC_DSEQCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DSEQCTRL_OFFSET 0x38 /**< \brief (ADC_DSEQCTRL offset) DMA Sequential Control */
+#define ADC_DSEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */
+
+#define ADC_DSEQCTRL_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQCTRL) Input Control */
+#define ADC_DSEQCTRL_INPUTCTRL (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos)
+#define ADC_DSEQCTRL_CTRLB_Pos 1 /**< \brief (ADC_DSEQCTRL) Control B */
+#define ADC_DSEQCTRL_CTRLB (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos)
+#define ADC_DSEQCTRL_REFCTRL_Pos 2 /**< \brief (ADC_DSEQCTRL) Reference Control */
+#define ADC_DSEQCTRL_REFCTRL (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos)
+#define ADC_DSEQCTRL_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQCTRL) Average Control */
+#define ADC_DSEQCTRL_AVGCTRL (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos)
+#define ADC_DSEQCTRL_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQCTRL) Sampling Time Control */
+#define ADC_DSEQCTRL_SAMPCTRL (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos)
+#define ADC_DSEQCTRL_WINLT_Pos 5 /**< \brief (ADC_DSEQCTRL) Window Monitor Lower Threshold */
+#define ADC_DSEQCTRL_WINLT (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos)
+#define ADC_DSEQCTRL_WINUT_Pos 6 /**< \brief (ADC_DSEQCTRL) Window Monitor Upper Threshold */
+#define ADC_DSEQCTRL_WINUT (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos)
+#define ADC_DSEQCTRL_GAINCORR_Pos 7 /**< \brief (ADC_DSEQCTRL) Gain Correction */
+#define ADC_DSEQCTRL_GAINCORR (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos)
+#define ADC_DSEQCTRL_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQCTRL) Offset Correction */
+#define ADC_DSEQCTRL_OFFSETCORR (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos)
+#define ADC_DSEQCTRL_AUTOSTART_Pos 31 /**< \brief (ADC_DSEQCTRL) ADC Auto-Start Conversion */
+#define ADC_DSEQCTRL_AUTOSTART (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos)
+#define ADC_DSEQCTRL_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */
+
+/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/ 32) DMA Sequencial Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */
+ uint32_t CTRLB:1; /*!< bit: 1 Control B */
+ uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */
+ uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */
+ uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */
+ uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */
+ uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */
+ uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */
+ uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */
+ uint32_t :22; /*!< bit: 9..30 Reserved */
+ uint32_t BUSY:1; /*!< bit: 31 DMA Sequencing Busy */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ADC_DSEQSTAT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DSEQSTAT_OFFSET 0x3C /**< \brief (ADC_DSEQSTAT offset) DMA Sequencial Status */
+#define ADC_DSEQSTAT_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */
+
+#define ADC_DSEQSTAT_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQSTAT) Input Control */
+#define ADC_DSEQSTAT_INPUTCTRL (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos)
+#define ADC_DSEQSTAT_CTRLB_Pos 1 /**< \brief (ADC_DSEQSTAT) Control B */
+#define ADC_DSEQSTAT_CTRLB (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos)
+#define ADC_DSEQSTAT_REFCTRL_Pos 2 /**< \brief (ADC_DSEQSTAT) Reference Control */
+#define ADC_DSEQSTAT_REFCTRL (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos)
+#define ADC_DSEQSTAT_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQSTAT) Average Control */
+#define ADC_DSEQSTAT_AVGCTRL (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos)
+#define ADC_DSEQSTAT_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQSTAT) Sampling Time Control */
+#define ADC_DSEQSTAT_SAMPCTRL (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos)
+#define ADC_DSEQSTAT_WINLT_Pos 5 /**< \brief (ADC_DSEQSTAT) Window Monitor Lower Threshold */
+#define ADC_DSEQSTAT_WINLT (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos)
+#define ADC_DSEQSTAT_WINUT_Pos 6 /**< \brief (ADC_DSEQSTAT) Window Monitor Upper Threshold */
+#define ADC_DSEQSTAT_WINUT (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos)
+#define ADC_DSEQSTAT_GAINCORR_Pos 7 /**< \brief (ADC_DSEQSTAT) Gain Correction */
+#define ADC_DSEQSTAT_GAINCORR (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos)
+#define ADC_DSEQSTAT_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQSTAT) Offset Correction */
+#define ADC_DSEQSTAT_OFFSETCORR (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos)
+#define ADC_DSEQSTAT_BUSY_Pos 31 /**< \brief (ADC_DSEQSTAT) DMA Sequencing Busy */
+#define ADC_DSEQSTAT_BUSY (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos)
+#define ADC_DSEQSTAT_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */
+
+/* -------- ADC_RESULT : (ADC Offset: 0x40) (R/ 16) Result Conversion Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_RESULT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_RESULT_OFFSET 0x40 /**< \brief (ADC_RESULT offset) Result Conversion Value */
+#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result Conversion Value */
+
+#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */
+#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos)
+#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
+#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */
+
+/* -------- ADC_RESS : (ADC Offset: 0x44) (R/ 16) Last Sample Result -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RESS:16; /*!< bit: 0..15 Last ADC conversion result */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_RESS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_RESS_OFFSET 0x44 /**< \brief (ADC_RESS offset) Last Sample Result */
+#define ADC_RESS_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESS reset_value) Last Sample Result */
+
+#define ADC_RESS_RESS_Pos 0 /**< \brief (ADC_RESS) Last ADC conversion result */
+#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos)
+#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos))
+#define ADC_RESS_MASK _U_(0xFFFF) /**< \brief (ADC_RESS) MASK Register */
+
+/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t BIASR2R:3; /*!< bit: 4.. 6 Bias R2R Ampli scaling */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_CALIB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CALIB_OFFSET 0x48 /**< \brief (ADC_CALIB offset) Calibration */
+#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */
+
+#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */
+#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos)
+#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos))
+#define ADC_CALIB_BIASR2R_Pos 4 /**< \brief (ADC_CALIB) Bias R2R Ampli scaling */
+#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos)
+#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos))
+#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */
+#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos)
+#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos))
+#define ADC_CALIB_MASK _U_(0x0777) /**< \brief (ADC_CALIB) MASK Register */
+
+/** \brief ADC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */
+ __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x03 (R/W 8) Debug Control */
+ __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x04 (R/W 16) Input Control */
+ __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x06 (R/W 16) Control B */
+ __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x08 (R/W 8) Reference Control */
+ RoReg8 Reserved1[0x1];
+ __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0A (R/W 8) Average Control */
+ __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0B (R/W 8) Sample Time Control */
+ __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */
+ __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */
+ __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x10 (R/W 16) Gain Correction */
+ __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x12 (R/W 16) Offset Correction */
+ __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x14 (R/W 8) Software Trigger */
+ RoReg8 Reserved2[0x17];
+ __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x2C (R/W 8) Interrupt Enable Clear */
+ __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x2D (R/W 8) Interrupt Enable Set */
+ __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */
+ __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x2F (R/ 8) Status */
+ __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x30 (R/ 32) Synchronization Busy */
+ __O ADC_DSEQDATA_Type DSEQDATA; /**< \brief Offset: 0x34 ( /W 32) DMA Sequencial Data */
+ __IO ADC_DSEQCTRL_Type DSEQCTRL; /**< \brief Offset: 0x38 (R/W 32) DMA Sequential Control */
+ __I ADC_DSEQSTAT_Type DSEQSTAT; /**< \brief Offset: 0x3C (R/ 32) DMA Sequencial Status */
+ __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x40 (R/ 16) Result Conversion Value */
+ RoReg8 Reserved3[0x2];
+ __I ADC_RESS_Type RESS; /**< \brief Offset: 0x44 (R/ 16) Last Sample Result */
+ RoReg8 Reserved4[0x2];
+ __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x48 (R/W 16) Calibration */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_ADC_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/aes.h b/sysmoOCTSIM/include/component/aes.h
index 64c7121..2831d0d 100644
--- a/sysmoOCTSIM/include/component/aes.h
+++ b/sysmoOCTSIM/include/component/aes.h
@@ -1,375 +1,375 @@
-/**
- * \file
- *
- * \brief Component description for AES
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_AES_COMPONENT_
-#define _SAME54_AES_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR AES */
-/* ========================================================================== */
-/** \addtogroup SAME54_AES Advanced Encryption Standard */
-/*@{*/
-
-#define AES_U2238
-#define REV_AES 0x220
-
-/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */
- uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */
- uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */
- uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */
- uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */
- uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */
- uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */
- uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */
- uint32_t :1; /*!< bit: 15 Reserved */
- uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} AES_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */
-#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */
-
-#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */
-#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos)
-#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */
-#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos)
-#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */
-#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))
-#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */
-#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */
-#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */
-#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */
-#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */
-#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */
-#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */
-#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */
-#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos)
-#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))
-#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
-#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
-#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
-#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
-#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
-#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos)
-#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos)
-#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos)
-#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos)
-#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos)
-#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */
-#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos)
-#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))
-#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */
-#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */
-#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */
-#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos)
-#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos)
-#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos)
-#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */
-#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos)
-#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */
-#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */
-#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos)
-#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos)
-#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */
-#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos)
-#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */
-#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */
-#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos)
-#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos)
-#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */
-#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos)
-#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
-#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */
-#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos)
-#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos)
-#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */
-#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos)
-#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
-#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */
-#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos)
-#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos)
-#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */
-#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos)
-#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
-#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */
-#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos)
-#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos)
-#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */
-#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos)
-#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))
-#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */
-
-/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */
- uint8_t NEWMSG:1; /*!< bit: 1 New message */
- uint8_t EOM:1; /*!< bit: 2 End of message */
- uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AES_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */
-#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */
-
-#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */
-#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos)
-#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */
-#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos)
-#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */
-#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos)
-#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */
-#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos)
-#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */
-
-/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
- uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AES_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */
-#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */
-#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos)
-#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */
-#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos)
-#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */
-
-/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
- uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AES_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */
-#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */
-
-#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */
-#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos)
-#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */
-#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos)
-#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */
-
-/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */
- __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */
- __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AES_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */
-#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */
-
-#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */
-#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos)
-#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */
-#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos)
-#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */
-
-/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AES_DATABUFPTR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */
-#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */
-
-#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */
-#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos)
-#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))
-#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */
-
-/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AES_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */
-#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */
-
-#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */
-#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos)
-#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */
-
-/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint32_t reg; /*!< Type used for register access */
-} AES_KEYWORD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */
-#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */
-#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */
-
-/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint32_t reg; /*!< Type used for register access */
-} AES_INDATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */
-#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */
-#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */
-
-/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint32_t reg; /*!< Type used for register access */
-} AES_INTVECTV_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */
-#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */
-#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */
-
-/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint32_t reg; /*!< Type used for register access */
-} AES_HASHKEY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */
-#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */
-#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */
-
-/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint32_t reg; /*!< Type used for register access */
-} AES_GHASH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */
-#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */
-#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */
-
-/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint32_t reg; /*!< Type used for register access */
-} AES_CIPLEN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */
-#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */
-#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */
-
-/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint32_t reg; /*!< Type used for register access */
-} AES_RANDSEED_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */
-#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */
-#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */
-
-/** \brief AES hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
- __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */
- __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */
- __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */
- __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */
- __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */
- __IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */
- RoReg8 Reserved1[0x2];
- __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */
- RoReg8 Reserved2[0xC];
- __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */
- __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */
- RoReg8 Reserved3[0x10];
- __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */
- __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */
- RoReg8 Reserved4[0x4];
- __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */
- __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */
-} Aes;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_AES_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for AES
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_AES_COMPONENT_
+#define _SAME54_AES_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR AES */
+/* ========================================================================== */
+/** \addtogroup SAME54_AES Advanced Encryption Standard */
+/*@{*/
+
+#define AES_U2238
+#define REV_AES 0x220
+
+/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */
+ uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */
+ uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */
+ uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */
+ uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */
+ uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */
+ uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */
+ uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} AES_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */
+#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */
+
+#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */
+#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos)
+#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */
+#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos)
+#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */
+#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))
+#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */
+#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */
+#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */
+#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */
+#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */
+#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */
+#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */
+#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */
+#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))
+#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
+#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
+#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
+#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
+#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
+#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */
+#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos)
+#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))
+#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */
+#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */
+#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */
+#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos)
+#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos)
+#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos)
+#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */
+#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos)
+#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */
+#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */
+#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos)
+#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos)
+#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */
+#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos)
+#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */
+#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */
+#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos)
+#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos)
+#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */
+#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos)
+#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
+#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */
+#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos)
+#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos)
+#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */
+#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos)
+#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
+#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */
+#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos)
+#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos)
+#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */
+#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos)
+#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
+#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */
+#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos)
+#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos)
+#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */
+#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos)
+#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))
+#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */
+
+/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */
+ uint8_t NEWMSG:1; /*!< bit: 1 New message */
+ uint8_t EOM:1; /*!< bit: 2 End of message */
+ uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AES_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */
+#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */
+
+#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */
+#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos)
+#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */
+#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos)
+#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */
+#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos)
+#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */
+#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos)
+#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */
+
+/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
+ uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AES_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */
+#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */
+#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos)
+#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */
+#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos)
+#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */
+
+/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
+ uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AES_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */
+#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */
+
+#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */
+#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos)
+#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */
+#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos)
+#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */
+
+/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */
+ __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */
+ __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AES_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */
+#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */
+
+#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */
+#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos)
+#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */
+#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos)
+#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */
+
+/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AES_DATABUFPTR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */
+#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */
+
+#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */
+#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos)
+#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))
+#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */
+
+/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AES_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */
+#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */
+
+#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */
+#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos)
+#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */
+
+/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} AES_KEYWORD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */
+#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */
+#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */
+
+/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} AES_INDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */
+#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */
+#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */
+
+/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} AES_INTVECTV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */
+#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */
+#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */
+
+/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} AES_HASHKEY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */
+#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */
+#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */
+
+/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} AES_GHASH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */
+#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */
+#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */
+
+/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} AES_CIPLEN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */
+#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */
+#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */
+
+/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} AES_RANDSEED_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */
+#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */
+#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */
+
+/** \brief AES hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */
+ __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */
+ __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */
+ __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */
+ __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */
+ __IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */
+ RoReg8 Reserved1[0x2];
+ __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */
+ RoReg8 Reserved2[0xC];
+ __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */
+ __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */
+ RoReg8 Reserved3[0x10];
+ __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */
+ __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */
+ RoReg8 Reserved4[0x4];
+ __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */
+ __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */
+} Aes;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_AES_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/can.h b/sysmoOCTSIM/include/component/can.h
index fbe0f5d..48b3cab 100644
--- a/sysmoOCTSIM/include/component/can.h
+++ b/sysmoOCTSIM/include/component/can.h
@@ -1,3187 +1,3187 @@
-/**
- * \file
- *
- * \brief Component description for CAN
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_CAN_COMPONENT_
-#define _SAME54_CAN_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR CAN */
-/* ========================================================================== */
-/** \addtogroup SAME54_CAN Control Area Network */
-/*@{*/
-
-#define CAN_U2003
-#define REV_CAN 0x321
-
-/* -------- CAN_CREL : (CAN Offset: 0x00) (R/ 32) Core Release -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :20; /*!< bit: 0..19 Reserved */
- uint32_t SUBSTEP:4; /*!< bit: 20..23 Sub-step of Core Release */
- uint32_t STEP:4; /*!< bit: 24..27 Step of Core Release */
- uint32_t REL:4; /*!< bit: 28..31 Core Release */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_CREL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_CREL_OFFSET 0x00 /**< \brief (CAN_CREL offset) Core Release */
-#define CAN_CREL_RESETVALUE _U_(0x32100000) /**< \brief (CAN_CREL reset_value) Core Release */
-
-#define CAN_CREL_SUBSTEP_Pos 20 /**< \brief (CAN_CREL) Sub-step of Core Release */
-#define CAN_CREL_SUBSTEP_Msk (_U_(0xF) << CAN_CREL_SUBSTEP_Pos)
-#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & ((value) << CAN_CREL_SUBSTEP_Pos))
-#define CAN_CREL_STEP_Pos 24 /**< \brief (CAN_CREL) Step of Core Release */
-#define CAN_CREL_STEP_Msk (_U_(0xF) << CAN_CREL_STEP_Pos)
-#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & ((value) << CAN_CREL_STEP_Pos))
-#define CAN_CREL_REL_Pos 28 /**< \brief (CAN_CREL) Core Release */
-#define CAN_CREL_REL_Msk (_U_(0xF) << CAN_CREL_REL_Pos)
-#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & ((value) << CAN_CREL_REL_Pos))
-#define CAN_CREL_MASK _U_(0xFFF00000) /**< \brief (CAN_CREL) MASK Register */
-
-/* -------- CAN_ENDN : (CAN Offset: 0x04) (R/ 32) Endian -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ETV:32; /*!< bit: 0..31 Endianness Test Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_ENDN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_ENDN_OFFSET 0x04 /**< \brief (CAN_ENDN offset) Endian */
-#define CAN_ENDN_RESETVALUE _U_(0x87654321) /**< \brief (CAN_ENDN reset_value) Endian */
-
-#define CAN_ENDN_ETV_Pos 0 /**< \brief (CAN_ENDN) Endianness Test Value */
-#define CAN_ENDN_ETV_Msk (_U_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos)
-#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & ((value) << CAN_ENDN_ETV_Pos))
-#define CAN_ENDN_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_ENDN) MASK Register */
-
-/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t QOS:2; /*!< bit: 0.. 1 Quality of Service */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_MRCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_MRCFG_OFFSET 0x08 /**< \brief (CAN_MRCFG offset) Message RAM Configuration */
-#define CAN_MRCFG_RESETVALUE _U_(0x00000002) /**< \brief (CAN_MRCFG reset_value) Message RAM Configuration */
-
-#define CAN_MRCFG_QOS_Pos 0 /**< \brief (CAN_MRCFG) Quality of Service */
-#define CAN_MRCFG_QOS_Msk (_U_(0x3) << CAN_MRCFG_QOS_Pos)
-#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & ((value) << CAN_MRCFG_QOS_Pos))
-#define CAN_MRCFG_QOS_DISABLE_Val _U_(0x0) /**< \brief (CAN_MRCFG) Background (no sensitive operation) */
-#define CAN_MRCFG_QOS_LOW_Val _U_(0x1) /**< \brief (CAN_MRCFG) Sensitive Bandwidth */
-#define CAN_MRCFG_QOS_MEDIUM_Val _U_(0x2) /**< \brief (CAN_MRCFG) Sensitive Latency */
-#define CAN_MRCFG_QOS_HIGH_Val _U_(0x3) /**< \brief (CAN_MRCFG) Critical Latency */
-#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos)
-#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos)
-#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos)
-#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos)
-#define CAN_MRCFG_MASK _U_(0x00000003) /**< \brief (CAN_MRCFG) MASK Register */
-
-/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DSJW:4; /*!< bit: 0.. 3 Data (Re)Synchronization Jump Width */
- uint32_t DTSEG2:4; /*!< bit: 4.. 7 Data time segment after sample point */
- uint32_t DTSEG1:5; /*!< bit: 8..12 Data time segment before sample point */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t DBRP:5; /*!< bit: 16..20 Data Baud Rate Prescaler */
- uint32_t :2; /*!< bit: 21..22 Reserved */
- uint32_t TDC:1; /*!< bit: 23 Tranceiver Delay Compensation */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_DBTP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_DBTP_OFFSET 0x0C /**< \brief (CAN_DBTP offset) Fast Bit Timing and Prescaler */
-#define CAN_DBTP_RESETVALUE _U_(0x00000A33) /**< \brief (CAN_DBTP reset_value) Fast Bit Timing and Prescaler */
-
-#define CAN_DBTP_DSJW_Pos 0 /**< \brief (CAN_DBTP) Data (Re)Synchronization Jump Width */
-#define CAN_DBTP_DSJW_Msk (_U_(0xF) << CAN_DBTP_DSJW_Pos)
-#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & ((value) << CAN_DBTP_DSJW_Pos))
-#define CAN_DBTP_DTSEG2_Pos 4 /**< \brief (CAN_DBTP) Data time segment after sample point */
-#define CAN_DBTP_DTSEG2_Msk (_U_(0xF) << CAN_DBTP_DTSEG2_Pos)
-#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & ((value) << CAN_DBTP_DTSEG2_Pos))
-#define CAN_DBTP_DTSEG1_Pos 8 /**< \brief (CAN_DBTP) Data time segment before sample point */
-#define CAN_DBTP_DTSEG1_Msk (_U_(0x1F) << CAN_DBTP_DTSEG1_Pos)
-#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & ((value) << CAN_DBTP_DTSEG1_Pos))
-#define CAN_DBTP_DBRP_Pos 16 /**< \brief (CAN_DBTP) Data Baud Rate Prescaler */
-#define CAN_DBTP_DBRP_Msk (_U_(0x1F) << CAN_DBTP_DBRP_Pos)
-#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & ((value) << CAN_DBTP_DBRP_Pos))
-#define CAN_DBTP_TDC_Pos 23 /**< \brief (CAN_DBTP) Tranceiver Delay Compensation */
-#define CAN_DBTP_TDC (_U_(0x1) << CAN_DBTP_TDC_Pos)
-#define CAN_DBTP_MASK _U_(0x009F1FFF) /**< \brief (CAN_DBTP) MASK Register */
-
-/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :4; /*!< bit: 0.. 3 Reserved */
- uint32_t LBCK:1; /*!< bit: 4 Loop Back Mode */
- uint32_t TX:2; /*!< bit: 5.. 6 Control of Transmit Pin */
- uint32_t RX:1; /*!< bit: 7 Receive Pin */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TEST_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TEST_OFFSET 0x10 /**< \brief (CAN_TEST offset) Test */
-#define CAN_TEST_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TEST reset_value) Test */
-
-#define CAN_TEST_LBCK_Pos 4 /**< \brief (CAN_TEST) Loop Back Mode */
-#define CAN_TEST_LBCK (_U_(0x1) << CAN_TEST_LBCK_Pos)
-#define CAN_TEST_TX_Pos 5 /**< \brief (CAN_TEST) Control of Transmit Pin */
-#define CAN_TEST_TX_Msk (_U_(0x3) << CAN_TEST_TX_Pos)
-#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & ((value) << CAN_TEST_TX_Pos))
-#define CAN_TEST_TX_CORE_Val _U_(0x0) /**< \brief (CAN_TEST) TX controlled by CAN core */
-#define CAN_TEST_TX_SAMPLE_Val _U_(0x1) /**< \brief (CAN_TEST) TX monitoring sample point */
-#define CAN_TEST_TX_DOMINANT_Val _U_(0x2) /**< \brief (CAN_TEST) Dominant (0) level at pin CAN_TX */
-#define CAN_TEST_TX_RECESSIVE_Val _U_(0x3) /**< \brief (CAN_TEST) Recessive (1) level at pin CAN_TX */
-#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos)
-#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos)
-#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos)
-#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos)
-#define CAN_TEST_RX_Pos 7 /**< \brief (CAN_TEST) Receive Pin */
-#define CAN_TEST_RX (_U_(0x1) << CAN_TEST_RX_Pos)
-#define CAN_TEST_MASK _U_(0x000000F0) /**< \brief (CAN_TEST) MASK Register */
-
-/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t WDC:8; /*!< bit: 0.. 7 Watchdog Configuration */
- uint32_t WDV:8; /*!< bit: 8..15 Watchdog Value */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RWD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RWD_OFFSET 0x14 /**< \brief (CAN_RWD offset) RAM Watchdog */
-#define CAN_RWD_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RWD reset_value) RAM Watchdog */
-
-#define CAN_RWD_WDC_Pos 0 /**< \brief (CAN_RWD) Watchdog Configuration */
-#define CAN_RWD_WDC_Msk (_U_(0xFF) << CAN_RWD_WDC_Pos)
-#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & ((value) << CAN_RWD_WDC_Pos))
-#define CAN_RWD_WDV_Pos 8 /**< \brief (CAN_RWD) Watchdog Value */
-#define CAN_RWD_WDV_Msk (_U_(0xFF) << CAN_RWD_WDV_Pos)
-#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & ((value) << CAN_RWD_WDV_Pos))
-#define CAN_RWD_MASK _U_(0x0000FFFF) /**< \brief (CAN_RWD) MASK Register */
-
-/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t INIT:1; /*!< bit: 0 Initialization */
- uint32_t CCE:1; /*!< bit: 1 Configuration Change Enable */
- uint32_t ASM:1; /*!< bit: 2 ASM Restricted Operation Mode */
- uint32_t CSA:1; /*!< bit: 3 Clock Stop Acknowledge */
- uint32_t CSR:1; /*!< bit: 4 Clock Stop Request */
- uint32_t MON:1; /*!< bit: 5 Bus Monitoring Mode */
- uint32_t DAR:1; /*!< bit: 6 Disable Automatic Retransmission */
- uint32_t TEST:1; /*!< bit: 7 Test Mode Enable */
- uint32_t FDOE:1; /*!< bit: 8 FD Operation Enable */
- uint32_t BRSE:1; /*!< bit: 9 Bit Rate Switch Enable */
- uint32_t :2; /*!< bit: 10..11 Reserved */
- uint32_t PXHD:1; /*!< bit: 12 Protocol Exception Handling Disable */
- uint32_t EFBI:1; /*!< bit: 13 Edge Filtering during Bus Integration */
- uint32_t TXP:1; /*!< bit: 14 Transmit Pause */
- uint32_t NISO:1; /*!< bit: 15 Non ISO Operation */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_CCCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_CCCR_OFFSET 0x18 /**< \brief (CAN_CCCR offset) CC Control */
-#define CAN_CCCR_RESETVALUE _U_(0x00000001) /**< \brief (CAN_CCCR reset_value) CC Control */
-
-#define CAN_CCCR_INIT_Pos 0 /**< \brief (CAN_CCCR) Initialization */
-#define CAN_CCCR_INIT (_U_(0x1) << CAN_CCCR_INIT_Pos)
-#define CAN_CCCR_CCE_Pos 1 /**< \brief (CAN_CCCR) Configuration Change Enable */
-#define CAN_CCCR_CCE (_U_(0x1) << CAN_CCCR_CCE_Pos)
-#define CAN_CCCR_ASM_Pos 2 /**< \brief (CAN_CCCR) ASM Restricted Operation Mode */
-#define CAN_CCCR_ASM (_U_(0x1) << CAN_CCCR_ASM_Pos)
-#define CAN_CCCR_CSA_Pos 3 /**< \brief (CAN_CCCR) Clock Stop Acknowledge */
-#define CAN_CCCR_CSA (_U_(0x1) << CAN_CCCR_CSA_Pos)
-#define CAN_CCCR_CSR_Pos 4 /**< \brief (CAN_CCCR) Clock Stop Request */
-#define CAN_CCCR_CSR (_U_(0x1) << CAN_CCCR_CSR_Pos)
-#define CAN_CCCR_MON_Pos 5 /**< \brief (CAN_CCCR) Bus Monitoring Mode */
-#define CAN_CCCR_MON (_U_(0x1) << CAN_CCCR_MON_Pos)
-#define CAN_CCCR_DAR_Pos 6 /**< \brief (CAN_CCCR) Disable Automatic Retransmission */
-#define CAN_CCCR_DAR (_U_(0x1) << CAN_CCCR_DAR_Pos)
-#define CAN_CCCR_TEST_Pos 7 /**< \brief (CAN_CCCR) Test Mode Enable */
-#define CAN_CCCR_TEST (_U_(0x1) << CAN_CCCR_TEST_Pos)
-#define CAN_CCCR_FDOE_Pos 8 /**< \brief (CAN_CCCR) FD Operation Enable */
-#define CAN_CCCR_FDOE (_U_(0x1) << CAN_CCCR_FDOE_Pos)
-#define CAN_CCCR_BRSE_Pos 9 /**< \brief (CAN_CCCR) Bit Rate Switch Enable */
-#define CAN_CCCR_BRSE (_U_(0x1) << CAN_CCCR_BRSE_Pos)
-#define CAN_CCCR_PXHD_Pos 12 /**< \brief (CAN_CCCR) Protocol Exception Handling Disable */
-#define CAN_CCCR_PXHD (_U_(0x1) << CAN_CCCR_PXHD_Pos)
-#define CAN_CCCR_EFBI_Pos 13 /**< \brief (CAN_CCCR) Edge Filtering during Bus Integration */
-#define CAN_CCCR_EFBI (_U_(0x1) << CAN_CCCR_EFBI_Pos)
-#define CAN_CCCR_TXP_Pos 14 /**< \brief (CAN_CCCR) Transmit Pause */
-#define CAN_CCCR_TXP (_U_(0x1) << CAN_CCCR_TXP_Pos)
-#define CAN_CCCR_NISO_Pos 15 /**< \brief (CAN_CCCR) Non ISO Operation */
-#define CAN_CCCR_NISO (_U_(0x1) << CAN_CCCR_NISO_Pos)
-#define CAN_CCCR_MASK _U_(0x0000F3FF) /**< \brief (CAN_CCCR) MASK Register */
-
-/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t NTSEG2:7; /*!< bit: 0.. 6 Nominal Time segment after sample point */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t NTSEG1:8; /*!< bit: 8..15 Nominal Time segment before sample point */
- uint32_t NBRP:9; /*!< bit: 16..24 Nominal Baud Rate Prescaler */
- uint32_t NSJW:7; /*!< bit: 25..31 Nominal (Re)Synchronization Jump Width */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_NBTP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_NBTP_OFFSET 0x1C /**< \brief (CAN_NBTP offset) Nominal Bit Timing and Prescaler */
-#define CAN_NBTP_RESETVALUE _U_(0x06000A03) /**< \brief (CAN_NBTP reset_value) Nominal Bit Timing and Prescaler */
-
-#define CAN_NBTP_NTSEG2_Pos 0 /**< \brief (CAN_NBTP) Nominal Time segment after sample point */
-#define CAN_NBTP_NTSEG2_Msk (_U_(0x7F) << CAN_NBTP_NTSEG2_Pos)
-#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & ((value) << CAN_NBTP_NTSEG2_Pos))
-#define CAN_NBTP_NTSEG1_Pos 8 /**< \brief (CAN_NBTP) Nominal Time segment before sample point */
-#define CAN_NBTP_NTSEG1_Msk (_U_(0xFF) << CAN_NBTP_NTSEG1_Pos)
-#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & ((value) << CAN_NBTP_NTSEG1_Pos))
-#define CAN_NBTP_NBRP_Pos 16 /**< \brief (CAN_NBTP) Nominal Baud Rate Prescaler */
-#define CAN_NBTP_NBRP_Msk (_U_(0x1FF) << CAN_NBTP_NBRP_Pos)
-#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & ((value) << CAN_NBTP_NBRP_Pos))
-#define CAN_NBTP_NSJW_Pos 25 /**< \brief (CAN_NBTP) Nominal (Re)Synchronization Jump Width */
-#define CAN_NBTP_NSJW_Msk (_U_(0x7F) << CAN_NBTP_NSJW_Pos)
-#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & ((value) << CAN_NBTP_NSJW_Pos))
-#define CAN_NBTP_MASK _U_(0xFFFFFF7F) /**< \brief (CAN_NBTP) MASK Register */
-
-/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TSS:2; /*!< bit: 0.. 1 Timestamp Select */
- uint32_t :14; /*!< bit: 2..15 Reserved */
- uint32_t TCP:4; /*!< bit: 16..19 Timestamp Counter Prescaler */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TSCC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TSCC_OFFSET 0x20 /**< \brief (CAN_TSCC offset) Timestamp Counter Configuration */
-#define CAN_TSCC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCC reset_value) Timestamp Counter Configuration */
-
-#define CAN_TSCC_TSS_Pos 0 /**< \brief (CAN_TSCC) Timestamp Select */
-#define CAN_TSCC_TSS_Msk (_U_(0x3) << CAN_TSCC_TSS_Pos)
-#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & ((value) << CAN_TSCC_TSS_Pos))
-#define CAN_TSCC_TSS_ZERO_Val _U_(0x0) /**< \brief (CAN_TSCC) Timestamp counter value always 0x0000 */
-#define CAN_TSCC_TSS_INC_Val _U_(0x1) /**< \brief (CAN_TSCC) Timestamp counter value incremented by TCP */
-#define CAN_TSCC_TSS_EXT_Val _U_(0x2) /**< \brief (CAN_TSCC) External timestamp counter value used */
-#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos)
-#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos)
-#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos)
-#define CAN_TSCC_TCP_Pos 16 /**< \brief (CAN_TSCC) Timestamp Counter Prescaler */
-#define CAN_TSCC_TCP_Msk (_U_(0xF) << CAN_TSCC_TCP_Pos)
-#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & ((value) << CAN_TSCC_TCP_Pos))
-#define CAN_TSCC_MASK _U_(0x000F0003) /**< \brief (CAN_TSCC) MASK Register */
-
-/* -------- CAN_TSCV : (CAN Offset: 0x24) (R/ 32) Timestamp Counter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TSC:16; /*!< bit: 0..15 Timestamp Counter */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TSCV_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TSCV_OFFSET 0x24 /**< \brief (CAN_TSCV offset) Timestamp Counter Value */
-#define CAN_TSCV_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCV reset_value) Timestamp Counter Value */
-
-#define CAN_TSCV_TSC_Pos 0 /**< \brief (CAN_TSCV) Timestamp Counter */
-#define CAN_TSCV_TSC_Msk (_U_(0xFFFF) << CAN_TSCV_TSC_Pos)
-#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & ((value) << CAN_TSCV_TSC_Pos))
-#define CAN_TSCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TSCV) MASK Register */
-
-/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ETOC:1; /*!< bit: 0 Enable Timeout Counter */
- uint32_t TOS:2; /*!< bit: 1.. 2 Timeout Select */
- uint32_t :13; /*!< bit: 3..15 Reserved */
- uint32_t TOP:16; /*!< bit: 16..31 Timeout Period */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TOCC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TOCC_OFFSET 0x28 /**< \brief (CAN_TOCC offset) Timeout Counter Configuration */
-#define CAN_TOCC_RESETVALUE _U_(0xFFFF0000) /**< \brief (CAN_TOCC reset_value) Timeout Counter Configuration */
-
-#define CAN_TOCC_ETOC_Pos 0 /**< \brief (CAN_TOCC) Enable Timeout Counter */
-#define CAN_TOCC_ETOC (_U_(0x1) << CAN_TOCC_ETOC_Pos)
-#define CAN_TOCC_TOS_Pos 1 /**< \brief (CAN_TOCC) Timeout Select */
-#define CAN_TOCC_TOS_Msk (_U_(0x3) << CAN_TOCC_TOS_Pos)
-#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & ((value) << CAN_TOCC_TOS_Pos))
-#define CAN_TOCC_TOS_CONT_Val _U_(0x0) /**< \brief (CAN_TOCC) Continuout operation */
-#define CAN_TOCC_TOS_TXEF_Val _U_(0x1) /**< \brief (CAN_TOCC) Timeout controlled by TX Event FIFO */
-#define CAN_TOCC_TOS_RXF0_Val _U_(0x2) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 0 */
-#define CAN_TOCC_TOS_RXF1_Val _U_(0x3) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 1 */
-#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos)
-#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos)
-#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos)
-#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos)
-#define CAN_TOCC_TOP_Pos 16 /**< \brief (CAN_TOCC) Timeout Period */
-#define CAN_TOCC_TOP_Msk (_U_(0xFFFF) << CAN_TOCC_TOP_Pos)
-#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & ((value) << CAN_TOCC_TOP_Pos))
-#define CAN_TOCC_MASK _U_(0xFFFF0007) /**< \brief (CAN_TOCC) MASK Register */
-
-/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TOC:16; /*!< bit: 0..15 Timeout Counter */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TOCV_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TOCV_OFFSET 0x2C /**< \brief (CAN_TOCV offset) Timeout Counter Value */
-#define CAN_TOCV_RESETVALUE _U_(0x0000FFFF) /**< \brief (CAN_TOCV reset_value) Timeout Counter Value */
-
-#define CAN_TOCV_TOC_Pos 0 /**< \brief (CAN_TOCV) Timeout Counter */
-#define CAN_TOCV_TOC_Msk (_U_(0xFFFF) << CAN_TOCV_TOC_Pos)
-#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & ((value) << CAN_TOCV_TOC_Pos))
-#define CAN_TOCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TOCV) MASK Register */
-
-/* -------- CAN_ECR : (CAN Offset: 0x40) (R/ 32) Error Counter -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TEC:8; /*!< bit: 0.. 7 Transmit Error Counter */
- uint32_t REC:7; /*!< bit: 8..14 Receive Error Counter */
- uint32_t RP:1; /*!< bit: 15 Receive Error Passive */
- uint32_t CEL:8; /*!< bit: 16..23 CAN Error Logging */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_ECR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_ECR_OFFSET 0x40 /**< \brief (CAN_ECR offset) Error Counter */
-#define CAN_ECR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ECR reset_value) Error Counter */
-
-#define CAN_ECR_TEC_Pos 0 /**< \brief (CAN_ECR) Transmit Error Counter */
-#define CAN_ECR_TEC_Msk (_U_(0xFF) << CAN_ECR_TEC_Pos)
-#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & ((value) << CAN_ECR_TEC_Pos))
-#define CAN_ECR_REC_Pos 8 /**< \brief (CAN_ECR) Receive Error Counter */
-#define CAN_ECR_REC_Msk (_U_(0x7F) << CAN_ECR_REC_Pos)
-#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & ((value) << CAN_ECR_REC_Pos))
-#define CAN_ECR_RP_Pos 15 /**< \brief (CAN_ECR) Receive Error Passive */
-#define CAN_ECR_RP (_U_(0x1) << CAN_ECR_RP_Pos)
-#define CAN_ECR_CEL_Pos 16 /**< \brief (CAN_ECR) CAN Error Logging */
-#define CAN_ECR_CEL_Msk (_U_(0xFF) << CAN_ECR_CEL_Pos)
-#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & ((value) << CAN_ECR_CEL_Pos))
-#define CAN_ECR_MASK _U_(0x00FFFFFF) /**< \brief (CAN_ECR) MASK Register */
-
-/* -------- CAN_PSR : (CAN Offset: 0x44) (R/ 32) Protocol Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t LEC:3; /*!< bit: 0.. 2 Last Error Code */
- uint32_t ACT:2; /*!< bit: 3.. 4 Activity */
- uint32_t EP:1; /*!< bit: 5 Error Passive */
- uint32_t EW:1; /*!< bit: 6 Warning Status */
- uint32_t BO:1; /*!< bit: 7 Bus_Off Status */
- uint32_t DLEC:3; /*!< bit: 8..10 Data Phase Last Error Code */
- uint32_t RESI:1; /*!< bit: 11 ESI flag of last received CAN FD Message */
- uint32_t RBRS:1; /*!< bit: 12 BRS flag of last received CAN FD Message */
- uint32_t RFDF:1; /*!< bit: 13 Received a CAN FD Message */
- uint32_t PXE:1; /*!< bit: 14 Protocol Exception Event */
- uint32_t :1; /*!< bit: 15 Reserved */
- uint32_t TDCV:7; /*!< bit: 16..22 Transmitter Delay Compensation Value */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_PSR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_PSR_OFFSET 0x44 /**< \brief (CAN_PSR offset) Protocol Status */
-#define CAN_PSR_RESETVALUE _U_(0x00000707) /**< \brief (CAN_PSR reset_value) Protocol Status */
-
-#define CAN_PSR_LEC_Pos 0 /**< \brief (CAN_PSR) Last Error Code */
-#define CAN_PSR_LEC_Msk (_U_(0x7) << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & ((value) << CAN_PSR_LEC_Pos))
-#define CAN_PSR_LEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */
-#define CAN_PSR_LEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */
-#define CAN_PSR_LEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */
-#define CAN_PSR_LEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */
-#define CAN_PSR_LEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */
-#define CAN_PSR_LEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */
-#define CAN_PSR_LEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */
-#define CAN_PSR_LEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */
-#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos)
-#define CAN_PSR_ACT_Pos 3 /**< \brief (CAN_PSR) Activity */
-#define CAN_PSR_ACT_Msk (_U_(0x3) << CAN_PSR_ACT_Pos)
-#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & ((value) << CAN_PSR_ACT_Pos))
-#define CAN_PSR_ACT_SYNC_Val _U_(0x0) /**< \brief (CAN_PSR) Node is synchronizing on CAN communication */
-#define CAN_PSR_ACT_IDLE_Val _U_(0x1) /**< \brief (CAN_PSR) Node is neither receiver nor transmitter */
-#define CAN_PSR_ACT_RX_Val _U_(0x2) /**< \brief (CAN_PSR) Node is operating as receiver */
-#define CAN_PSR_ACT_TX_Val _U_(0x3) /**< \brief (CAN_PSR) Node is operating as transmitter */
-#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos)
-#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos)
-#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos)
-#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos)
-#define CAN_PSR_EP_Pos 5 /**< \brief (CAN_PSR) Error Passive */
-#define CAN_PSR_EP (_U_(0x1) << CAN_PSR_EP_Pos)
-#define CAN_PSR_EW_Pos 6 /**< \brief (CAN_PSR) Warning Status */
-#define CAN_PSR_EW (_U_(0x1) << CAN_PSR_EW_Pos)
-#define CAN_PSR_BO_Pos 7 /**< \brief (CAN_PSR) Bus_Off Status */
-#define CAN_PSR_BO (_U_(0x1) << CAN_PSR_BO_Pos)
-#define CAN_PSR_DLEC_Pos 8 /**< \brief (CAN_PSR) Data Phase Last Error Code */
-#define CAN_PSR_DLEC_Msk (_U_(0x7) << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & ((value) << CAN_PSR_DLEC_Pos))
-#define CAN_PSR_DLEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */
-#define CAN_PSR_DLEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */
-#define CAN_PSR_DLEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */
-#define CAN_PSR_DLEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */
-#define CAN_PSR_DLEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */
-#define CAN_PSR_DLEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */
-#define CAN_PSR_DLEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */
-#define CAN_PSR_DLEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */
-#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_RESI_Pos 11 /**< \brief (CAN_PSR) ESI flag of last received CAN FD Message */
-#define CAN_PSR_RESI (_U_(0x1) << CAN_PSR_RESI_Pos)
-#define CAN_PSR_RBRS_Pos 12 /**< \brief (CAN_PSR) BRS flag of last received CAN FD Message */
-#define CAN_PSR_RBRS (_U_(0x1) << CAN_PSR_RBRS_Pos)
-#define CAN_PSR_RFDF_Pos 13 /**< \brief (CAN_PSR) Received a CAN FD Message */
-#define CAN_PSR_RFDF (_U_(0x1) << CAN_PSR_RFDF_Pos)
-#define CAN_PSR_PXE_Pos 14 /**< \brief (CAN_PSR) Protocol Exception Event */
-#define CAN_PSR_PXE (_U_(0x1) << CAN_PSR_PXE_Pos)
-#define CAN_PSR_TDCV_Pos 16 /**< \brief (CAN_PSR) Transmitter Delay Compensation Value */
-#define CAN_PSR_TDCV_Msk (_U_(0x7F) << CAN_PSR_TDCV_Pos)
-#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & ((value) << CAN_PSR_TDCV_Pos))
-#define CAN_PSR_MASK _U_(0x007F7FFF) /**< \brief (CAN_PSR) MASK Register */
-
-/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TDCF:7; /*!< bit: 0.. 6 Transmitter Delay Compensation Filter Length */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t TDCO:7; /*!< bit: 8..14 Transmitter Delay Compensation Offset */
- uint32_t :17; /*!< bit: 15..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TDCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TDCR_OFFSET 0x48 /**< \brief (CAN_TDCR offset) Extended ID Filter Configuration */
-#define CAN_TDCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TDCR reset_value) Extended ID Filter Configuration */
-
-#define CAN_TDCR_TDCF_Pos 0 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Filter Length */
-#define CAN_TDCR_TDCF_Msk (_U_(0x7F) << CAN_TDCR_TDCF_Pos)
-#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & ((value) << CAN_TDCR_TDCF_Pos))
-#define CAN_TDCR_TDCO_Pos 8 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Offset */
-#define CAN_TDCR_TDCO_Msk (_U_(0x7F) << CAN_TDCR_TDCO_Pos)
-#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & ((value) << CAN_TDCR_TDCO_Pos))
-#define CAN_TDCR_MASK _U_(0x00007F7F) /**< \brief (CAN_TDCR) MASK Register */
-
-/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RF0N:1; /*!< bit: 0 Rx FIFO 0 New Message */
- uint32_t RF0W:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached */
- uint32_t RF0F:1; /*!< bit: 2 Rx FIFO 0 Full */
- uint32_t RF0L:1; /*!< bit: 3 Rx FIFO 0 Message Lost */
- uint32_t RF1N:1; /*!< bit: 4 Rx FIFO 1 New Message */
- uint32_t RF1W:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached */
- uint32_t RF1F:1; /*!< bit: 6 Rx FIFO 1 FIFO Full */
- uint32_t RF1L:1; /*!< bit: 7 Rx FIFO 1 Message Lost */
- uint32_t HPM:1; /*!< bit: 8 High Priority Message */
- uint32_t TC:1; /*!< bit: 9 Timestamp Completed */
- uint32_t TCF:1; /*!< bit: 10 Transmission Cancellation Finished */
- uint32_t TFE:1; /*!< bit: 11 Tx FIFO Empty */
- uint32_t TEFN:1; /*!< bit: 12 Tx Event FIFO New Entry */
- uint32_t TEFW:1; /*!< bit: 13 Tx Event FIFO Watermark Reached */
- uint32_t TEFF:1; /*!< bit: 14 Tx Event FIFO Full */
- uint32_t TEFL:1; /*!< bit: 15 Tx Event FIFO Element Lost */
- uint32_t TSW:1; /*!< bit: 16 Timestamp Wraparound */
- uint32_t MRAF:1; /*!< bit: 17 Message RAM Access Failure */
- uint32_t TOO:1; /*!< bit: 18 Timeout Occurred */
- uint32_t DRX:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer */
- uint32_t BEC:1; /*!< bit: 20 Bit Error Corrected */
- uint32_t BEU:1; /*!< bit: 21 Bit Error Uncorrected */
- uint32_t ELO:1; /*!< bit: 22 Error Logging Overflow */
- uint32_t EP:1; /*!< bit: 23 Error Passive */
- uint32_t EW:1; /*!< bit: 24 Warning Status */
- uint32_t BO:1; /*!< bit: 25 Bus_Off Status */
- uint32_t WDI:1; /*!< bit: 26 Watchdog Interrupt */
- uint32_t PEA:1; /*!< bit: 27 Protocol Error in Arbitration Phase */
- uint32_t PED:1; /*!< bit: 28 Protocol Error in Data Phase */
- uint32_t ARA:1; /*!< bit: 29 Access to Reserved Address */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_IR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_IR_OFFSET 0x50 /**< \brief (CAN_IR offset) Interrupt */
-#define CAN_IR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IR reset_value) Interrupt */
-
-#define CAN_IR_RF0N_Pos 0 /**< \brief (CAN_IR) Rx FIFO 0 New Message */
-#define CAN_IR_RF0N (_U_(0x1) << CAN_IR_RF0N_Pos)
-#define CAN_IR_RF0W_Pos 1 /**< \brief (CAN_IR) Rx FIFO 0 Watermark Reached */
-#define CAN_IR_RF0W (_U_(0x1) << CAN_IR_RF0W_Pos)
-#define CAN_IR_RF0F_Pos 2 /**< \brief (CAN_IR) Rx FIFO 0 Full */
-#define CAN_IR_RF0F (_U_(0x1) << CAN_IR_RF0F_Pos)
-#define CAN_IR_RF0L_Pos 3 /**< \brief (CAN_IR) Rx FIFO 0 Message Lost */
-#define CAN_IR_RF0L (_U_(0x1) << CAN_IR_RF0L_Pos)
-#define CAN_IR_RF1N_Pos 4 /**< \brief (CAN_IR) Rx FIFO 1 New Message */
-#define CAN_IR_RF1N (_U_(0x1) << CAN_IR_RF1N_Pos)
-#define CAN_IR_RF1W_Pos 5 /**< \brief (CAN_IR) Rx FIFO 1 Watermark Reached */
-#define CAN_IR_RF1W (_U_(0x1) << CAN_IR_RF1W_Pos)
-#define CAN_IR_RF1F_Pos 6 /**< \brief (CAN_IR) Rx FIFO 1 FIFO Full */
-#define CAN_IR_RF1F (_U_(0x1) << CAN_IR_RF1F_Pos)
-#define CAN_IR_RF1L_Pos 7 /**< \brief (CAN_IR) Rx FIFO 1 Message Lost */
-#define CAN_IR_RF1L (_U_(0x1) << CAN_IR_RF1L_Pos)
-#define CAN_IR_HPM_Pos 8 /**< \brief (CAN_IR) High Priority Message */
-#define CAN_IR_HPM (_U_(0x1) << CAN_IR_HPM_Pos)
-#define CAN_IR_TC_Pos 9 /**< \brief (CAN_IR) Timestamp Completed */
-#define CAN_IR_TC (_U_(0x1) << CAN_IR_TC_Pos)
-#define CAN_IR_TCF_Pos 10 /**< \brief (CAN_IR) Transmission Cancellation Finished */
-#define CAN_IR_TCF (_U_(0x1) << CAN_IR_TCF_Pos)
-#define CAN_IR_TFE_Pos 11 /**< \brief (CAN_IR) Tx FIFO Empty */
-#define CAN_IR_TFE (_U_(0x1) << CAN_IR_TFE_Pos)
-#define CAN_IR_TEFN_Pos 12 /**< \brief (CAN_IR) Tx Event FIFO New Entry */
-#define CAN_IR_TEFN (_U_(0x1) << CAN_IR_TEFN_Pos)
-#define CAN_IR_TEFW_Pos 13 /**< \brief (CAN_IR) Tx Event FIFO Watermark Reached */
-#define CAN_IR_TEFW (_U_(0x1) << CAN_IR_TEFW_Pos)
-#define CAN_IR_TEFF_Pos 14 /**< \brief (CAN_IR) Tx Event FIFO Full */
-#define CAN_IR_TEFF (_U_(0x1) << CAN_IR_TEFF_Pos)
-#define CAN_IR_TEFL_Pos 15 /**< \brief (CAN_IR) Tx Event FIFO Element Lost */
-#define CAN_IR_TEFL (_U_(0x1) << CAN_IR_TEFL_Pos)
-#define CAN_IR_TSW_Pos 16 /**< \brief (CAN_IR) Timestamp Wraparound */
-#define CAN_IR_TSW (_U_(0x1) << CAN_IR_TSW_Pos)
-#define CAN_IR_MRAF_Pos 17 /**< \brief (CAN_IR) Message RAM Access Failure */
-#define CAN_IR_MRAF (_U_(0x1) << CAN_IR_MRAF_Pos)
-#define CAN_IR_TOO_Pos 18 /**< \brief (CAN_IR) Timeout Occurred */
-#define CAN_IR_TOO (_U_(0x1) << CAN_IR_TOO_Pos)
-#define CAN_IR_DRX_Pos 19 /**< \brief (CAN_IR) Message stored to Dedicated Rx Buffer */
-#define CAN_IR_DRX (_U_(0x1) << CAN_IR_DRX_Pos)
-#define CAN_IR_BEC_Pos 20 /**< \brief (CAN_IR) Bit Error Corrected */
-#define CAN_IR_BEC (_U_(0x1) << CAN_IR_BEC_Pos)
-#define CAN_IR_BEU_Pos 21 /**< \brief (CAN_IR) Bit Error Uncorrected */
-#define CAN_IR_BEU (_U_(0x1) << CAN_IR_BEU_Pos)
-#define CAN_IR_ELO_Pos 22 /**< \brief (CAN_IR) Error Logging Overflow */
-#define CAN_IR_ELO (_U_(0x1) << CAN_IR_ELO_Pos)
-#define CAN_IR_EP_Pos 23 /**< \brief (CAN_IR) Error Passive */
-#define CAN_IR_EP (_U_(0x1) << CAN_IR_EP_Pos)
-#define CAN_IR_EW_Pos 24 /**< \brief (CAN_IR) Warning Status */
-#define CAN_IR_EW (_U_(0x1) << CAN_IR_EW_Pos)
-#define CAN_IR_BO_Pos 25 /**< \brief (CAN_IR) Bus_Off Status */
-#define CAN_IR_BO (_U_(0x1) << CAN_IR_BO_Pos)
-#define CAN_IR_WDI_Pos 26 /**< \brief (CAN_IR) Watchdog Interrupt */
-#define CAN_IR_WDI (_U_(0x1) << CAN_IR_WDI_Pos)
-#define CAN_IR_PEA_Pos 27 /**< \brief (CAN_IR) Protocol Error in Arbitration Phase */
-#define CAN_IR_PEA (_U_(0x1) << CAN_IR_PEA_Pos)
-#define CAN_IR_PED_Pos 28 /**< \brief (CAN_IR) Protocol Error in Data Phase */
-#define CAN_IR_PED (_U_(0x1) << CAN_IR_PED_Pos)
-#define CAN_IR_ARA_Pos 29 /**< \brief (CAN_IR) Access to Reserved Address */
-#define CAN_IR_ARA (_U_(0x1) << CAN_IR_ARA_Pos)
-#define CAN_IR_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IR) MASK Register */
-
-/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RF0NE:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Enable */
- uint32_t RF0WE:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Enable */
- uint32_t RF0FE:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Enable */
- uint32_t RF0LE:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Enable */
- uint32_t RF1NE:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Enable */
- uint32_t RF1WE:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Enable */
- uint32_t RF1FE:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Enable */
- uint32_t RF1LE:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Enable */
- uint32_t HPME:1; /*!< bit: 8 High Priority Message Interrupt Enable */
- uint32_t TCE:1; /*!< bit: 9 Timestamp Completed Interrupt Enable */
- uint32_t TCFE:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Enable */
- uint32_t TFEE:1; /*!< bit: 11 Tx FIFO Empty Interrupt Enable */
- uint32_t TEFNE:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Enable */
- uint32_t TEFWE:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Enable */
- uint32_t TEFFE:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Enable */
- uint32_t TEFLE:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Enable */
- uint32_t TSWE:1; /*!< bit: 16 Timestamp Wraparound Interrupt Enable */
- uint32_t MRAFE:1; /*!< bit: 17 Message RAM Access Failure Interrupt Enable */
- uint32_t TOOE:1; /*!< bit: 18 Timeout Occurred Interrupt Enable */
- uint32_t DRXE:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Enable */
- uint32_t BECE:1; /*!< bit: 20 Bit Error Corrected Interrupt Enable */
- uint32_t BEUE:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Enable */
- uint32_t ELOE:1; /*!< bit: 22 Error Logging Overflow Interrupt Enable */
- uint32_t EPE:1; /*!< bit: 23 Error Passive Interrupt Enable */
- uint32_t EWE:1; /*!< bit: 24 Warning Status Interrupt Enable */
- uint32_t BOE:1; /*!< bit: 25 Bus_Off Status Interrupt Enable */
- uint32_t WDIE:1; /*!< bit: 26 Watchdog Interrupt Interrupt Enable */
- uint32_t PEAE:1; /*!< bit: 27 Protocol Error in Arbitration Phase Enable */
- uint32_t PEDE:1; /*!< bit: 28 Protocol Error in Data Phase Enable */
- uint32_t ARAE:1; /*!< bit: 29 Access to Reserved Address Enable */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_IE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_IE_OFFSET 0x54 /**< \brief (CAN_IE offset) Interrupt Enable */
-#define CAN_IE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IE reset_value) Interrupt Enable */
-
-#define CAN_IE_RF0NE_Pos 0 /**< \brief (CAN_IE) Rx FIFO 0 New Message Interrupt Enable */
-#define CAN_IE_RF0NE (_U_(0x1) << CAN_IE_RF0NE_Pos)
-#define CAN_IE_RF0WE_Pos 1 /**< \brief (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable */
-#define CAN_IE_RF0WE (_U_(0x1) << CAN_IE_RF0WE_Pos)
-#define CAN_IE_RF0FE_Pos 2 /**< \brief (CAN_IE) Rx FIFO 0 Full Interrupt Enable */
-#define CAN_IE_RF0FE (_U_(0x1) << CAN_IE_RF0FE_Pos)
-#define CAN_IE_RF0LE_Pos 3 /**< \brief (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable */
-#define CAN_IE_RF0LE (_U_(0x1) << CAN_IE_RF0LE_Pos)
-#define CAN_IE_RF1NE_Pos 4 /**< \brief (CAN_IE) Rx FIFO 1 New Message Interrupt Enable */
-#define CAN_IE_RF1NE (_U_(0x1) << CAN_IE_RF1NE_Pos)
-#define CAN_IE_RF1WE_Pos 5 /**< \brief (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable */
-#define CAN_IE_RF1WE (_U_(0x1) << CAN_IE_RF1WE_Pos)
-#define CAN_IE_RF1FE_Pos 6 /**< \brief (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable */
-#define CAN_IE_RF1FE (_U_(0x1) << CAN_IE_RF1FE_Pos)
-#define CAN_IE_RF1LE_Pos 7 /**< \brief (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable */
-#define CAN_IE_RF1LE (_U_(0x1) << CAN_IE_RF1LE_Pos)
-#define CAN_IE_HPME_Pos 8 /**< \brief (CAN_IE) High Priority Message Interrupt Enable */
-#define CAN_IE_HPME (_U_(0x1) << CAN_IE_HPME_Pos)
-#define CAN_IE_TCE_Pos 9 /**< \brief (CAN_IE) Timestamp Completed Interrupt Enable */
-#define CAN_IE_TCE (_U_(0x1) << CAN_IE_TCE_Pos)
-#define CAN_IE_TCFE_Pos 10 /**< \brief (CAN_IE) Transmission Cancellation Finished Interrupt Enable */
-#define CAN_IE_TCFE (_U_(0x1) << CAN_IE_TCFE_Pos)
-#define CAN_IE_TFEE_Pos 11 /**< \brief (CAN_IE) Tx FIFO Empty Interrupt Enable */
-#define CAN_IE_TFEE (_U_(0x1) << CAN_IE_TFEE_Pos)
-#define CAN_IE_TEFNE_Pos 12 /**< \brief (CAN_IE) Tx Event FIFO New Entry Interrupt Enable */
-#define CAN_IE_TEFNE (_U_(0x1) << CAN_IE_TEFNE_Pos)
-#define CAN_IE_TEFWE_Pos 13 /**< \brief (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */
-#define CAN_IE_TEFWE (_U_(0x1) << CAN_IE_TEFWE_Pos)
-#define CAN_IE_TEFFE_Pos 14 /**< \brief (CAN_IE) Tx Event FIFO Full Interrupt Enable */
-#define CAN_IE_TEFFE (_U_(0x1) << CAN_IE_TEFFE_Pos)
-#define CAN_IE_TEFLE_Pos 15 /**< \brief (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable */
-#define CAN_IE_TEFLE (_U_(0x1) << CAN_IE_TEFLE_Pos)
-#define CAN_IE_TSWE_Pos 16 /**< \brief (CAN_IE) Timestamp Wraparound Interrupt Enable */
-#define CAN_IE_TSWE (_U_(0x1) << CAN_IE_TSWE_Pos)
-#define CAN_IE_MRAFE_Pos 17 /**< \brief (CAN_IE) Message RAM Access Failure Interrupt Enable */
-#define CAN_IE_MRAFE (_U_(0x1) << CAN_IE_MRAFE_Pos)
-#define CAN_IE_TOOE_Pos 18 /**< \brief (CAN_IE) Timeout Occurred Interrupt Enable */
-#define CAN_IE_TOOE (_U_(0x1) << CAN_IE_TOOE_Pos)
-#define CAN_IE_DRXE_Pos 19 /**< \brief (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable */
-#define CAN_IE_DRXE (_U_(0x1) << CAN_IE_DRXE_Pos)
-#define CAN_IE_BECE_Pos 20 /**< \brief (CAN_IE) Bit Error Corrected Interrupt Enable */
-#define CAN_IE_BECE (_U_(0x1) << CAN_IE_BECE_Pos)
-#define CAN_IE_BEUE_Pos 21 /**< \brief (CAN_IE) Bit Error Uncorrected Interrupt Enable */
-#define CAN_IE_BEUE (_U_(0x1) << CAN_IE_BEUE_Pos)
-#define CAN_IE_ELOE_Pos 22 /**< \brief (CAN_IE) Error Logging Overflow Interrupt Enable */
-#define CAN_IE_ELOE (_U_(0x1) << CAN_IE_ELOE_Pos)
-#define CAN_IE_EPE_Pos 23 /**< \brief (CAN_IE) Error Passive Interrupt Enable */
-#define CAN_IE_EPE (_U_(0x1) << CAN_IE_EPE_Pos)
-#define CAN_IE_EWE_Pos 24 /**< \brief (CAN_IE) Warning Status Interrupt Enable */
-#define CAN_IE_EWE (_U_(0x1) << CAN_IE_EWE_Pos)
-#define CAN_IE_BOE_Pos 25 /**< \brief (CAN_IE) Bus_Off Status Interrupt Enable */
-#define CAN_IE_BOE (_U_(0x1) << CAN_IE_BOE_Pos)
-#define CAN_IE_WDIE_Pos 26 /**< \brief (CAN_IE) Watchdog Interrupt Interrupt Enable */
-#define CAN_IE_WDIE (_U_(0x1) << CAN_IE_WDIE_Pos)
-#define CAN_IE_PEAE_Pos 27 /**< \brief (CAN_IE) Protocol Error in Arbitration Phase Enable */
-#define CAN_IE_PEAE (_U_(0x1) << CAN_IE_PEAE_Pos)
-#define CAN_IE_PEDE_Pos 28 /**< \brief (CAN_IE) Protocol Error in Data Phase Enable */
-#define CAN_IE_PEDE (_U_(0x1) << CAN_IE_PEDE_Pos)
-#define CAN_IE_ARAE_Pos 29 /**< \brief (CAN_IE) Access to Reserved Address Enable */
-#define CAN_IE_ARAE (_U_(0x1) << CAN_IE_ARAE_Pos)
-#define CAN_IE_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IE) MASK Register */
-
-/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RF0NL:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Line */
- uint32_t RF0WL:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Line */
- uint32_t RF0FL:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Line */
- uint32_t RF0LL:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Line */
- uint32_t RF1NL:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Line */
- uint32_t RF1WL:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Line */
- uint32_t RF1FL:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Line */
- uint32_t RF1LL:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Line */
- uint32_t HPML:1; /*!< bit: 8 High Priority Message Interrupt Line */
- uint32_t TCL:1; /*!< bit: 9 Timestamp Completed Interrupt Line */
- uint32_t TCFL:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Line */
- uint32_t TFEL:1; /*!< bit: 11 Tx FIFO Empty Interrupt Line */
- uint32_t TEFNL:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Line */
- uint32_t TEFWL:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Line */
- uint32_t TEFFL:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Line */
- uint32_t TEFLL:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Line */
- uint32_t TSWL:1; /*!< bit: 16 Timestamp Wraparound Interrupt Line */
- uint32_t MRAFL:1; /*!< bit: 17 Message RAM Access Failure Interrupt Line */
- uint32_t TOOL:1; /*!< bit: 18 Timeout Occurred Interrupt Line */
- uint32_t DRXL:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Line */
- uint32_t BECL:1; /*!< bit: 20 Bit Error Corrected Interrupt Line */
- uint32_t BEUL:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Line */
- uint32_t ELOL:1; /*!< bit: 22 Error Logging Overflow Interrupt Line */
- uint32_t EPL:1; /*!< bit: 23 Error Passive Interrupt Line */
- uint32_t EWL:1; /*!< bit: 24 Warning Status Interrupt Line */
- uint32_t BOL:1; /*!< bit: 25 Bus_Off Status Interrupt Line */
- uint32_t WDIL:1; /*!< bit: 26 Watchdog Interrupt Interrupt Line */
- uint32_t PEAL:1; /*!< bit: 27 Protocol Error in Arbitration Phase Line */
- uint32_t PEDL:1; /*!< bit: 28 Protocol Error in Data Phase Line */
- uint32_t ARAL:1; /*!< bit: 29 Access to Reserved Address Line */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_ILS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_ILS_OFFSET 0x58 /**< \brief (CAN_ILS offset) Interrupt Line Select */
-#define CAN_ILS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILS reset_value) Interrupt Line Select */
-
-#define CAN_ILS_RF0NL_Pos 0 /**< \brief (CAN_ILS) Rx FIFO 0 New Message Interrupt Line */
-#define CAN_ILS_RF0NL (_U_(0x1) << CAN_ILS_RF0NL_Pos)
-#define CAN_ILS_RF0WL_Pos 1 /**< \brief (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line */
-#define CAN_ILS_RF0WL (_U_(0x1) << CAN_ILS_RF0WL_Pos)
-#define CAN_ILS_RF0FL_Pos 2 /**< \brief (CAN_ILS) Rx FIFO 0 Full Interrupt Line */
-#define CAN_ILS_RF0FL (_U_(0x1) << CAN_ILS_RF0FL_Pos)
-#define CAN_ILS_RF0LL_Pos 3 /**< \brief (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line */
-#define CAN_ILS_RF0LL (_U_(0x1) << CAN_ILS_RF0LL_Pos)
-#define CAN_ILS_RF1NL_Pos 4 /**< \brief (CAN_ILS) Rx FIFO 1 New Message Interrupt Line */
-#define CAN_ILS_RF1NL (_U_(0x1) << CAN_ILS_RF1NL_Pos)
-#define CAN_ILS_RF1WL_Pos 5 /**< \brief (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line */
-#define CAN_ILS_RF1WL (_U_(0x1) << CAN_ILS_RF1WL_Pos)
-#define CAN_ILS_RF1FL_Pos 6 /**< \brief (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line */
-#define CAN_ILS_RF1FL (_U_(0x1) << CAN_ILS_RF1FL_Pos)
-#define CAN_ILS_RF1LL_Pos 7 /**< \brief (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line */
-#define CAN_ILS_RF1LL (_U_(0x1) << CAN_ILS_RF1LL_Pos)
-#define CAN_ILS_HPML_Pos 8 /**< \brief (CAN_ILS) High Priority Message Interrupt Line */
-#define CAN_ILS_HPML (_U_(0x1) << CAN_ILS_HPML_Pos)
-#define CAN_ILS_TCL_Pos 9 /**< \brief (CAN_ILS) Timestamp Completed Interrupt Line */
-#define CAN_ILS_TCL (_U_(0x1) << CAN_ILS_TCL_Pos)
-#define CAN_ILS_TCFL_Pos 10 /**< \brief (CAN_ILS) Transmission Cancellation Finished Interrupt Line */
-#define CAN_ILS_TCFL (_U_(0x1) << CAN_ILS_TCFL_Pos)
-#define CAN_ILS_TFEL_Pos 11 /**< \brief (CAN_ILS) Tx FIFO Empty Interrupt Line */
-#define CAN_ILS_TFEL (_U_(0x1) << CAN_ILS_TFEL_Pos)
-#define CAN_ILS_TEFNL_Pos 12 /**< \brief (CAN_ILS) Tx Event FIFO New Entry Interrupt Line */
-#define CAN_ILS_TEFNL (_U_(0x1) << CAN_ILS_TEFNL_Pos)
-#define CAN_ILS_TEFWL_Pos 13 /**< \brief (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */
-#define CAN_ILS_TEFWL (_U_(0x1) << CAN_ILS_TEFWL_Pos)
-#define CAN_ILS_TEFFL_Pos 14 /**< \brief (CAN_ILS) Tx Event FIFO Full Interrupt Line */
-#define CAN_ILS_TEFFL (_U_(0x1) << CAN_ILS_TEFFL_Pos)
-#define CAN_ILS_TEFLL_Pos 15 /**< \brief (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line */
-#define CAN_ILS_TEFLL (_U_(0x1) << CAN_ILS_TEFLL_Pos)
-#define CAN_ILS_TSWL_Pos 16 /**< \brief (CAN_ILS) Timestamp Wraparound Interrupt Line */
-#define CAN_ILS_TSWL (_U_(0x1) << CAN_ILS_TSWL_Pos)
-#define CAN_ILS_MRAFL_Pos 17 /**< \brief (CAN_ILS) Message RAM Access Failure Interrupt Line */
-#define CAN_ILS_MRAFL (_U_(0x1) << CAN_ILS_MRAFL_Pos)
-#define CAN_ILS_TOOL_Pos 18 /**< \brief (CAN_ILS) Timeout Occurred Interrupt Line */
-#define CAN_ILS_TOOL (_U_(0x1) << CAN_ILS_TOOL_Pos)
-#define CAN_ILS_DRXL_Pos 19 /**< \brief (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line */
-#define CAN_ILS_DRXL (_U_(0x1) << CAN_ILS_DRXL_Pos)
-#define CAN_ILS_BECL_Pos 20 /**< \brief (CAN_ILS) Bit Error Corrected Interrupt Line */
-#define CAN_ILS_BECL (_U_(0x1) << CAN_ILS_BECL_Pos)
-#define CAN_ILS_BEUL_Pos 21 /**< \brief (CAN_ILS) Bit Error Uncorrected Interrupt Line */
-#define CAN_ILS_BEUL (_U_(0x1) << CAN_ILS_BEUL_Pos)
-#define CAN_ILS_ELOL_Pos 22 /**< \brief (CAN_ILS) Error Logging Overflow Interrupt Line */
-#define CAN_ILS_ELOL (_U_(0x1) << CAN_ILS_ELOL_Pos)
-#define CAN_ILS_EPL_Pos 23 /**< \brief (CAN_ILS) Error Passive Interrupt Line */
-#define CAN_ILS_EPL (_U_(0x1) << CAN_ILS_EPL_Pos)
-#define CAN_ILS_EWL_Pos 24 /**< \brief (CAN_ILS) Warning Status Interrupt Line */
-#define CAN_ILS_EWL (_U_(0x1) << CAN_ILS_EWL_Pos)
-#define CAN_ILS_BOL_Pos 25 /**< \brief (CAN_ILS) Bus_Off Status Interrupt Line */
-#define CAN_ILS_BOL (_U_(0x1) << CAN_ILS_BOL_Pos)
-#define CAN_ILS_WDIL_Pos 26 /**< \brief (CAN_ILS) Watchdog Interrupt Interrupt Line */
-#define CAN_ILS_WDIL (_U_(0x1) << CAN_ILS_WDIL_Pos)
-#define CAN_ILS_PEAL_Pos 27 /**< \brief (CAN_ILS) Protocol Error in Arbitration Phase Line */
-#define CAN_ILS_PEAL (_U_(0x1) << CAN_ILS_PEAL_Pos)
-#define CAN_ILS_PEDL_Pos 28 /**< \brief (CAN_ILS) Protocol Error in Data Phase Line */
-#define CAN_ILS_PEDL (_U_(0x1) << CAN_ILS_PEDL_Pos)
-#define CAN_ILS_ARAL_Pos 29 /**< \brief (CAN_ILS) Access to Reserved Address Line */
-#define CAN_ILS_ARAL (_U_(0x1) << CAN_ILS_ARAL_Pos)
-#define CAN_ILS_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_ILS) MASK Register */
-
-/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EINT0:1; /*!< bit: 0 Enable Interrupt Line 0 */
- uint32_t EINT1:1; /*!< bit: 1 Enable Interrupt Line 1 */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_ILE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_ILE_OFFSET 0x5C /**< \brief (CAN_ILE offset) Interrupt Line Enable */
-#define CAN_ILE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILE reset_value) Interrupt Line Enable */
-
-#define CAN_ILE_EINT0_Pos 0 /**< \brief (CAN_ILE) Enable Interrupt Line 0 */
-#define CAN_ILE_EINT0 (_U_(0x1) << CAN_ILE_EINT0_Pos)
-#define CAN_ILE_EINT1_Pos 1 /**< \brief (CAN_ILE) Enable Interrupt Line 1 */
-#define CAN_ILE_EINT1 (_U_(0x1) << CAN_ILE_EINT1_Pos)
-#define CAN_ILE_MASK _U_(0x00000003) /**< \brief (CAN_ILE) MASK Register */
-
-/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RRFE:1; /*!< bit: 0 Reject Remote Frames Extended */
- uint32_t RRFS:1; /*!< bit: 1 Reject Remote Frames Standard */
- uint32_t ANFE:2; /*!< bit: 2.. 3 Accept Non-matching Frames Extended */
- uint32_t ANFS:2; /*!< bit: 4.. 5 Accept Non-matching Frames Standard */
- uint32_t :26; /*!< bit: 6..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_GFC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_GFC_OFFSET 0x80 /**< \brief (CAN_GFC offset) Global Filter Configuration */
-#define CAN_GFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_GFC reset_value) Global Filter Configuration */
-
-#define CAN_GFC_RRFE_Pos 0 /**< \brief (CAN_GFC) Reject Remote Frames Extended */
-#define CAN_GFC_RRFE (_U_(0x1) << CAN_GFC_RRFE_Pos)
-#define CAN_GFC_RRFS_Pos 1 /**< \brief (CAN_GFC) Reject Remote Frames Standard */
-#define CAN_GFC_RRFS (_U_(0x1) << CAN_GFC_RRFS_Pos)
-#define CAN_GFC_ANFE_Pos 2 /**< \brief (CAN_GFC) Accept Non-matching Frames Extended */
-#define CAN_GFC_ANFE_Msk (_U_(0x3) << CAN_GFC_ANFE_Pos)
-#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & ((value) << CAN_GFC_ANFE_Pos))
-#define CAN_GFC_ANFE_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */
-#define CAN_GFC_ANFE_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */
-#define CAN_GFC_ANFE_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */
-#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos)
-#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos)
-#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos)
-#define CAN_GFC_ANFS_Pos 4 /**< \brief (CAN_GFC) Accept Non-matching Frames Standard */
-#define CAN_GFC_ANFS_Msk (_U_(0x3) << CAN_GFC_ANFS_Pos)
-#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & ((value) << CAN_GFC_ANFS_Pos))
-#define CAN_GFC_ANFS_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */
-#define CAN_GFC_ANFS_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */
-#define CAN_GFC_ANFS_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */
-#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos)
-#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos)
-#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos)
-#define CAN_GFC_MASK _U_(0x0000003F) /**< \brief (CAN_GFC) MASK Register */
-
-/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t FLSSA:16; /*!< bit: 0..15 Filter List Standard Start Address */
- uint32_t LSS:8; /*!< bit: 16..23 List Size Standard */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_SIDFC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_SIDFC_OFFSET 0x84 /**< \brief (CAN_SIDFC offset) Standard ID Filter Configuration */
-#define CAN_SIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFC reset_value) Standard ID Filter Configuration */
-
-#define CAN_SIDFC_FLSSA_Pos 0 /**< \brief (CAN_SIDFC) Filter List Standard Start Address */
-#define CAN_SIDFC_FLSSA_Msk (_U_(0xFFFF) << CAN_SIDFC_FLSSA_Pos)
-#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & ((value) << CAN_SIDFC_FLSSA_Pos))
-#define CAN_SIDFC_LSS_Pos 16 /**< \brief (CAN_SIDFC) List Size Standard */
-#define CAN_SIDFC_LSS_Msk (_U_(0xFF) << CAN_SIDFC_LSS_Pos)
-#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & ((value) << CAN_SIDFC_LSS_Pos))
-#define CAN_SIDFC_MASK _U_(0x00FFFFFF) /**< \brief (CAN_SIDFC) MASK Register */
-
-/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t FLESA:16; /*!< bit: 0..15 Filter List Extended Start Address */
- uint32_t LSE:7; /*!< bit: 16..22 List Size Extended */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_XIDFC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_XIDFC_OFFSET 0x88 /**< \brief (CAN_XIDFC offset) Extended ID Filter Configuration */
-#define CAN_XIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFC reset_value) Extended ID Filter Configuration */
-
-#define CAN_XIDFC_FLESA_Pos 0 /**< \brief (CAN_XIDFC) Filter List Extended Start Address */
-#define CAN_XIDFC_FLESA_Msk (_U_(0xFFFF) << CAN_XIDFC_FLESA_Pos)
-#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & ((value) << CAN_XIDFC_FLESA_Pos))
-#define CAN_XIDFC_LSE_Pos 16 /**< \brief (CAN_XIDFC) List Size Extended */
-#define CAN_XIDFC_LSE_Msk (_U_(0x7F) << CAN_XIDFC_LSE_Pos)
-#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & ((value) << CAN_XIDFC_LSE_Pos))
-#define CAN_XIDFC_MASK _U_(0x007FFFFF) /**< \brief (CAN_XIDFC) MASK Register */
-
-/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EIDM:29; /*!< bit: 0..28 Extended ID Mask */
- uint32_t :3; /*!< bit: 29..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_XIDAM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_XIDAM_OFFSET 0x90 /**< \brief (CAN_XIDAM offset) Extended ID AND Mask */
-#define CAN_XIDAM_RESETVALUE _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM reset_value) Extended ID AND Mask */
-
-#define CAN_XIDAM_EIDM_Pos 0 /**< \brief (CAN_XIDAM) Extended ID Mask */
-#define CAN_XIDAM_EIDM_Msk (_U_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos)
-#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & ((value) << CAN_XIDAM_EIDM_Pos))
-#define CAN_XIDAM_MASK _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM) MASK Register */
-
-/* -------- CAN_HPMS : (CAN Offset: 0x94) (R/ 32) High Priority Message Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t BIDX:6; /*!< bit: 0.. 5 Buffer Index */
- uint32_t MSI:2; /*!< bit: 6.. 7 Message Storage Indicator */
- uint32_t FIDX:7; /*!< bit: 8..14 Filter Index */
- uint32_t FLST:1; /*!< bit: 15 Filter List */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_HPMS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_HPMS_OFFSET 0x94 /**< \brief (CAN_HPMS offset) High Priority Message Status */
-#define CAN_HPMS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_HPMS reset_value) High Priority Message Status */
-
-#define CAN_HPMS_BIDX_Pos 0 /**< \brief (CAN_HPMS) Buffer Index */
-#define CAN_HPMS_BIDX_Msk (_U_(0x3F) << CAN_HPMS_BIDX_Pos)
-#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & ((value) << CAN_HPMS_BIDX_Pos))
-#define CAN_HPMS_MSI_Pos 6 /**< \brief (CAN_HPMS) Message Storage Indicator */
-#define CAN_HPMS_MSI_Msk (_U_(0x3) << CAN_HPMS_MSI_Pos)
-#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & ((value) << CAN_HPMS_MSI_Pos))
-#define CAN_HPMS_MSI_NONE_Val _U_(0x0) /**< \brief (CAN_HPMS) No FIFO selected */
-#define CAN_HPMS_MSI_LOST_Val _U_(0x1) /**< \brief (CAN_HPMS) FIFO message lost */
-#define CAN_HPMS_MSI_FIFO0_Val _U_(0x2) /**< \brief (CAN_HPMS) Message stored in FIFO 0 */
-#define CAN_HPMS_MSI_FIFO1_Val _U_(0x3) /**< \brief (CAN_HPMS) Message stored in FIFO 1 */
-#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos)
-#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos)
-#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos)
-#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos)
-#define CAN_HPMS_FIDX_Pos 8 /**< \brief (CAN_HPMS) Filter Index */
-#define CAN_HPMS_FIDX_Msk (_U_(0x7F) << CAN_HPMS_FIDX_Pos)
-#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & ((value) << CAN_HPMS_FIDX_Pos))
-#define CAN_HPMS_FLST_Pos 15 /**< \brief (CAN_HPMS) Filter List */
-#define CAN_HPMS_FLST (_U_(0x1) << CAN_HPMS_FLST_Pos)
-#define CAN_HPMS_MASK _U_(0x0000FFFF) /**< \brief (CAN_HPMS) MASK Register */
-
-/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ND0:1; /*!< bit: 0 New Data 0 */
- uint32_t ND1:1; /*!< bit: 1 New Data 1 */
- uint32_t ND2:1; /*!< bit: 2 New Data 2 */
- uint32_t ND3:1; /*!< bit: 3 New Data 3 */
- uint32_t ND4:1; /*!< bit: 4 New Data 4 */
- uint32_t ND5:1; /*!< bit: 5 New Data 5 */
- uint32_t ND6:1; /*!< bit: 6 New Data 6 */
- uint32_t ND7:1; /*!< bit: 7 New Data 7 */
- uint32_t ND8:1; /*!< bit: 8 New Data 8 */
- uint32_t ND9:1; /*!< bit: 9 New Data 9 */
- uint32_t ND10:1; /*!< bit: 10 New Data 10 */
- uint32_t ND11:1; /*!< bit: 11 New Data 11 */
- uint32_t ND12:1; /*!< bit: 12 New Data 12 */
- uint32_t ND13:1; /*!< bit: 13 New Data 13 */
- uint32_t ND14:1; /*!< bit: 14 New Data 14 */
- uint32_t ND15:1; /*!< bit: 15 New Data 15 */
- uint32_t ND16:1; /*!< bit: 16 New Data 16 */
- uint32_t ND17:1; /*!< bit: 17 New Data 17 */
- uint32_t ND18:1; /*!< bit: 18 New Data 18 */
- uint32_t ND19:1; /*!< bit: 19 New Data 19 */
- uint32_t ND20:1; /*!< bit: 20 New Data 20 */
- uint32_t ND21:1; /*!< bit: 21 New Data 21 */
- uint32_t ND22:1; /*!< bit: 22 New Data 22 */
- uint32_t ND23:1; /*!< bit: 23 New Data 23 */
- uint32_t ND24:1; /*!< bit: 24 New Data 24 */
- uint32_t ND25:1; /*!< bit: 25 New Data 25 */
- uint32_t ND26:1; /*!< bit: 26 New Data 26 */
- uint32_t ND27:1; /*!< bit: 27 New Data 27 */
- uint32_t ND28:1; /*!< bit: 28 New Data 28 */
- uint32_t ND29:1; /*!< bit: 29 New Data 29 */
- uint32_t ND30:1; /*!< bit: 30 New Data 30 */
- uint32_t ND31:1; /*!< bit: 31 New Data 31 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_NDAT1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_NDAT1_OFFSET 0x98 /**< \brief (CAN_NDAT1 offset) New Data 1 */
-#define CAN_NDAT1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_NDAT1 reset_value) New Data 1 */
-
-#define CAN_NDAT1_ND0_Pos 0 /**< \brief (CAN_NDAT1) New Data 0 */
-#define CAN_NDAT1_ND0 (_U_(0x1) << CAN_NDAT1_ND0_Pos)
-#define CAN_NDAT1_ND1_Pos 1 /**< \brief (CAN_NDAT1) New Data 1 */
-#define CAN_NDAT1_ND1 (_U_(0x1) << CAN_NDAT1_ND1_Pos)
-#define CAN_NDAT1_ND2_Pos 2 /**< \brief (CAN_NDAT1) New Data 2 */
-#define CAN_NDAT1_ND2 (_U_(0x1) << CAN_NDAT1_ND2_Pos)
-#define CAN_NDAT1_ND3_Pos 3 /**< \brief (CAN_NDAT1) New Data 3 */
-#define CAN_NDAT1_ND3 (_U_(0x1) << CAN_NDAT1_ND3_Pos)
-#define CAN_NDAT1_ND4_Pos 4 /**< \brief (CAN_NDAT1) New Data 4 */
-#define CAN_NDAT1_ND4 (_U_(0x1) << CAN_NDAT1_ND4_Pos)
-#define CAN_NDAT1_ND5_Pos 5 /**< \brief (CAN_NDAT1) New Data 5 */
-#define CAN_NDAT1_ND5 (_U_(0x1) << CAN_NDAT1_ND5_Pos)
-#define CAN_NDAT1_ND6_Pos 6 /**< \brief (CAN_NDAT1) New Data 6 */
-#define CAN_NDAT1_ND6 (_U_(0x1) << CAN_NDAT1_ND6_Pos)
-#define CAN_NDAT1_ND7_Pos 7 /**< \brief (CAN_NDAT1) New Data 7 */
-#define CAN_NDAT1_ND7 (_U_(0x1) << CAN_NDAT1_ND7_Pos)
-#define CAN_NDAT1_ND8_Pos 8 /**< \brief (CAN_NDAT1) New Data 8 */
-#define CAN_NDAT1_ND8 (_U_(0x1) << CAN_NDAT1_ND8_Pos)
-#define CAN_NDAT1_ND9_Pos 9 /**< \brief (CAN_NDAT1) New Data 9 */
-#define CAN_NDAT1_ND9 (_U_(0x1) << CAN_NDAT1_ND9_Pos)
-#define CAN_NDAT1_ND10_Pos 10 /**< \brief (CAN_NDAT1) New Data 10 */
-#define CAN_NDAT1_ND10 (_U_(0x1) << CAN_NDAT1_ND10_Pos)
-#define CAN_NDAT1_ND11_Pos 11 /**< \brief (CAN_NDAT1) New Data 11 */
-#define CAN_NDAT1_ND11 (_U_(0x1) << CAN_NDAT1_ND11_Pos)
-#define CAN_NDAT1_ND12_Pos 12 /**< \brief (CAN_NDAT1) New Data 12 */
-#define CAN_NDAT1_ND12 (_U_(0x1) << CAN_NDAT1_ND12_Pos)
-#define CAN_NDAT1_ND13_Pos 13 /**< \brief (CAN_NDAT1) New Data 13 */
-#define CAN_NDAT1_ND13 (_U_(0x1) << CAN_NDAT1_ND13_Pos)
-#define CAN_NDAT1_ND14_Pos 14 /**< \brief (CAN_NDAT1) New Data 14 */
-#define CAN_NDAT1_ND14 (_U_(0x1) << CAN_NDAT1_ND14_Pos)
-#define CAN_NDAT1_ND15_Pos 15 /**< \brief (CAN_NDAT1) New Data 15 */
-#define CAN_NDAT1_ND15 (_U_(0x1) << CAN_NDAT1_ND15_Pos)
-#define CAN_NDAT1_ND16_Pos 16 /**< \brief (CAN_NDAT1) New Data 16 */
-#define CAN_NDAT1_ND16 (_U_(0x1) << CAN_NDAT1_ND16_Pos)
-#define CAN_NDAT1_ND17_Pos 17 /**< \brief (CAN_NDAT1) New Data 17 */
-#define CAN_NDAT1_ND17 (_U_(0x1) << CAN_NDAT1_ND17_Pos)
-#define CAN_NDAT1_ND18_Pos 18 /**< \brief (CAN_NDAT1) New Data 18 */
-#define CAN_NDAT1_ND18 (_U_(0x1) << CAN_NDAT1_ND18_Pos)
-#define CAN_NDAT1_ND19_Pos 19 /**< \brief (CAN_NDAT1) New Data 19 */
-#define CAN_NDAT1_ND19 (_U_(0x1) << CAN_NDAT1_ND19_Pos)
-#define CAN_NDAT1_ND20_Pos 20 /**< \brief (CAN_NDAT1) New Data 20 */
-#define CAN_NDAT1_ND20 (_U_(0x1) << CAN_NDAT1_ND20_Pos)
-#define CAN_NDAT1_ND21_Pos 21 /**< \brief (CAN_NDAT1) New Data 21 */
-#define CAN_NDAT1_ND21 (_U_(0x1) << CAN_NDAT1_ND21_Pos)
-#define CAN_NDAT1_ND22_Pos 22 /**< \brief (CAN_NDAT1) New Data 22 */
-#define CAN_NDAT1_ND22 (_U_(0x1) << CAN_NDAT1_ND22_Pos)
-#define CAN_NDAT1_ND23_Pos 23 /**< \brief (CAN_NDAT1) New Data 23 */
-#define CAN_NDAT1_ND23 (_U_(0x1) << CAN_NDAT1_ND23_Pos)
-#define CAN_NDAT1_ND24_Pos 24 /**< \brief (CAN_NDAT1) New Data 24 */
-#define CAN_NDAT1_ND24 (_U_(0x1) << CAN_NDAT1_ND24_Pos)
-#define CAN_NDAT1_ND25_Pos 25 /**< \brief (CAN_NDAT1) New Data 25 */
-#define CAN_NDAT1_ND25 (_U_(0x1) << CAN_NDAT1_ND25_Pos)
-#define CAN_NDAT1_ND26_Pos 26 /**< \brief (CAN_NDAT1) New Data 26 */
-#define CAN_NDAT1_ND26 (_U_(0x1) << CAN_NDAT1_ND26_Pos)
-#define CAN_NDAT1_ND27_Pos 27 /**< \brief (CAN_NDAT1) New Data 27 */
-#define CAN_NDAT1_ND27 (_U_(0x1) << CAN_NDAT1_ND27_Pos)
-#define CAN_NDAT1_ND28_Pos 28 /**< \brief (CAN_NDAT1) New Data 28 */
-#define CAN_NDAT1_ND28 (_U_(0x1) << CAN_NDAT1_ND28_Pos)
-#define CAN_NDAT1_ND29_Pos 29 /**< \brief (CAN_NDAT1) New Data 29 */
-#define CAN_NDAT1_ND29 (_U_(0x1) << CAN_NDAT1_ND29_Pos)
-#define CAN_NDAT1_ND30_Pos 30 /**< \brief (CAN_NDAT1) New Data 30 */
-#define CAN_NDAT1_ND30 (_U_(0x1) << CAN_NDAT1_ND30_Pos)
-#define CAN_NDAT1_ND31_Pos 31 /**< \brief (CAN_NDAT1) New Data 31 */
-#define CAN_NDAT1_ND31 (_U_(0x1) << CAN_NDAT1_ND31_Pos)
-#define CAN_NDAT1_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_NDAT1) MASK Register */
-
-/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ND32:1; /*!< bit: 0 New Data 32 */
- uint32_t ND33:1; /*!< bit: 1 New Data 33 */
- uint32_t ND34:1; /*!< bit: 2 New Data 34 */
- uint32_t ND35:1; /*!< bit: 3 New Data 35 */
- uint32_t ND36:1; /*!< bit: 4 New Data 36 */
- uint32_t ND37:1; /*!< bit: 5 New Data 37 */
- uint32_t ND38:1; /*!< bit: 6 New Data 38 */
- uint32_t ND39:1; /*!< bit: 7 New Data 39 */
- uint32_t ND40:1; /*!< bit: 8 New Data 40 */
- uint32_t ND41:1; /*!< bit: 9 New Data 41 */
- uint32_t ND42:1; /*!< bit: 10 New Data 42 */
- uint32_t ND43:1; /*!< bit: 11 New Data 43 */
- uint32_t ND44:1; /*!< bit: 12 New Data 44 */
- uint32_t ND45:1; /*!< bit: 13 New Data 45 */
- uint32_t ND46:1; /*!< bit: 14 New Data 46 */
- uint32_t ND47:1; /*!< bit: 15 New Data 47 */
- uint32_t ND48:1; /*!< bit: 16 New Data 48 */
- uint32_t ND49:1; /*!< bit: 17 New Data 49 */
- uint32_t ND50:1; /*!< bit: 18 New Data 50 */
- uint32_t ND51:1; /*!< bit: 19 New Data 51 */
- uint32_t ND52:1; /*!< bit: 20 New Data 52 */
- uint32_t ND53:1; /*!< bit: 21 New Data 53 */
- uint32_t ND54:1; /*!< bit: 22 New Data 54 */
- uint32_t ND55:1; /*!< bit: 23 New Data 55 */
- uint32_t ND56:1; /*!< bit: 24 New Data 56 */
- uint32_t ND57:1; /*!< bit: 25 New Data 57 */
- uint32_t ND58:1; /*!< bit: 26 New Data 58 */
- uint32_t ND59:1; /*!< bit: 27 New Data 59 */
- uint32_t ND60:1; /*!< bit: 28 New Data 60 */
- uint32_t ND61:1; /*!< bit: 29 New Data 61 */
- uint32_t ND62:1; /*!< bit: 30 New Data 62 */
- uint32_t ND63:1; /*!< bit: 31 New Data 63 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_NDAT2_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_NDAT2_OFFSET 0x9C /**< \brief (CAN_NDAT2 offset) New Data 2 */
-#define CAN_NDAT2_RESETVALUE _U_(0x00000000) /**< \brief (CAN_NDAT2 reset_value) New Data 2 */
-
-#define CAN_NDAT2_ND32_Pos 0 /**< \brief (CAN_NDAT2) New Data 32 */
-#define CAN_NDAT2_ND32 (_U_(0x1) << CAN_NDAT2_ND32_Pos)
-#define CAN_NDAT2_ND33_Pos 1 /**< \brief (CAN_NDAT2) New Data 33 */
-#define CAN_NDAT2_ND33 (_U_(0x1) << CAN_NDAT2_ND33_Pos)
-#define CAN_NDAT2_ND34_Pos 2 /**< \brief (CAN_NDAT2) New Data 34 */
-#define CAN_NDAT2_ND34 (_U_(0x1) << CAN_NDAT2_ND34_Pos)
-#define CAN_NDAT2_ND35_Pos 3 /**< \brief (CAN_NDAT2) New Data 35 */
-#define CAN_NDAT2_ND35 (_U_(0x1) << CAN_NDAT2_ND35_Pos)
-#define CAN_NDAT2_ND36_Pos 4 /**< \brief (CAN_NDAT2) New Data 36 */
-#define CAN_NDAT2_ND36 (_U_(0x1) << CAN_NDAT2_ND36_Pos)
-#define CAN_NDAT2_ND37_Pos 5 /**< \brief (CAN_NDAT2) New Data 37 */
-#define CAN_NDAT2_ND37 (_U_(0x1) << CAN_NDAT2_ND37_Pos)
-#define CAN_NDAT2_ND38_Pos 6 /**< \brief (CAN_NDAT2) New Data 38 */
-#define CAN_NDAT2_ND38 (_U_(0x1) << CAN_NDAT2_ND38_Pos)
-#define CAN_NDAT2_ND39_Pos 7 /**< \brief (CAN_NDAT2) New Data 39 */
-#define CAN_NDAT2_ND39 (_U_(0x1) << CAN_NDAT2_ND39_Pos)
-#define CAN_NDAT2_ND40_Pos 8 /**< \brief (CAN_NDAT2) New Data 40 */
-#define CAN_NDAT2_ND40 (_U_(0x1) << CAN_NDAT2_ND40_Pos)
-#define CAN_NDAT2_ND41_Pos 9 /**< \brief (CAN_NDAT2) New Data 41 */
-#define CAN_NDAT2_ND41 (_U_(0x1) << CAN_NDAT2_ND41_Pos)
-#define CAN_NDAT2_ND42_Pos 10 /**< \brief (CAN_NDAT2) New Data 42 */
-#define CAN_NDAT2_ND42 (_U_(0x1) << CAN_NDAT2_ND42_Pos)
-#define CAN_NDAT2_ND43_Pos 11 /**< \brief (CAN_NDAT2) New Data 43 */
-#define CAN_NDAT2_ND43 (_U_(0x1) << CAN_NDAT2_ND43_Pos)
-#define CAN_NDAT2_ND44_Pos 12 /**< \brief (CAN_NDAT2) New Data 44 */
-#define CAN_NDAT2_ND44 (_U_(0x1) << CAN_NDAT2_ND44_Pos)
-#define CAN_NDAT2_ND45_Pos 13 /**< \brief (CAN_NDAT2) New Data 45 */
-#define CAN_NDAT2_ND45 (_U_(0x1) << CAN_NDAT2_ND45_Pos)
-#define CAN_NDAT2_ND46_Pos 14 /**< \brief (CAN_NDAT2) New Data 46 */
-#define CAN_NDAT2_ND46 (_U_(0x1) << CAN_NDAT2_ND46_Pos)
-#define CAN_NDAT2_ND47_Pos 15 /**< \brief (CAN_NDAT2) New Data 47 */
-#define CAN_NDAT2_ND47 (_U_(0x1) << CAN_NDAT2_ND47_Pos)
-#define CAN_NDAT2_ND48_Pos 16 /**< \brief (CAN_NDAT2) New Data 48 */
-#define CAN_NDAT2_ND48 (_U_(0x1) << CAN_NDAT2_ND48_Pos)
-#define CAN_NDAT2_ND49_Pos 17 /**< \brief (CAN_NDAT2) New Data 49 */
-#define CAN_NDAT2_ND49 (_U_(0x1) << CAN_NDAT2_ND49_Pos)
-#define CAN_NDAT2_ND50_Pos 18 /**< \brief (CAN_NDAT2) New Data 50 */
-#define CAN_NDAT2_ND50 (_U_(0x1) << CAN_NDAT2_ND50_Pos)
-#define CAN_NDAT2_ND51_Pos 19 /**< \brief (CAN_NDAT2) New Data 51 */
-#define CAN_NDAT2_ND51 (_U_(0x1) << CAN_NDAT2_ND51_Pos)
-#define CAN_NDAT2_ND52_Pos 20 /**< \brief (CAN_NDAT2) New Data 52 */
-#define CAN_NDAT2_ND52 (_U_(0x1) << CAN_NDAT2_ND52_Pos)
-#define CAN_NDAT2_ND53_Pos 21 /**< \brief (CAN_NDAT2) New Data 53 */
-#define CAN_NDAT2_ND53 (_U_(0x1) << CAN_NDAT2_ND53_Pos)
-#define CAN_NDAT2_ND54_Pos 22 /**< \brief (CAN_NDAT2) New Data 54 */
-#define CAN_NDAT2_ND54 (_U_(0x1) << CAN_NDAT2_ND54_Pos)
-#define CAN_NDAT2_ND55_Pos 23 /**< \brief (CAN_NDAT2) New Data 55 */
-#define CAN_NDAT2_ND55 (_U_(0x1) << CAN_NDAT2_ND55_Pos)
-#define CAN_NDAT2_ND56_Pos 24 /**< \brief (CAN_NDAT2) New Data 56 */
-#define CAN_NDAT2_ND56 (_U_(0x1) << CAN_NDAT2_ND56_Pos)
-#define CAN_NDAT2_ND57_Pos 25 /**< \brief (CAN_NDAT2) New Data 57 */
-#define CAN_NDAT2_ND57 (_U_(0x1) << CAN_NDAT2_ND57_Pos)
-#define CAN_NDAT2_ND58_Pos 26 /**< \brief (CAN_NDAT2) New Data 58 */
-#define CAN_NDAT2_ND58 (_U_(0x1) << CAN_NDAT2_ND58_Pos)
-#define CAN_NDAT2_ND59_Pos 27 /**< \brief (CAN_NDAT2) New Data 59 */
-#define CAN_NDAT2_ND59 (_U_(0x1) << CAN_NDAT2_ND59_Pos)
-#define CAN_NDAT2_ND60_Pos 28 /**< \brief (CAN_NDAT2) New Data 60 */
-#define CAN_NDAT2_ND60 (_U_(0x1) << CAN_NDAT2_ND60_Pos)
-#define CAN_NDAT2_ND61_Pos 29 /**< \brief (CAN_NDAT2) New Data 61 */
-#define CAN_NDAT2_ND61 (_U_(0x1) << CAN_NDAT2_ND61_Pos)
-#define CAN_NDAT2_ND62_Pos 30 /**< \brief (CAN_NDAT2) New Data 62 */
-#define CAN_NDAT2_ND62 (_U_(0x1) << CAN_NDAT2_ND62_Pos)
-#define CAN_NDAT2_ND63_Pos 31 /**< \brief (CAN_NDAT2) New Data 63 */
-#define CAN_NDAT2_ND63 (_U_(0x1) << CAN_NDAT2_ND63_Pos)
-#define CAN_NDAT2_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_NDAT2) MASK Register */
-
-/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t F0SA:16; /*!< bit: 0..15 Rx FIFO 0 Start Address */
- uint32_t F0S:7; /*!< bit: 16..22 Rx FIFO 0 Size */
- uint32_t :1; /*!< bit: 23 Reserved */
- uint32_t F0WM:7; /*!< bit: 24..30 Rx FIFO 0 Watermark */
- uint32_t F0OM:1; /*!< bit: 31 FIFO 0 Operation Mode */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF0C_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF0C_OFFSET 0xA0 /**< \brief (CAN_RXF0C offset) Rx FIFO 0 Configuration */
-#define CAN_RXF0C_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0C reset_value) Rx FIFO 0 Configuration */
-
-#define CAN_RXF0C_F0SA_Pos 0 /**< \brief (CAN_RXF0C) Rx FIFO 0 Start Address */
-#define CAN_RXF0C_F0SA_Msk (_U_(0xFFFF) << CAN_RXF0C_F0SA_Pos)
-#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & ((value) << CAN_RXF0C_F0SA_Pos))
-#define CAN_RXF0C_F0S_Pos 16 /**< \brief (CAN_RXF0C) Rx FIFO 0 Size */
-#define CAN_RXF0C_F0S_Msk (_U_(0x7F) << CAN_RXF0C_F0S_Pos)
-#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & ((value) << CAN_RXF0C_F0S_Pos))
-#define CAN_RXF0C_F0WM_Pos 24 /**< \brief (CAN_RXF0C) Rx FIFO 0 Watermark */
-#define CAN_RXF0C_F0WM_Msk (_U_(0x7F) << CAN_RXF0C_F0WM_Pos)
-#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & ((value) << CAN_RXF0C_F0WM_Pos))
-#define CAN_RXF0C_F0OM_Pos 31 /**< \brief (CAN_RXF0C) FIFO 0 Operation Mode */
-#define CAN_RXF0C_F0OM (_U_(0x1) << CAN_RXF0C_F0OM_Pos)
-#define CAN_RXF0C_MASK _U_(0xFF7FFFFF) /**< \brief (CAN_RXF0C) MASK Register */
-
-/* -------- CAN_RXF0S : (CAN Offset: 0xA4) (R/ 32) Rx FIFO 0 Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t F0FL:7; /*!< bit: 0.. 6 Rx FIFO 0 Fill Level */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t F0GI:6; /*!< bit: 8..13 Rx FIFO 0 Get Index */
- uint32_t :2; /*!< bit: 14..15 Reserved */
- uint32_t F0PI:6; /*!< bit: 16..21 Rx FIFO 0 Put Index */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t F0F:1; /*!< bit: 24 Rx FIFO 0 Full */
- uint32_t RF0L:1; /*!< bit: 25 Rx FIFO 0 Message Lost */
- uint32_t :6; /*!< bit: 26..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF0S_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF0S_OFFSET 0xA4 /**< \brief (CAN_RXF0S offset) Rx FIFO 0 Status */
-#define CAN_RXF0S_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0S reset_value) Rx FIFO 0 Status */
-
-#define CAN_RXF0S_F0FL_Pos 0 /**< \brief (CAN_RXF0S) Rx FIFO 0 Fill Level */
-#define CAN_RXF0S_F0FL_Msk (_U_(0x7F) << CAN_RXF0S_F0FL_Pos)
-#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & ((value) << CAN_RXF0S_F0FL_Pos))
-#define CAN_RXF0S_F0GI_Pos 8 /**< \brief (CAN_RXF0S) Rx FIFO 0 Get Index */
-#define CAN_RXF0S_F0GI_Msk (_U_(0x3F) << CAN_RXF0S_F0GI_Pos)
-#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & ((value) << CAN_RXF0S_F0GI_Pos))
-#define CAN_RXF0S_F0PI_Pos 16 /**< \brief (CAN_RXF0S) Rx FIFO 0 Put Index */
-#define CAN_RXF0S_F0PI_Msk (_U_(0x3F) << CAN_RXF0S_F0PI_Pos)
-#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & ((value) << CAN_RXF0S_F0PI_Pos))
-#define CAN_RXF0S_F0F_Pos 24 /**< \brief (CAN_RXF0S) Rx FIFO 0 Full */
-#define CAN_RXF0S_F0F (_U_(0x1) << CAN_RXF0S_F0F_Pos)
-#define CAN_RXF0S_RF0L_Pos 25 /**< \brief (CAN_RXF0S) Rx FIFO 0 Message Lost */
-#define CAN_RXF0S_RF0L (_U_(0x1) << CAN_RXF0S_RF0L_Pos)
-#define CAN_RXF0S_MASK _U_(0x033F3F7F) /**< \brief (CAN_RXF0S) MASK Register */
-
-/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t F0AI:6; /*!< bit: 0.. 5 Rx FIFO 0 Acknowledge Index */
- uint32_t :26; /*!< bit: 6..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF0A_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF0A_OFFSET 0xA8 /**< \brief (CAN_RXF0A offset) Rx FIFO 0 Acknowledge */
-#define CAN_RXF0A_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0A reset_value) Rx FIFO 0 Acknowledge */
-
-#define CAN_RXF0A_F0AI_Pos 0 /**< \brief (CAN_RXF0A) Rx FIFO 0 Acknowledge Index */
-#define CAN_RXF0A_F0AI_Msk (_U_(0x3F) << CAN_RXF0A_F0AI_Pos)
-#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & ((value) << CAN_RXF0A_F0AI_Pos))
-#define CAN_RXF0A_MASK _U_(0x0000003F) /**< \brief (CAN_RXF0A) MASK Register */
-
-/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RBSA:16; /*!< bit: 0..15 Rx Buffer Start Address */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXBC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXBC_OFFSET 0xAC /**< \brief (CAN_RXBC offset) Rx Buffer Configuration */
-#define CAN_RXBC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBC reset_value) Rx Buffer Configuration */
-
-#define CAN_RXBC_RBSA_Pos 0 /**< \brief (CAN_RXBC) Rx Buffer Start Address */
-#define CAN_RXBC_RBSA_Msk (_U_(0xFFFF) << CAN_RXBC_RBSA_Pos)
-#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & ((value) << CAN_RXBC_RBSA_Pos))
-#define CAN_RXBC_MASK _U_(0x0000FFFF) /**< \brief (CAN_RXBC) MASK Register */
-
-/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t F1SA:16; /*!< bit: 0..15 Rx FIFO 1 Start Address */
- uint32_t F1S:7; /*!< bit: 16..22 Rx FIFO 1 Size */
- uint32_t :1; /*!< bit: 23 Reserved */
- uint32_t F1WM:7; /*!< bit: 24..30 Rx FIFO 1 Watermark */
- uint32_t F1OM:1; /*!< bit: 31 FIFO 1 Operation Mode */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF1C_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF1C_OFFSET 0xB0 /**< \brief (CAN_RXF1C offset) Rx FIFO 1 Configuration */
-#define CAN_RXF1C_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1C reset_value) Rx FIFO 1 Configuration */
-
-#define CAN_RXF1C_F1SA_Pos 0 /**< \brief (CAN_RXF1C) Rx FIFO 1 Start Address */
-#define CAN_RXF1C_F1SA_Msk (_U_(0xFFFF) << CAN_RXF1C_F1SA_Pos)
-#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & ((value) << CAN_RXF1C_F1SA_Pos))
-#define CAN_RXF1C_F1S_Pos 16 /**< \brief (CAN_RXF1C) Rx FIFO 1 Size */
-#define CAN_RXF1C_F1S_Msk (_U_(0x7F) << CAN_RXF1C_F1S_Pos)
-#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & ((value) << CAN_RXF1C_F1S_Pos))
-#define CAN_RXF1C_F1WM_Pos 24 /**< \brief (CAN_RXF1C) Rx FIFO 1 Watermark */
-#define CAN_RXF1C_F1WM_Msk (_U_(0x7F) << CAN_RXF1C_F1WM_Pos)
-#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & ((value) << CAN_RXF1C_F1WM_Pos))
-#define CAN_RXF1C_F1OM_Pos 31 /**< \brief (CAN_RXF1C) FIFO 1 Operation Mode */
-#define CAN_RXF1C_F1OM (_U_(0x1) << CAN_RXF1C_F1OM_Pos)
-#define CAN_RXF1C_MASK _U_(0xFF7FFFFF) /**< \brief (CAN_RXF1C) MASK Register */
-
-/* -------- CAN_RXF1S : (CAN Offset: 0xB4) (R/ 32) Rx FIFO 1 Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t F1FL:7; /*!< bit: 0.. 6 Rx FIFO 1 Fill Level */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t F1GI:6; /*!< bit: 8..13 Rx FIFO 1 Get Index */
- uint32_t :2; /*!< bit: 14..15 Reserved */
- uint32_t F1PI:6; /*!< bit: 16..21 Rx FIFO 1 Put Index */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t F1F:1; /*!< bit: 24 Rx FIFO 1 Full */
- uint32_t RF1L:1; /*!< bit: 25 Rx FIFO 1 Message Lost */
- uint32_t :4; /*!< bit: 26..29 Reserved */
- uint32_t DMS:2; /*!< bit: 30..31 Debug Message Status */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF1S_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF1S_OFFSET 0xB4 /**< \brief (CAN_RXF1S offset) Rx FIFO 1 Status */
-#define CAN_RXF1S_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1S reset_value) Rx FIFO 1 Status */
-
-#define CAN_RXF1S_F1FL_Pos 0 /**< \brief (CAN_RXF1S) Rx FIFO 1 Fill Level */
-#define CAN_RXF1S_F1FL_Msk (_U_(0x7F) << CAN_RXF1S_F1FL_Pos)
-#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & ((value) << CAN_RXF1S_F1FL_Pos))
-#define CAN_RXF1S_F1GI_Pos 8 /**< \brief (CAN_RXF1S) Rx FIFO 1 Get Index */
-#define CAN_RXF1S_F1GI_Msk (_U_(0x3F) << CAN_RXF1S_F1GI_Pos)
-#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & ((value) << CAN_RXF1S_F1GI_Pos))
-#define CAN_RXF1S_F1PI_Pos 16 /**< \brief (CAN_RXF1S) Rx FIFO 1 Put Index */
-#define CAN_RXF1S_F1PI_Msk (_U_(0x3F) << CAN_RXF1S_F1PI_Pos)
-#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & ((value) << CAN_RXF1S_F1PI_Pos))
-#define CAN_RXF1S_F1F_Pos 24 /**< \brief (CAN_RXF1S) Rx FIFO 1 Full */
-#define CAN_RXF1S_F1F (_U_(0x1) << CAN_RXF1S_F1F_Pos)
-#define CAN_RXF1S_RF1L_Pos 25 /**< \brief (CAN_RXF1S) Rx FIFO 1 Message Lost */
-#define CAN_RXF1S_RF1L (_U_(0x1) << CAN_RXF1S_RF1L_Pos)
-#define CAN_RXF1S_DMS_Pos 30 /**< \brief (CAN_RXF1S) Debug Message Status */
-#define CAN_RXF1S_DMS_Msk (_U_(0x3) << CAN_RXF1S_DMS_Pos)
-#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & ((value) << CAN_RXF1S_DMS_Pos))
-#define CAN_RXF1S_DMS_IDLE_Val _U_(0x0) /**< \brief (CAN_RXF1S) Idle state */
-#define CAN_RXF1S_DMS_DBGA_Val _U_(0x1) /**< \brief (CAN_RXF1S) Debug message A received */
-#define CAN_RXF1S_DMS_DBGB_Val _U_(0x2) /**< \brief (CAN_RXF1S) Debug message A/B received */
-#define CAN_RXF1S_DMS_DBGC_Val _U_(0x3) /**< \brief (CAN_RXF1S) Debug message A/B/C received, DMA request set */
-#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos)
-#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos)
-#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos)
-#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos)
-#define CAN_RXF1S_MASK _U_(0xC33F3F7F) /**< \brief (CAN_RXF1S) MASK Register */
-
-/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t F1AI:6; /*!< bit: 0.. 5 Rx FIFO 1 Acknowledge Index */
- uint32_t :26; /*!< bit: 6..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF1A_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF1A_OFFSET 0xB8 /**< \brief (CAN_RXF1A offset) Rx FIFO 1 Acknowledge */
-#define CAN_RXF1A_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1A reset_value) Rx FIFO 1 Acknowledge */
-
-#define CAN_RXF1A_F1AI_Pos 0 /**< \brief (CAN_RXF1A) Rx FIFO 1 Acknowledge Index */
-#define CAN_RXF1A_F1AI_Msk (_U_(0x3F) << CAN_RXF1A_F1AI_Pos)
-#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & ((value) << CAN_RXF1A_F1AI_Pos))
-#define CAN_RXF1A_MASK _U_(0x0000003F) /**< \brief (CAN_RXF1A) MASK Register */
-
-/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t F0DS:3; /*!< bit: 0.. 2 Rx FIFO 0 Data Field Size */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t F1DS:3; /*!< bit: 4.. 6 Rx FIFO 1 Data Field Size */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t RBDS:3; /*!< bit: 8..10 Rx Buffer Data Field Size */
- uint32_t :21; /*!< bit: 11..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXESC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXESC_OFFSET 0xBC /**< \brief (CAN_RXESC offset) Rx Buffer / FIFO Element Size Configuration */
-#define CAN_RXESC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXESC reset_value) Rx Buffer / FIFO Element Size Configuration */
-
-#define CAN_RXESC_F0DS_Pos 0 /**< \brief (CAN_RXESC) Rx FIFO 0 Data Field Size */
-#define CAN_RXESC_F0DS_Msk (_U_(0x7) << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & ((value) << CAN_RXESC_F0DS_Pos))
-#define CAN_RXESC_F0DS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */
-#define CAN_RXESC_F0DS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */
-#define CAN_RXESC_F0DS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */
-#define CAN_RXESC_F0DS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */
-#define CAN_RXESC_F0DS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */
-#define CAN_RXESC_F0DS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */
-#define CAN_RXESC_F0DS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */
-#define CAN_RXESC_F0DS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */
-#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F1DS_Pos 4 /**< \brief (CAN_RXESC) Rx FIFO 1 Data Field Size */
-#define CAN_RXESC_F1DS_Msk (_U_(0x7) << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & ((value) << CAN_RXESC_F1DS_Pos))
-#define CAN_RXESC_F1DS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */
-#define CAN_RXESC_F1DS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */
-#define CAN_RXESC_F1DS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */
-#define CAN_RXESC_F1DS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */
-#define CAN_RXESC_F1DS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */
-#define CAN_RXESC_F1DS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */
-#define CAN_RXESC_F1DS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */
-#define CAN_RXESC_F1DS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */
-#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_RBDS_Pos 8 /**< \brief (CAN_RXESC) Rx Buffer Data Field Size */
-#define CAN_RXESC_RBDS_Msk (_U_(0x7) << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & ((value) << CAN_RXESC_RBDS_Pos))
-#define CAN_RXESC_RBDS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */
-#define CAN_RXESC_RBDS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */
-#define CAN_RXESC_RBDS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */
-#define CAN_RXESC_RBDS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */
-#define CAN_RXESC_RBDS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */
-#define CAN_RXESC_RBDS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */
-#define CAN_RXESC_RBDS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */
-#define CAN_RXESC_RBDS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */
-#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_MASK _U_(0x00000777) /**< \brief (CAN_RXESC) MASK Register */
-
-/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TBSA:16; /*!< bit: 0..15 Tx Buffers Start Address */
- uint32_t NDTB:6; /*!< bit: 16..21 Number of Dedicated Transmit Buffers */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t TFQS:6; /*!< bit: 24..29 Transmit FIFO/Queue Size */
- uint32_t TFQM:1; /*!< bit: 30 Tx FIFO/Queue Mode */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBC_OFFSET 0xC0 /**< \brief (CAN_TXBC offset) Tx Buffer Configuration */
-#define CAN_TXBC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBC reset_value) Tx Buffer Configuration */
-
-#define CAN_TXBC_TBSA_Pos 0 /**< \brief (CAN_TXBC) Tx Buffers Start Address */
-#define CAN_TXBC_TBSA_Msk (_U_(0xFFFF) << CAN_TXBC_TBSA_Pos)
-#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & ((value) << CAN_TXBC_TBSA_Pos))
-#define CAN_TXBC_NDTB_Pos 16 /**< \brief (CAN_TXBC) Number of Dedicated Transmit Buffers */
-#define CAN_TXBC_NDTB_Msk (_U_(0x3F) << CAN_TXBC_NDTB_Pos)
-#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & ((value) << CAN_TXBC_NDTB_Pos))
-#define CAN_TXBC_TFQS_Pos 24 /**< \brief (CAN_TXBC) Transmit FIFO/Queue Size */
-#define CAN_TXBC_TFQS_Msk (_U_(0x3F) << CAN_TXBC_TFQS_Pos)
-#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & ((value) << CAN_TXBC_TFQS_Pos))
-#define CAN_TXBC_TFQM_Pos 30 /**< \brief (CAN_TXBC) Tx FIFO/Queue Mode */
-#define CAN_TXBC_TFQM (_U_(0x1) << CAN_TXBC_TFQM_Pos)
-#define CAN_TXBC_MASK _U_(0x7F3FFFFF) /**< \brief (CAN_TXBC) MASK Register */
-
-/* -------- CAN_TXFQS : (CAN Offset: 0xC4) (R/ 32) Tx FIFO / Queue Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TFFL:6; /*!< bit: 0.. 5 Tx FIFO Free Level */
- uint32_t :2; /*!< bit: 6.. 7 Reserved */
- uint32_t TFGI:5; /*!< bit: 8..12 Tx FIFO Get Index */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t TFQPI:5; /*!< bit: 16..20 Tx FIFO/Queue Put Index */
- uint32_t TFQF:1; /*!< bit: 21 Tx FIFO/Queue Full */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXFQS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXFQS_OFFSET 0xC4 /**< \brief (CAN_TXFQS offset) Tx FIFO / Queue Status */
-#define CAN_TXFQS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXFQS reset_value) Tx FIFO / Queue Status */
-
-#define CAN_TXFQS_TFFL_Pos 0 /**< \brief (CAN_TXFQS) Tx FIFO Free Level */
-#define CAN_TXFQS_TFFL_Msk (_U_(0x3F) << CAN_TXFQS_TFFL_Pos)
-#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & ((value) << CAN_TXFQS_TFFL_Pos))
-#define CAN_TXFQS_TFGI_Pos 8 /**< \brief (CAN_TXFQS) Tx FIFO Get Index */
-#define CAN_TXFQS_TFGI_Msk (_U_(0x1F) << CAN_TXFQS_TFGI_Pos)
-#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & ((value) << CAN_TXFQS_TFGI_Pos))
-#define CAN_TXFQS_TFQPI_Pos 16 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Put Index */
-#define CAN_TXFQS_TFQPI_Msk (_U_(0x1F) << CAN_TXFQS_TFQPI_Pos)
-#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & ((value) << CAN_TXFQS_TFQPI_Pos))
-#define CAN_TXFQS_TFQF_Pos 21 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Full */
-#define CAN_TXFQS_TFQF (_U_(0x1) << CAN_TXFQS_TFQF_Pos)
-#define CAN_TXFQS_MASK _U_(0x003F1F3F) /**< \brief (CAN_TXFQS) MASK Register */
-
-/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TBDS:3; /*!< bit: 0.. 2 Tx Buffer Data Field Size */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXESC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXESC_OFFSET 0xC8 /**< \brief (CAN_TXESC offset) Tx Buffer Element Size Configuration */
-#define CAN_TXESC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXESC reset_value) Tx Buffer Element Size Configuration */
-
-#define CAN_TXESC_TBDS_Pos 0 /**< \brief (CAN_TXESC) Tx Buffer Data Field Size */
-#define CAN_TXESC_TBDS_Msk (_U_(0x7) << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & ((value) << CAN_TXESC_TBDS_Pos))
-#define CAN_TXESC_TBDS_DATA8_Val _U_(0x0) /**< \brief (CAN_TXESC) 8 byte data field */
-#define CAN_TXESC_TBDS_DATA12_Val _U_(0x1) /**< \brief (CAN_TXESC) 12 byte data field */
-#define CAN_TXESC_TBDS_DATA16_Val _U_(0x2) /**< \brief (CAN_TXESC) 16 byte data field */
-#define CAN_TXESC_TBDS_DATA20_Val _U_(0x3) /**< \brief (CAN_TXESC) 20 byte data field */
-#define CAN_TXESC_TBDS_DATA24_Val _U_(0x4) /**< \brief (CAN_TXESC) 24 byte data field */
-#define CAN_TXESC_TBDS_DATA32_Val _U_(0x5) /**< \brief (CAN_TXESC) 32 byte data field */
-#define CAN_TXESC_TBDS_DATA48_Val _U_(0x6) /**< \brief (CAN_TXESC) 48 byte data field */
-#define CAN_TXESC_TBDS_DATA64_Val _U_(0x7) /**< \brief (CAN_TXESC) 64 byte data field */
-#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_MASK _U_(0x00000007) /**< \brief (CAN_TXESC) MASK Register */
-
-/* -------- CAN_TXBRP : (CAN Offset: 0xCC) (R/ 32) Tx Buffer Request Pending -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TRP0:1; /*!< bit: 0 Transmission Request Pending 0 */
- uint32_t TRP1:1; /*!< bit: 1 Transmission Request Pending 1 */
- uint32_t TRP2:1; /*!< bit: 2 Transmission Request Pending 2 */
- uint32_t TRP3:1; /*!< bit: 3 Transmission Request Pending 3 */
- uint32_t TRP4:1; /*!< bit: 4 Transmission Request Pending 4 */
- uint32_t TRP5:1; /*!< bit: 5 Transmission Request Pending 5 */
- uint32_t TRP6:1; /*!< bit: 6 Transmission Request Pending 6 */
- uint32_t TRP7:1; /*!< bit: 7 Transmission Request Pending 7 */
- uint32_t TRP8:1; /*!< bit: 8 Transmission Request Pending 8 */
- uint32_t TRP9:1; /*!< bit: 9 Transmission Request Pending 9 */
- uint32_t TRP10:1; /*!< bit: 10 Transmission Request Pending 10 */
- uint32_t TRP11:1; /*!< bit: 11 Transmission Request Pending 11 */
- uint32_t TRP12:1; /*!< bit: 12 Transmission Request Pending 12 */
- uint32_t TRP13:1; /*!< bit: 13 Transmission Request Pending 13 */
- uint32_t TRP14:1; /*!< bit: 14 Transmission Request Pending 14 */
- uint32_t TRP15:1; /*!< bit: 15 Transmission Request Pending 15 */
- uint32_t TRP16:1; /*!< bit: 16 Transmission Request Pending 16 */
- uint32_t TRP17:1; /*!< bit: 17 Transmission Request Pending 17 */
- uint32_t TRP18:1; /*!< bit: 18 Transmission Request Pending 18 */
- uint32_t TRP19:1; /*!< bit: 19 Transmission Request Pending 19 */
- uint32_t TRP20:1; /*!< bit: 20 Transmission Request Pending 20 */
- uint32_t TRP21:1; /*!< bit: 21 Transmission Request Pending 21 */
- uint32_t TRP22:1; /*!< bit: 22 Transmission Request Pending 22 */
- uint32_t TRP23:1; /*!< bit: 23 Transmission Request Pending 23 */
- uint32_t TRP24:1; /*!< bit: 24 Transmission Request Pending 24 */
- uint32_t TRP25:1; /*!< bit: 25 Transmission Request Pending 25 */
- uint32_t TRP26:1; /*!< bit: 26 Transmission Request Pending 26 */
- uint32_t TRP27:1; /*!< bit: 27 Transmission Request Pending 27 */
- uint32_t TRP28:1; /*!< bit: 28 Transmission Request Pending 28 */
- uint32_t TRP29:1; /*!< bit: 29 Transmission Request Pending 29 */
- uint32_t TRP30:1; /*!< bit: 30 Transmission Request Pending 30 */
- uint32_t TRP31:1; /*!< bit: 31 Transmission Request Pending 31 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBRP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBRP_OFFSET 0xCC /**< \brief (CAN_TXBRP offset) Tx Buffer Request Pending */
-#define CAN_TXBRP_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBRP reset_value) Tx Buffer Request Pending */
-
-#define CAN_TXBRP_TRP0_Pos 0 /**< \brief (CAN_TXBRP) Transmission Request Pending 0 */
-#define CAN_TXBRP_TRP0 (_U_(0x1) << CAN_TXBRP_TRP0_Pos)
-#define CAN_TXBRP_TRP1_Pos 1 /**< \brief (CAN_TXBRP) Transmission Request Pending 1 */
-#define CAN_TXBRP_TRP1 (_U_(0x1) << CAN_TXBRP_TRP1_Pos)
-#define CAN_TXBRP_TRP2_Pos 2 /**< \brief (CAN_TXBRP) Transmission Request Pending 2 */
-#define CAN_TXBRP_TRP2 (_U_(0x1) << CAN_TXBRP_TRP2_Pos)
-#define CAN_TXBRP_TRP3_Pos 3 /**< \brief (CAN_TXBRP) Transmission Request Pending 3 */
-#define CAN_TXBRP_TRP3 (_U_(0x1) << CAN_TXBRP_TRP3_Pos)
-#define CAN_TXBRP_TRP4_Pos 4 /**< \brief (CAN_TXBRP) Transmission Request Pending 4 */
-#define CAN_TXBRP_TRP4 (_U_(0x1) << CAN_TXBRP_TRP4_Pos)
-#define CAN_TXBRP_TRP5_Pos 5 /**< \brief (CAN_TXBRP) Transmission Request Pending 5 */
-#define CAN_TXBRP_TRP5 (_U_(0x1) << CAN_TXBRP_TRP5_Pos)
-#define CAN_TXBRP_TRP6_Pos 6 /**< \brief (CAN_TXBRP) Transmission Request Pending 6 */
-#define CAN_TXBRP_TRP6 (_U_(0x1) << CAN_TXBRP_TRP6_Pos)
-#define CAN_TXBRP_TRP7_Pos 7 /**< \brief (CAN_TXBRP) Transmission Request Pending 7 */
-#define CAN_TXBRP_TRP7 (_U_(0x1) << CAN_TXBRP_TRP7_Pos)
-#define CAN_TXBRP_TRP8_Pos 8 /**< \brief (CAN_TXBRP) Transmission Request Pending 8 */
-#define CAN_TXBRP_TRP8 (_U_(0x1) << CAN_TXBRP_TRP8_Pos)
-#define CAN_TXBRP_TRP9_Pos 9 /**< \brief (CAN_TXBRP) Transmission Request Pending 9 */
-#define CAN_TXBRP_TRP9 (_U_(0x1) << CAN_TXBRP_TRP9_Pos)
-#define CAN_TXBRP_TRP10_Pos 10 /**< \brief (CAN_TXBRP) Transmission Request Pending 10 */
-#define CAN_TXBRP_TRP10 (_U_(0x1) << CAN_TXBRP_TRP10_Pos)
-#define CAN_TXBRP_TRP11_Pos 11 /**< \brief (CAN_TXBRP) Transmission Request Pending 11 */
-#define CAN_TXBRP_TRP11 (_U_(0x1) << CAN_TXBRP_TRP11_Pos)
-#define CAN_TXBRP_TRP12_Pos 12 /**< \brief (CAN_TXBRP) Transmission Request Pending 12 */
-#define CAN_TXBRP_TRP12 (_U_(0x1) << CAN_TXBRP_TRP12_Pos)
-#define CAN_TXBRP_TRP13_Pos 13 /**< \brief (CAN_TXBRP) Transmission Request Pending 13 */
-#define CAN_TXBRP_TRP13 (_U_(0x1) << CAN_TXBRP_TRP13_Pos)
-#define CAN_TXBRP_TRP14_Pos 14 /**< \brief (CAN_TXBRP) Transmission Request Pending 14 */
-#define CAN_TXBRP_TRP14 (_U_(0x1) << CAN_TXBRP_TRP14_Pos)
-#define CAN_TXBRP_TRP15_Pos 15 /**< \brief (CAN_TXBRP) Transmission Request Pending 15 */
-#define CAN_TXBRP_TRP15 (_U_(0x1) << CAN_TXBRP_TRP15_Pos)
-#define CAN_TXBRP_TRP16_Pos 16 /**< \brief (CAN_TXBRP) Transmission Request Pending 16 */
-#define CAN_TXBRP_TRP16 (_U_(0x1) << CAN_TXBRP_TRP16_Pos)
-#define CAN_TXBRP_TRP17_Pos 17 /**< \brief (CAN_TXBRP) Transmission Request Pending 17 */
-#define CAN_TXBRP_TRP17 (_U_(0x1) << CAN_TXBRP_TRP17_Pos)
-#define CAN_TXBRP_TRP18_Pos 18 /**< \brief (CAN_TXBRP) Transmission Request Pending 18 */
-#define CAN_TXBRP_TRP18 (_U_(0x1) << CAN_TXBRP_TRP18_Pos)
-#define CAN_TXBRP_TRP19_Pos 19 /**< \brief (CAN_TXBRP) Transmission Request Pending 19 */
-#define CAN_TXBRP_TRP19 (_U_(0x1) << CAN_TXBRP_TRP19_Pos)
-#define CAN_TXBRP_TRP20_Pos 20 /**< \brief (CAN_TXBRP) Transmission Request Pending 20 */
-#define CAN_TXBRP_TRP20 (_U_(0x1) << CAN_TXBRP_TRP20_Pos)
-#define CAN_TXBRP_TRP21_Pos 21 /**< \brief (CAN_TXBRP) Transmission Request Pending 21 */
-#define CAN_TXBRP_TRP21 (_U_(0x1) << CAN_TXBRP_TRP21_Pos)
-#define CAN_TXBRP_TRP22_Pos 22 /**< \brief (CAN_TXBRP) Transmission Request Pending 22 */
-#define CAN_TXBRP_TRP22 (_U_(0x1) << CAN_TXBRP_TRP22_Pos)
-#define CAN_TXBRP_TRP23_Pos 23 /**< \brief (CAN_TXBRP) Transmission Request Pending 23 */
-#define CAN_TXBRP_TRP23 (_U_(0x1) << CAN_TXBRP_TRP23_Pos)
-#define CAN_TXBRP_TRP24_Pos 24 /**< \brief (CAN_TXBRP) Transmission Request Pending 24 */
-#define CAN_TXBRP_TRP24 (_U_(0x1) << CAN_TXBRP_TRP24_Pos)
-#define CAN_TXBRP_TRP25_Pos 25 /**< \brief (CAN_TXBRP) Transmission Request Pending 25 */
-#define CAN_TXBRP_TRP25 (_U_(0x1) << CAN_TXBRP_TRP25_Pos)
-#define CAN_TXBRP_TRP26_Pos 26 /**< \brief (CAN_TXBRP) Transmission Request Pending 26 */
-#define CAN_TXBRP_TRP26 (_U_(0x1) << CAN_TXBRP_TRP26_Pos)
-#define CAN_TXBRP_TRP27_Pos 27 /**< \brief (CAN_TXBRP) Transmission Request Pending 27 */
-#define CAN_TXBRP_TRP27 (_U_(0x1) << CAN_TXBRP_TRP27_Pos)
-#define CAN_TXBRP_TRP28_Pos 28 /**< \brief (CAN_TXBRP) Transmission Request Pending 28 */
-#define CAN_TXBRP_TRP28 (_U_(0x1) << CAN_TXBRP_TRP28_Pos)
-#define CAN_TXBRP_TRP29_Pos 29 /**< \brief (CAN_TXBRP) Transmission Request Pending 29 */
-#define CAN_TXBRP_TRP29 (_U_(0x1) << CAN_TXBRP_TRP29_Pos)
-#define CAN_TXBRP_TRP30_Pos 30 /**< \brief (CAN_TXBRP) Transmission Request Pending 30 */
-#define CAN_TXBRP_TRP30 (_U_(0x1) << CAN_TXBRP_TRP30_Pos)
-#define CAN_TXBRP_TRP31_Pos 31 /**< \brief (CAN_TXBRP) Transmission Request Pending 31 */
-#define CAN_TXBRP_TRP31 (_U_(0x1) << CAN_TXBRP_TRP31_Pos)
-#define CAN_TXBRP_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBRP) MASK Register */
-
-/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t AR0:1; /*!< bit: 0 Add Request 0 */
- uint32_t AR1:1; /*!< bit: 1 Add Request 1 */
- uint32_t AR2:1; /*!< bit: 2 Add Request 2 */
- uint32_t AR3:1; /*!< bit: 3 Add Request 3 */
- uint32_t AR4:1; /*!< bit: 4 Add Request 4 */
- uint32_t AR5:1; /*!< bit: 5 Add Request 5 */
- uint32_t AR6:1; /*!< bit: 6 Add Request 6 */
- uint32_t AR7:1; /*!< bit: 7 Add Request 7 */
- uint32_t AR8:1; /*!< bit: 8 Add Request 8 */
- uint32_t AR9:1; /*!< bit: 9 Add Request 9 */
- uint32_t AR10:1; /*!< bit: 10 Add Request 10 */
- uint32_t AR11:1; /*!< bit: 11 Add Request 11 */
- uint32_t AR12:1; /*!< bit: 12 Add Request 12 */
- uint32_t AR13:1; /*!< bit: 13 Add Request 13 */
- uint32_t AR14:1; /*!< bit: 14 Add Request 14 */
- uint32_t AR15:1; /*!< bit: 15 Add Request 15 */
- uint32_t AR16:1; /*!< bit: 16 Add Request 16 */
- uint32_t AR17:1; /*!< bit: 17 Add Request 17 */
- uint32_t AR18:1; /*!< bit: 18 Add Request 18 */
- uint32_t AR19:1; /*!< bit: 19 Add Request 19 */
- uint32_t AR20:1; /*!< bit: 20 Add Request 20 */
- uint32_t AR21:1; /*!< bit: 21 Add Request 21 */
- uint32_t AR22:1; /*!< bit: 22 Add Request 22 */
- uint32_t AR23:1; /*!< bit: 23 Add Request 23 */
- uint32_t AR24:1; /*!< bit: 24 Add Request 24 */
- uint32_t AR25:1; /*!< bit: 25 Add Request 25 */
- uint32_t AR26:1; /*!< bit: 26 Add Request 26 */
- uint32_t AR27:1; /*!< bit: 27 Add Request 27 */
- uint32_t AR28:1; /*!< bit: 28 Add Request 28 */
- uint32_t AR29:1; /*!< bit: 29 Add Request 29 */
- uint32_t AR30:1; /*!< bit: 30 Add Request 30 */
- uint32_t AR31:1; /*!< bit: 31 Add Request 31 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBAR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBAR_OFFSET 0xD0 /**< \brief (CAN_TXBAR offset) Tx Buffer Add Request */
-#define CAN_TXBAR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBAR reset_value) Tx Buffer Add Request */
-
-#define CAN_TXBAR_AR0_Pos 0 /**< \brief (CAN_TXBAR) Add Request 0 */
-#define CAN_TXBAR_AR0 (_U_(0x1) << CAN_TXBAR_AR0_Pos)
-#define CAN_TXBAR_AR1_Pos 1 /**< \brief (CAN_TXBAR) Add Request 1 */
-#define CAN_TXBAR_AR1 (_U_(0x1) << CAN_TXBAR_AR1_Pos)
-#define CAN_TXBAR_AR2_Pos 2 /**< \brief (CAN_TXBAR) Add Request 2 */
-#define CAN_TXBAR_AR2 (_U_(0x1) << CAN_TXBAR_AR2_Pos)
-#define CAN_TXBAR_AR3_Pos 3 /**< \brief (CAN_TXBAR) Add Request 3 */
-#define CAN_TXBAR_AR3 (_U_(0x1) << CAN_TXBAR_AR3_Pos)
-#define CAN_TXBAR_AR4_Pos 4 /**< \brief (CAN_TXBAR) Add Request 4 */
-#define CAN_TXBAR_AR4 (_U_(0x1) << CAN_TXBAR_AR4_Pos)
-#define CAN_TXBAR_AR5_Pos 5 /**< \brief (CAN_TXBAR) Add Request 5 */
-#define CAN_TXBAR_AR5 (_U_(0x1) << CAN_TXBAR_AR5_Pos)
-#define CAN_TXBAR_AR6_Pos 6 /**< \brief (CAN_TXBAR) Add Request 6 */
-#define CAN_TXBAR_AR6 (_U_(0x1) << CAN_TXBAR_AR6_Pos)
-#define CAN_TXBAR_AR7_Pos 7 /**< \brief (CAN_TXBAR) Add Request 7 */
-#define CAN_TXBAR_AR7 (_U_(0x1) << CAN_TXBAR_AR7_Pos)
-#define CAN_TXBAR_AR8_Pos 8 /**< \brief (CAN_TXBAR) Add Request 8 */
-#define CAN_TXBAR_AR8 (_U_(0x1) << CAN_TXBAR_AR8_Pos)
-#define CAN_TXBAR_AR9_Pos 9 /**< \brief (CAN_TXBAR) Add Request 9 */
-#define CAN_TXBAR_AR9 (_U_(0x1) << CAN_TXBAR_AR9_Pos)
-#define CAN_TXBAR_AR10_Pos 10 /**< \brief (CAN_TXBAR) Add Request 10 */
-#define CAN_TXBAR_AR10 (_U_(0x1) << CAN_TXBAR_AR10_Pos)
-#define CAN_TXBAR_AR11_Pos 11 /**< \brief (CAN_TXBAR) Add Request 11 */
-#define CAN_TXBAR_AR11 (_U_(0x1) << CAN_TXBAR_AR11_Pos)
-#define CAN_TXBAR_AR12_Pos 12 /**< \brief (CAN_TXBAR) Add Request 12 */
-#define CAN_TXBAR_AR12 (_U_(0x1) << CAN_TXBAR_AR12_Pos)
-#define CAN_TXBAR_AR13_Pos 13 /**< \brief (CAN_TXBAR) Add Request 13 */
-#define CAN_TXBAR_AR13 (_U_(0x1) << CAN_TXBAR_AR13_Pos)
-#define CAN_TXBAR_AR14_Pos 14 /**< \brief (CAN_TXBAR) Add Request 14 */
-#define CAN_TXBAR_AR14 (_U_(0x1) << CAN_TXBAR_AR14_Pos)
-#define CAN_TXBAR_AR15_Pos 15 /**< \brief (CAN_TXBAR) Add Request 15 */
-#define CAN_TXBAR_AR15 (_U_(0x1) << CAN_TXBAR_AR15_Pos)
-#define CAN_TXBAR_AR16_Pos 16 /**< \brief (CAN_TXBAR) Add Request 16 */
-#define CAN_TXBAR_AR16 (_U_(0x1) << CAN_TXBAR_AR16_Pos)
-#define CAN_TXBAR_AR17_Pos 17 /**< \brief (CAN_TXBAR) Add Request 17 */
-#define CAN_TXBAR_AR17 (_U_(0x1) << CAN_TXBAR_AR17_Pos)
-#define CAN_TXBAR_AR18_Pos 18 /**< \brief (CAN_TXBAR) Add Request 18 */
-#define CAN_TXBAR_AR18 (_U_(0x1) << CAN_TXBAR_AR18_Pos)
-#define CAN_TXBAR_AR19_Pos 19 /**< \brief (CAN_TXBAR) Add Request 19 */
-#define CAN_TXBAR_AR19 (_U_(0x1) << CAN_TXBAR_AR19_Pos)
-#define CAN_TXBAR_AR20_Pos 20 /**< \brief (CAN_TXBAR) Add Request 20 */
-#define CAN_TXBAR_AR20 (_U_(0x1) << CAN_TXBAR_AR20_Pos)
-#define CAN_TXBAR_AR21_Pos 21 /**< \brief (CAN_TXBAR) Add Request 21 */
-#define CAN_TXBAR_AR21 (_U_(0x1) << CAN_TXBAR_AR21_Pos)
-#define CAN_TXBAR_AR22_Pos 22 /**< \brief (CAN_TXBAR) Add Request 22 */
-#define CAN_TXBAR_AR22 (_U_(0x1) << CAN_TXBAR_AR22_Pos)
-#define CAN_TXBAR_AR23_Pos 23 /**< \brief (CAN_TXBAR) Add Request 23 */
-#define CAN_TXBAR_AR23 (_U_(0x1) << CAN_TXBAR_AR23_Pos)
-#define CAN_TXBAR_AR24_Pos 24 /**< \brief (CAN_TXBAR) Add Request 24 */
-#define CAN_TXBAR_AR24 (_U_(0x1) << CAN_TXBAR_AR24_Pos)
-#define CAN_TXBAR_AR25_Pos 25 /**< \brief (CAN_TXBAR) Add Request 25 */
-#define CAN_TXBAR_AR25 (_U_(0x1) << CAN_TXBAR_AR25_Pos)
-#define CAN_TXBAR_AR26_Pos 26 /**< \brief (CAN_TXBAR) Add Request 26 */
-#define CAN_TXBAR_AR26 (_U_(0x1) << CAN_TXBAR_AR26_Pos)
-#define CAN_TXBAR_AR27_Pos 27 /**< \brief (CAN_TXBAR) Add Request 27 */
-#define CAN_TXBAR_AR27 (_U_(0x1) << CAN_TXBAR_AR27_Pos)
-#define CAN_TXBAR_AR28_Pos 28 /**< \brief (CAN_TXBAR) Add Request 28 */
-#define CAN_TXBAR_AR28 (_U_(0x1) << CAN_TXBAR_AR28_Pos)
-#define CAN_TXBAR_AR29_Pos 29 /**< \brief (CAN_TXBAR) Add Request 29 */
-#define CAN_TXBAR_AR29 (_U_(0x1) << CAN_TXBAR_AR29_Pos)
-#define CAN_TXBAR_AR30_Pos 30 /**< \brief (CAN_TXBAR) Add Request 30 */
-#define CAN_TXBAR_AR30 (_U_(0x1) << CAN_TXBAR_AR30_Pos)
-#define CAN_TXBAR_AR31_Pos 31 /**< \brief (CAN_TXBAR) Add Request 31 */
-#define CAN_TXBAR_AR31 (_U_(0x1) << CAN_TXBAR_AR31_Pos)
-#define CAN_TXBAR_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBAR) MASK Register */
-
-/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CR0:1; /*!< bit: 0 Cancellation Request 0 */
- uint32_t CR1:1; /*!< bit: 1 Cancellation Request 1 */
- uint32_t CR2:1; /*!< bit: 2 Cancellation Request 2 */
- uint32_t CR3:1; /*!< bit: 3 Cancellation Request 3 */
- uint32_t CR4:1; /*!< bit: 4 Cancellation Request 4 */
- uint32_t CR5:1; /*!< bit: 5 Cancellation Request 5 */
- uint32_t CR6:1; /*!< bit: 6 Cancellation Request 6 */
- uint32_t CR7:1; /*!< bit: 7 Cancellation Request 7 */
- uint32_t CR8:1; /*!< bit: 8 Cancellation Request 8 */
- uint32_t CR9:1; /*!< bit: 9 Cancellation Request 9 */
- uint32_t CR10:1; /*!< bit: 10 Cancellation Request 10 */
- uint32_t CR11:1; /*!< bit: 11 Cancellation Request 11 */
- uint32_t CR12:1; /*!< bit: 12 Cancellation Request 12 */
- uint32_t CR13:1; /*!< bit: 13 Cancellation Request 13 */
- uint32_t CR14:1; /*!< bit: 14 Cancellation Request 14 */
- uint32_t CR15:1; /*!< bit: 15 Cancellation Request 15 */
- uint32_t CR16:1; /*!< bit: 16 Cancellation Request 16 */
- uint32_t CR17:1; /*!< bit: 17 Cancellation Request 17 */
- uint32_t CR18:1; /*!< bit: 18 Cancellation Request 18 */
- uint32_t CR19:1; /*!< bit: 19 Cancellation Request 19 */
- uint32_t CR20:1; /*!< bit: 20 Cancellation Request 20 */
- uint32_t CR21:1; /*!< bit: 21 Cancellation Request 21 */
- uint32_t CR22:1; /*!< bit: 22 Cancellation Request 22 */
- uint32_t CR23:1; /*!< bit: 23 Cancellation Request 23 */
- uint32_t CR24:1; /*!< bit: 24 Cancellation Request 24 */
- uint32_t CR25:1; /*!< bit: 25 Cancellation Request 25 */
- uint32_t CR26:1; /*!< bit: 26 Cancellation Request 26 */
- uint32_t CR27:1; /*!< bit: 27 Cancellation Request 27 */
- uint32_t CR28:1; /*!< bit: 28 Cancellation Request 28 */
- uint32_t CR29:1; /*!< bit: 29 Cancellation Request 29 */
- uint32_t CR30:1; /*!< bit: 30 Cancellation Request 30 */
- uint32_t CR31:1; /*!< bit: 31 Cancellation Request 31 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBCR_OFFSET 0xD4 /**< \brief (CAN_TXBCR offset) Tx Buffer Cancellation Request */
-#define CAN_TXBCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCR reset_value) Tx Buffer Cancellation Request */
-
-#define CAN_TXBCR_CR0_Pos 0 /**< \brief (CAN_TXBCR) Cancellation Request 0 */
-#define CAN_TXBCR_CR0 (_U_(0x1) << CAN_TXBCR_CR0_Pos)
-#define CAN_TXBCR_CR1_Pos 1 /**< \brief (CAN_TXBCR) Cancellation Request 1 */
-#define CAN_TXBCR_CR1 (_U_(0x1) << CAN_TXBCR_CR1_Pos)
-#define CAN_TXBCR_CR2_Pos 2 /**< \brief (CAN_TXBCR) Cancellation Request 2 */
-#define CAN_TXBCR_CR2 (_U_(0x1) << CAN_TXBCR_CR2_Pos)
-#define CAN_TXBCR_CR3_Pos 3 /**< \brief (CAN_TXBCR) Cancellation Request 3 */
-#define CAN_TXBCR_CR3 (_U_(0x1) << CAN_TXBCR_CR3_Pos)
-#define CAN_TXBCR_CR4_Pos 4 /**< \brief (CAN_TXBCR) Cancellation Request 4 */
-#define CAN_TXBCR_CR4 (_U_(0x1) << CAN_TXBCR_CR4_Pos)
-#define CAN_TXBCR_CR5_Pos 5 /**< \brief (CAN_TXBCR) Cancellation Request 5 */
-#define CAN_TXBCR_CR5 (_U_(0x1) << CAN_TXBCR_CR5_Pos)
-#define CAN_TXBCR_CR6_Pos 6 /**< \brief (CAN_TXBCR) Cancellation Request 6 */
-#define CAN_TXBCR_CR6 (_U_(0x1) << CAN_TXBCR_CR6_Pos)
-#define CAN_TXBCR_CR7_Pos 7 /**< \brief (CAN_TXBCR) Cancellation Request 7 */
-#define CAN_TXBCR_CR7 (_U_(0x1) << CAN_TXBCR_CR7_Pos)
-#define CAN_TXBCR_CR8_Pos 8 /**< \brief (CAN_TXBCR) Cancellation Request 8 */
-#define CAN_TXBCR_CR8 (_U_(0x1) << CAN_TXBCR_CR8_Pos)
-#define CAN_TXBCR_CR9_Pos 9 /**< \brief (CAN_TXBCR) Cancellation Request 9 */
-#define CAN_TXBCR_CR9 (_U_(0x1) << CAN_TXBCR_CR9_Pos)
-#define CAN_TXBCR_CR10_Pos 10 /**< \brief (CAN_TXBCR) Cancellation Request 10 */
-#define CAN_TXBCR_CR10 (_U_(0x1) << CAN_TXBCR_CR10_Pos)
-#define CAN_TXBCR_CR11_Pos 11 /**< \brief (CAN_TXBCR) Cancellation Request 11 */
-#define CAN_TXBCR_CR11 (_U_(0x1) << CAN_TXBCR_CR11_Pos)
-#define CAN_TXBCR_CR12_Pos 12 /**< \brief (CAN_TXBCR) Cancellation Request 12 */
-#define CAN_TXBCR_CR12 (_U_(0x1) << CAN_TXBCR_CR12_Pos)
-#define CAN_TXBCR_CR13_Pos 13 /**< \brief (CAN_TXBCR) Cancellation Request 13 */
-#define CAN_TXBCR_CR13 (_U_(0x1) << CAN_TXBCR_CR13_Pos)
-#define CAN_TXBCR_CR14_Pos 14 /**< \brief (CAN_TXBCR) Cancellation Request 14 */
-#define CAN_TXBCR_CR14 (_U_(0x1) << CAN_TXBCR_CR14_Pos)
-#define CAN_TXBCR_CR15_Pos 15 /**< \brief (CAN_TXBCR) Cancellation Request 15 */
-#define CAN_TXBCR_CR15 (_U_(0x1) << CAN_TXBCR_CR15_Pos)
-#define CAN_TXBCR_CR16_Pos 16 /**< \brief (CAN_TXBCR) Cancellation Request 16 */
-#define CAN_TXBCR_CR16 (_U_(0x1) << CAN_TXBCR_CR16_Pos)
-#define CAN_TXBCR_CR17_Pos 17 /**< \brief (CAN_TXBCR) Cancellation Request 17 */
-#define CAN_TXBCR_CR17 (_U_(0x1) << CAN_TXBCR_CR17_Pos)
-#define CAN_TXBCR_CR18_Pos 18 /**< \brief (CAN_TXBCR) Cancellation Request 18 */
-#define CAN_TXBCR_CR18 (_U_(0x1) << CAN_TXBCR_CR18_Pos)
-#define CAN_TXBCR_CR19_Pos 19 /**< \brief (CAN_TXBCR) Cancellation Request 19 */
-#define CAN_TXBCR_CR19 (_U_(0x1) << CAN_TXBCR_CR19_Pos)
-#define CAN_TXBCR_CR20_Pos 20 /**< \brief (CAN_TXBCR) Cancellation Request 20 */
-#define CAN_TXBCR_CR20 (_U_(0x1) << CAN_TXBCR_CR20_Pos)
-#define CAN_TXBCR_CR21_Pos 21 /**< \brief (CAN_TXBCR) Cancellation Request 21 */
-#define CAN_TXBCR_CR21 (_U_(0x1) << CAN_TXBCR_CR21_Pos)
-#define CAN_TXBCR_CR22_Pos 22 /**< \brief (CAN_TXBCR) Cancellation Request 22 */
-#define CAN_TXBCR_CR22 (_U_(0x1) << CAN_TXBCR_CR22_Pos)
-#define CAN_TXBCR_CR23_Pos 23 /**< \brief (CAN_TXBCR) Cancellation Request 23 */
-#define CAN_TXBCR_CR23 (_U_(0x1) << CAN_TXBCR_CR23_Pos)
-#define CAN_TXBCR_CR24_Pos 24 /**< \brief (CAN_TXBCR) Cancellation Request 24 */
-#define CAN_TXBCR_CR24 (_U_(0x1) << CAN_TXBCR_CR24_Pos)
-#define CAN_TXBCR_CR25_Pos 25 /**< \brief (CAN_TXBCR) Cancellation Request 25 */
-#define CAN_TXBCR_CR25 (_U_(0x1) << CAN_TXBCR_CR25_Pos)
-#define CAN_TXBCR_CR26_Pos 26 /**< \brief (CAN_TXBCR) Cancellation Request 26 */
-#define CAN_TXBCR_CR26 (_U_(0x1) << CAN_TXBCR_CR26_Pos)
-#define CAN_TXBCR_CR27_Pos 27 /**< \brief (CAN_TXBCR) Cancellation Request 27 */
-#define CAN_TXBCR_CR27 (_U_(0x1) << CAN_TXBCR_CR27_Pos)
-#define CAN_TXBCR_CR28_Pos 28 /**< \brief (CAN_TXBCR) Cancellation Request 28 */
-#define CAN_TXBCR_CR28 (_U_(0x1) << CAN_TXBCR_CR28_Pos)
-#define CAN_TXBCR_CR29_Pos 29 /**< \brief (CAN_TXBCR) Cancellation Request 29 */
-#define CAN_TXBCR_CR29 (_U_(0x1) << CAN_TXBCR_CR29_Pos)
-#define CAN_TXBCR_CR30_Pos 30 /**< \brief (CAN_TXBCR) Cancellation Request 30 */
-#define CAN_TXBCR_CR30 (_U_(0x1) << CAN_TXBCR_CR30_Pos)
-#define CAN_TXBCR_CR31_Pos 31 /**< \brief (CAN_TXBCR) Cancellation Request 31 */
-#define CAN_TXBCR_CR31 (_U_(0x1) << CAN_TXBCR_CR31_Pos)
-#define CAN_TXBCR_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCR) MASK Register */
-
-/* -------- CAN_TXBTO : (CAN Offset: 0xD8) (R/ 32) Tx Buffer Transmission Occurred -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TO0:1; /*!< bit: 0 Transmission Occurred 0 */
- uint32_t TO1:1; /*!< bit: 1 Transmission Occurred 1 */
- uint32_t TO2:1; /*!< bit: 2 Transmission Occurred 2 */
- uint32_t TO3:1; /*!< bit: 3 Transmission Occurred 3 */
- uint32_t TO4:1; /*!< bit: 4 Transmission Occurred 4 */
- uint32_t TO5:1; /*!< bit: 5 Transmission Occurred 5 */
- uint32_t TO6:1; /*!< bit: 6 Transmission Occurred 6 */
- uint32_t TO7:1; /*!< bit: 7 Transmission Occurred 7 */
- uint32_t TO8:1; /*!< bit: 8 Transmission Occurred 8 */
- uint32_t TO9:1; /*!< bit: 9 Transmission Occurred 9 */
- uint32_t TO10:1; /*!< bit: 10 Transmission Occurred 10 */
- uint32_t TO11:1; /*!< bit: 11 Transmission Occurred 11 */
- uint32_t TO12:1; /*!< bit: 12 Transmission Occurred 12 */
- uint32_t TO13:1; /*!< bit: 13 Transmission Occurred 13 */
- uint32_t TO14:1; /*!< bit: 14 Transmission Occurred 14 */
- uint32_t TO15:1; /*!< bit: 15 Transmission Occurred 15 */
- uint32_t TO16:1; /*!< bit: 16 Transmission Occurred 16 */
- uint32_t TO17:1; /*!< bit: 17 Transmission Occurred 17 */
- uint32_t TO18:1; /*!< bit: 18 Transmission Occurred 18 */
- uint32_t TO19:1; /*!< bit: 19 Transmission Occurred 19 */
- uint32_t TO20:1; /*!< bit: 20 Transmission Occurred 20 */
- uint32_t TO21:1; /*!< bit: 21 Transmission Occurred 21 */
- uint32_t TO22:1; /*!< bit: 22 Transmission Occurred 22 */
- uint32_t TO23:1; /*!< bit: 23 Transmission Occurred 23 */
- uint32_t TO24:1; /*!< bit: 24 Transmission Occurred 24 */
- uint32_t TO25:1; /*!< bit: 25 Transmission Occurred 25 */
- uint32_t TO26:1; /*!< bit: 26 Transmission Occurred 26 */
- uint32_t TO27:1; /*!< bit: 27 Transmission Occurred 27 */
- uint32_t TO28:1; /*!< bit: 28 Transmission Occurred 28 */
- uint32_t TO29:1; /*!< bit: 29 Transmission Occurred 29 */
- uint32_t TO30:1; /*!< bit: 30 Transmission Occurred 30 */
- uint32_t TO31:1; /*!< bit: 31 Transmission Occurred 31 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBTO_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBTO_OFFSET 0xD8 /**< \brief (CAN_TXBTO offset) Tx Buffer Transmission Occurred */
-#define CAN_TXBTO_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBTO reset_value) Tx Buffer Transmission Occurred */
-
-#define CAN_TXBTO_TO0_Pos 0 /**< \brief (CAN_TXBTO) Transmission Occurred 0 */
-#define CAN_TXBTO_TO0 (_U_(0x1) << CAN_TXBTO_TO0_Pos)
-#define CAN_TXBTO_TO1_Pos 1 /**< \brief (CAN_TXBTO) Transmission Occurred 1 */
-#define CAN_TXBTO_TO1 (_U_(0x1) << CAN_TXBTO_TO1_Pos)
-#define CAN_TXBTO_TO2_Pos 2 /**< \brief (CAN_TXBTO) Transmission Occurred 2 */
-#define CAN_TXBTO_TO2 (_U_(0x1) << CAN_TXBTO_TO2_Pos)
-#define CAN_TXBTO_TO3_Pos 3 /**< \brief (CAN_TXBTO) Transmission Occurred 3 */
-#define CAN_TXBTO_TO3 (_U_(0x1) << CAN_TXBTO_TO3_Pos)
-#define CAN_TXBTO_TO4_Pos 4 /**< \brief (CAN_TXBTO) Transmission Occurred 4 */
-#define CAN_TXBTO_TO4 (_U_(0x1) << CAN_TXBTO_TO4_Pos)
-#define CAN_TXBTO_TO5_Pos 5 /**< \brief (CAN_TXBTO) Transmission Occurred 5 */
-#define CAN_TXBTO_TO5 (_U_(0x1) << CAN_TXBTO_TO5_Pos)
-#define CAN_TXBTO_TO6_Pos 6 /**< \brief (CAN_TXBTO) Transmission Occurred 6 */
-#define CAN_TXBTO_TO6 (_U_(0x1) << CAN_TXBTO_TO6_Pos)
-#define CAN_TXBTO_TO7_Pos 7 /**< \brief (CAN_TXBTO) Transmission Occurred 7 */
-#define CAN_TXBTO_TO7 (_U_(0x1) << CAN_TXBTO_TO7_Pos)
-#define CAN_TXBTO_TO8_Pos 8 /**< \brief (CAN_TXBTO) Transmission Occurred 8 */
-#define CAN_TXBTO_TO8 (_U_(0x1) << CAN_TXBTO_TO8_Pos)
-#define CAN_TXBTO_TO9_Pos 9 /**< \brief (CAN_TXBTO) Transmission Occurred 9 */
-#define CAN_TXBTO_TO9 (_U_(0x1) << CAN_TXBTO_TO9_Pos)
-#define CAN_TXBTO_TO10_Pos 10 /**< \brief (CAN_TXBTO) Transmission Occurred 10 */
-#define CAN_TXBTO_TO10 (_U_(0x1) << CAN_TXBTO_TO10_Pos)
-#define CAN_TXBTO_TO11_Pos 11 /**< \brief (CAN_TXBTO) Transmission Occurred 11 */
-#define CAN_TXBTO_TO11 (_U_(0x1) << CAN_TXBTO_TO11_Pos)
-#define CAN_TXBTO_TO12_Pos 12 /**< \brief (CAN_TXBTO) Transmission Occurred 12 */
-#define CAN_TXBTO_TO12 (_U_(0x1) << CAN_TXBTO_TO12_Pos)
-#define CAN_TXBTO_TO13_Pos 13 /**< \brief (CAN_TXBTO) Transmission Occurred 13 */
-#define CAN_TXBTO_TO13 (_U_(0x1) << CAN_TXBTO_TO13_Pos)
-#define CAN_TXBTO_TO14_Pos 14 /**< \brief (CAN_TXBTO) Transmission Occurred 14 */
-#define CAN_TXBTO_TO14 (_U_(0x1) << CAN_TXBTO_TO14_Pos)
-#define CAN_TXBTO_TO15_Pos 15 /**< \brief (CAN_TXBTO) Transmission Occurred 15 */
-#define CAN_TXBTO_TO15 (_U_(0x1) << CAN_TXBTO_TO15_Pos)
-#define CAN_TXBTO_TO16_Pos 16 /**< \brief (CAN_TXBTO) Transmission Occurred 16 */
-#define CAN_TXBTO_TO16 (_U_(0x1) << CAN_TXBTO_TO16_Pos)
-#define CAN_TXBTO_TO17_Pos 17 /**< \brief (CAN_TXBTO) Transmission Occurred 17 */
-#define CAN_TXBTO_TO17 (_U_(0x1) << CAN_TXBTO_TO17_Pos)
-#define CAN_TXBTO_TO18_Pos 18 /**< \brief (CAN_TXBTO) Transmission Occurred 18 */
-#define CAN_TXBTO_TO18 (_U_(0x1) << CAN_TXBTO_TO18_Pos)
-#define CAN_TXBTO_TO19_Pos 19 /**< \brief (CAN_TXBTO) Transmission Occurred 19 */
-#define CAN_TXBTO_TO19 (_U_(0x1) << CAN_TXBTO_TO19_Pos)
-#define CAN_TXBTO_TO20_Pos 20 /**< \brief (CAN_TXBTO) Transmission Occurred 20 */
-#define CAN_TXBTO_TO20 (_U_(0x1) << CAN_TXBTO_TO20_Pos)
-#define CAN_TXBTO_TO21_Pos 21 /**< \brief (CAN_TXBTO) Transmission Occurred 21 */
-#define CAN_TXBTO_TO21 (_U_(0x1) << CAN_TXBTO_TO21_Pos)
-#define CAN_TXBTO_TO22_Pos 22 /**< \brief (CAN_TXBTO) Transmission Occurred 22 */
-#define CAN_TXBTO_TO22 (_U_(0x1) << CAN_TXBTO_TO22_Pos)
-#define CAN_TXBTO_TO23_Pos 23 /**< \brief (CAN_TXBTO) Transmission Occurred 23 */
-#define CAN_TXBTO_TO23 (_U_(0x1) << CAN_TXBTO_TO23_Pos)
-#define CAN_TXBTO_TO24_Pos 24 /**< \brief (CAN_TXBTO) Transmission Occurred 24 */
-#define CAN_TXBTO_TO24 (_U_(0x1) << CAN_TXBTO_TO24_Pos)
-#define CAN_TXBTO_TO25_Pos 25 /**< \brief (CAN_TXBTO) Transmission Occurred 25 */
-#define CAN_TXBTO_TO25 (_U_(0x1) << CAN_TXBTO_TO25_Pos)
-#define CAN_TXBTO_TO26_Pos 26 /**< \brief (CAN_TXBTO) Transmission Occurred 26 */
-#define CAN_TXBTO_TO26 (_U_(0x1) << CAN_TXBTO_TO26_Pos)
-#define CAN_TXBTO_TO27_Pos 27 /**< \brief (CAN_TXBTO) Transmission Occurred 27 */
-#define CAN_TXBTO_TO27 (_U_(0x1) << CAN_TXBTO_TO27_Pos)
-#define CAN_TXBTO_TO28_Pos 28 /**< \brief (CAN_TXBTO) Transmission Occurred 28 */
-#define CAN_TXBTO_TO28 (_U_(0x1) << CAN_TXBTO_TO28_Pos)
-#define CAN_TXBTO_TO29_Pos 29 /**< \brief (CAN_TXBTO) Transmission Occurred 29 */
-#define CAN_TXBTO_TO29 (_U_(0x1) << CAN_TXBTO_TO29_Pos)
-#define CAN_TXBTO_TO30_Pos 30 /**< \brief (CAN_TXBTO) Transmission Occurred 30 */
-#define CAN_TXBTO_TO30 (_U_(0x1) << CAN_TXBTO_TO30_Pos)
-#define CAN_TXBTO_TO31_Pos 31 /**< \brief (CAN_TXBTO) Transmission Occurred 31 */
-#define CAN_TXBTO_TO31 (_U_(0x1) << CAN_TXBTO_TO31_Pos)
-#define CAN_TXBTO_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBTO) MASK Register */
-
-/* -------- CAN_TXBCF : (CAN Offset: 0xDC) (R/ 32) Tx Buffer Cancellation Finished -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CF0:1; /*!< bit: 0 Tx Buffer Cancellation Finished 0 */
- uint32_t CF1:1; /*!< bit: 1 Tx Buffer Cancellation Finished 1 */
- uint32_t CF2:1; /*!< bit: 2 Tx Buffer Cancellation Finished 2 */
- uint32_t CF3:1; /*!< bit: 3 Tx Buffer Cancellation Finished 3 */
- uint32_t CF4:1; /*!< bit: 4 Tx Buffer Cancellation Finished 4 */
- uint32_t CF5:1; /*!< bit: 5 Tx Buffer Cancellation Finished 5 */
- uint32_t CF6:1; /*!< bit: 6 Tx Buffer Cancellation Finished 6 */
- uint32_t CF7:1; /*!< bit: 7 Tx Buffer Cancellation Finished 7 */
- uint32_t CF8:1; /*!< bit: 8 Tx Buffer Cancellation Finished 8 */
- uint32_t CF9:1; /*!< bit: 9 Tx Buffer Cancellation Finished 9 */
- uint32_t CF10:1; /*!< bit: 10 Tx Buffer Cancellation Finished 10 */
- uint32_t CF11:1; /*!< bit: 11 Tx Buffer Cancellation Finished 11 */
- uint32_t CF12:1; /*!< bit: 12 Tx Buffer Cancellation Finished 12 */
- uint32_t CF13:1; /*!< bit: 13 Tx Buffer Cancellation Finished 13 */
- uint32_t CF14:1; /*!< bit: 14 Tx Buffer Cancellation Finished 14 */
- uint32_t CF15:1; /*!< bit: 15 Tx Buffer Cancellation Finished 15 */
- uint32_t CF16:1; /*!< bit: 16 Tx Buffer Cancellation Finished 16 */
- uint32_t CF17:1; /*!< bit: 17 Tx Buffer Cancellation Finished 17 */
- uint32_t CF18:1; /*!< bit: 18 Tx Buffer Cancellation Finished 18 */
- uint32_t CF19:1; /*!< bit: 19 Tx Buffer Cancellation Finished 19 */
- uint32_t CF20:1; /*!< bit: 20 Tx Buffer Cancellation Finished 20 */
- uint32_t CF21:1; /*!< bit: 21 Tx Buffer Cancellation Finished 21 */
- uint32_t CF22:1; /*!< bit: 22 Tx Buffer Cancellation Finished 22 */
- uint32_t CF23:1; /*!< bit: 23 Tx Buffer Cancellation Finished 23 */
- uint32_t CF24:1; /*!< bit: 24 Tx Buffer Cancellation Finished 24 */
- uint32_t CF25:1; /*!< bit: 25 Tx Buffer Cancellation Finished 25 */
- uint32_t CF26:1; /*!< bit: 26 Tx Buffer Cancellation Finished 26 */
- uint32_t CF27:1; /*!< bit: 27 Tx Buffer Cancellation Finished 27 */
- uint32_t CF28:1; /*!< bit: 28 Tx Buffer Cancellation Finished 28 */
- uint32_t CF29:1; /*!< bit: 29 Tx Buffer Cancellation Finished 29 */
- uint32_t CF30:1; /*!< bit: 30 Tx Buffer Cancellation Finished 30 */
- uint32_t CF31:1; /*!< bit: 31 Tx Buffer Cancellation Finished 31 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBCF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBCF_OFFSET 0xDC /**< \brief (CAN_TXBCF offset) Tx Buffer Cancellation Finished */
-#define CAN_TXBCF_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCF reset_value) Tx Buffer Cancellation Finished */
-
-#define CAN_TXBCF_CF0_Pos 0 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 0 */
-#define CAN_TXBCF_CF0 (_U_(0x1) << CAN_TXBCF_CF0_Pos)
-#define CAN_TXBCF_CF1_Pos 1 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 1 */
-#define CAN_TXBCF_CF1 (_U_(0x1) << CAN_TXBCF_CF1_Pos)
-#define CAN_TXBCF_CF2_Pos 2 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 2 */
-#define CAN_TXBCF_CF2 (_U_(0x1) << CAN_TXBCF_CF2_Pos)
-#define CAN_TXBCF_CF3_Pos 3 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 3 */
-#define CAN_TXBCF_CF3 (_U_(0x1) << CAN_TXBCF_CF3_Pos)
-#define CAN_TXBCF_CF4_Pos 4 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 4 */
-#define CAN_TXBCF_CF4 (_U_(0x1) << CAN_TXBCF_CF4_Pos)
-#define CAN_TXBCF_CF5_Pos 5 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 5 */
-#define CAN_TXBCF_CF5 (_U_(0x1) << CAN_TXBCF_CF5_Pos)
-#define CAN_TXBCF_CF6_Pos 6 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 6 */
-#define CAN_TXBCF_CF6 (_U_(0x1) << CAN_TXBCF_CF6_Pos)
-#define CAN_TXBCF_CF7_Pos 7 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 7 */
-#define CAN_TXBCF_CF7 (_U_(0x1) << CAN_TXBCF_CF7_Pos)
-#define CAN_TXBCF_CF8_Pos 8 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 8 */
-#define CAN_TXBCF_CF8 (_U_(0x1) << CAN_TXBCF_CF8_Pos)
-#define CAN_TXBCF_CF9_Pos 9 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 9 */
-#define CAN_TXBCF_CF9 (_U_(0x1) << CAN_TXBCF_CF9_Pos)
-#define CAN_TXBCF_CF10_Pos 10 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 10 */
-#define CAN_TXBCF_CF10 (_U_(0x1) << CAN_TXBCF_CF10_Pos)
-#define CAN_TXBCF_CF11_Pos 11 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 11 */
-#define CAN_TXBCF_CF11 (_U_(0x1) << CAN_TXBCF_CF11_Pos)
-#define CAN_TXBCF_CF12_Pos 12 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 12 */
-#define CAN_TXBCF_CF12 (_U_(0x1) << CAN_TXBCF_CF12_Pos)
-#define CAN_TXBCF_CF13_Pos 13 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 13 */
-#define CAN_TXBCF_CF13 (_U_(0x1) << CAN_TXBCF_CF13_Pos)
-#define CAN_TXBCF_CF14_Pos 14 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 14 */
-#define CAN_TXBCF_CF14 (_U_(0x1) << CAN_TXBCF_CF14_Pos)
-#define CAN_TXBCF_CF15_Pos 15 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 15 */
-#define CAN_TXBCF_CF15 (_U_(0x1) << CAN_TXBCF_CF15_Pos)
-#define CAN_TXBCF_CF16_Pos 16 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 16 */
-#define CAN_TXBCF_CF16 (_U_(0x1) << CAN_TXBCF_CF16_Pos)
-#define CAN_TXBCF_CF17_Pos 17 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 17 */
-#define CAN_TXBCF_CF17 (_U_(0x1) << CAN_TXBCF_CF17_Pos)
-#define CAN_TXBCF_CF18_Pos 18 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 18 */
-#define CAN_TXBCF_CF18 (_U_(0x1) << CAN_TXBCF_CF18_Pos)
-#define CAN_TXBCF_CF19_Pos 19 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 19 */
-#define CAN_TXBCF_CF19 (_U_(0x1) << CAN_TXBCF_CF19_Pos)
-#define CAN_TXBCF_CF20_Pos 20 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 20 */
-#define CAN_TXBCF_CF20 (_U_(0x1) << CAN_TXBCF_CF20_Pos)
-#define CAN_TXBCF_CF21_Pos 21 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 21 */
-#define CAN_TXBCF_CF21 (_U_(0x1) << CAN_TXBCF_CF21_Pos)
-#define CAN_TXBCF_CF22_Pos 22 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 22 */
-#define CAN_TXBCF_CF22 (_U_(0x1) << CAN_TXBCF_CF22_Pos)
-#define CAN_TXBCF_CF23_Pos 23 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 23 */
-#define CAN_TXBCF_CF23 (_U_(0x1) << CAN_TXBCF_CF23_Pos)
-#define CAN_TXBCF_CF24_Pos 24 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 24 */
-#define CAN_TXBCF_CF24 (_U_(0x1) << CAN_TXBCF_CF24_Pos)
-#define CAN_TXBCF_CF25_Pos 25 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 25 */
-#define CAN_TXBCF_CF25 (_U_(0x1) << CAN_TXBCF_CF25_Pos)
-#define CAN_TXBCF_CF26_Pos 26 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 26 */
-#define CAN_TXBCF_CF26 (_U_(0x1) << CAN_TXBCF_CF26_Pos)
-#define CAN_TXBCF_CF27_Pos 27 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 27 */
-#define CAN_TXBCF_CF27 (_U_(0x1) << CAN_TXBCF_CF27_Pos)
-#define CAN_TXBCF_CF28_Pos 28 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 28 */
-#define CAN_TXBCF_CF28 (_U_(0x1) << CAN_TXBCF_CF28_Pos)
-#define CAN_TXBCF_CF29_Pos 29 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 29 */
-#define CAN_TXBCF_CF29 (_U_(0x1) << CAN_TXBCF_CF29_Pos)
-#define CAN_TXBCF_CF30_Pos 30 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 30 */
-#define CAN_TXBCF_CF30 (_U_(0x1) << CAN_TXBCF_CF30_Pos)
-#define CAN_TXBCF_CF31_Pos 31 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 31 */
-#define CAN_TXBCF_CF31 (_U_(0x1) << CAN_TXBCF_CF31_Pos)
-#define CAN_TXBCF_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCF) MASK Register */
-
-/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TIE0:1; /*!< bit: 0 Transmission Interrupt Enable 0 */
- uint32_t TIE1:1; /*!< bit: 1 Transmission Interrupt Enable 1 */
- uint32_t TIE2:1; /*!< bit: 2 Transmission Interrupt Enable 2 */
- uint32_t TIE3:1; /*!< bit: 3 Transmission Interrupt Enable 3 */
- uint32_t TIE4:1; /*!< bit: 4 Transmission Interrupt Enable 4 */
- uint32_t TIE5:1; /*!< bit: 5 Transmission Interrupt Enable 5 */
- uint32_t TIE6:1; /*!< bit: 6 Transmission Interrupt Enable 6 */
- uint32_t TIE7:1; /*!< bit: 7 Transmission Interrupt Enable 7 */
- uint32_t TIE8:1; /*!< bit: 8 Transmission Interrupt Enable 8 */
- uint32_t TIE9:1; /*!< bit: 9 Transmission Interrupt Enable 9 */
- uint32_t TIE10:1; /*!< bit: 10 Transmission Interrupt Enable 10 */
- uint32_t TIE11:1; /*!< bit: 11 Transmission Interrupt Enable 11 */
- uint32_t TIE12:1; /*!< bit: 12 Transmission Interrupt Enable 12 */
- uint32_t TIE13:1; /*!< bit: 13 Transmission Interrupt Enable 13 */
- uint32_t TIE14:1; /*!< bit: 14 Transmission Interrupt Enable 14 */
- uint32_t TIE15:1; /*!< bit: 15 Transmission Interrupt Enable 15 */
- uint32_t TIE16:1; /*!< bit: 16 Transmission Interrupt Enable 16 */
- uint32_t TIE17:1; /*!< bit: 17 Transmission Interrupt Enable 17 */
- uint32_t TIE18:1; /*!< bit: 18 Transmission Interrupt Enable 18 */
- uint32_t TIE19:1; /*!< bit: 19 Transmission Interrupt Enable 19 */
- uint32_t TIE20:1; /*!< bit: 20 Transmission Interrupt Enable 20 */
- uint32_t TIE21:1; /*!< bit: 21 Transmission Interrupt Enable 21 */
- uint32_t TIE22:1; /*!< bit: 22 Transmission Interrupt Enable 22 */
- uint32_t TIE23:1; /*!< bit: 23 Transmission Interrupt Enable 23 */
- uint32_t TIE24:1; /*!< bit: 24 Transmission Interrupt Enable 24 */
- uint32_t TIE25:1; /*!< bit: 25 Transmission Interrupt Enable 25 */
- uint32_t TIE26:1; /*!< bit: 26 Transmission Interrupt Enable 26 */
- uint32_t TIE27:1; /*!< bit: 27 Transmission Interrupt Enable 27 */
- uint32_t TIE28:1; /*!< bit: 28 Transmission Interrupt Enable 28 */
- uint32_t TIE29:1; /*!< bit: 29 Transmission Interrupt Enable 29 */
- uint32_t TIE30:1; /*!< bit: 30 Transmission Interrupt Enable 30 */
- uint32_t TIE31:1; /*!< bit: 31 Transmission Interrupt Enable 31 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBTIE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBTIE_OFFSET 0xE0 /**< \brief (CAN_TXBTIE offset) Tx Buffer Transmission Interrupt Enable */
-#define CAN_TXBTIE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBTIE reset_value) Tx Buffer Transmission Interrupt Enable */
-
-#define CAN_TXBTIE_TIE0_Pos 0 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 0 */
-#define CAN_TXBTIE_TIE0 (_U_(0x1) << CAN_TXBTIE_TIE0_Pos)
-#define CAN_TXBTIE_TIE1_Pos 1 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 1 */
-#define CAN_TXBTIE_TIE1 (_U_(0x1) << CAN_TXBTIE_TIE1_Pos)
-#define CAN_TXBTIE_TIE2_Pos 2 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 2 */
-#define CAN_TXBTIE_TIE2 (_U_(0x1) << CAN_TXBTIE_TIE2_Pos)
-#define CAN_TXBTIE_TIE3_Pos 3 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 3 */
-#define CAN_TXBTIE_TIE3 (_U_(0x1) << CAN_TXBTIE_TIE3_Pos)
-#define CAN_TXBTIE_TIE4_Pos 4 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 4 */
-#define CAN_TXBTIE_TIE4 (_U_(0x1) << CAN_TXBTIE_TIE4_Pos)
-#define CAN_TXBTIE_TIE5_Pos 5 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 5 */
-#define CAN_TXBTIE_TIE5 (_U_(0x1) << CAN_TXBTIE_TIE5_Pos)
-#define CAN_TXBTIE_TIE6_Pos 6 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 6 */
-#define CAN_TXBTIE_TIE6 (_U_(0x1) << CAN_TXBTIE_TIE6_Pos)
-#define CAN_TXBTIE_TIE7_Pos 7 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 7 */
-#define CAN_TXBTIE_TIE7 (_U_(0x1) << CAN_TXBTIE_TIE7_Pos)
-#define CAN_TXBTIE_TIE8_Pos 8 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 8 */
-#define CAN_TXBTIE_TIE8 (_U_(0x1) << CAN_TXBTIE_TIE8_Pos)
-#define CAN_TXBTIE_TIE9_Pos 9 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 9 */
-#define CAN_TXBTIE_TIE9 (_U_(0x1) << CAN_TXBTIE_TIE9_Pos)
-#define CAN_TXBTIE_TIE10_Pos 10 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 10 */
-#define CAN_TXBTIE_TIE10 (_U_(0x1) << CAN_TXBTIE_TIE10_Pos)
-#define CAN_TXBTIE_TIE11_Pos 11 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 11 */
-#define CAN_TXBTIE_TIE11 (_U_(0x1) << CAN_TXBTIE_TIE11_Pos)
-#define CAN_TXBTIE_TIE12_Pos 12 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 12 */
-#define CAN_TXBTIE_TIE12 (_U_(0x1) << CAN_TXBTIE_TIE12_Pos)
-#define CAN_TXBTIE_TIE13_Pos 13 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 13 */
-#define CAN_TXBTIE_TIE13 (_U_(0x1) << CAN_TXBTIE_TIE13_Pos)
-#define CAN_TXBTIE_TIE14_Pos 14 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 14 */
-#define CAN_TXBTIE_TIE14 (_U_(0x1) << CAN_TXBTIE_TIE14_Pos)
-#define CAN_TXBTIE_TIE15_Pos 15 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 15 */
-#define CAN_TXBTIE_TIE15 (_U_(0x1) << CAN_TXBTIE_TIE15_Pos)
-#define CAN_TXBTIE_TIE16_Pos 16 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 16 */
-#define CAN_TXBTIE_TIE16 (_U_(0x1) << CAN_TXBTIE_TIE16_Pos)
-#define CAN_TXBTIE_TIE17_Pos 17 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 17 */
-#define CAN_TXBTIE_TIE17 (_U_(0x1) << CAN_TXBTIE_TIE17_Pos)
-#define CAN_TXBTIE_TIE18_Pos 18 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 18 */
-#define CAN_TXBTIE_TIE18 (_U_(0x1) << CAN_TXBTIE_TIE18_Pos)
-#define CAN_TXBTIE_TIE19_Pos 19 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 19 */
-#define CAN_TXBTIE_TIE19 (_U_(0x1) << CAN_TXBTIE_TIE19_Pos)
-#define CAN_TXBTIE_TIE20_Pos 20 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 20 */
-#define CAN_TXBTIE_TIE20 (_U_(0x1) << CAN_TXBTIE_TIE20_Pos)
-#define CAN_TXBTIE_TIE21_Pos 21 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 21 */
-#define CAN_TXBTIE_TIE21 (_U_(0x1) << CAN_TXBTIE_TIE21_Pos)
-#define CAN_TXBTIE_TIE22_Pos 22 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 22 */
-#define CAN_TXBTIE_TIE22 (_U_(0x1) << CAN_TXBTIE_TIE22_Pos)
-#define CAN_TXBTIE_TIE23_Pos 23 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 23 */
-#define CAN_TXBTIE_TIE23 (_U_(0x1) << CAN_TXBTIE_TIE23_Pos)
-#define CAN_TXBTIE_TIE24_Pos 24 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 24 */
-#define CAN_TXBTIE_TIE24 (_U_(0x1) << CAN_TXBTIE_TIE24_Pos)
-#define CAN_TXBTIE_TIE25_Pos 25 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 25 */
-#define CAN_TXBTIE_TIE25 (_U_(0x1) << CAN_TXBTIE_TIE25_Pos)
-#define CAN_TXBTIE_TIE26_Pos 26 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 26 */
-#define CAN_TXBTIE_TIE26 (_U_(0x1) << CAN_TXBTIE_TIE26_Pos)
-#define CAN_TXBTIE_TIE27_Pos 27 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 27 */
-#define CAN_TXBTIE_TIE27 (_U_(0x1) << CAN_TXBTIE_TIE27_Pos)
-#define CAN_TXBTIE_TIE28_Pos 28 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 28 */
-#define CAN_TXBTIE_TIE28 (_U_(0x1) << CAN_TXBTIE_TIE28_Pos)
-#define CAN_TXBTIE_TIE29_Pos 29 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 29 */
-#define CAN_TXBTIE_TIE29 (_U_(0x1) << CAN_TXBTIE_TIE29_Pos)
-#define CAN_TXBTIE_TIE30_Pos 30 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 30 */
-#define CAN_TXBTIE_TIE30 (_U_(0x1) << CAN_TXBTIE_TIE30_Pos)
-#define CAN_TXBTIE_TIE31_Pos 31 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 31 */
-#define CAN_TXBTIE_TIE31 (_U_(0x1) << CAN_TXBTIE_TIE31_Pos)
-#define CAN_TXBTIE_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBTIE) MASK Register */
-
-/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CFIE0:1; /*!< bit: 0 Cancellation Finished Interrupt Enable 0 */
- uint32_t CFIE1:1; /*!< bit: 1 Cancellation Finished Interrupt Enable 1 */
- uint32_t CFIE2:1; /*!< bit: 2 Cancellation Finished Interrupt Enable 2 */
- uint32_t CFIE3:1; /*!< bit: 3 Cancellation Finished Interrupt Enable 3 */
- uint32_t CFIE4:1; /*!< bit: 4 Cancellation Finished Interrupt Enable 4 */
- uint32_t CFIE5:1; /*!< bit: 5 Cancellation Finished Interrupt Enable 5 */
- uint32_t CFIE6:1; /*!< bit: 6 Cancellation Finished Interrupt Enable 6 */
- uint32_t CFIE7:1; /*!< bit: 7 Cancellation Finished Interrupt Enable 7 */
- uint32_t CFIE8:1; /*!< bit: 8 Cancellation Finished Interrupt Enable 8 */
- uint32_t CFIE9:1; /*!< bit: 9 Cancellation Finished Interrupt Enable 9 */
- uint32_t CFIE10:1; /*!< bit: 10 Cancellation Finished Interrupt Enable 10 */
- uint32_t CFIE11:1; /*!< bit: 11 Cancellation Finished Interrupt Enable 11 */
- uint32_t CFIE12:1; /*!< bit: 12 Cancellation Finished Interrupt Enable 12 */
- uint32_t CFIE13:1; /*!< bit: 13 Cancellation Finished Interrupt Enable 13 */
- uint32_t CFIE14:1; /*!< bit: 14 Cancellation Finished Interrupt Enable 14 */
- uint32_t CFIE15:1; /*!< bit: 15 Cancellation Finished Interrupt Enable 15 */
- uint32_t CFIE16:1; /*!< bit: 16 Cancellation Finished Interrupt Enable 16 */
- uint32_t CFIE17:1; /*!< bit: 17 Cancellation Finished Interrupt Enable 17 */
- uint32_t CFIE18:1; /*!< bit: 18 Cancellation Finished Interrupt Enable 18 */
- uint32_t CFIE19:1; /*!< bit: 19 Cancellation Finished Interrupt Enable 19 */
- uint32_t CFIE20:1; /*!< bit: 20 Cancellation Finished Interrupt Enable 20 */
- uint32_t CFIE21:1; /*!< bit: 21 Cancellation Finished Interrupt Enable 21 */
- uint32_t CFIE22:1; /*!< bit: 22 Cancellation Finished Interrupt Enable 22 */
- uint32_t CFIE23:1; /*!< bit: 23 Cancellation Finished Interrupt Enable 23 */
- uint32_t CFIE24:1; /*!< bit: 24 Cancellation Finished Interrupt Enable 24 */
- uint32_t CFIE25:1; /*!< bit: 25 Cancellation Finished Interrupt Enable 25 */
- uint32_t CFIE26:1; /*!< bit: 26 Cancellation Finished Interrupt Enable 26 */
- uint32_t CFIE27:1; /*!< bit: 27 Cancellation Finished Interrupt Enable 27 */
- uint32_t CFIE28:1; /*!< bit: 28 Cancellation Finished Interrupt Enable 28 */
- uint32_t CFIE29:1; /*!< bit: 29 Cancellation Finished Interrupt Enable 29 */
- uint32_t CFIE30:1; /*!< bit: 30 Cancellation Finished Interrupt Enable 30 */
- uint32_t CFIE31:1; /*!< bit: 31 Cancellation Finished Interrupt Enable 31 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBCIE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBCIE_OFFSET 0xE4 /**< \brief (CAN_TXBCIE offset) Tx Buffer Cancellation Finished Interrupt Enable */
-#define CAN_TXBCIE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCIE reset_value) Tx Buffer Cancellation Finished Interrupt Enable */
-
-#define CAN_TXBCIE_CFIE0_Pos 0 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 */
-#define CAN_TXBCIE_CFIE0 (_U_(0x1) << CAN_TXBCIE_CFIE0_Pos)
-#define CAN_TXBCIE_CFIE1_Pos 1 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 */
-#define CAN_TXBCIE_CFIE1 (_U_(0x1) << CAN_TXBCIE_CFIE1_Pos)
-#define CAN_TXBCIE_CFIE2_Pos 2 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 */
-#define CAN_TXBCIE_CFIE2 (_U_(0x1) << CAN_TXBCIE_CFIE2_Pos)
-#define CAN_TXBCIE_CFIE3_Pos 3 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 */
-#define CAN_TXBCIE_CFIE3 (_U_(0x1) << CAN_TXBCIE_CFIE3_Pos)
-#define CAN_TXBCIE_CFIE4_Pos 4 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 */
-#define CAN_TXBCIE_CFIE4 (_U_(0x1) << CAN_TXBCIE_CFIE4_Pos)
-#define CAN_TXBCIE_CFIE5_Pos 5 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 */
-#define CAN_TXBCIE_CFIE5 (_U_(0x1) << CAN_TXBCIE_CFIE5_Pos)
-#define CAN_TXBCIE_CFIE6_Pos 6 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 */
-#define CAN_TXBCIE_CFIE6 (_U_(0x1) << CAN_TXBCIE_CFIE6_Pos)
-#define CAN_TXBCIE_CFIE7_Pos 7 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 */
-#define CAN_TXBCIE_CFIE7 (_U_(0x1) << CAN_TXBCIE_CFIE7_Pos)
-#define CAN_TXBCIE_CFIE8_Pos 8 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 */
-#define CAN_TXBCIE_CFIE8 (_U_(0x1) << CAN_TXBCIE_CFIE8_Pos)
-#define CAN_TXBCIE_CFIE9_Pos 9 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 */
-#define CAN_TXBCIE_CFIE9 (_U_(0x1) << CAN_TXBCIE_CFIE9_Pos)
-#define CAN_TXBCIE_CFIE10_Pos 10 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 */
-#define CAN_TXBCIE_CFIE10 (_U_(0x1) << CAN_TXBCIE_CFIE10_Pos)
-#define CAN_TXBCIE_CFIE11_Pos 11 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 */
-#define CAN_TXBCIE_CFIE11 (_U_(0x1) << CAN_TXBCIE_CFIE11_Pos)
-#define CAN_TXBCIE_CFIE12_Pos 12 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 */
-#define CAN_TXBCIE_CFIE12 (_U_(0x1) << CAN_TXBCIE_CFIE12_Pos)
-#define CAN_TXBCIE_CFIE13_Pos 13 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 */
-#define CAN_TXBCIE_CFIE13 (_U_(0x1) << CAN_TXBCIE_CFIE13_Pos)
-#define CAN_TXBCIE_CFIE14_Pos 14 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 */
-#define CAN_TXBCIE_CFIE14 (_U_(0x1) << CAN_TXBCIE_CFIE14_Pos)
-#define CAN_TXBCIE_CFIE15_Pos 15 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 */
-#define CAN_TXBCIE_CFIE15 (_U_(0x1) << CAN_TXBCIE_CFIE15_Pos)
-#define CAN_TXBCIE_CFIE16_Pos 16 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 */
-#define CAN_TXBCIE_CFIE16 (_U_(0x1) << CAN_TXBCIE_CFIE16_Pos)
-#define CAN_TXBCIE_CFIE17_Pos 17 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 */
-#define CAN_TXBCIE_CFIE17 (_U_(0x1) << CAN_TXBCIE_CFIE17_Pos)
-#define CAN_TXBCIE_CFIE18_Pos 18 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 */
-#define CAN_TXBCIE_CFIE18 (_U_(0x1) << CAN_TXBCIE_CFIE18_Pos)
-#define CAN_TXBCIE_CFIE19_Pos 19 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 */
-#define CAN_TXBCIE_CFIE19 (_U_(0x1) << CAN_TXBCIE_CFIE19_Pos)
-#define CAN_TXBCIE_CFIE20_Pos 20 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 */
-#define CAN_TXBCIE_CFIE20 (_U_(0x1) << CAN_TXBCIE_CFIE20_Pos)
-#define CAN_TXBCIE_CFIE21_Pos 21 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 */
-#define CAN_TXBCIE_CFIE21 (_U_(0x1) << CAN_TXBCIE_CFIE21_Pos)
-#define CAN_TXBCIE_CFIE22_Pos 22 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 */
-#define CAN_TXBCIE_CFIE22 (_U_(0x1) << CAN_TXBCIE_CFIE22_Pos)
-#define CAN_TXBCIE_CFIE23_Pos 23 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 */
-#define CAN_TXBCIE_CFIE23 (_U_(0x1) << CAN_TXBCIE_CFIE23_Pos)
-#define CAN_TXBCIE_CFIE24_Pos 24 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 */
-#define CAN_TXBCIE_CFIE24 (_U_(0x1) << CAN_TXBCIE_CFIE24_Pos)
-#define CAN_TXBCIE_CFIE25_Pos 25 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 */
-#define CAN_TXBCIE_CFIE25 (_U_(0x1) << CAN_TXBCIE_CFIE25_Pos)
-#define CAN_TXBCIE_CFIE26_Pos 26 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 */
-#define CAN_TXBCIE_CFIE26 (_U_(0x1) << CAN_TXBCIE_CFIE26_Pos)
-#define CAN_TXBCIE_CFIE27_Pos 27 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 */
-#define CAN_TXBCIE_CFIE27 (_U_(0x1) << CAN_TXBCIE_CFIE27_Pos)
-#define CAN_TXBCIE_CFIE28_Pos 28 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 */
-#define CAN_TXBCIE_CFIE28 (_U_(0x1) << CAN_TXBCIE_CFIE28_Pos)
-#define CAN_TXBCIE_CFIE29_Pos 29 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 */
-#define CAN_TXBCIE_CFIE29 (_U_(0x1) << CAN_TXBCIE_CFIE29_Pos)
-#define CAN_TXBCIE_CFIE30_Pos 30 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 */
-#define CAN_TXBCIE_CFIE30 (_U_(0x1) << CAN_TXBCIE_CFIE30_Pos)
-#define CAN_TXBCIE_CFIE31_Pos 31 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 */
-#define CAN_TXBCIE_CFIE31 (_U_(0x1) << CAN_TXBCIE_CFIE31_Pos)
-#define CAN_TXBCIE_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCIE) MASK Register */
-
-/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EFSA:16; /*!< bit: 0..15 Event FIFO Start Address */
- uint32_t EFS:6; /*!< bit: 16..21 Event FIFO Size */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t EFWM:6; /*!< bit: 24..29 Event FIFO Watermark */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXEFC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXEFC_OFFSET 0xF0 /**< \brief (CAN_TXEFC offset) Tx Event FIFO Configuration */
-#define CAN_TXEFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFC reset_value) Tx Event FIFO Configuration */
-
-#define CAN_TXEFC_EFSA_Pos 0 /**< \brief (CAN_TXEFC) Event FIFO Start Address */
-#define CAN_TXEFC_EFSA_Msk (_U_(0xFFFF) << CAN_TXEFC_EFSA_Pos)
-#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & ((value) << CAN_TXEFC_EFSA_Pos))
-#define CAN_TXEFC_EFS_Pos 16 /**< \brief (CAN_TXEFC) Event FIFO Size */
-#define CAN_TXEFC_EFS_Msk (_U_(0x3F) << CAN_TXEFC_EFS_Pos)
-#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & ((value) << CAN_TXEFC_EFS_Pos))
-#define CAN_TXEFC_EFWM_Pos 24 /**< \brief (CAN_TXEFC) Event FIFO Watermark */
-#define CAN_TXEFC_EFWM_Msk (_U_(0x3F) << CAN_TXEFC_EFWM_Pos)
-#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & ((value) << CAN_TXEFC_EFWM_Pos))
-#define CAN_TXEFC_MASK _U_(0x3F3FFFFF) /**< \brief (CAN_TXEFC) MASK Register */
-
-/* -------- CAN_TXEFS : (CAN Offset: 0xF4) (R/ 32) Tx Event FIFO Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EFFL:6; /*!< bit: 0.. 5 Event FIFO Fill Level */
- uint32_t :2; /*!< bit: 6.. 7 Reserved */
- uint32_t EFGI:5; /*!< bit: 8..12 Event FIFO Get Index */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t EFPI:5; /*!< bit: 16..20 Event FIFO Put Index */
- uint32_t :3; /*!< bit: 21..23 Reserved */
- uint32_t EFF:1; /*!< bit: 24 Event FIFO Full */
- uint32_t TEFL:1; /*!< bit: 25 Tx Event FIFO Element Lost */
- uint32_t :6; /*!< bit: 26..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXEFS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXEFS_OFFSET 0xF4 /**< \brief (CAN_TXEFS offset) Tx Event FIFO Status */
-#define CAN_TXEFS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFS reset_value) Tx Event FIFO Status */
-
-#define CAN_TXEFS_EFFL_Pos 0 /**< \brief (CAN_TXEFS) Event FIFO Fill Level */
-#define CAN_TXEFS_EFFL_Msk (_U_(0x3F) << CAN_TXEFS_EFFL_Pos)
-#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & ((value) << CAN_TXEFS_EFFL_Pos))
-#define CAN_TXEFS_EFGI_Pos 8 /**< \brief (CAN_TXEFS) Event FIFO Get Index */
-#define CAN_TXEFS_EFGI_Msk (_U_(0x1F) << CAN_TXEFS_EFGI_Pos)
-#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & ((value) << CAN_TXEFS_EFGI_Pos))
-#define CAN_TXEFS_EFPI_Pos 16 /**< \brief (CAN_TXEFS) Event FIFO Put Index */
-#define CAN_TXEFS_EFPI_Msk (_U_(0x1F) << CAN_TXEFS_EFPI_Pos)
-#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & ((value) << CAN_TXEFS_EFPI_Pos))
-#define CAN_TXEFS_EFF_Pos 24 /**< \brief (CAN_TXEFS) Event FIFO Full */
-#define CAN_TXEFS_EFF (_U_(0x1) << CAN_TXEFS_EFF_Pos)
-#define CAN_TXEFS_TEFL_Pos 25 /**< \brief (CAN_TXEFS) Tx Event FIFO Element Lost */
-#define CAN_TXEFS_TEFL (_U_(0x1) << CAN_TXEFS_TEFL_Pos)
-#define CAN_TXEFS_MASK _U_(0x031F1F3F) /**< \brief (CAN_TXEFS) MASK Register */
-
-/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EFAI:5; /*!< bit: 0.. 4 Event FIFO Acknowledge Index */
- uint32_t :27; /*!< bit: 5..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXEFA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXEFA_OFFSET 0xF8 /**< \brief (CAN_TXEFA offset) Tx Event FIFO Acknowledge */
-#define CAN_TXEFA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFA reset_value) Tx Event FIFO Acknowledge */
-
-#define CAN_TXEFA_EFAI_Pos 0 /**< \brief (CAN_TXEFA) Event FIFO Acknowledge Index */
-#define CAN_TXEFA_EFAI_Msk (_U_(0x1F) << CAN_TXEFA_EFAI_Pos)
-#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & ((value) << CAN_TXEFA_EFAI_Pos))
-#define CAN_TXEFA_MASK _U_(0x0000001F) /**< \brief (CAN_TXEFA) MASK Register */
-
-/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ID:29; /*!< bit: 0..28 Identifier */
- uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
- uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
- uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXBE_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXBE_0_OFFSET 0x00 /**< \brief (CAN_RXBE_0 offset) Rx Buffer Element 0 */
-#define CAN_RXBE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_0 reset_value) Rx Buffer Element 0 */
-
-#define CAN_RXBE_0_ID_Pos 0 /**< \brief (CAN_RXBE_0) Identifier */
-#define CAN_RXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos)
-#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & ((value) << CAN_RXBE_0_ID_Pos))
-#define CAN_RXBE_0_RTR_Pos 29 /**< \brief (CAN_RXBE_0) Remote Transmission Request */
-#define CAN_RXBE_0_RTR (_U_(0x1) << CAN_RXBE_0_RTR_Pos)
-#define CAN_RXBE_0_XTD_Pos 30 /**< \brief (CAN_RXBE_0) Extended Identifier */
-#define CAN_RXBE_0_XTD (_U_(0x1) << CAN_RXBE_0_XTD_Pos)
-#define CAN_RXBE_0_ESI_Pos 31 /**< \brief (CAN_RXBE_0) Error State Indicator */
-#define CAN_RXBE_0_ESI (_U_(0x1) << CAN_RXBE_0_ESI_Pos)
-#define CAN_RXBE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXBE_0) MASK Register */
-
-/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */
- uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
- uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
- uint32_t FDF:1; /*!< bit: 21 FD Format */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */
- uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXBE_1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXBE_1_OFFSET 0x04 /**< \brief (CAN_RXBE_1 offset) Rx Buffer Element 1 */
-#define CAN_RXBE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_1 reset_value) Rx Buffer Element 1 */
-
-#define CAN_RXBE_1_RXTS_Pos 0 /**< \brief (CAN_RXBE_1) Rx Timestamp */
-#define CAN_RXBE_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXBE_1_RXTS_Pos)
-#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & ((value) << CAN_RXBE_1_RXTS_Pos))
-#define CAN_RXBE_1_DLC_Pos 16 /**< \brief (CAN_RXBE_1) Data Length Code */
-#define CAN_RXBE_1_DLC_Msk (_U_(0xF) << CAN_RXBE_1_DLC_Pos)
-#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & ((value) << CAN_RXBE_1_DLC_Pos))
-#define CAN_RXBE_1_BRS_Pos 20 /**< \brief (CAN_RXBE_1) Bit Rate Search */
-#define CAN_RXBE_1_BRS (_U_(0x1) << CAN_RXBE_1_BRS_Pos)
-#define CAN_RXBE_1_FDF_Pos 21 /**< \brief (CAN_RXBE_1) FD Format */
-#define CAN_RXBE_1_FDF (_U_(0x1) << CAN_RXBE_1_FDF_Pos)
-#define CAN_RXBE_1_FIDX_Pos 24 /**< \brief (CAN_RXBE_1) Filter Index */
-#define CAN_RXBE_1_FIDX_Msk (_U_(0x7F) << CAN_RXBE_1_FIDX_Pos)
-#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & ((value) << CAN_RXBE_1_FIDX_Pos))
-#define CAN_RXBE_1_ANMF_Pos 31 /**< \brief (CAN_RXBE_1) Accepted Non-matching Frame */
-#define CAN_RXBE_1_ANMF (_U_(0x1) << CAN_RXBE_1_ANMF_Pos)
-#define CAN_RXBE_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXBE_1) MASK Register */
-
-/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
- uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
- uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
- uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXBE_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXBE_DATA_OFFSET 0x08 /**< \brief (CAN_RXBE_DATA offset) Rx Buffer Element Data */
-#define CAN_RXBE_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_DATA reset_value) Rx Buffer Element Data */
-
-#define CAN_RXBE_DATA_DB0_Pos 0 /**< \brief (CAN_RXBE_DATA) Data Byte 0 */
-#define CAN_RXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB0_Pos)
-#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & ((value) << CAN_RXBE_DATA_DB0_Pos))
-#define CAN_RXBE_DATA_DB1_Pos 8 /**< \brief (CAN_RXBE_DATA) Data Byte 1 */
-#define CAN_RXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB1_Pos)
-#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & ((value) << CAN_RXBE_DATA_DB1_Pos))
-#define CAN_RXBE_DATA_DB2_Pos 16 /**< \brief (CAN_RXBE_DATA) Data Byte 2 */
-#define CAN_RXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB2_Pos)
-#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & ((value) << CAN_RXBE_DATA_DB2_Pos))
-#define CAN_RXBE_DATA_DB3_Pos 24 /**< \brief (CAN_RXBE_DATA) Data Byte 3 */
-#define CAN_RXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB3_Pos)
-#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & ((value) << CAN_RXBE_DATA_DB3_Pos))
-#define CAN_RXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXBE_DATA) MASK Register */
-
-/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ID:29; /*!< bit: 0..28 Identifier */
- uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
- uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
- uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF0E_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF0E_0_OFFSET 0x00 /**< \brief (CAN_RXF0E_0 offset) Rx FIFO 0 Element 0 */
-#define CAN_RXF0E_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_0 reset_value) Rx FIFO 0 Element 0 */
-
-#define CAN_RXF0E_0_ID_Pos 0 /**< \brief (CAN_RXF0E_0) Identifier */
-#define CAN_RXF0E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos)
-#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & ((value) << CAN_RXF0E_0_ID_Pos))
-#define CAN_RXF0E_0_RTR_Pos 29 /**< \brief (CAN_RXF0E_0) Remote Transmission Request */
-#define CAN_RXF0E_0_RTR (_U_(0x1) << CAN_RXF0E_0_RTR_Pos)
-#define CAN_RXF0E_0_XTD_Pos 30 /**< \brief (CAN_RXF0E_0) Extended Identifier */
-#define CAN_RXF0E_0_XTD (_U_(0x1) << CAN_RXF0E_0_XTD_Pos)
-#define CAN_RXF0E_0_ESI_Pos 31 /**< \brief (CAN_RXF0E_0) Error State Indicator */
-#define CAN_RXF0E_0_ESI (_U_(0x1) << CAN_RXF0E_0_ESI_Pos)
-#define CAN_RXF0E_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF0E_0) MASK Register */
-
-/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */
- uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
- uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
- uint32_t FDF:1; /*!< bit: 21 FD Format */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */
- uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF0E_1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF0E_1_OFFSET 0x04 /**< \brief (CAN_RXF0E_1 offset) Rx FIFO 0 Element 1 */
-#define CAN_RXF0E_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_1 reset_value) Rx FIFO 0 Element 1 */
-
-#define CAN_RXF0E_1_RXTS_Pos 0 /**< \brief (CAN_RXF0E_1) Rx Timestamp */
-#define CAN_RXF0E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos)
-#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & ((value) << CAN_RXF0E_1_RXTS_Pos))
-#define CAN_RXF0E_1_DLC_Pos 16 /**< \brief (CAN_RXF0E_1) Data Length Code */
-#define CAN_RXF0E_1_DLC_Msk (_U_(0xF) << CAN_RXF0E_1_DLC_Pos)
-#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & ((value) << CAN_RXF0E_1_DLC_Pos))
-#define CAN_RXF0E_1_BRS_Pos 20 /**< \brief (CAN_RXF0E_1) Bit Rate Search */
-#define CAN_RXF0E_1_BRS (_U_(0x1) << CAN_RXF0E_1_BRS_Pos)
-#define CAN_RXF0E_1_FDF_Pos 21 /**< \brief (CAN_RXF0E_1) FD Format */
-#define CAN_RXF0E_1_FDF (_U_(0x1) << CAN_RXF0E_1_FDF_Pos)
-#define CAN_RXF0E_1_FIDX_Pos 24 /**< \brief (CAN_RXF0E_1) Filter Index */
-#define CAN_RXF0E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF0E_1_FIDX_Pos)
-#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & ((value) << CAN_RXF0E_1_FIDX_Pos))
-#define CAN_RXF0E_1_ANMF_Pos 31 /**< \brief (CAN_RXF0E_1) Accepted Non-matching Frame */
-#define CAN_RXF0E_1_ANMF (_U_(0x1) << CAN_RXF0E_1_ANMF_Pos)
-#define CAN_RXF0E_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXF0E_1) MASK Register */
-
-/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
- uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
- uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
- uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF0E_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF0E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF0E_DATA offset) Rx FIFO 0 Element Data */
-#define CAN_RXF0E_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_DATA reset_value) Rx FIFO 0 Element Data */
-
-#define CAN_RXF0E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF0E_DATA) Data Byte 0 */
-#define CAN_RXF0E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB0_Pos)
-#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & ((value) << CAN_RXF0E_DATA_DB0_Pos))
-#define CAN_RXF0E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF0E_DATA) Data Byte 1 */
-#define CAN_RXF0E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB1_Pos)
-#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & ((value) << CAN_RXF0E_DATA_DB1_Pos))
-#define CAN_RXF0E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF0E_DATA) Data Byte 2 */
-#define CAN_RXF0E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB2_Pos)
-#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & ((value) << CAN_RXF0E_DATA_DB2_Pos))
-#define CAN_RXF0E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF0E_DATA) Data Byte 3 */
-#define CAN_RXF0E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB3_Pos)
-#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & ((value) << CAN_RXF0E_DATA_DB3_Pos))
-#define CAN_RXF0E_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF0E_DATA) MASK Register */
-
-/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ID:29; /*!< bit: 0..28 Identifier */
- uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
- uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
- uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF1E_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF1E_0_OFFSET 0x00 /**< \brief (CAN_RXF1E_0 offset) Rx FIFO 1 Element 0 */
-#define CAN_RXF1E_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_0 reset_value) Rx FIFO 1 Element 0 */
-
-#define CAN_RXF1E_0_ID_Pos 0 /**< \brief (CAN_RXF1E_0) Identifier */
-#define CAN_RXF1E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos)
-#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & ((value) << CAN_RXF1E_0_ID_Pos))
-#define CAN_RXF1E_0_RTR_Pos 29 /**< \brief (CAN_RXF1E_0) Remote Transmission Request */
-#define CAN_RXF1E_0_RTR (_U_(0x1) << CAN_RXF1E_0_RTR_Pos)
-#define CAN_RXF1E_0_XTD_Pos 30 /**< \brief (CAN_RXF1E_0) Extended Identifier */
-#define CAN_RXF1E_0_XTD (_U_(0x1) << CAN_RXF1E_0_XTD_Pos)
-#define CAN_RXF1E_0_ESI_Pos 31 /**< \brief (CAN_RXF1E_0) Error State Indicator */
-#define CAN_RXF1E_0_ESI (_U_(0x1) << CAN_RXF1E_0_ESI_Pos)
-#define CAN_RXF1E_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF1E_0) MASK Register */
-
-/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */
- uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
- uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
- uint32_t FDF:1; /*!< bit: 21 FD Format */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */
- uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF1E_1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF1E_1_OFFSET 0x04 /**< \brief (CAN_RXF1E_1 offset) Rx FIFO 1 Element 1 */
-#define CAN_RXF1E_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_1 reset_value) Rx FIFO 1 Element 1 */
-
-#define CAN_RXF1E_1_RXTS_Pos 0 /**< \brief (CAN_RXF1E_1) Rx Timestamp */
-#define CAN_RXF1E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos)
-#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & ((value) << CAN_RXF1E_1_RXTS_Pos))
-#define CAN_RXF1E_1_DLC_Pos 16 /**< \brief (CAN_RXF1E_1) Data Length Code */
-#define CAN_RXF1E_1_DLC_Msk (_U_(0xF) << CAN_RXF1E_1_DLC_Pos)
-#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & ((value) << CAN_RXF1E_1_DLC_Pos))
-#define CAN_RXF1E_1_BRS_Pos 20 /**< \brief (CAN_RXF1E_1) Bit Rate Search */
-#define CAN_RXF1E_1_BRS (_U_(0x1) << CAN_RXF1E_1_BRS_Pos)
-#define CAN_RXF1E_1_FDF_Pos 21 /**< \brief (CAN_RXF1E_1) FD Format */
-#define CAN_RXF1E_1_FDF (_U_(0x1) << CAN_RXF1E_1_FDF_Pos)
-#define CAN_RXF1E_1_FIDX_Pos 24 /**< \brief (CAN_RXF1E_1) Filter Index */
-#define CAN_RXF1E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF1E_1_FIDX_Pos)
-#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & ((value) << CAN_RXF1E_1_FIDX_Pos))
-#define CAN_RXF1E_1_ANMF_Pos 31 /**< \brief (CAN_RXF1E_1) Accepted Non-matching Frame */
-#define CAN_RXF1E_1_ANMF (_U_(0x1) << CAN_RXF1E_1_ANMF_Pos)
-#define CAN_RXF1E_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXF1E_1) MASK Register */
-
-/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
- uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
- uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
- uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF1E_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF1E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF1E_DATA offset) Rx FIFO 1 Element Data */
-#define CAN_RXF1E_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_DATA reset_value) Rx FIFO 1 Element Data */
-
-#define CAN_RXF1E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF1E_DATA) Data Byte 0 */
-#define CAN_RXF1E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB0_Pos)
-#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & ((value) << CAN_RXF1E_DATA_DB0_Pos))
-#define CAN_RXF1E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF1E_DATA) Data Byte 1 */
-#define CAN_RXF1E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB1_Pos)
-#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & ((value) << CAN_RXF1E_DATA_DB1_Pos))
-#define CAN_RXF1E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF1E_DATA) Data Byte 2 */
-#define CAN_RXF1E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB2_Pos)
-#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & ((value) << CAN_RXF1E_DATA_DB2_Pos))
-#define CAN_RXF1E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF1E_DATA) Data Byte 3 */
-#define CAN_RXF1E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB3_Pos)
-#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & ((value) << CAN_RXF1E_DATA_DB3_Pos))
-#define CAN_RXF1E_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF1E_DATA) MASK Register */
-
-/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SFID2:11; /*!< bit: 0..10 Standard Filter ID 2 */
- uint32_t :5; /*!< bit: 11..15 Reserved */
- uint32_t SFID1:11; /*!< bit: 16..26 Standard Filter ID 1 */
- uint32_t SFEC:3; /*!< bit: 27..29 Standard Filter Element Configuration */
- uint32_t SFT:2; /*!< bit: 30..31 Standard Filter Type */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_SIDFE_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_SIDFE_0_OFFSET 0x00 /**< \brief (CAN_SIDFE_0 offset) Standard Message ID Filter Element */
-#define CAN_SIDFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFE_0 reset_value) Standard Message ID Filter Element */
-
-#define CAN_SIDFE_0_SFID2_Pos 0 /**< \brief (CAN_SIDFE_0) Standard Filter ID 2 */
-#define CAN_SIDFE_0_SFID2_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID2_Pos)
-#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & ((value) << CAN_SIDFE_0_SFID2_Pos))
-#define CAN_SIDFE_0_SFID1_Pos 16 /**< \brief (CAN_SIDFE_0) Standard Filter ID 1 */
-#define CAN_SIDFE_0_SFID1_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID1_Pos)
-#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & ((value) << CAN_SIDFE_0_SFID1_Pos))
-#define CAN_SIDFE_0_SFEC_Pos 27 /**< \brief (CAN_SIDFE_0) Standard Filter Element Configuration */
-#define CAN_SIDFE_0_SFEC_Msk (_U_(0x7) << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & ((value) << CAN_SIDFE_0_SFEC_Pos))
-#define CAN_SIDFE_0_SFEC_DISABLE_Val _U_(0x0) /**< \brief (CAN_SIDFE_0) Disable filter element */
-#define CAN_SIDFE_0_SFEC_STF0M_Val _U_(0x1) /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */
-#define CAN_SIDFE_0_SFEC_STF1M_Val _U_(0x2) /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */
-#define CAN_SIDFE_0_SFEC_REJECT_Val _U_(0x3) /**< \brief (CAN_SIDFE_0) Reject ID if filter match */
-#define CAN_SIDFE_0_SFEC_PRIORITY_Val _U_(0x4) /**< \brief (CAN_SIDFE_0) Set priority if filter match */
-#define CAN_SIDFE_0_SFEC_PRIF0M_Val _U_(0x5) /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */
-#define CAN_SIDFE_0_SFEC_PRIF1M_Val _U_(0x6) /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */
-#define CAN_SIDFE_0_SFEC_STRXBUF_Val _U_(0x7) /**< \brief (CAN_SIDFE_0) Store into Rx Buffer */
-#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFT_Pos 30 /**< \brief (CAN_SIDFE_0) Standard Filter Type */
-#define CAN_SIDFE_0_SFT_Msk (_U_(0x3) << CAN_SIDFE_0_SFT_Pos)
-#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & ((value) << CAN_SIDFE_0_SFT_Pos))
-#define CAN_SIDFE_0_SFT_RANGE_Val _U_(0x0) /**< \brief (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */
-#define CAN_SIDFE_0_SFT_DUAL_Val _U_(0x1) /**< \brief (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */
-#define CAN_SIDFE_0_SFT_CLASSIC_Val _U_(0x2) /**< \brief (CAN_SIDFE_0) Classic filter */
-#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos)
-#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos)
-#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos)
-#define CAN_SIDFE_0_MASK _U_(0xFFFF07FF) /**< \brief (CAN_SIDFE_0) MASK Register */
-
-/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ID:29; /*!< bit: 0..28 Identifier */
- uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
- uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
- uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBE_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBE_0_OFFSET 0x00 /**< \brief (CAN_TXBE_0 offset) Tx Buffer Element 0 */
-#define CAN_TXBE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_0 reset_value) Tx Buffer Element 0 */
-
-#define CAN_TXBE_0_ID_Pos 0 /**< \brief (CAN_TXBE_0) Identifier */
-#define CAN_TXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos)
-#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & ((value) << CAN_TXBE_0_ID_Pos))
-#define CAN_TXBE_0_RTR_Pos 29 /**< \brief (CAN_TXBE_0) Remote Transmission Request */
-#define CAN_TXBE_0_RTR (_U_(0x1) << CAN_TXBE_0_RTR_Pos)
-#define CAN_TXBE_0_XTD_Pos 30 /**< \brief (CAN_TXBE_0) Extended Identifier */
-#define CAN_TXBE_0_XTD (_U_(0x1) << CAN_TXBE_0_XTD_Pos)
-#define CAN_TXBE_0_ESI_Pos 31 /**< \brief (CAN_TXBE_0) Error State Indicator */
-#define CAN_TXBE_0_ESI (_U_(0x1) << CAN_TXBE_0_ESI_Pos)
-#define CAN_TXBE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBE_0) MASK Register */
-
-/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t DLC:4; /*!< bit: 16..19 Identifier */
- uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
- uint32_t FDF:1; /*!< bit: 21 FD Format */
- uint32_t :1; /*!< bit: 22 Reserved */
- uint32_t EFC:1; /*!< bit: 23 Event FIFO Control */
- uint32_t MM:8; /*!< bit: 24..31 Message Marker */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBE_1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBE_1_OFFSET 0x04 /**< \brief (CAN_TXBE_1 offset) Tx Buffer Element 1 */
-#define CAN_TXBE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_1 reset_value) Tx Buffer Element 1 */
-
-#define CAN_TXBE_1_DLC_Pos 16 /**< \brief (CAN_TXBE_1) Identifier */
-#define CAN_TXBE_1_DLC_Msk (_U_(0xF) << CAN_TXBE_1_DLC_Pos)
-#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & ((value) << CAN_TXBE_1_DLC_Pos))
-#define CAN_TXBE_1_BRS_Pos 20 /**< \brief (CAN_TXBE_1) Bit Rate Search */
-#define CAN_TXBE_1_BRS (_U_(0x1) << CAN_TXBE_1_BRS_Pos)
-#define CAN_TXBE_1_FDF_Pos 21 /**< \brief (CAN_TXBE_1) FD Format */
-#define CAN_TXBE_1_FDF (_U_(0x1) << CAN_TXBE_1_FDF_Pos)
-#define CAN_TXBE_1_EFC_Pos 23 /**< \brief (CAN_TXBE_1) Event FIFO Control */
-#define CAN_TXBE_1_EFC (_U_(0x1) << CAN_TXBE_1_EFC_Pos)
-#define CAN_TXBE_1_MM_Pos 24 /**< \brief (CAN_TXBE_1) Message Marker */
-#define CAN_TXBE_1_MM_Msk (_U_(0xFF) << CAN_TXBE_1_MM_Pos)
-#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & ((value) << CAN_TXBE_1_MM_Pos))
-#define CAN_TXBE_1_MASK _U_(0xFFBF0000) /**< \brief (CAN_TXBE_1) MASK Register */
-
-/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
- uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
- uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
- uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBE_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBE_DATA_OFFSET 0x08 /**< \brief (CAN_TXBE_DATA offset) Tx Buffer Element Data */
-#define CAN_TXBE_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_DATA reset_value) Tx Buffer Element Data */
-
-#define CAN_TXBE_DATA_DB0_Pos 0 /**< \brief (CAN_TXBE_DATA) Data Byte 0 */
-#define CAN_TXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB0_Pos)
-#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & ((value) << CAN_TXBE_DATA_DB0_Pos))
-#define CAN_TXBE_DATA_DB1_Pos 8 /**< \brief (CAN_TXBE_DATA) Data Byte 1 */
-#define CAN_TXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB1_Pos)
-#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & ((value) << CAN_TXBE_DATA_DB1_Pos))
-#define CAN_TXBE_DATA_DB2_Pos 16 /**< \brief (CAN_TXBE_DATA) Data Byte 2 */
-#define CAN_TXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB2_Pos)
-#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & ((value) << CAN_TXBE_DATA_DB2_Pos))
-#define CAN_TXBE_DATA_DB3_Pos 24 /**< \brief (CAN_TXBE_DATA) Data Byte 3 */
-#define CAN_TXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB3_Pos)
-#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & ((value) << CAN_TXBE_DATA_DB3_Pos))
-#define CAN_TXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBE_DATA) MASK Register */
-
-/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ID:29; /*!< bit: 0..28 Identifier */
- uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
- uint32_t XTD:1; /*!< bit: 30 Extended Indentifier */
- uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXEFE_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXEFE_0_OFFSET 0x00 /**< \brief (CAN_TXEFE_0 offset) Tx Event FIFO Element 0 */
-#define CAN_TXEFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFE_0 reset_value) Tx Event FIFO Element 0 */
-
-#define CAN_TXEFE_0_ID_Pos 0 /**< \brief (CAN_TXEFE_0) Identifier */
-#define CAN_TXEFE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos)
-#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & ((value) << CAN_TXEFE_0_ID_Pos))
-#define CAN_TXEFE_0_RTR_Pos 29 /**< \brief (CAN_TXEFE_0) Remote Transmission Request */
-#define CAN_TXEFE_0_RTR (_U_(0x1) << CAN_TXEFE_0_RTR_Pos)
-#define CAN_TXEFE_0_XTD_Pos 30 /**< \brief (CAN_TXEFE_0) Extended Indentifier */
-#define CAN_TXEFE_0_XTD (_U_(0x1) << CAN_TXEFE_0_XTD_Pos)
-#define CAN_TXEFE_0_ESI_Pos 31 /**< \brief (CAN_TXEFE_0) Error State Indicator */
-#define CAN_TXEFE_0_ESI (_U_(0x1) << CAN_TXEFE_0_ESI_Pos)
-#define CAN_TXEFE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXEFE_0) MASK Register */
-
-/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TXTS:16; /*!< bit: 0..15 Tx Timestamp */
- uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
- uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
- uint32_t FDF:1; /*!< bit: 21 FD Format */
- uint32_t ET:2; /*!< bit: 22..23 Event Type */
- uint32_t MM:8; /*!< bit: 24..31 Message Marker */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXEFE_1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXEFE_1_OFFSET 0x04 /**< \brief (CAN_TXEFE_1 offset) Tx Event FIFO Element 1 */
-#define CAN_TXEFE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFE_1 reset_value) Tx Event FIFO Element 1 */
-
-#define CAN_TXEFE_1_TXTS_Pos 0 /**< \brief (CAN_TXEFE_1) Tx Timestamp */
-#define CAN_TXEFE_1_TXTS_Msk (_U_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos)
-#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & ((value) << CAN_TXEFE_1_TXTS_Pos))
-#define CAN_TXEFE_1_DLC_Pos 16 /**< \brief (CAN_TXEFE_1) Data Length Code */
-#define CAN_TXEFE_1_DLC_Msk (_U_(0xF) << CAN_TXEFE_1_DLC_Pos)
-#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & ((value) << CAN_TXEFE_1_DLC_Pos))
-#define CAN_TXEFE_1_BRS_Pos 20 /**< \brief (CAN_TXEFE_1) Bit Rate Search */
-#define CAN_TXEFE_1_BRS (_U_(0x1) << CAN_TXEFE_1_BRS_Pos)
-#define CAN_TXEFE_1_FDF_Pos 21 /**< \brief (CAN_TXEFE_1) FD Format */
-#define CAN_TXEFE_1_FDF (_U_(0x1) << CAN_TXEFE_1_FDF_Pos)
-#define CAN_TXEFE_1_ET_Pos 22 /**< \brief (CAN_TXEFE_1) Event Type */
-#define CAN_TXEFE_1_ET_Msk (_U_(0x3) << CAN_TXEFE_1_ET_Pos)
-#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & ((value) << CAN_TXEFE_1_ET_Pos))
-#define CAN_TXEFE_1_ET_TXE_Val _U_(0x1) /**< \brief (CAN_TXEFE_1) Tx event */
-#define CAN_TXEFE_1_ET_TXC_Val _U_(0x2) /**< \brief (CAN_TXEFE_1) Transmission in spite of cancellation */
-#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos)
-#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos)
-#define CAN_TXEFE_1_MM_Pos 24 /**< \brief (CAN_TXEFE_1) Message Marker */
-#define CAN_TXEFE_1_MM_Msk (_U_(0xFF) << CAN_TXEFE_1_MM_Pos)
-#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & ((value) << CAN_TXEFE_1_MM_Pos))
-#define CAN_TXEFE_1_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXEFE_1) MASK Register */
-
-/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EFID1:29; /*!< bit: 0..28 Extended Filter ID 1 */
- uint32_t EFEC:3; /*!< bit: 29..31 Extended Filter Element Configuration */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_XIDFE_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_XIDFE_0_OFFSET 0x00 /**< \brief (CAN_XIDFE_0 offset) Extended Message ID Filter Element 0 */
-#define CAN_XIDFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFE_0 reset_value) Extended Message ID Filter Element 0 */
-
-#define CAN_XIDFE_0_EFID1_Pos 0 /**< \brief (CAN_XIDFE_0) Extended Filter ID 1 */
-#define CAN_XIDFE_0_EFID1_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos)
-#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & ((value) << CAN_XIDFE_0_EFID1_Pos))
-#define CAN_XIDFE_0_EFEC_Pos 29 /**< \brief (CAN_XIDFE_0) Extended Filter Element Configuration */
-#define CAN_XIDFE_0_EFEC_Msk (_U_(0x7) << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & ((value) << CAN_XIDFE_0_EFEC_Pos))
-#define CAN_XIDFE_0_EFEC_DISABLE_Val _U_(0x0) /**< \brief (CAN_XIDFE_0) Disable filter element */
-#define CAN_XIDFE_0_EFEC_STF0M_Val _U_(0x1) /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */
-#define CAN_XIDFE_0_EFEC_STF1M_Val _U_(0x2) /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */
-#define CAN_XIDFE_0_EFEC_REJECT_Val _U_(0x3) /**< \brief (CAN_XIDFE_0) Reject ID if filter match */
-#define CAN_XIDFE_0_EFEC_PRIORITY_Val _U_(0x4) /**< \brief (CAN_XIDFE_0) Set priority if filter match */
-#define CAN_XIDFE_0_EFEC_PRIF0M_Val _U_(0x5) /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */
-#define CAN_XIDFE_0_EFEC_PRIF1M_Val _U_(0x6) /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */
-#define CAN_XIDFE_0_EFEC_STRXBUF_Val _U_(0x7) /**< \brief (CAN_XIDFE_0) Store into Rx Buffer */
-#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_XIDFE_0) MASK Register */
-
-/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EFID2:29; /*!< bit: 0..28 Extended Filter ID 2 */
- uint32_t :1; /*!< bit: 29 Reserved */
- uint32_t EFT:2; /*!< bit: 30..31 Extended Filter Type */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_XIDFE_1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_XIDFE_1_OFFSET 0x04 /**< \brief (CAN_XIDFE_1 offset) Extended Message ID Filter Element 1 */
-#define CAN_XIDFE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFE_1 reset_value) Extended Message ID Filter Element 1 */
-
-#define CAN_XIDFE_1_EFID2_Pos 0 /**< \brief (CAN_XIDFE_1) Extended Filter ID 2 */
-#define CAN_XIDFE_1_EFID2_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos)
-#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & ((value) << CAN_XIDFE_1_EFID2_Pos))
-#define CAN_XIDFE_1_EFT_Pos 30 /**< \brief (CAN_XIDFE_1) Extended Filter Type */
-#define CAN_XIDFE_1_EFT_Msk (_U_(0x3) << CAN_XIDFE_1_EFT_Pos)
-#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & ((value) << CAN_XIDFE_1_EFT_Pos))
-#define CAN_XIDFE_1_EFT_RANGEM_Val _U_(0x0) /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */
-#define CAN_XIDFE_1_EFT_DUAL_Val _U_(0x1) /**< \brief (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */
-#define CAN_XIDFE_1_EFT_CLASSIC_Val _U_(0x2) /**< \brief (CAN_XIDFE_1) Classic filter */
-#define CAN_XIDFE_1_EFT_RANGE_Val _U_(0x3) /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */
-#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos)
-#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos)
-#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos)
-#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos)
-#define CAN_XIDFE_1_MASK _U_(0xDFFFFFFF) /**< \brief (CAN_XIDFE_1) MASK Register */
-
-/** \brief CAN APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __I CAN_CREL_Type CREL; /**< \brief Offset: 0x00 (R/ 32) Core Release */
- __I CAN_ENDN_Type ENDN; /**< \brief Offset: 0x04 (R/ 32) Endian */
- __IO CAN_MRCFG_Type MRCFG; /**< \brief Offset: 0x08 (R/W 32) Message RAM Configuration */
- __IO CAN_DBTP_Type DBTP; /**< \brief Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */
- __IO CAN_TEST_Type TEST; /**< \brief Offset: 0x10 (R/W 32) Test */
- __IO CAN_RWD_Type RWD; /**< \brief Offset: 0x14 (R/W 32) RAM Watchdog */
- __IO CAN_CCCR_Type CCCR; /**< \brief Offset: 0x18 (R/W 32) CC Control */
- __IO CAN_NBTP_Type NBTP; /**< \brief Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */
- __IO CAN_TSCC_Type TSCC; /**< \brief Offset: 0x20 (R/W 32) Timestamp Counter Configuration */
- __I CAN_TSCV_Type TSCV; /**< \brief Offset: 0x24 (R/ 32) Timestamp Counter Value */
- __IO CAN_TOCC_Type TOCC; /**< \brief Offset: 0x28 (R/W 32) Timeout Counter Configuration */
- __IO CAN_TOCV_Type TOCV; /**< \brief Offset: 0x2C (R/W 32) Timeout Counter Value */
- RoReg8 Reserved1[0x10];
- __I CAN_ECR_Type ECR; /**< \brief Offset: 0x40 (R/ 32) Error Counter */
- __I CAN_PSR_Type PSR; /**< \brief Offset: 0x44 (R/ 32) Protocol Status */
- __IO CAN_TDCR_Type TDCR; /**< \brief Offset: 0x48 (R/W 32) Extended ID Filter Configuration */
- RoReg8 Reserved2[0x4];
- __IO CAN_IR_Type IR; /**< \brief Offset: 0x50 (R/W 32) Interrupt */
- __IO CAN_IE_Type IE; /**< \brief Offset: 0x54 (R/W 32) Interrupt Enable */
- __IO CAN_ILS_Type ILS; /**< \brief Offset: 0x58 (R/W 32) Interrupt Line Select */
- __IO CAN_ILE_Type ILE; /**< \brief Offset: 0x5C (R/W 32) Interrupt Line Enable */
- RoReg8 Reserved3[0x20];
- __IO CAN_GFC_Type GFC; /**< \brief Offset: 0x80 (R/W 32) Global Filter Configuration */
- __IO CAN_SIDFC_Type SIDFC; /**< \brief Offset: 0x84 (R/W 32) Standard ID Filter Configuration */
- __IO CAN_XIDFC_Type XIDFC; /**< \brief Offset: 0x88 (R/W 32) Extended ID Filter Configuration */
- RoReg8 Reserved4[0x4];
- __IO CAN_XIDAM_Type XIDAM; /**< \brief Offset: 0x90 (R/W 32) Extended ID AND Mask */
- __I CAN_HPMS_Type HPMS; /**< \brief Offset: 0x94 (R/ 32) High Priority Message Status */
- __IO CAN_NDAT1_Type NDAT1; /**< \brief Offset: 0x98 (R/W 32) New Data 1 */
- __IO CAN_NDAT2_Type NDAT2; /**< \brief Offset: 0x9C (R/W 32) New Data 2 */
- __IO CAN_RXF0C_Type RXF0C; /**< \brief Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */
- __I CAN_RXF0S_Type RXF0S; /**< \brief Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */
- __IO CAN_RXF0A_Type RXF0A; /**< \brief Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */
- __IO CAN_RXBC_Type RXBC; /**< \brief Offset: 0xAC (R/W 32) Rx Buffer Configuration */
- __IO CAN_RXF1C_Type RXF1C; /**< \brief Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */
- __I CAN_RXF1S_Type RXF1S; /**< \brief Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */
- __IO CAN_RXF1A_Type RXF1A; /**< \brief Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */
- __IO CAN_RXESC_Type RXESC; /**< \brief Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */
- __IO CAN_TXBC_Type TXBC; /**< \brief Offset: 0xC0 (R/W 32) Tx Buffer Configuration */
- __I CAN_TXFQS_Type TXFQS; /**< \brief Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */
- __IO CAN_TXESC_Type TXESC; /**< \brief Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */
- __I CAN_TXBRP_Type TXBRP; /**< \brief Offset: 0xCC (R/ 32) Tx Buffer Request Pending */
- __IO CAN_TXBAR_Type TXBAR; /**< \brief Offset: 0xD0 (R/W 32) Tx Buffer Add Request */
- __IO CAN_TXBCR_Type TXBCR; /**< \brief Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */
- __I CAN_TXBTO_Type TXBTO; /**< \brief Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */
- __I CAN_TXBCF_Type TXBCF; /**< \brief Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */
- __IO CAN_TXBTIE_Type TXBTIE; /**< \brief Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */
- __IO CAN_TXBCIE_Type TXBCIE; /**< \brief Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */
- RoReg8 Reserved5[0x8];
- __IO CAN_TXEFC_Type TXEFC; /**< \brief Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */
- __I CAN_TXEFS_Type TXEFS; /**< \brief Offset: 0xF4 (R/ 32) Tx Event FIFO Status */
- __IO CAN_TXEFA_Type TXEFA; /**< \brief Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */
-} Can;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_rxbe hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO CAN_RXBE_0_Type RXBE_0; /**< \brief Offset: 0x00 (R/W 32) Rx Buffer Element 0 */
- __IO CAN_RXBE_1_Type RXBE_1; /**< \brief Offset: 0x04 (R/W 32) Rx Buffer Element 1 */
- __IO CAN_RXBE_DATA_Type RXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx Buffer Element Data */
-} CanMramRxbe
-#ifdef __GNUC__
- __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_rxf0e hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO CAN_RXF0E_0_Type RXF0E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */
- __IO CAN_RXF0E_1_Type RXF0E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */
- __IO CAN_RXF0E_DATA_Type RXF0E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */
-} CanMramRxf0e
-#ifdef __GNUC__
- __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_rxf1e hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO CAN_RXF1E_0_Type RXF1E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */
- __IO CAN_RXF1E_1_Type RXF1E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */
- __IO CAN_RXF1E_DATA_Type RXF1E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */
-} CanMramRxf1e
-#ifdef __GNUC__
- __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_sidfe hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO CAN_SIDFE_0_Type SIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Standard Message ID Filter Element */
-} CanMramSidfe
-#ifdef __GNUC__
- __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_txbe hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO CAN_TXBE_0_Type TXBE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Buffer Element 0 */
- __IO CAN_TXBE_1_Type TXBE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Buffer Element 1 */
- __IO CAN_TXBE_DATA_Type TXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Tx Buffer Element Data */
-} CanMramTxbe
-#ifdef __GNUC__
- __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_txefe hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO CAN_TXEFE_0_Type TXEFE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */
- __IO CAN_TXEFE_1_Type TXEFE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */
-} CanMramTxefe
-#ifdef __GNUC__
- __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_xifde hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO CAN_XIDFE_0_Type XIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */
- __IO CAN_XIDFE_1_Type XIDFE_1; /**< \brief Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */
-} CanMramXifde
-#ifdef __GNUC__
- __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SECTION_CAN_MRAM_RXBE
-#define SECTION_CAN_MRAM_RXF0E
-#define SECTION_CAN_MRAM_RXF1E
-#define SECTION_CAN_MRAM_SIDFE
-#define SECTION_CAN_MRAM_TXBE
-#define SECTION_CAN_MRAM_TXEFE
-#define SECTION_CAN_MRAM_XIFDE
-
-/*@}*/
-
-#endif /* _SAME54_CAN_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for CAN
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_CAN_COMPONENT_
+#define _SAME54_CAN_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR CAN */
+/* ========================================================================== */
+/** \addtogroup SAME54_CAN Control Area Network */
+/*@{*/
+
+#define CAN_U2003
+#define REV_CAN 0x321
+
+/* -------- CAN_CREL : (CAN Offset: 0x00) (R/ 32) Core Release -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :20; /*!< bit: 0..19 Reserved */
+ uint32_t SUBSTEP:4; /*!< bit: 20..23 Sub-step of Core Release */
+ uint32_t STEP:4; /*!< bit: 24..27 Step of Core Release */
+ uint32_t REL:4; /*!< bit: 28..31 Core Release */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_CREL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_CREL_OFFSET 0x00 /**< \brief (CAN_CREL offset) Core Release */
+#define CAN_CREL_RESETVALUE _U_(0x32100000) /**< \brief (CAN_CREL reset_value) Core Release */
+
+#define CAN_CREL_SUBSTEP_Pos 20 /**< \brief (CAN_CREL) Sub-step of Core Release */
+#define CAN_CREL_SUBSTEP_Msk (_U_(0xF) << CAN_CREL_SUBSTEP_Pos)
+#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & ((value) << CAN_CREL_SUBSTEP_Pos))
+#define CAN_CREL_STEP_Pos 24 /**< \brief (CAN_CREL) Step of Core Release */
+#define CAN_CREL_STEP_Msk (_U_(0xF) << CAN_CREL_STEP_Pos)
+#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & ((value) << CAN_CREL_STEP_Pos))
+#define CAN_CREL_REL_Pos 28 /**< \brief (CAN_CREL) Core Release */
+#define CAN_CREL_REL_Msk (_U_(0xF) << CAN_CREL_REL_Pos)
+#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & ((value) << CAN_CREL_REL_Pos))
+#define CAN_CREL_MASK _U_(0xFFF00000) /**< \brief (CAN_CREL) MASK Register */
+
+/* -------- CAN_ENDN : (CAN Offset: 0x04) (R/ 32) Endian -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ETV:32; /*!< bit: 0..31 Endianness Test Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_ENDN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_ENDN_OFFSET 0x04 /**< \brief (CAN_ENDN offset) Endian */
+#define CAN_ENDN_RESETVALUE _U_(0x87654321) /**< \brief (CAN_ENDN reset_value) Endian */
+
+#define CAN_ENDN_ETV_Pos 0 /**< \brief (CAN_ENDN) Endianness Test Value */
+#define CAN_ENDN_ETV_Msk (_U_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos)
+#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & ((value) << CAN_ENDN_ETV_Pos))
+#define CAN_ENDN_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_ENDN) MASK Register */
+
+/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t QOS:2; /*!< bit: 0.. 1 Quality of Service */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_MRCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_MRCFG_OFFSET 0x08 /**< \brief (CAN_MRCFG offset) Message RAM Configuration */
+#define CAN_MRCFG_RESETVALUE _U_(0x00000002) /**< \brief (CAN_MRCFG reset_value) Message RAM Configuration */
+
+#define CAN_MRCFG_QOS_Pos 0 /**< \brief (CAN_MRCFG) Quality of Service */
+#define CAN_MRCFG_QOS_Msk (_U_(0x3) << CAN_MRCFG_QOS_Pos)
+#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & ((value) << CAN_MRCFG_QOS_Pos))
+#define CAN_MRCFG_QOS_DISABLE_Val _U_(0x0) /**< \brief (CAN_MRCFG) Background (no sensitive operation) */
+#define CAN_MRCFG_QOS_LOW_Val _U_(0x1) /**< \brief (CAN_MRCFG) Sensitive Bandwidth */
+#define CAN_MRCFG_QOS_MEDIUM_Val _U_(0x2) /**< \brief (CAN_MRCFG) Sensitive Latency */
+#define CAN_MRCFG_QOS_HIGH_Val _U_(0x3) /**< \brief (CAN_MRCFG) Critical Latency */
+#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos)
+#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos)
+#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos)
+#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos)
+#define CAN_MRCFG_MASK _U_(0x00000003) /**< \brief (CAN_MRCFG) MASK Register */
+
+/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DSJW:4; /*!< bit: 0.. 3 Data (Re)Synchronization Jump Width */
+ uint32_t DTSEG2:4; /*!< bit: 4.. 7 Data time segment after sample point */
+ uint32_t DTSEG1:5; /*!< bit: 8..12 Data time segment before sample point */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t DBRP:5; /*!< bit: 16..20 Data Baud Rate Prescaler */
+ uint32_t :2; /*!< bit: 21..22 Reserved */
+ uint32_t TDC:1; /*!< bit: 23 Tranceiver Delay Compensation */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_DBTP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_DBTP_OFFSET 0x0C /**< \brief (CAN_DBTP offset) Fast Bit Timing and Prescaler */
+#define CAN_DBTP_RESETVALUE _U_(0x00000A33) /**< \brief (CAN_DBTP reset_value) Fast Bit Timing and Prescaler */
+
+#define CAN_DBTP_DSJW_Pos 0 /**< \brief (CAN_DBTP) Data (Re)Synchronization Jump Width */
+#define CAN_DBTP_DSJW_Msk (_U_(0xF) << CAN_DBTP_DSJW_Pos)
+#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & ((value) << CAN_DBTP_DSJW_Pos))
+#define CAN_DBTP_DTSEG2_Pos 4 /**< \brief (CAN_DBTP) Data time segment after sample point */
+#define CAN_DBTP_DTSEG2_Msk (_U_(0xF) << CAN_DBTP_DTSEG2_Pos)
+#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & ((value) << CAN_DBTP_DTSEG2_Pos))
+#define CAN_DBTP_DTSEG1_Pos 8 /**< \brief (CAN_DBTP) Data time segment before sample point */
+#define CAN_DBTP_DTSEG1_Msk (_U_(0x1F) << CAN_DBTP_DTSEG1_Pos)
+#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & ((value) << CAN_DBTP_DTSEG1_Pos))
+#define CAN_DBTP_DBRP_Pos 16 /**< \brief (CAN_DBTP) Data Baud Rate Prescaler */
+#define CAN_DBTP_DBRP_Msk (_U_(0x1F) << CAN_DBTP_DBRP_Pos)
+#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & ((value) << CAN_DBTP_DBRP_Pos))
+#define CAN_DBTP_TDC_Pos 23 /**< \brief (CAN_DBTP) Tranceiver Delay Compensation */
+#define CAN_DBTP_TDC (_U_(0x1) << CAN_DBTP_TDC_Pos)
+#define CAN_DBTP_MASK _U_(0x009F1FFF) /**< \brief (CAN_DBTP) MASK Register */
+
+/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :4; /*!< bit: 0.. 3 Reserved */
+ uint32_t LBCK:1; /*!< bit: 4 Loop Back Mode */
+ uint32_t TX:2; /*!< bit: 5.. 6 Control of Transmit Pin */
+ uint32_t RX:1; /*!< bit: 7 Receive Pin */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TEST_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TEST_OFFSET 0x10 /**< \brief (CAN_TEST offset) Test */
+#define CAN_TEST_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TEST reset_value) Test */
+
+#define CAN_TEST_LBCK_Pos 4 /**< \brief (CAN_TEST) Loop Back Mode */
+#define CAN_TEST_LBCK (_U_(0x1) << CAN_TEST_LBCK_Pos)
+#define CAN_TEST_TX_Pos 5 /**< \brief (CAN_TEST) Control of Transmit Pin */
+#define CAN_TEST_TX_Msk (_U_(0x3) << CAN_TEST_TX_Pos)
+#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & ((value) << CAN_TEST_TX_Pos))
+#define CAN_TEST_TX_CORE_Val _U_(0x0) /**< \brief (CAN_TEST) TX controlled by CAN core */
+#define CAN_TEST_TX_SAMPLE_Val _U_(0x1) /**< \brief (CAN_TEST) TX monitoring sample point */
+#define CAN_TEST_TX_DOMINANT_Val _U_(0x2) /**< \brief (CAN_TEST) Dominant (0) level at pin CAN_TX */
+#define CAN_TEST_TX_RECESSIVE_Val _U_(0x3) /**< \brief (CAN_TEST) Recessive (1) level at pin CAN_TX */
+#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos)
+#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos)
+#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos)
+#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos)
+#define CAN_TEST_RX_Pos 7 /**< \brief (CAN_TEST) Receive Pin */
+#define CAN_TEST_RX (_U_(0x1) << CAN_TEST_RX_Pos)
+#define CAN_TEST_MASK _U_(0x000000F0) /**< \brief (CAN_TEST) MASK Register */
+
+/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WDC:8; /*!< bit: 0.. 7 Watchdog Configuration */
+ uint32_t WDV:8; /*!< bit: 8..15 Watchdog Value */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RWD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RWD_OFFSET 0x14 /**< \brief (CAN_RWD offset) RAM Watchdog */
+#define CAN_RWD_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RWD reset_value) RAM Watchdog */
+
+#define CAN_RWD_WDC_Pos 0 /**< \brief (CAN_RWD) Watchdog Configuration */
+#define CAN_RWD_WDC_Msk (_U_(0xFF) << CAN_RWD_WDC_Pos)
+#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & ((value) << CAN_RWD_WDC_Pos))
+#define CAN_RWD_WDV_Pos 8 /**< \brief (CAN_RWD) Watchdog Value */
+#define CAN_RWD_WDV_Msk (_U_(0xFF) << CAN_RWD_WDV_Pos)
+#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & ((value) << CAN_RWD_WDV_Pos))
+#define CAN_RWD_MASK _U_(0x0000FFFF) /**< \brief (CAN_RWD) MASK Register */
+
+/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t INIT:1; /*!< bit: 0 Initialization */
+ uint32_t CCE:1; /*!< bit: 1 Configuration Change Enable */
+ uint32_t ASM:1; /*!< bit: 2 ASM Restricted Operation Mode */
+ uint32_t CSA:1; /*!< bit: 3 Clock Stop Acknowledge */
+ uint32_t CSR:1; /*!< bit: 4 Clock Stop Request */
+ uint32_t MON:1; /*!< bit: 5 Bus Monitoring Mode */
+ uint32_t DAR:1; /*!< bit: 6 Disable Automatic Retransmission */
+ uint32_t TEST:1; /*!< bit: 7 Test Mode Enable */
+ uint32_t FDOE:1; /*!< bit: 8 FD Operation Enable */
+ uint32_t BRSE:1; /*!< bit: 9 Bit Rate Switch Enable */
+ uint32_t :2; /*!< bit: 10..11 Reserved */
+ uint32_t PXHD:1; /*!< bit: 12 Protocol Exception Handling Disable */
+ uint32_t EFBI:1; /*!< bit: 13 Edge Filtering during Bus Integration */
+ uint32_t TXP:1; /*!< bit: 14 Transmit Pause */
+ uint32_t NISO:1; /*!< bit: 15 Non ISO Operation */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_CCCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_CCCR_OFFSET 0x18 /**< \brief (CAN_CCCR offset) CC Control */
+#define CAN_CCCR_RESETVALUE _U_(0x00000001) /**< \brief (CAN_CCCR reset_value) CC Control */
+
+#define CAN_CCCR_INIT_Pos 0 /**< \brief (CAN_CCCR) Initialization */
+#define CAN_CCCR_INIT (_U_(0x1) << CAN_CCCR_INIT_Pos)
+#define CAN_CCCR_CCE_Pos 1 /**< \brief (CAN_CCCR) Configuration Change Enable */
+#define CAN_CCCR_CCE (_U_(0x1) << CAN_CCCR_CCE_Pos)
+#define CAN_CCCR_ASM_Pos 2 /**< \brief (CAN_CCCR) ASM Restricted Operation Mode */
+#define CAN_CCCR_ASM (_U_(0x1) << CAN_CCCR_ASM_Pos)
+#define CAN_CCCR_CSA_Pos 3 /**< \brief (CAN_CCCR) Clock Stop Acknowledge */
+#define CAN_CCCR_CSA (_U_(0x1) << CAN_CCCR_CSA_Pos)
+#define CAN_CCCR_CSR_Pos 4 /**< \brief (CAN_CCCR) Clock Stop Request */
+#define CAN_CCCR_CSR (_U_(0x1) << CAN_CCCR_CSR_Pos)
+#define CAN_CCCR_MON_Pos 5 /**< \brief (CAN_CCCR) Bus Monitoring Mode */
+#define CAN_CCCR_MON (_U_(0x1) << CAN_CCCR_MON_Pos)
+#define CAN_CCCR_DAR_Pos 6 /**< \brief (CAN_CCCR) Disable Automatic Retransmission */
+#define CAN_CCCR_DAR (_U_(0x1) << CAN_CCCR_DAR_Pos)
+#define CAN_CCCR_TEST_Pos 7 /**< \brief (CAN_CCCR) Test Mode Enable */
+#define CAN_CCCR_TEST (_U_(0x1) << CAN_CCCR_TEST_Pos)
+#define CAN_CCCR_FDOE_Pos 8 /**< \brief (CAN_CCCR) FD Operation Enable */
+#define CAN_CCCR_FDOE (_U_(0x1) << CAN_CCCR_FDOE_Pos)
+#define CAN_CCCR_BRSE_Pos 9 /**< \brief (CAN_CCCR) Bit Rate Switch Enable */
+#define CAN_CCCR_BRSE (_U_(0x1) << CAN_CCCR_BRSE_Pos)
+#define CAN_CCCR_PXHD_Pos 12 /**< \brief (CAN_CCCR) Protocol Exception Handling Disable */
+#define CAN_CCCR_PXHD (_U_(0x1) << CAN_CCCR_PXHD_Pos)
+#define CAN_CCCR_EFBI_Pos 13 /**< \brief (CAN_CCCR) Edge Filtering during Bus Integration */
+#define CAN_CCCR_EFBI (_U_(0x1) << CAN_CCCR_EFBI_Pos)
+#define CAN_CCCR_TXP_Pos 14 /**< \brief (CAN_CCCR) Transmit Pause */
+#define CAN_CCCR_TXP (_U_(0x1) << CAN_CCCR_TXP_Pos)
+#define CAN_CCCR_NISO_Pos 15 /**< \brief (CAN_CCCR) Non ISO Operation */
+#define CAN_CCCR_NISO (_U_(0x1) << CAN_CCCR_NISO_Pos)
+#define CAN_CCCR_MASK _U_(0x0000F3FF) /**< \brief (CAN_CCCR) MASK Register */
+
+/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NTSEG2:7; /*!< bit: 0.. 6 Nominal Time segment after sample point */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t NTSEG1:8; /*!< bit: 8..15 Nominal Time segment before sample point */
+ uint32_t NBRP:9; /*!< bit: 16..24 Nominal Baud Rate Prescaler */
+ uint32_t NSJW:7; /*!< bit: 25..31 Nominal (Re)Synchronization Jump Width */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_NBTP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_NBTP_OFFSET 0x1C /**< \brief (CAN_NBTP offset) Nominal Bit Timing and Prescaler */
+#define CAN_NBTP_RESETVALUE _U_(0x06000A03) /**< \brief (CAN_NBTP reset_value) Nominal Bit Timing and Prescaler */
+
+#define CAN_NBTP_NTSEG2_Pos 0 /**< \brief (CAN_NBTP) Nominal Time segment after sample point */
+#define CAN_NBTP_NTSEG2_Msk (_U_(0x7F) << CAN_NBTP_NTSEG2_Pos)
+#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & ((value) << CAN_NBTP_NTSEG2_Pos))
+#define CAN_NBTP_NTSEG1_Pos 8 /**< \brief (CAN_NBTP) Nominal Time segment before sample point */
+#define CAN_NBTP_NTSEG1_Msk (_U_(0xFF) << CAN_NBTP_NTSEG1_Pos)
+#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & ((value) << CAN_NBTP_NTSEG1_Pos))
+#define CAN_NBTP_NBRP_Pos 16 /**< \brief (CAN_NBTP) Nominal Baud Rate Prescaler */
+#define CAN_NBTP_NBRP_Msk (_U_(0x1FF) << CAN_NBTP_NBRP_Pos)
+#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & ((value) << CAN_NBTP_NBRP_Pos))
+#define CAN_NBTP_NSJW_Pos 25 /**< \brief (CAN_NBTP) Nominal (Re)Synchronization Jump Width */
+#define CAN_NBTP_NSJW_Msk (_U_(0x7F) << CAN_NBTP_NSJW_Pos)
+#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & ((value) << CAN_NBTP_NSJW_Pos))
+#define CAN_NBTP_MASK _U_(0xFFFFFF7F) /**< \brief (CAN_NBTP) MASK Register */
+
+/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TSS:2; /*!< bit: 0.. 1 Timestamp Select */
+ uint32_t :14; /*!< bit: 2..15 Reserved */
+ uint32_t TCP:4; /*!< bit: 16..19 Timestamp Counter Prescaler */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TSCC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TSCC_OFFSET 0x20 /**< \brief (CAN_TSCC offset) Timestamp Counter Configuration */
+#define CAN_TSCC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCC reset_value) Timestamp Counter Configuration */
+
+#define CAN_TSCC_TSS_Pos 0 /**< \brief (CAN_TSCC) Timestamp Select */
+#define CAN_TSCC_TSS_Msk (_U_(0x3) << CAN_TSCC_TSS_Pos)
+#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & ((value) << CAN_TSCC_TSS_Pos))
+#define CAN_TSCC_TSS_ZERO_Val _U_(0x0) /**< \brief (CAN_TSCC) Timestamp counter value always 0x0000 */
+#define CAN_TSCC_TSS_INC_Val _U_(0x1) /**< \brief (CAN_TSCC) Timestamp counter value incremented by TCP */
+#define CAN_TSCC_TSS_EXT_Val _U_(0x2) /**< \brief (CAN_TSCC) External timestamp counter value used */
+#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos)
+#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos)
+#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos)
+#define CAN_TSCC_TCP_Pos 16 /**< \brief (CAN_TSCC) Timestamp Counter Prescaler */
+#define CAN_TSCC_TCP_Msk (_U_(0xF) << CAN_TSCC_TCP_Pos)
+#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & ((value) << CAN_TSCC_TCP_Pos))
+#define CAN_TSCC_MASK _U_(0x000F0003) /**< \brief (CAN_TSCC) MASK Register */
+
+/* -------- CAN_TSCV : (CAN Offset: 0x24) (R/ 32) Timestamp Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TSC:16; /*!< bit: 0..15 Timestamp Counter */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TSCV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TSCV_OFFSET 0x24 /**< \brief (CAN_TSCV offset) Timestamp Counter Value */
+#define CAN_TSCV_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCV reset_value) Timestamp Counter Value */
+
+#define CAN_TSCV_TSC_Pos 0 /**< \brief (CAN_TSCV) Timestamp Counter */
+#define CAN_TSCV_TSC_Msk (_U_(0xFFFF) << CAN_TSCV_TSC_Pos)
+#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & ((value) << CAN_TSCV_TSC_Pos))
+#define CAN_TSCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TSCV) MASK Register */
+
+/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ETOC:1; /*!< bit: 0 Enable Timeout Counter */
+ uint32_t TOS:2; /*!< bit: 1.. 2 Timeout Select */
+ uint32_t :13; /*!< bit: 3..15 Reserved */
+ uint32_t TOP:16; /*!< bit: 16..31 Timeout Period */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TOCC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TOCC_OFFSET 0x28 /**< \brief (CAN_TOCC offset) Timeout Counter Configuration */
+#define CAN_TOCC_RESETVALUE _U_(0xFFFF0000) /**< \brief (CAN_TOCC reset_value) Timeout Counter Configuration */
+
+#define CAN_TOCC_ETOC_Pos 0 /**< \brief (CAN_TOCC) Enable Timeout Counter */
+#define CAN_TOCC_ETOC (_U_(0x1) << CAN_TOCC_ETOC_Pos)
+#define CAN_TOCC_TOS_Pos 1 /**< \brief (CAN_TOCC) Timeout Select */
+#define CAN_TOCC_TOS_Msk (_U_(0x3) << CAN_TOCC_TOS_Pos)
+#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & ((value) << CAN_TOCC_TOS_Pos))
+#define CAN_TOCC_TOS_CONT_Val _U_(0x0) /**< \brief (CAN_TOCC) Continuout operation */
+#define CAN_TOCC_TOS_TXEF_Val _U_(0x1) /**< \brief (CAN_TOCC) Timeout controlled by TX Event FIFO */
+#define CAN_TOCC_TOS_RXF0_Val _U_(0x2) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 0 */
+#define CAN_TOCC_TOS_RXF1_Val _U_(0x3) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 1 */
+#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos)
+#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos)
+#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos)
+#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos)
+#define CAN_TOCC_TOP_Pos 16 /**< \brief (CAN_TOCC) Timeout Period */
+#define CAN_TOCC_TOP_Msk (_U_(0xFFFF) << CAN_TOCC_TOP_Pos)
+#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & ((value) << CAN_TOCC_TOP_Pos))
+#define CAN_TOCC_MASK _U_(0xFFFF0007) /**< \brief (CAN_TOCC) MASK Register */
+
+/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TOC:16; /*!< bit: 0..15 Timeout Counter */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TOCV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TOCV_OFFSET 0x2C /**< \brief (CAN_TOCV offset) Timeout Counter Value */
+#define CAN_TOCV_RESETVALUE _U_(0x0000FFFF) /**< \brief (CAN_TOCV reset_value) Timeout Counter Value */
+
+#define CAN_TOCV_TOC_Pos 0 /**< \brief (CAN_TOCV) Timeout Counter */
+#define CAN_TOCV_TOC_Msk (_U_(0xFFFF) << CAN_TOCV_TOC_Pos)
+#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & ((value) << CAN_TOCV_TOC_Pos))
+#define CAN_TOCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TOCV) MASK Register */
+
+/* -------- CAN_ECR : (CAN Offset: 0x40) (R/ 32) Error Counter -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TEC:8; /*!< bit: 0.. 7 Transmit Error Counter */
+ uint32_t REC:7; /*!< bit: 8..14 Receive Error Counter */
+ uint32_t RP:1; /*!< bit: 15 Receive Error Passive */
+ uint32_t CEL:8; /*!< bit: 16..23 CAN Error Logging */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_ECR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_ECR_OFFSET 0x40 /**< \brief (CAN_ECR offset) Error Counter */
+#define CAN_ECR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ECR reset_value) Error Counter */
+
+#define CAN_ECR_TEC_Pos 0 /**< \brief (CAN_ECR) Transmit Error Counter */
+#define CAN_ECR_TEC_Msk (_U_(0xFF) << CAN_ECR_TEC_Pos)
+#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & ((value) << CAN_ECR_TEC_Pos))
+#define CAN_ECR_REC_Pos 8 /**< \brief (CAN_ECR) Receive Error Counter */
+#define CAN_ECR_REC_Msk (_U_(0x7F) << CAN_ECR_REC_Pos)
+#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & ((value) << CAN_ECR_REC_Pos))
+#define CAN_ECR_RP_Pos 15 /**< \brief (CAN_ECR) Receive Error Passive */
+#define CAN_ECR_RP (_U_(0x1) << CAN_ECR_RP_Pos)
+#define CAN_ECR_CEL_Pos 16 /**< \brief (CAN_ECR) CAN Error Logging */
+#define CAN_ECR_CEL_Msk (_U_(0xFF) << CAN_ECR_CEL_Pos)
+#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & ((value) << CAN_ECR_CEL_Pos))
+#define CAN_ECR_MASK _U_(0x00FFFFFF) /**< \brief (CAN_ECR) MASK Register */
+
+/* -------- CAN_PSR : (CAN Offset: 0x44) (R/ 32) Protocol Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LEC:3; /*!< bit: 0.. 2 Last Error Code */
+ uint32_t ACT:2; /*!< bit: 3.. 4 Activity */
+ uint32_t EP:1; /*!< bit: 5 Error Passive */
+ uint32_t EW:1; /*!< bit: 6 Warning Status */
+ uint32_t BO:1; /*!< bit: 7 Bus_Off Status */
+ uint32_t DLEC:3; /*!< bit: 8..10 Data Phase Last Error Code */
+ uint32_t RESI:1; /*!< bit: 11 ESI flag of last received CAN FD Message */
+ uint32_t RBRS:1; /*!< bit: 12 BRS flag of last received CAN FD Message */
+ uint32_t RFDF:1; /*!< bit: 13 Received a CAN FD Message */
+ uint32_t PXE:1; /*!< bit: 14 Protocol Exception Event */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t TDCV:7; /*!< bit: 16..22 Transmitter Delay Compensation Value */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_PSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_PSR_OFFSET 0x44 /**< \brief (CAN_PSR offset) Protocol Status */
+#define CAN_PSR_RESETVALUE _U_(0x00000707) /**< \brief (CAN_PSR reset_value) Protocol Status */
+
+#define CAN_PSR_LEC_Pos 0 /**< \brief (CAN_PSR) Last Error Code */
+#define CAN_PSR_LEC_Msk (_U_(0x7) << CAN_PSR_LEC_Pos)
+#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & ((value) << CAN_PSR_LEC_Pos))
+#define CAN_PSR_LEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */
+#define CAN_PSR_LEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */
+#define CAN_PSR_LEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */
+#define CAN_PSR_LEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */
+#define CAN_PSR_LEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */
+#define CAN_PSR_LEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */
+#define CAN_PSR_LEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */
+#define CAN_PSR_LEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */
+#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos)
+#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos)
+#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos)
+#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos)
+#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos)
+#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos)
+#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos)
+#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos)
+#define CAN_PSR_ACT_Pos 3 /**< \brief (CAN_PSR) Activity */
+#define CAN_PSR_ACT_Msk (_U_(0x3) << CAN_PSR_ACT_Pos)
+#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & ((value) << CAN_PSR_ACT_Pos))
+#define CAN_PSR_ACT_SYNC_Val _U_(0x0) /**< \brief (CAN_PSR) Node is synchronizing on CAN communication */
+#define CAN_PSR_ACT_IDLE_Val _U_(0x1) /**< \brief (CAN_PSR) Node is neither receiver nor transmitter */
+#define CAN_PSR_ACT_RX_Val _U_(0x2) /**< \brief (CAN_PSR) Node is operating as receiver */
+#define CAN_PSR_ACT_TX_Val _U_(0x3) /**< \brief (CAN_PSR) Node is operating as transmitter */
+#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos)
+#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos)
+#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos)
+#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos)
+#define CAN_PSR_EP_Pos 5 /**< \brief (CAN_PSR) Error Passive */
+#define CAN_PSR_EP (_U_(0x1) << CAN_PSR_EP_Pos)
+#define CAN_PSR_EW_Pos 6 /**< \brief (CAN_PSR) Warning Status */
+#define CAN_PSR_EW (_U_(0x1) << CAN_PSR_EW_Pos)
+#define CAN_PSR_BO_Pos 7 /**< \brief (CAN_PSR) Bus_Off Status */
+#define CAN_PSR_BO (_U_(0x1) << CAN_PSR_BO_Pos)
+#define CAN_PSR_DLEC_Pos 8 /**< \brief (CAN_PSR) Data Phase Last Error Code */
+#define CAN_PSR_DLEC_Msk (_U_(0x7) << CAN_PSR_DLEC_Pos)
+#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & ((value) << CAN_PSR_DLEC_Pos))
+#define CAN_PSR_DLEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */
+#define CAN_PSR_DLEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */
+#define CAN_PSR_DLEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */
+#define CAN_PSR_DLEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */
+#define CAN_PSR_DLEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */
+#define CAN_PSR_DLEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */
+#define CAN_PSR_DLEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */
+#define CAN_PSR_DLEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */
+#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos)
+#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos)
+#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos)
+#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos)
+#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos)
+#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos)
+#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos)
+#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos)
+#define CAN_PSR_RESI_Pos 11 /**< \brief (CAN_PSR) ESI flag of last received CAN FD Message */
+#define CAN_PSR_RESI (_U_(0x1) << CAN_PSR_RESI_Pos)
+#define CAN_PSR_RBRS_Pos 12 /**< \brief (CAN_PSR) BRS flag of last received CAN FD Message */
+#define CAN_PSR_RBRS (_U_(0x1) << CAN_PSR_RBRS_Pos)
+#define CAN_PSR_RFDF_Pos 13 /**< \brief (CAN_PSR) Received a CAN FD Message */
+#define CAN_PSR_RFDF (_U_(0x1) << CAN_PSR_RFDF_Pos)
+#define CAN_PSR_PXE_Pos 14 /**< \brief (CAN_PSR) Protocol Exception Event */
+#define CAN_PSR_PXE (_U_(0x1) << CAN_PSR_PXE_Pos)
+#define CAN_PSR_TDCV_Pos 16 /**< \brief (CAN_PSR) Transmitter Delay Compensation Value */
+#define CAN_PSR_TDCV_Msk (_U_(0x7F) << CAN_PSR_TDCV_Pos)
+#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & ((value) << CAN_PSR_TDCV_Pos))
+#define CAN_PSR_MASK _U_(0x007F7FFF) /**< \brief (CAN_PSR) MASK Register */
+
+/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TDCF:7; /*!< bit: 0.. 6 Transmitter Delay Compensation Filter Length */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t TDCO:7; /*!< bit: 8..14 Transmitter Delay Compensation Offset */
+ uint32_t :17; /*!< bit: 15..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TDCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TDCR_OFFSET 0x48 /**< \brief (CAN_TDCR offset) Extended ID Filter Configuration */
+#define CAN_TDCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TDCR reset_value) Extended ID Filter Configuration */
+
+#define CAN_TDCR_TDCF_Pos 0 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Filter Length */
+#define CAN_TDCR_TDCF_Msk (_U_(0x7F) << CAN_TDCR_TDCF_Pos)
+#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & ((value) << CAN_TDCR_TDCF_Pos))
+#define CAN_TDCR_TDCO_Pos 8 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Offset */
+#define CAN_TDCR_TDCO_Msk (_U_(0x7F) << CAN_TDCR_TDCO_Pos)
+#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & ((value) << CAN_TDCR_TDCO_Pos))
+#define CAN_TDCR_MASK _U_(0x00007F7F) /**< \brief (CAN_TDCR) MASK Register */
+
+/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RF0N:1; /*!< bit: 0 Rx FIFO 0 New Message */
+ uint32_t RF0W:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached */
+ uint32_t RF0F:1; /*!< bit: 2 Rx FIFO 0 Full */
+ uint32_t RF0L:1; /*!< bit: 3 Rx FIFO 0 Message Lost */
+ uint32_t RF1N:1; /*!< bit: 4 Rx FIFO 1 New Message */
+ uint32_t RF1W:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached */
+ uint32_t RF1F:1; /*!< bit: 6 Rx FIFO 1 FIFO Full */
+ uint32_t RF1L:1; /*!< bit: 7 Rx FIFO 1 Message Lost */
+ uint32_t HPM:1; /*!< bit: 8 High Priority Message */
+ uint32_t TC:1; /*!< bit: 9 Timestamp Completed */
+ uint32_t TCF:1; /*!< bit: 10 Transmission Cancellation Finished */
+ uint32_t TFE:1; /*!< bit: 11 Tx FIFO Empty */
+ uint32_t TEFN:1; /*!< bit: 12 Tx Event FIFO New Entry */
+ uint32_t TEFW:1; /*!< bit: 13 Tx Event FIFO Watermark Reached */
+ uint32_t TEFF:1; /*!< bit: 14 Tx Event FIFO Full */
+ uint32_t TEFL:1; /*!< bit: 15 Tx Event FIFO Element Lost */
+ uint32_t TSW:1; /*!< bit: 16 Timestamp Wraparound */
+ uint32_t MRAF:1; /*!< bit: 17 Message RAM Access Failure */
+ uint32_t TOO:1; /*!< bit: 18 Timeout Occurred */
+ uint32_t DRX:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer */
+ uint32_t BEC:1; /*!< bit: 20 Bit Error Corrected */
+ uint32_t BEU:1; /*!< bit: 21 Bit Error Uncorrected */
+ uint32_t ELO:1; /*!< bit: 22 Error Logging Overflow */
+ uint32_t EP:1; /*!< bit: 23 Error Passive */
+ uint32_t EW:1; /*!< bit: 24 Warning Status */
+ uint32_t BO:1; /*!< bit: 25 Bus_Off Status */
+ uint32_t WDI:1; /*!< bit: 26 Watchdog Interrupt */
+ uint32_t PEA:1; /*!< bit: 27 Protocol Error in Arbitration Phase */
+ uint32_t PED:1; /*!< bit: 28 Protocol Error in Data Phase */
+ uint32_t ARA:1; /*!< bit: 29 Access to Reserved Address */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_IR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_IR_OFFSET 0x50 /**< \brief (CAN_IR offset) Interrupt */
+#define CAN_IR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IR reset_value) Interrupt */
+
+#define CAN_IR_RF0N_Pos 0 /**< \brief (CAN_IR) Rx FIFO 0 New Message */
+#define CAN_IR_RF0N (_U_(0x1) << CAN_IR_RF0N_Pos)
+#define CAN_IR_RF0W_Pos 1 /**< \brief (CAN_IR) Rx FIFO 0 Watermark Reached */
+#define CAN_IR_RF0W (_U_(0x1) << CAN_IR_RF0W_Pos)
+#define CAN_IR_RF0F_Pos 2 /**< \brief (CAN_IR) Rx FIFO 0 Full */
+#define CAN_IR_RF0F (_U_(0x1) << CAN_IR_RF0F_Pos)
+#define CAN_IR_RF0L_Pos 3 /**< \brief (CAN_IR) Rx FIFO 0 Message Lost */
+#define CAN_IR_RF0L (_U_(0x1) << CAN_IR_RF0L_Pos)
+#define CAN_IR_RF1N_Pos 4 /**< \brief (CAN_IR) Rx FIFO 1 New Message */
+#define CAN_IR_RF1N (_U_(0x1) << CAN_IR_RF1N_Pos)
+#define CAN_IR_RF1W_Pos 5 /**< \brief (CAN_IR) Rx FIFO 1 Watermark Reached */
+#define CAN_IR_RF1W (_U_(0x1) << CAN_IR_RF1W_Pos)
+#define CAN_IR_RF1F_Pos 6 /**< \brief (CAN_IR) Rx FIFO 1 FIFO Full */
+#define CAN_IR_RF1F (_U_(0x1) << CAN_IR_RF1F_Pos)
+#define CAN_IR_RF1L_Pos 7 /**< \brief (CAN_IR) Rx FIFO 1 Message Lost */
+#define CAN_IR_RF1L (_U_(0x1) << CAN_IR_RF1L_Pos)
+#define CAN_IR_HPM_Pos 8 /**< \brief (CAN_IR) High Priority Message */
+#define CAN_IR_HPM (_U_(0x1) << CAN_IR_HPM_Pos)
+#define CAN_IR_TC_Pos 9 /**< \brief (CAN_IR) Timestamp Completed */
+#define CAN_IR_TC (_U_(0x1) << CAN_IR_TC_Pos)
+#define CAN_IR_TCF_Pos 10 /**< \brief (CAN_IR) Transmission Cancellation Finished */
+#define CAN_IR_TCF (_U_(0x1) << CAN_IR_TCF_Pos)
+#define CAN_IR_TFE_Pos 11 /**< \brief (CAN_IR) Tx FIFO Empty */
+#define CAN_IR_TFE (_U_(0x1) << CAN_IR_TFE_Pos)
+#define CAN_IR_TEFN_Pos 12 /**< \brief (CAN_IR) Tx Event FIFO New Entry */
+#define CAN_IR_TEFN (_U_(0x1) << CAN_IR_TEFN_Pos)
+#define CAN_IR_TEFW_Pos 13 /**< \brief (CAN_IR) Tx Event FIFO Watermark Reached */
+#define CAN_IR_TEFW (_U_(0x1) << CAN_IR_TEFW_Pos)
+#define CAN_IR_TEFF_Pos 14 /**< \brief (CAN_IR) Tx Event FIFO Full */
+#define CAN_IR_TEFF (_U_(0x1) << CAN_IR_TEFF_Pos)
+#define CAN_IR_TEFL_Pos 15 /**< \brief (CAN_IR) Tx Event FIFO Element Lost */
+#define CAN_IR_TEFL (_U_(0x1) << CAN_IR_TEFL_Pos)
+#define CAN_IR_TSW_Pos 16 /**< \brief (CAN_IR) Timestamp Wraparound */
+#define CAN_IR_TSW (_U_(0x1) << CAN_IR_TSW_Pos)
+#define CAN_IR_MRAF_Pos 17 /**< \brief (CAN_IR) Message RAM Access Failure */
+#define CAN_IR_MRAF (_U_(0x1) << CAN_IR_MRAF_Pos)
+#define CAN_IR_TOO_Pos 18 /**< \brief (CAN_IR) Timeout Occurred */
+#define CAN_IR_TOO (_U_(0x1) << CAN_IR_TOO_Pos)
+#define CAN_IR_DRX_Pos 19 /**< \brief (CAN_IR) Message stored to Dedicated Rx Buffer */
+#define CAN_IR_DRX (_U_(0x1) << CAN_IR_DRX_Pos)
+#define CAN_IR_BEC_Pos 20 /**< \brief (CAN_IR) Bit Error Corrected */
+#define CAN_IR_BEC (_U_(0x1) << CAN_IR_BEC_Pos)
+#define CAN_IR_BEU_Pos 21 /**< \brief (CAN_IR) Bit Error Uncorrected */
+#define CAN_IR_BEU (_U_(0x1) << CAN_IR_BEU_Pos)
+#define CAN_IR_ELO_Pos 22 /**< \brief (CAN_IR) Error Logging Overflow */
+#define CAN_IR_ELO (_U_(0x1) << CAN_IR_ELO_Pos)
+#define CAN_IR_EP_Pos 23 /**< \brief (CAN_IR) Error Passive */
+#define CAN_IR_EP (_U_(0x1) << CAN_IR_EP_Pos)
+#define CAN_IR_EW_Pos 24 /**< \brief (CAN_IR) Warning Status */
+#define CAN_IR_EW (_U_(0x1) << CAN_IR_EW_Pos)
+#define CAN_IR_BO_Pos 25 /**< \brief (CAN_IR) Bus_Off Status */
+#define CAN_IR_BO (_U_(0x1) << CAN_IR_BO_Pos)
+#define CAN_IR_WDI_Pos 26 /**< \brief (CAN_IR) Watchdog Interrupt */
+#define CAN_IR_WDI (_U_(0x1) << CAN_IR_WDI_Pos)
+#define CAN_IR_PEA_Pos 27 /**< \brief (CAN_IR) Protocol Error in Arbitration Phase */
+#define CAN_IR_PEA (_U_(0x1) << CAN_IR_PEA_Pos)
+#define CAN_IR_PED_Pos 28 /**< \brief (CAN_IR) Protocol Error in Data Phase */
+#define CAN_IR_PED (_U_(0x1) << CAN_IR_PED_Pos)
+#define CAN_IR_ARA_Pos 29 /**< \brief (CAN_IR) Access to Reserved Address */
+#define CAN_IR_ARA (_U_(0x1) << CAN_IR_ARA_Pos)
+#define CAN_IR_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IR) MASK Register */
+
+/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RF0NE:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Enable */
+ uint32_t RF0WE:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Enable */
+ uint32_t RF0FE:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Enable */
+ uint32_t RF0LE:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Enable */
+ uint32_t RF1NE:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Enable */
+ uint32_t RF1WE:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Enable */
+ uint32_t RF1FE:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Enable */
+ uint32_t RF1LE:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Enable */
+ uint32_t HPME:1; /*!< bit: 8 High Priority Message Interrupt Enable */
+ uint32_t TCE:1; /*!< bit: 9 Timestamp Completed Interrupt Enable */
+ uint32_t TCFE:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Enable */
+ uint32_t TFEE:1; /*!< bit: 11 Tx FIFO Empty Interrupt Enable */
+ uint32_t TEFNE:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Enable */
+ uint32_t TEFWE:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Enable */
+ uint32_t TEFFE:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Enable */
+ uint32_t TEFLE:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Enable */
+ uint32_t TSWE:1; /*!< bit: 16 Timestamp Wraparound Interrupt Enable */
+ uint32_t MRAFE:1; /*!< bit: 17 Message RAM Access Failure Interrupt Enable */
+ uint32_t TOOE:1; /*!< bit: 18 Timeout Occurred Interrupt Enable */
+ uint32_t DRXE:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Enable */
+ uint32_t BECE:1; /*!< bit: 20 Bit Error Corrected Interrupt Enable */
+ uint32_t BEUE:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Enable */
+ uint32_t ELOE:1; /*!< bit: 22 Error Logging Overflow Interrupt Enable */
+ uint32_t EPE:1; /*!< bit: 23 Error Passive Interrupt Enable */
+ uint32_t EWE:1; /*!< bit: 24 Warning Status Interrupt Enable */
+ uint32_t BOE:1; /*!< bit: 25 Bus_Off Status Interrupt Enable */
+ uint32_t WDIE:1; /*!< bit: 26 Watchdog Interrupt Interrupt Enable */
+ uint32_t PEAE:1; /*!< bit: 27 Protocol Error in Arbitration Phase Enable */
+ uint32_t PEDE:1; /*!< bit: 28 Protocol Error in Data Phase Enable */
+ uint32_t ARAE:1; /*!< bit: 29 Access to Reserved Address Enable */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_IE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_IE_OFFSET 0x54 /**< \brief (CAN_IE offset) Interrupt Enable */
+#define CAN_IE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IE reset_value) Interrupt Enable */
+
+#define CAN_IE_RF0NE_Pos 0 /**< \brief (CAN_IE) Rx FIFO 0 New Message Interrupt Enable */
+#define CAN_IE_RF0NE (_U_(0x1) << CAN_IE_RF0NE_Pos)
+#define CAN_IE_RF0WE_Pos 1 /**< \brief (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable */
+#define CAN_IE_RF0WE (_U_(0x1) << CAN_IE_RF0WE_Pos)
+#define CAN_IE_RF0FE_Pos 2 /**< \brief (CAN_IE) Rx FIFO 0 Full Interrupt Enable */
+#define CAN_IE_RF0FE (_U_(0x1) << CAN_IE_RF0FE_Pos)
+#define CAN_IE_RF0LE_Pos 3 /**< \brief (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable */
+#define CAN_IE_RF0LE (_U_(0x1) << CAN_IE_RF0LE_Pos)
+#define CAN_IE_RF1NE_Pos 4 /**< \brief (CAN_IE) Rx FIFO 1 New Message Interrupt Enable */
+#define CAN_IE_RF1NE (_U_(0x1) << CAN_IE_RF1NE_Pos)
+#define CAN_IE_RF1WE_Pos 5 /**< \brief (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable */
+#define CAN_IE_RF1WE (_U_(0x1) << CAN_IE_RF1WE_Pos)
+#define CAN_IE_RF1FE_Pos 6 /**< \brief (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable */
+#define CAN_IE_RF1FE (_U_(0x1) << CAN_IE_RF1FE_Pos)
+#define CAN_IE_RF1LE_Pos 7 /**< \brief (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable */
+#define CAN_IE_RF1LE (_U_(0x1) << CAN_IE_RF1LE_Pos)
+#define CAN_IE_HPME_Pos 8 /**< \brief (CAN_IE) High Priority Message Interrupt Enable */
+#define CAN_IE_HPME (_U_(0x1) << CAN_IE_HPME_Pos)
+#define CAN_IE_TCE_Pos 9 /**< \brief (CAN_IE) Timestamp Completed Interrupt Enable */
+#define CAN_IE_TCE (_U_(0x1) << CAN_IE_TCE_Pos)
+#define CAN_IE_TCFE_Pos 10 /**< \brief (CAN_IE) Transmission Cancellation Finished Interrupt Enable */
+#define CAN_IE_TCFE (_U_(0x1) << CAN_IE_TCFE_Pos)
+#define CAN_IE_TFEE_Pos 11 /**< \brief (CAN_IE) Tx FIFO Empty Interrupt Enable */
+#define CAN_IE_TFEE (_U_(0x1) << CAN_IE_TFEE_Pos)
+#define CAN_IE_TEFNE_Pos 12 /**< \brief (CAN_IE) Tx Event FIFO New Entry Interrupt Enable */
+#define CAN_IE_TEFNE (_U_(0x1) << CAN_IE_TEFNE_Pos)
+#define CAN_IE_TEFWE_Pos 13 /**< \brief (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */
+#define CAN_IE_TEFWE (_U_(0x1) << CAN_IE_TEFWE_Pos)
+#define CAN_IE_TEFFE_Pos 14 /**< \brief (CAN_IE) Tx Event FIFO Full Interrupt Enable */
+#define CAN_IE_TEFFE (_U_(0x1) << CAN_IE_TEFFE_Pos)
+#define CAN_IE_TEFLE_Pos 15 /**< \brief (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable */
+#define CAN_IE_TEFLE (_U_(0x1) << CAN_IE_TEFLE_Pos)
+#define CAN_IE_TSWE_Pos 16 /**< \brief (CAN_IE) Timestamp Wraparound Interrupt Enable */
+#define CAN_IE_TSWE (_U_(0x1) << CAN_IE_TSWE_Pos)
+#define CAN_IE_MRAFE_Pos 17 /**< \brief (CAN_IE) Message RAM Access Failure Interrupt Enable */
+#define CAN_IE_MRAFE (_U_(0x1) << CAN_IE_MRAFE_Pos)
+#define CAN_IE_TOOE_Pos 18 /**< \brief (CAN_IE) Timeout Occurred Interrupt Enable */
+#define CAN_IE_TOOE (_U_(0x1) << CAN_IE_TOOE_Pos)
+#define CAN_IE_DRXE_Pos 19 /**< \brief (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable */
+#define CAN_IE_DRXE (_U_(0x1) << CAN_IE_DRXE_Pos)
+#define CAN_IE_BECE_Pos 20 /**< \brief (CAN_IE) Bit Error Corrected Interrupt Enable */
+#define CAN_IE_BECE (_U_(0x1) << CAN_IE_BECE_Pos)
+#define CAN_IE_BEUE_Pos 21 /**< \brief (CAN_IE) Bit Error Uncorrected Interrupt Enable */
+#define CAN_IE_BEUE (_U_(0x1) << CAN_IE_BEUE_Pos)
+#define CAN_IE_ELOE_Pos 22 /**< \brief (CAN_IE) Error Logging Overflow Interrupt Enable */
+#define CAN_IE_ELOE (_U_(0x1) << CAN_IE_ELOE_Pos)
+#define CAN_IE_EPE_Pos 23 /**< \brief (CAN_IE) Error Passive Interrupt Enable */
+#define CAN_IE_EPE (_U_(0x1) << CAN_IE_EPE_Pos)
+#define CAN_IE_EWE_Pos 24 /**< \brief (CAN_IE) Warning Status Interrupt Enable */
+#define CAN_IE_EWE (_U_(0x1) << CAN_IE_EWE_Pos)
+#define CAN_IE_BOE_Pos 25 /**< \brief (CAN_IE) Bus_Off Status Interrupt Enable */
+#define CAN_IE_BOE (_U_(0x1) << CAN_IE_BOE_Pos)
+#define CAN_IE_WDIE_Pos 26 /**< \brief (CAN_IE) Watchdog Interrupt Interrupt Enable */
+#define CAN_IE_WDIE (_U_(0x1) << CAN_IE_WDIE_Pos)
+#define CAN_IE_PEAE_Pos 27 /**< \brief (CAN_IE) Protocol Error in Arbitration Phase Enable */
+#define CAN_IE_PEAE (_U_(0x1) << CAN_IE_PEAE_Pos)
+#define CAN_IE_PEDE_Pos 28 /**< \brief (CAN_IE) Protocol Error in Data Phase Enable */
+#define CAN_IE_PEDE (_U_(0x1) << CAN_IE_PEDE_Pos)
+#define CAN_IE_ARAE_Pos 29 /**< \brief (CAN_IE) Access to Reserved Address Enable */
+#define CAN_IE_ARAE (_U_(0x1) << CAN_IE_ARAE_Pos)
+#define CAN_IE_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IE) MASK Register */
+
+/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RF0NL:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Line */
+ uint32_t RF0WL:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Line */
+ uint32_t RF0FL:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Line */
+ uint32_t RF0LL:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Line */
+ uint32_t RF1NL:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Line */
+ uint32_t RF1WL:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Line */
+ uint32_t RF1FL:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Line */
+ uint32_t RF1LL:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Line */
+ uint32_t HPML:1; /*!< bit: 8 High Priority Message Interrupt Line */
+ uint32_t TCL:1; /*!< bit: 9 Timestamp Completed Interrupt Line */
+ uint32_t TCFL:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Line */
+ uint32_t TFEL:1; /*!< bit: 11 Tx FIFO Empty Interrupt Line */
+ uint32_t TEFNL:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Line */
+ uint32_t TEFWL:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Line */
+ uint32_t TEFFL:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Line */
+ uint32_t TEFLL:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Line */
+ uint32_t TSWL:1; /*!< bit: 16 Timestamp Wraparound Interrupt Line */
+ uint32_t MRAFL:1; /*!< bit: 17 Message RAM Access Failure Interrupt Line */
+ uint32_t TOOL:1; /*!< bit: 18 Timeout Occurred Interrupt Line */
+ uint32_t DRXL:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Line */
+ uint32_t BECL:1; /*!< bit: 20 Bit Error Corrected Interrupt Line */
+ uint32_t BEUL:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Line */
+ uint32_t ELOL:1; /*!< bit: 22 Error Logging Overflow Interrupt Line */
+ uint32_t EPL:1; /*!< bit: 23 Error Passive Interrupt Line */
+ uint32_t EWL:1; /*!< bit: 24 Warning Status Interrupt Line */
+ uint32_t BOL:1; /*!< bit: 25 Bus_Off Status Interrupt Line */
+ uint32_t WDIL:1; /*!< bit: 26 Watchdog Interrupt Interrupt Line */
+ uint32_t PEAL:1; /*!< bit: 27 Protocol Error in Arbitration Phase Line */
+ uint32_t PEDL:1; /*!< bit: 28 Protocol Error in Data Phase Line */
+ uint32_t ARAL:1; /*!< bit: 29 Access to Reserved Address Line */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_ILS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_ILS_OFFSET 0x58 /**< \brief (CAN_ILS offset) Interrupt Line Select */
+#define CAN_ILS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILS reset_value) Interrupt Line Select */
+
+#define CAN_ILS_RF0NL_Pos 0 /**< \brief (CAN_ILS) Rx FIFO 0 New Message Interrupt Line */
+#define CAN_ILS_RF0NL (_U_(0x1) << CAN_ILS_RF0NL_Pos)
+#define CAN_ILS_RF0WL_Pos 1 /**< \brief (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line */
+#define CAN_ILS_RF0WL (_U_(0x1) << CAN_ILS_RF0WL_Pos)
+#define CAN_ILS_RF0FL_Pos 2 /**< \brief (CAN_ILS) Rx FIFO 0 Full Interrupt Line */
+#define CAN_ILS_RF0FL (_U_(0x1) << CAN_ILS_RF0FL_Pos)
+#define CAN_ILS_RF0LL_Pos 3 /**< \brief (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line */
+#define CAN_ILS_RF0LL (_U_(0x1) << CAN_ILS_RF0LL_Pos)
+#define CAN_ILS_RF1NL_Pos 4 /**< \brief (CAN_ILS) Rx FIFO 1 New Message Interrupt Line */
+#define CAN_ILS_RF1NL (_U_(0x1) << CAN_ILS_RF1NL_Pos)
+#define CAN_ILS_RF1WL_Pos 5 /**< \brief (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line */
+#define CAN_ILS_RF1WL (_U_(0x1) << CAN_ILS_RF1WL_Pos)
+#define CAN_ILS_RF1FL_Pos 6 /**< \brief (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line */
+#define CAN_ILS_RF1FL (_U_(0x1) << CAN_ILS_RF1FL_Pos)
+#define CAN_ILS_RF1LL_Pos 7 /**< \brief (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line */
+#define CAN_ILS_RF1LL (_U_(0x1) << CAN_ILS_RF1LL_Pos)
+#define CAN_ILS_HPML_Pos 8 /**< \brief (CAN_ILS) High Priority Message Interrupt Line */
+#define CAN_ILS_HPML (_U_(0x1) << CAN_ILS_HPML_Pos)
+#define CAN_ILS_TCL_Pos 9 /**< \brief (CAN_ILS) Timestamp Completed Interrupt Line */
+#define CAN_ILS_TCL (_U_(0x1) << CAN_ILS_TCL_Pos)
+#define CAN_ILS_TCFL_Pos 10 /**< \brief (CAN_ILS) Transmission Cancellation Finished Interrupt Line */
+#define CAN_ILS_TCFL (_U_(0x1) << CAN_ILS_TCFL_Pos)
+#define CAN_ILS_TFEL_Pos 11 /**< \brief (CAN_ILS) Tx FIFO Empty Interrupt Line */
+#define CAN_ILS_TFEL (_U_(0x1) << CAN_ILS_TFEL_Pos)
+#define CAN_ILS_TEFNL_Pos 12 /**< \brief (CAN_ILS) Tx Event FIFO New Entry Interrupt Line */
+#define CAN_ILS_TEFNL (_U_(0x1) << CAN_ILS_TEFNL_Pos)
+#define CAN_ILS_TEFWL_Pos 13 /**< \brief (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */
+#define CAN_ILS_TEFWL (_U_(0x1) << CAN_ILS_TEFWL_Pos)
+#define CAN_ILS_TEFFL_Pos 14 /**< \brief (CAN_ILS) Tx Event FIFO Full Interrupt Line */
+#define CAN_ILS_TEFFL (_U_(0x1) << CAN_ILS_TEFFL_Pos)
+#define CAN_ILS_TEFLL_Pos 15 /**< \brief (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line */
+#define CAN_ILS_TEFLL (_U_(0x1) << CAN_ILS_TEFLL_Pos)
+#define CAN_ILS_TSWL_Pos 16 /**< \brief (CAN_ILS) Timestamp Wraparound Interrupt Line */
+#define CAN_ILS_TSWL (_U_(0x1) << CAN_ILS_TSWL_Pos)
+#define CAN_ILS_MRAFL_Pos 17 /**< \brief (CAN_ILS) Message RAM Access Failure Interrupt Line */
+#define CAN_ILS_MRAFL (_U_(0x1) << CAN_ILS_MRAFL_Pos)
+#define CAN_ILS_TOOL_Pos 18 /**< \brief (CAN_ILS) Timeout Occurred Interrupt Line */
+#define CAN_ILS_TOOL (_U_(0x1) << CAN_ILS_TOOL_Pos)
+#define CAN_ILS_DRXL_Pos 19 /**< \brief (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line */
+#define CAN_ILS_DRXL (_U_(0x1) << CAN_ILS_DRXL_Pos)
+#define CAN_ILS_BECL_Pos 20 /**< \brief (CAN_ILS) Bit Error Corrected Interrupt Line */
+#define CAN_ILS_BECL (_U_(0x1) << CAN_ILS_BECL_Pos)
+#define CAN_ILS_BEUL_Pos 21 /**< \brief (CAN_ILS) Bit Error Uncorrected Interrupt Line */
+#define CAN_ILS_BEUL (_U_(0x1) << CAN_ILS_BEUL_Pos)
+#define CAN_ILS_ELOL_Pos 22 /**< \brief (CAN_ILS) Error Logging Overflow Interrupt Line */
+#define CAN_ILS_ELOL (_U_(0x1) << CAN_ILS_ELOL_Pos)
+#define CAN_ILS_EPL_Pos 23 /**< \brief (CAN_ILS) Error Passive Interrupt Line */
+#define CAN_ILS_EPL (_U_(0x1) << CAN_ILS_EPL_Pos)
+#define CAN_ILS_EWL_Pos 24 /**< \brief (CAN_ILS) Warning Status Interrupt Line */
+#define CAN_ILS_EWL (_U_(0x1) << CAN_ILS_EWL_Pos)
+#define CAN_ILS_BOL_Pos 25 /**< \brief (CAN_ILS) Bus_Off Status Interrupt Line */
+#define CAN_ILS_BOL (_U_(0x1) << CAN_ILS_BOL_Pos)
+#define CAN_ILS_WDIL_Pos 26 /**< \brief (CAN_ILS) Watchdog Interrupt Interrupt Line */
+#define CAN_ILS_WDIL (_U_(0x1) << CAN_ILS_WDIL_Pos)
+#define CAN_ILS_PEAL_Pos 27 /**< \brief (CAN_ILS) Protocol Error in Arbitration Phase Line */
+#define CAN_ILS_PEAL (_U_(0x1) << CAN_ILS_PEAL_Pos)
+#define CAN_ILS_PEDL_Pos 28 /**< \brief (CAN_ILS) Protocol Error in Data Phase Line */
+#define CAN_ILS_PEDL (_U_(0x1) << CAN_ILS_PEDL_Pos)
+#define CAN_ILS_ARAL_Pos 29 /**< \brief (CAN_ILS) Access to Reserved Address Line */
+#define CAN_ILS_ARAL (_U_(0x1) << CAN_ILS_ARAL_Pos)
+#define CAN_ILS_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_ILS) MASK Register */
+
+/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EINT0:1; /*!< bit: 0 Enable Interrupt Line 0 */
+ uint32_t EINT1:1; /*!< bit: 1 Enable Interrupt Line 1 */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_ILE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_ILE_OFFSET 0x5C /**< \brief (CAN_ILE offset) Interrupt Line Enable */
+#define CAN_ILE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILE reset_value) Interrupt Line Enable */
+
+#define CAN_ILE_EINT0_Pos 0 /**< \brief (CAN_ILE) Enable Interrupt Line 0 */
+#define CAN_ILE_EINT0 (_U_(0x1) << CAN_ILE_EINT0_Pos)
+#define CAN_ILE_EINT1_Pos 1 /**< \brief (CAN_ILE) Enable Interrupt Line 1 */
+#define CAN_ILE_EINT1 (_U_(0x1) << CAN_ILE_EINT1_Pos)
+#define CAN_ILE_MASK _U_(0x00000003) /**< \brief (CAN_ILE) MASK Register */
+
+/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RRFE:1; /*!< bit: 0 Reject Remote Frames Extended */
+ uint32_t RRFS:1; /*!< bit: 1 Reject Remote Frames Standard */
+ uint32_t ANFE:2; /*!< bit: 2.. 3 Accept Non-matching Frames Extended */
+ uint32_t ANFS:2; /*!< bit: 4.. 5 Accept Non-matching Frames Standard */
+ uint32_t :26; /*!< bit: 6..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_GFC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_GFC_OFFSET 0x80 /**< \brief (CAN_GFC offset) Global Filter Configuration */
+#define CAN_GFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_GFC reset_value) Global Filter Configuration */
+
+#define CAN_GFC_RRFE_Pos 0 /**< \brief (CAN_GFC) Reject Remote Frames Extended */
+#define CAN_GFC_RRFE (_U_(0x1) << CAN_GFC_RRFE_Pos)
+#define CAN_GFC_RRFS_Pos 1 /**< \brief (CAN_GFC) Reject Remote Frames Standard */
+#define CAN_GFC_RRFS (_U_(0x1) << CAN_GFC_RRFS_Pos)
+#define CAN_GFC_ANFE_Pos 2 /**< \brief (CAN_GFC) Accept Non-matching Frames Extended */
+#define CAN_GFC_ANFE_Msk (_U_(0x3) << CAN_GFC_ANFE_Pos)
+#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & ((value) << CAN_GFC_ANFE_Pos))
+#define CAN_GFC_ANFE_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */
+#define CAN_GFC_ANFE_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */
+#define CAN_GFC_ANFE_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */
+#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos)
+#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos)
+#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos)
+#define CAN_GFC_ANFS_Pos 4 /**< \brief (CAN_GFC) Accept Non-matching Frames Standard */
+#define CAN_GFC_ANFS_Msk (_U_(0x3) << CAN_GFC_ANFS_Pos)
+#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & ((value) << CAN_GFC_ANFS_Pos))
+#define CAN_GFC_ANFS_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */
+#define CAN_GFC_ANFS_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */
+#define CAN_GFC_ANFS_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */
+#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos)
+#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos)
+#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos)
+#define CAN_GFC_MASK _U_(0x0000003F) /**< \brief (CAN_GFC) MASK Register */
+
+/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FLSSA:16; /*!< bit: 0..15 Filter List Standard Start Address */
+ uint32_t LSS:8; /*!< bit: 16..23 List Size Standard */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_SIDFC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_SIDFC_OFFSET 0x84 /**< \brief (CAN_SIDFC offset) Standard ID Filter Configuration */
+#define CAN_SIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFC reset_value) Standard ID Filter Configuration */
+
+#define CAN_SIDFC_FLSSA_Pos 0 /**< \brief (CAN_SIDFC) Filter List Standard Start Address */
+#define CAN_SIDFC_FLSSA_Msk (_U_(0xFFFF) << CAN_SIDFC_FLSSA_Pos)
+#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & ((value) << CAN_SIDFC_FLSSA_Pos))
+#define CAN_SIDFC_LSS_Pos 16 /**< \brief (CAN_SIDFC) List Size Standard */
+#define CAN_SIDFC_LSS_Msk (_U_(0xFF) << CAN_SIDFC_LSS_Pos)
+#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & ((value) << CAN_SIDFC_LSS_Pos))
+#define CAN_SIDFC_MASK _U_(0x00FFFFFF) /**< \brief (CAN_SIDFC) MASK Register */
+
+/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FLESA:16; /*!< bit: 0..15 Filter List Extended Start Address */
+ uint32_t LSE:7; /*!< bit: 16..22 List Size Extended */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_XIDFC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_XIDFC_OFFSET 0x88 /**< \brief (CAN_XIDFC offset) Extended ID Filter Configuration */
+#define CAN_XIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFC reset_value) Extended ID Filter Configuration */
+
+#define CAN_XIDFC_FLESA_Pos 0 /**< \brief (CAN_XIDFC) Filter List Extended Start Address */
+#define CAN_XIDFC_FLESA_Msk (_U_(0xFFFF) << CAN_XIDFC_FLESA_Pos)
+#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & ((value) << CAN_XIDFC_FLESA_Pos))
+#define CAN_XIDFC_LSE_Pos 16 /**< \brief (CAN_XIDFC) List Size Extended */
+#define CAN_XIDFC_LSE_Msk (_U_(0x7F) << CAN_XIDFC_LSE_Pos)
+#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & ((value) << CAN_XIDFC_LSE_Pos))
+#define CAN_XIDFC_MASK _U_(0x007FFFFF) /**< \brief (CAN_XIDFC) MASK Register */
+
+/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EIDM:29; /*!< bit: 0..28 Extended ID Mask */
+ uint32_t :3; /*!< bit: 29..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_XIDAM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_XIDAM_OFFSET 0x90 /**< \brief (CAN_XIDAM offset) Extended ID AND Mask */
+#define CAN_XIDAM_RESETVALUE _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM reset_value) Extended ID AND Mask */
+
+#define CAN_XIDAM_EIDM_Pos 0 /**< \brief (CAN_XIDAM) Extended ID Mask */
+#define CAN_XIDAM_EIDM_Msk (_U_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos)
+#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & ((value) << CAN_XIDAM_EIDM_Pos))
+#define CAN_XIDAM_MASK _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM) MASK Register */
+
+/* -------- CAN_HPMS : (CAN Offset: 0x94) (R/ 32) High Priority Message Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BIDX:6; /*!< bit: 0.. 5 Buffer Index */
+ uint32_t MSI:2; /*!< bit: 6.. 7 Message Storage Indicator */
+ uint32_t FIDX:7; /*!< bit: 8..14 Filter Index */
+ uint32_t FLST:1; /*!< bit: 15 Filter List */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_HPMS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_HPMS_OFFSET 0x94 /**< \brief (CAN_HPMS offset) High Priority Message Status */
+#define CAN_HPMS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_HPMS reset_value) High Priority Message Status */
+
+#define CAN_HPMS_BIDX_Pos 0 /**< \brief (CAN_HPMS) Buffer Index */
+#define CAN_HPMS_BIDX_Msk (_U_(0x3F) << CAN_HPMS_BIDX_Pos)
+#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & ((value) << CAN_HPMS_BIDX_Pos))
+#define CAN_HPMS_MSI_Pos 6 /**< \brief (CAN_HPMS) Message Storage Indicator */
+#define CAN_HPMS_MSI_Msk (_U_(0x3) << CAN_HPMS_MSI_Pos)
+#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & ((value) << CAN_HPMS_MSI_Pos))
+#define CAN_HPMS_MSI_NONE_Val _U_(0x0) /**< \brief (CAN_HPMS) No FIFO selected */
+#define CAN_HPMS_MSI_LOST_Val _U_(0x1) /**< \brief (CAN_HPMS) FIFO message lost */
+#define CAN_HPMS_MSI_FIFO0_Val _U_(0x2) /**< \brief (CAN_HPMS) Message stored in FIFO 0 */
+#define CAN_HPMS_MSI_FIFO1_Val _U_(0x3) /**< \brief (CAN_HPMS) Message stored in FIFO 1 */
+#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos)
+#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos)
+#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos)
+#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos)
+#define CAN_HPMS_FIDX_Pos 8 /**< \brief (CAN_HPMS) Filter Index */
+#define CAN_HPMS_FIDX_Msk (_U_(0x7F) << CAN_HPMS_FIDX_Pos)
+#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & ((value) << CAN_HPMS_FIDX_Pos))
+#define CAN_HPMS_FLST_Pos 15 /**< \brief (CAN_HPMS) Filter List */
+#define CAN_HPMS_FLST (_U_(0x1) << CAN_HPMS_FLST_Pos)
+#define CAN_HPMS_MASK _U_(0x0000FFFF) /**< \brief (CAN_HPMS) MASK Register */
+
+/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ND0:1; /*!< bit: 0 New Data 0 */
+ uint32_t ND1:1; /*!< bit: 1 New Data 1 */
+ uint32_t ND2:1; /*!< bit: 2 New Data 2 */
+ uint32_t ND3:1; /*!< bit: 3 New Data 3 */
+ uint32_t ND4:1; /*!< bit: 4 New Data 4 */
+ uint32_t ND5:1; /*!< bit: 5 New Data 5 */
+ uint32_t ND6:1; /*!< bit: 6 New Data 6 */
+ uint32_t ND7:1; /*!< bit: 7 New Data 7 */
+ uint32_t ND8:1; /*!< bit: 8 New Data 8 */
+ uint32_t ND9:1; /*!< bit: 9 New Data 9 */
+ uint32_t ND10:1; /*!< bit: 10 New Data 10 */
+ uint32_t ND11:1; /*!< bit: 11 New Data 11 */
+ uint32_t ND12:1; /*!< bit: 12 New Data 12 */
+ uint32_t ND13:1; /*!< bit: 13 New Data 13 */
+ uint32_t ND14:1; /*!< bit: 14 New Data 14 */
+ uint32_t ND15:1; /*!< bit: 15 New Data 15 */
+ uint32_t ND16:1; /*!< bit: 16 New Data 16 */
+ uint32_t ND17:1; /*!< bit: 17 New Data 17 */
+ uint32_t ND18:1; /*!< bit: 18 New Data 18 */
+ uint32_t ND19:1; /*!< bit: 19 New Data 19 */
+ uint32_t ND20:1; /*!< bit: 20 New Data 20 */
+ uint32_t ND21:1; /*!< bit: 21 New Data 21 */
+ uint32_t ND22:1; /*!< bit: 22 New Data 22 */
+ uint32_t ND23:1; /*!< bit: 23 New Data 23 */
+ uint32_t ND24:1; /*!< bit: 24 New Data 24 */
+ uint32_t ND25:1; /*!< bit: 25 New Data 25 */
+ uint32_t ND26:1; /*!< bit: 26 New Data 26 */
+ uint32_t ND27:1; /*!< bit: 27 New Data 27 */
+ uint32_t ND28:1; /*!< bit: 28 New Data 28 */
+ uint32_t ND29:1; /*!< bit: 29 New Data 29 */
+ uint32_t ND30:1; /*!< bit: 30 New Data 30 */
+ uint32_t ND31:1; /*!< bit: 31 New Data 31 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_NDAT1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_NDAT1_OFFSET 0x98 /**< \brief (CAN_NDAT1 offset) New Data 1 */
+#define CAN_NDAT1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_NDAT1 reset_value) New Data 1 */
+
+#define CAN_NDAT1_ND0_Pos 0 /**< \brief (CAN_NDAT1) New Data 0 */
+#define CAN_NDAT1_ND0 (_U_(0x1) << CAN_NDAT1_ND0_Pos)
+#define CAN_NDAT1_ND1_Pos 1 /**< \brief (CAN_NDAT1) New Data 1 */
+#define CAN_NDAT1_ND1 (_U_(0x1) << CAN_NDAT1_ND1_Pos)
+#define CAN_NDAT1_ND2_Pos 2 /**< \brief (CAN_NDAT1) New Data 2 */
+#define CAN_NDAT1_ND2 (_U_(0x1) << CAN_NDAT1_ND2_Pos)
+#define CAN_NDAT1_ND3_Pos 3 /**< \brief (CAN_NDAT1) New Data 3 */
+#define CAN_NDAT1_ND3 (_U_(0x1) << CAN_NDAT1_ND3_Pos)
+#define CAN_NDAT1_ND4_Pos 4 /**< \brief (CAN_NDAT1) New Data 4 */
+#define CAN_NDAT1_ND4 (_U_(0x1) << CAN_NDAT1_ND4_Pos)
+#define CAN_NDAT1_ND5_Pos 5 /**< \brief (CAN_NDAT1) New Data 5 */
+#define CAN_NDAT1_ND5 (_U_(0x1) << CAN_NDAT1_ND5_Pos)
+#define CAN_NDAT1_ND6_Pos 6 /**< \brief (CAN_NDAT1) New Data 6 */
+#define CAN_NDAT1_ND6 (_U_(0x1) << CAN_NDAT1_ND6_Pos)
+#define CAN_NDAT1_ND7_Pos 7 /**< \brief (CAN_NDAT1) New Data 7 */
+#define CAN_NDAT1_ND7 (_U_(0x1) << CAN_NDAT1_ND7_Pos)
+#define CAN_NDAT1_ND8_Pos 8 /**< \brief (CAN_NDAT1) New Data 8 */
+#define CAN_NDAT1_ND8 (_U_(0x1) << CAN_NDAT1_ND8_Pos)
+#define CAN_NDAT1_ND9_Pos 9 /**< \brief (CAN_NDAT1) New Data 9 */
+#define CAN_NDAT1_ND9 (_U_(0x1) << CAN_NDAT1_ND9_Pos)
+#define CAN_NDAT1_ND10_Pos 10 /**< \brief (CAN_NDAT1) New Data 10 */
+#define CAN_NDAT1_ND10 (_U_(0x1) << CAN_NDAT1_ND10_Pos)
+#define CAN_NDAT1_ND11_Pos 11 /**< \brief (CAN_NDAT1) New Data 11 */
+#define CAN_NDAT1_ND11 (_U_(0x1) << CAN_NDAT1_ND11_Pos)
+#define CAN_NDAT1_ND12_Pos 12 /**< \brief (CAN_NDAT1) New Data 12 */
+#define CAN_NDAT1_ND12 (_U_(0x1) << CAN_NDAT1_ND12_Pos)
+#define CAN_NDAT1_ND13_Pos 13 /**< \brief (CAN_NDAT1) New Data 13 */
+#define CAN_NDAT1_ND13 (_U_(0x1) << CAN_NDAT1_ND13_Pos)
+#define CAN_NDAT1_ND14_Pos 14 /**< \brief (CAN_NDAT1) New Data 14 */
+#define CAN_NDAT1_ND14 (_U_(0x1) << CAN_NDAT1_ND14_Pos)
+#define CAN_NDAT1_ND15_Pos 15 /**< \brief (CAN_NDAT1) New Data 15 */
+#define CAN_NDAT1_ND15 (_U_(0x1) << CAN_NDAT1_ND15_Pos)
+#define CAN_NDAT1_ND16_Pos 16 /**< \brief (CAN_NDAT1) New Data 16 */
+#define CAN_NDAT1_ND16 (_U_(0x1) << CAN_NDAT1_ND16_Pos)
+#define CAN_NDAT1_ND17_Pos 17 /**< \brief (CAN_NDAT1) New Data 17 */
+#define CAN_NDAT1_ND17 (_U_(0x1) << CAN_NDAT1_ND17_Pos)
+#define CAN_NDAT1_ND18_Pos 18 /**< \brief (CAN_NDAT1) New Data 18 */
+#define CAN_NDAT1_ND18 (_U_(0x1) << CAN_NDAT1_ND18_Pos)
+#define CAN_NDAT1_ND19_Pos 19 /**< \brief (CAN_NDAT1) New Data 19 */
+#define CAN_NDAT1_ND19 (_U_(0x1) << CAN_NDAT1_ND19_Pos)
+#define CAN_NDAT1_ND20_Pos 20 /**< \brief (CAN_NDAT1) New Data 20 */
+#define CAN_NDAT1_ND20 (_U_(0x1) << CAN_NDAT1_ND20_Pos)
+#define CAN_NDAT1_ND21_Pos 21 /**< \brief (CAN_NDAT1) New Data 21 */
+#define CAN_NDAT1_ND21 (_U_(0x1) << CAN_NDAT1_ND21_Pos)
+#define CAN_NDAT1_ND22_Pos 22 /**< \brief (CAN_NDAT1) New Data 22 */
+#define CAN_NDAT1_ND22 (_U_(0x1) << CAN_NDAT1_ND22_Pos)
+#define CAN_NDAT1_ND23_Pos 23 /**< \brief (CAN_NDAT1) New Data 23 */
+#define CAN_NDAT1_ND23 (_U_(0x1) << CAN_NDAT1_ND23_Pos)
+#define CAN_NDAT1_ND24_Pos 24 /**< \brief (CAN_NDAT1) New Data 24 */
+#define CAN_NDAT1_ND24 (_U_(0x1) << CAN_NDAT1_ND24_Pos)
+#define CAN_NDAT1_ND25_Pos 25 /**< \brief (CAN_NDAT1) New Data 25 */
+#define CAN_NDAT1_ND25 (_U_(0x1) << CAN_NDAT1_ND25_Pos)
+#define CAN_NDAT1_ND26_Pos 26 /**< \brief (CAN_NDAT1) New Data 26 */
+#define CAN_NDAT1_ND26 (_U_(0x1) << CAN_NDAT1_ND26_Pos)
+#define CAN_NDAT1_ND27_Pos 27 /**< \brief (CAN_NDAT1) New Data 27 */
+#define CAN_NDAT1_ND27 (_U_(0x1) << CAN_NDAT1_ND27_Pos)
+#define CAN_NDAT1_ND28_Pos 28 /**< \brief (CAN_NDAT1) New Data 28 */
+#define CAN_NDAT1_ND28 (_U_(0x1) << CAN_NDAT1_ND28_Pos)
+#define CAN_NDAT1_ND29_Pos 29 /**< \brief (CAN_NDAT1) New Data 29 */
+#define CAN_NDAT1_ND29 (_U_(0x1) << CAN_NDAT1_ND29_Pos)
+#define CAN_NDAT1_ND30_Pos 30 /**< \brief (CAN_NDAT1) New Data 30 */
+#define CAN_NDAT1_ND30 (_U_(0x1) << CAN_NDAT1_ND30_Pos)
+#define CAN_NDAT1_ND31_Pos 31 /**< \brief (CAN_NDAT1) New Data 31 */
+#define CAN_NDAT1_ND31 (_U_(0x1) << CAN_NDAT1_ND31_Pos)
+#define CAN_NDAT1_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_NDAT1) MASK Register */
+
+/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ND32:1; /*!< bit: 0 New Data 32 */
+ uint32_t ND33:1; /*!< bit: 1 New Data 33 */
+ uint32_t ND34:1; /*!< bit: 2 New Data 34 */
+ uint32_t ND35:1; /*!< bit: 3 New Data 35 */
+ uint32_t ND36:1; /*!< bit: 4 New Data 36 */
+ uint32_t ND37:1; /*!< bit: 5 New Data 37 */
+ uint32_t ND38:1; /*!< bit: 6 New Data 38 */
+ uint32_t ND39:1; /*!< bit: 7 New Data 39 */
+ uint32_t ND40:1; /*!< bit: 8 New Data 40 */
+ uint32_t ND41:1; /*!< bit: 9 New Data 41 */
+ uint32_t ND42:1; /*!< bit: 10 New Data 42 */
+ uint32_t ND43:1; /*!< bit: 11 New Data 43 */
+ uint32_t ND44:1; /*!< bit: 12 New Data 44 */
+ uint32_t ND45:1; /*!< bit: 13 New Data 45 */
+ uint32_t ND46:1; /*!< bit: 14 New Data 46 */
+ uint32_t ND47:1; /*!< bit: 15 New Data 47 */
+ uint32_t ND48:1; /*!< bit: 16 New Data 48 */
+ uint32_t ND49:1; /*!< bit: 17 New Data 49 */
+ uint32_t ND50:1; /*!< bit: 18 New Data 50 */
+ uint32_t ND51:1; /*!< bit: 19 New Data 51 */
+ uint32_t ND52:1; /*!< bit: 20 New Data 52 */
+ uint32_t ND53:1; /*!< bit: 21 New Data 53 */
+ uint32_t ND54:1; /*!< bit: 22 New Data 54 */
+ uint32_t ND55:1; /*!< bit: 23 New Data 55 */
+ uint32_t ND56:1; /*!< bit: 24 New Data 56 */
+ uint32_t ND57:1; /*!< bit: 25 New Data 57 */
+ uint32_t ND58:1; /*!< bit: 26 New Data 58 */
+ uint32_t ND59:1; /*!< bit: 27 New Data 59 */
+ uint32_t ND60:1; /*!< bit: 28 New Data 60 */
+ uint32_t ND61:1; /*!< bit: 29 New Data 61 */
+ uint32_t ND62:1; /*!< bit: 30 New Data 62 */
+ uint32_t ND63:1; /*!< bit: 31 New Data 63 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_NDAT2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_NDAT2_OFFSET 0x9C /**< \brief (CAN_NDAT2 offset) New Data 2 */
+#define CAN_NDAT2_RESETVALUE _U_(0x00000000) /**< \brief (CAN_NDAT2 reset_value) New Data 2 */
+
+#define CAN_NDAT2_ND32_Pos 0 /**< \brief (CAN_NDAT2) New Data 32 */
+#define CAN_NDAT2_ND32 (_U_(0x1) << CAN_NDAT2_ND32_Pos)
+#define CAN_NDAT2_ND33_Pos 1 /**< \brief (CAN_NDAT2) New Data 33 */
+#define CAN_NDAT2_ND33 (_U_(0x1) << CAN_NDAT2_ND33_Pos)
+#define CAN_NDAT2_ND34_Pos 2 /**< \brief (CAN_NDAT2) New Data 34 */
+#define CAN_NDAT2_ND34 (_U_(0x1) << CAN_NDAT2_ND34_Pos)
+#define CAN_NDAT2_ND35_Pos 3 /**< \brief (CAN_NDAT2) New Data 35 */
+#define CAN_NDAT2_ND35 (_U_(0x1) << CAN_NDAT2_ND35_Pos)
+#define CAN_NDAT2_ND36_Pos 4 /**< \brief (CAN_NDAT2) New Data 36 */
+#define CAN_NDAT2_ND36 (_U_(0x1) << CAN_NDAT2_ND36_Pos)
+#define CAN_NDAT2_ND37_Pos 5 /**< \brief (CAN_NDAT2) New Data 37 */
+#define CAN_NDAT2_ND37 (_U_(0x1) << CAN_NDAT2_ND37_Pos)
+#define CAN_NDAT2_ND38_Pos 6 /**< \brief (CAN_NDAT2) New Data 38 */
+#define CAN_NDAT2_ND38 (_U_(0x1) << CAN_NDAT2_ND38_Pos)
+#define CAN_NDAT2_ND39_Pos 7 /**< \brief (CAN_NDAT2) New Data 39 */
+#define CAN_NDAT2_ND39 (_U_(0x1) << CAN_NDAT2_ND39_Pos)
+#define CAN_NDAT2_ND40_Pos 8 /**< \brief (CAN_NDAT2) New Data 40 */
+#define CAN_NDAT2_ND40 (_U_(0x1) << CAN_NDAT2_ND40_Pos)
+#define CAN_NDAT2_ND41_Pos 9 /**< \brief (CAN_NDAT2) New Data 41 */
+#define CAN_NDAT2_ND41 (_U_(0x1) << CAN_NDAT2_ND41_Pos)
+#define CAN_NDAT2_ND42_Pos 10 /**< \brief (CAN_NDAT2) New Data 42 */
+#define CAN_NDAT2_ND42 (_U_(0x1) << CAN_NDAT2_ND42_Pos)
+#define CAN_NDAT2_ND43_Pos 11 /**< \brief (CAN_NDAT2) New Data 43 */
+#define CAN_NDAT2_ND43 (_U_(0x1) << CAN_NDAT2_ND43_Pos)
+#define CAN_NDAT2_ND44_Pos 12 /**< \brief (CAN_NDAT2) New Data 44 */
+#define CAN_NDAT2_ND44 (_U_(0x1) << CAN_NDAT2_ND44_Pos)
+#define CAN_NDAT2_ND45_Pos 13 /**< \brief (CAN_NDAT2) New Data 45 */
+#define CAN_NDAT2_ND45 (_U_(0x1) << CAN_NDAT2_ND45_Pos)
+#define CAN_NDAT2_ND46_Pos 14 /**< \brief (CAN_NDAT2) New Data 46 */
+#define CAN_NDAT2_ND46 (_U_(0x1) << CAN_NDAT2_ND46_Pos)
+#define CAN_NDAT2_ND47_Pos 15 /**< \brief (CAN_NDAT2) New Data 47 */
+#define CAN_NDAT2_ND47 (_U_(0x1) << CAN_NDAT2_ND47_Pos)
+#define CAN_NDAT2_ND48_Pos 16 /**< \brief (CAN_NDAT2) New Data 48 */
+#define CAN_NDAT2_ND48 (_U_(0x1) << CAN_NDAT2_ND48_Pos)
+#define CAN_NDAT2_ND49_Pos 17 /**< \brief (CAN_NDAT2) New Data 49 */
+#define CAN_NDAT2_ND49 (_U_(0x1) << CAN_NDAT2_ND49_Pos)
+#define CAN_NDAT2_ND50_Pos 18 /**< \brief (CAN_NDAT2) New Data 50 */
+#define CAN_NDAT2_ND50 (_U_(0x1) << CAN_NDAT2_ND50_Pos)
+#define CAN_NDAT2_ND51_Pos 19 /**< \brief (CAN_NDAT2) New Data 51 */
+#define CAN_NDAT2_ND51 (_U_(0x1) << CAN_NDAT2_ND51_Pos)
+#define CAN_NDAT2_ND52_Pos 20 /**< \brief (CAN_NDAT2) New Data 52 */
+#define CAN_NDAT2_ND52 (_U_(0x1) << CAN_NDAT2_ND52_Pos)
+#define CAN_NDAT2_ND53_Pos 21 /**< \brief (CAN_NDAT2) New Data 53 */
+#define CAN_NDAT2_ND53 (_U_(0x1) << CAN_NDAT2_ND53_Pos)
+#define CAN_NDAT2_ND54_Pos 22 /**< \brief (CAN_NDAT2) New Data 54 */
+#define CAN_NDAT2_ND54 (_U_(0x1) << CAN_NDAT2_ND54_Pos)
+#define CAN_NDAT2_ND55_Pos 23 /**< \brief (CAN_NDAT2) New Data 55 */
+#define CAN_NDAT2_ND55 (_U_(0x1) << CAN_NDAT2_ND55_Pos)
+#define CAN_NDAT2_ND56_Pos 24 /**< \brief (CAN_NDAT2) New Data 56 */
+#define CAN_NDAT2_ND56 (_U_(0x1) << CAN_NDAT2_ND56_Pos)
+#define CAN_NDAT2_ND57_Pos 25 /**< \brief (CAN_NDAT2) New Data 57 */
+#define CAN_NDAT2_ND57 (_U_(0x1) << CAN_NDAT2_ND57_Pos)
+#define CAN_NDAT2_ND58_Pos 26 /**< \brief (CAN_NDAT2) New Data 58 */
+#define CAN_NDAT2_ND58 (_U_(0x1) << CAN_NDAT2_ND58_Pos)
+#define CAN_NDAT2_ND59_Pos 27 /**< \brief (CAN_NDAT2) New Data 59 */
+#define CAN_NDAT2_ND59 (_U_(0x1) << CAN_NDAT2_ND59_Pos)
+#define CAN_NDAT2_ND60_Pos 28 /**< \brief (CAN_NDAT2) New Data 60 */
+#define CAN_NDAT2_ND60 (_U_(0x1) << CAN_NDAT2_ND60_Pos)
+#define CAN_NDAT2_ND61_Pos 29 /**< \brief (CAN_NDAT2) New Data 61 */
+#define CAN_NDAT2_ND61 (_U_(0x1) << CAN_NDAT2_ND61_Pos)
+#define CAN_NDAT2_ND62_Pos 30 /**< \brief (CAN_NDAT2) New Data 62 */
+#define CAN_NDAT2_ND62 (_U_(0x1) << CAN_NDAT2_ND62_Pos)
+#define CAN_NDAT2_ND63_Pos 31 /**< \brief (CAN_NDAT2) New Data 63 */
+#define CAN_NDAT2_ND63 (_U_(0x1) << CAN_NDAT2_ND63_Pos)
+#define CAN_NDAT2_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_NDAT2) MASK Register */
+
+/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t F0SA:16; /*!< bit: 0..15 Rx FIFO 0 Start Address */
+ uint32_t F0S:7; /*!< bit: 16..22 Rx FIFO 0 Size */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t F0WM:7; /*!< bit: 24..30 Rx FIFO 0 Watermark */
+ uint32_t F0OM:1; /*!< bit: 31 FIFO 0 Operation Mode */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF0C_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF0C_OFFSET 0xA0 /**< \brief (CAN_RXF0C offset) Rx FIFO 0 Configuration */
+#define CAN_RXF0C_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0C reset_value) Rx FIFO 0 Configuration */
+
+#define CAN_RXF0C_F0SA_Pos 0 /**< \brief (CAN_RXF0C) Rx FIFO 0 Start Address */
+#define CAN_RXF0C_F0SA_Msk (_U_(0xFFFF) << CAN_RXF0C_F0SA_Pos)
+#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & ((value) << CAN_RXF0C_F0SA_Pos))
+#define CAN_RXF0C_F0S_Pos 16 /**< \brief (CAN_RXF0C) Rx FIFO 0 Size */
+#define CAN_RXF0C_F0S_Msk (_U_(0x7F) << CAN_RXF0C_F0S_Pos)
+#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & ((value) << CAN_RXF0C_F0S_Pos))
+#define CAN_RXF0C_F0WM_Pos 24 /**< \brief (CAN_RXF0C) Rx FIFO 0 Watermark */
+#define CAN_RXF0C_F0WM_Msk (_U_(0x7F) << CAN_RXF0C_F0WM_Pos)
+#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & ((value) << CAN_RXF0C_F0WM_Pos))
+#define CAN_RXF0C_F0OM_Pos 31 /**< \brief (CAN_RXF0C) FIFO 0 Operation Mode */
+#define CAN_RXF0C_F0OM (_U_(0x1) << CAN_RXF0C_F0OM_Pos)
+#define CAN_RXF0C_MASK _U_(0xFF7FFFFF) /**< \brief (CAN_RXF0C) MASK Register */
+
+/* -------- CAN_RXF0S : (CAN Offset: 0xA4) (R/ 32) Rx FIFO 0 Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t F0FL:7; /*!< bit: 0.. 6 Rx FIFO 0 Fill Level */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t F0GI:6; /*!< bit: 8..13 Rx FIFO 0 Get Index */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t F0PI:6; /*!< bit: 16..21 Rx FIFO 0 Put Index */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t F0F:1; /*!< bit: 24 Rx FIFO 0 Full */
+ uint32_t RF0L:1; /*!< bit: 25 Rx FIFO 0 Message Lost */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF0S_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF0S_OFFSET 0xA4 /**< \brief (CAN_RXF0S offset) Rx FIFO 0 Status */
+#define CAN_RXF0S_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0S reset_value) Rx FIFO 0 Status */
+
+#define CAN_RXF0S_F0FL_Pos 0 /**< \brief (CAN_RXF0S) Rx FIFO 0 Fill Level */
+#define CAN_RXF0S_F0FL_Msk (_U_(0x7F) << CAN_RXF0S_F0FL_Pos)
+#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & ((value) << CAN_RXF0S_F0FL_Pos))
+#define CAN_RXF0S_F0GI_Pos 8 /**< \brief (CAN_RXF0S) Rx FIFO 0 Get Index */
+#define CAN_RXF0S_F0GI_Msk (_U_(0x3F) << CAN_RXF0S_F0GI_Pos)
+#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & ((value) << CAN_RXF0S_F0GI_Pos))
+#define CAN_RXF0S_F0PI_Pos 16 /**< \brief (CAN_RXF0S) Rx FIFO 0 Put Index */
+#define CAN_RXF0S_F0PI_Msk (_U_(0x3F) << CAN_RXF0S_F0PI_Pos)
+#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & ((value) << CAN_RXF0S_F0PI_Pos))
+#define CAN_RXF0S_F0F_Pos 24 /**< \brief (CAN_RXF0S) Rx FIFO 0 Full */
+#define CAN_RXF0S_F0F (_U_(0x1) << CAN_RXF0S_F0F_Pos)
+#define CAN_RXF0S_RF0L_Pos 25 /**< \brief (CAN_RXF0S) Rx FIFO 0 Message Lost */
+#define CAN_RXF0S_RF0L (_U_(0x1) << CAN_RXF0S_RF0L_Pos)
+#define CAN_RXF0S_MASK _U_(0x033F3F7F) /**< \brief (CAN_RXF0S) MASK Register */
+
+/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t F0AI:6; /*!< bit: 0.. 5 Rx FIFO 0 Acknowledge Index */
+ uint32_t :26; /*!< bit: 6..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF0A_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF0A_OFFSET 0xA8 /**< \brief (CAN_RXF0A offset) Rx FIFO 0 Acknowledge */
+#define CAN_RXF0A_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0A reset_value) Rx FIFO 0 Acknowledge */
+
+#define CAN_RXF0A_F0AI_Pos 0 /**< \brief (CAN_RXF0A) Rx FIFO 0 Acknowledge Index */
+#define CAN_RXF0A_F0AI_Msk (_U_(0x3F) << CAN_RXF0A_F0AI_Pos)
+#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & ((value) << CAN_RXF0A_F0AI_Pos))
+#define CAN_RXF0A_MASK _U_(0x0000003F) /**< \brief (CAN_RXF0A) MASK Register */
+
+/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RBSA:16; /*!< bit: 0..15 Rx Buffer Start Address */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXBC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXBC_OFFSET 0xAC /**< \brief (CAN_RXBC offset) Rx Buffer Configuration */
+#define CAN_RXBC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBC reset_value) Rx Buffer Configuration */
+
+#define CAN_RXBC_RBSA_Pos 0 /**< \brief (CAN_RXBC) Rx Buffer Start Address */
+#define CAN_RXBC_RBSA_Msk (_U_(0xFFFF) << CAN_RXBC_RBSA_Pos)
+#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & ((value) << CAN_RXBC_RBSA_Pos))
+#define CAN_RXBC_MASK _U_(0x0000FFFF) /**< \brief (CAN_RXBC) MASK Register */
+
+/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t F1SA:16; /*!< bit: 0..15 Rx FIFO 1 Start Address */
+ uint32_t F1S:7; /*!< bit: 16..22 Rx FIFO 1 Size */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t F1WM:7; /*!< bit: 24..30 Rx FIFO 1 Watermark */
+ uint32_t F1OM:1; /*!< bit: 31 FIFO 1 Operation Mode */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF1C_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF1C_OFFSET 0xB0 /**< \brief (CAN_RXF1C offset) Rx FIFO 1 Configuration */
+#define CAN_RXF1C_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1C reset_value) Rx FIFO 1 Configuration */
+
+#define CAN_RXF1C_F1SA_Pos 0 /**< \brief (CAN_RXF1C) Rx FIFO 1 Start Address */
+#define CAN_RXF1C_F1SA_Msk (_U_(0xFFFF) << CAN_RXF1C_F1SA_Pos)
+#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & ((value) << CAN_RXF1C_F1SA_Pos))
+#define CAN_RXF1C_F1S_Pos 16 /**< \brief (CAN_RXF1C) Rx FIFO 1 Size */
+#define CAN_RXF1C_F1S_Msk (_U_(0x7F) << CAN_RXF1C_F1S_Pos)
+#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & ((value) << CAN_RXF1C_F1S_Pos))
+#define CAN_RXF1C_F1WM_Pos 24 /**< \brief (CAN_RXF1C) Rx FIFO 1 Watermark */
+#define CAN_RXF1C_F1WM_Msk (_U_(0x7F) << CAN_RXF1C_F1WM_Pos)
+#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & ((value) << CAN_RXF1C_F1WM_Pos))
+#define CAN_RXF1C_F1OM_Pos 31 /**< \brief (CAN_RXF1C) FIFO 1 Operation Mode */
+#define CAN_RXF1C_F1OM (_U_(0x1) << CAN_RXF1C_F1OM_Pos)
+#define CAN_RXF1C_MASK _U_(0xFF7FFFFF) /**< \brief (CAN_RXF1C) MASK Register */
+
+/* -------- CAN_RXF1S : (CAN Offset: 0xB4) (R/ 32) Rx FIFO 1 Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t F1FL:7; /*!< bit: 0.. 6 Rx FIFO 1 Fill Level */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t F1GI:6; /*!< bit: 8..13 Rx FIFO 1 Get Index */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t F1PI:6; /*!< bit: 16..21 Rx FIFO 1 Put Index */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t F1F:1; /*!< bit: 24 Rx FIFO 1 Full */
+ uint32_t RF1L:1; /*!< bit: 25 Rx FIFO 1 Message Lost */
+ uint32_t :4; /*!< bit: 26..29 Reserved */
+ uint32_t DMS:2; /*!< bit: 30..31 Debug Message Status */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF1S_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF1S_OFFSET 0xB4 /**< \brief (CAN_RXF1S offset) Rx FIFO 1 Status */
+#define CAN_RXF1S_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1S reset_value) Rx FIFO 1 Status */
+
+#define CAN_RXF1S_F1FL_Pos 0 /**< \brief (CAN_RXF1S) Rx FIFO 1 Fill Level */
+#define CAN_RXF1S_F1FL_Msk (_U_(0x7F) << CAN_RXF1S_F1FL_Pos)
+#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & ((value) << CAN_RXF1S_F1FL_Pos))
+#define CAN_RXF1S_F1GI_Pos 8 /**< \brief (CAN_RXF1S) Rx FIFO 1 Get Index */
+#define CAN_RXF1S_F1GI_Msk (_U_(0x3F) << CAN_RXF1S_F1GI_Pos)
+#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & ((value) << CAN_RXF1S_F1GI_Pos))
+#define CAN_RXF1S_F1PI_Pos 16 /**< \brief (CAN_RXF1S) Rx FIFO 1 Put Index */
+#define CAN_RXF1S_F1PI_Msk (_U_(0x3F) << CAN_RXF1S_F1PI_Pos)
+#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & ((value) << CAN_RXF1S_F1PI_Pos))
+#define CAN_RXF1S_F1F_Pos 24 /**< \brief (CAN_RXF1S) Rx FIFO 1 Full */
+#define CAN_RXF1S_F1F (_U_(0x1) << CAN_RXF1S_F1F_Pos)
+#define CAN_RXF1S_RF1L_Pos 25 /**< \brief (CAN_RXF1S) Rx FIFO 1 Message Lost */
+#define CAN_RXF1S_RF1L (_U_(0x1) << CAN_RXF1S_RF1L_Pos)
+#define CAN_RXF1S_DMS_Pos 30 /**< \brief (CAN_RXF1S) Debug Message Status */
+#define CAN_RXF1S_DMS_Msk (_U_(0x3) << CAN_RXF1S_DMS_Pos)
+#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & ((value) << CAN_RXF1S_DMS_Pos))
+#define CAN_RXF1S_DMS_IDLE_Val _U_(0x0) /**< \brief (CAN_RXF1S) Idle state */
+#define CAN_RXF1S_DMS_DBGA_Val _U_(0x1) /**< \brief (CAN_RXF1S) Debug message A received */
+#define CAN_RXF1S_DMS_DBGB_Val _U_(0x2) /**< \brief (CAN_RXF1S) Debug message A/B received */
+#define CAN_RXF1S_DMS_DBGC_Val _U_(0x3) /**< \brief (CAN_RXF1S) Debug message A/B/C received, DMA request set */
+#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos)
+#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos)
+#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos)
+#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos)
+#define CAN_RXF1S_MASK _U_(0xC33F3F7F) /**< \brief (CAN_RXF1S) MASK Register */
+
+/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t F1AI:6; /*!< bit: 0.. 5 Rx FIFO 1 Acknowledge Index */
+ uint32_t :26; /*!< bit: 6..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF1A_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF1A_OFFSET 0xB8 /**< \brief (CAN_RXF1A offset) Rx FIFO 1 Acknowledge */
+#define CAN_RXF1A_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1A reset_value) Rx FIFO 1 Acknowledge */
+
+#define CAN_RXF1A_F1AI_Pos 0 /**< \brief (CAN_RXF1A) Rx FIFO 1 Acknowledge Index */
+#define CAN_RXF1A_F1AI_Msk (_U_(0x3F) << CAN_RXF1A_F1AI_Pos)
+#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & ((value) << CAN_RXF1A_F1AI_Pos))
+#define CAN_RXF1A_MASK _U_(0x0000003F) /**< \brief (CAN_RXF1A) MASK Register */
+
+/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t F0DS:3; /*!< bit: 0.. 2 Rx FIFO 0 Data Field Size */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t F1DS:3; /*!< bit: 4.. 6 Rx FIFO 1 Data Field Size */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t RBDS:3; /*!< bit: 8..10 Rx Buffer Data Field Size */
+ uint32_t :21; /*!< bit: 11..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXESC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXESC_OFFSET 0xBC /**< \brief (CAN_RXESC offset) Rx Buffer / FIFO Element Size Configuration */
+#define CAN_RXESC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXESC reset_value) Rx Buffer / FIFO Element Size Configuration */
+
+#define CAN_RXESC_F0DS_Pos 0 /**< \brief (CAN_RXESC) Rx FIFO 0 Data Field Size */
+#define CAN_RXESC_F0DS_Msk (_U_(0x7) << CAN_RXESC_F0DS_Pos)
+#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & ((value) << CAN_RXESC_F0DS_Pos))
+#define CAN_RXESC_F0DS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */
+#define CAN_RXESC_F0DS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */
+#define CAN_RXESC_F0DS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */
+#define CAN_RXESC_F0DS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */
+#define CAN_RXESC_F0DS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */
+#define CAN_RXESC_F0DS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */
+#define CAN_RXESC_F0DS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */
+#define CAN_RXESC_F0DS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */
+#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos)
+#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos)
+#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos)
+#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos)
+#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos)
+#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos)
+#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos)
+#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos)
+#define CAN_RXESC_F1DS_Pos 4 /**< \brief (CAN_RXESC) Rx FIFO 1 Data Field Size */
+#define CAN_RXESC_F1DS_Msk (_U_(0x7) << CAN_RXESC_F1DS_Pos)
+#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & ((value) << CAN_RXESC_F1DS_Pos))
+#define CAN_RXESC_F1DS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */
+#define CAN_RXESC_F1DS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */
+#define CAN_RXESC_F1DS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */
+#define CAN_RXESC_F1DS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */
+#define CAN_RXESC_F1DS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */
+#define CAN_RXESC_F1DS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */
+#define CAN_RXESC_F1DS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */
+#define CAN_RXESC_F1DS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */
+#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos)
+#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos)
+#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos)
+#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos)
+#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos)
+#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos)
+#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos)
+#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos)
+#define CAN_RXESC_RBDS_Pos 8 /**< \brief (CAN_RXESC) Rx Buffer Data Field Size */
+#define CAN_RXESC_RBDS_Msk (_U_(0x7) << CAN_RXESC_RBDS_Pos)
+#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & ((value) << CAN_RXESC_RBDS_Pos))
+#define CAN_RXESC_RBDS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */
+#define CAN_RXESC_RBDS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */
+#define CAN_RXESC_RBDS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */
+#define CAN_RXESC_RBDS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */
+#define CAN_RXESC_RBDS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */
+#define CAN_RXESC_RBDS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */
+#define CAN_RXESC_RBDS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */
+#define CAN_RXESC_RBDS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */
+#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos)
+#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos)
+#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos)
+#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos)
+#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos)
+#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos)
+#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos)
+#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos)
+#define CAN_RXESC_MASK _U_(0x00000777) /**< \brief (CAN_RXESC) MASK Register */
+
+/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TBSA:16; /*!< bit: 0..15 Tx Buffers Start Address */
+ uint32_t NDTB:6; /*!< bit: 16..21 Number of Dedicated Transmit Buffers */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t TFQS:6; /*!< bit: 24..29 Transmit FIFO/Queue Size */
+ uint32_t TFQM:1; /*!< bit: 30 Tx FIFO/Queue Mode */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBC_OFFSET 0xC0 /**< \brief (CAN_TXBC offset) Tx Buffer Configuration */
+#define CAN_TXBC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBC reset_value) Tx Buffer Configuration */
+
+#define CAN_TXBC_TBSA_Pos 0 /**< \brief (CAN_TXBC) Tx Buffers Start Address */
+#define CAN_TXBC_TBSA_Msk (_U_(0xFFFF) << CAN_TXBC_TBSA_Pos)
+#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & ((value) << CAN_TXBC_TBSA_Pos))
+#define CAN_TXBC_NDTB_Pos 16 /**< \brief (CAN_TXBC) Number of Dedicated Transmit Buffers */
+#define CAN_TXBC_NDTB_Msk (_U_(0x3F) << CAN_TXBC_NDTB_Pos)
+#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & ((value) << CAN_TXBC_NDTB_Pos))
+#define CAN_TXBC_TFQS_Pos 24 /**< \brief (CAN_TXBC) Transmit FIFO/Queue Size */
+#define CAN_TXBC_TFQS_Msk (_U_(0x3F) << CAN_TXBC_TFQS_Pos)
+#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & ((value) << CAN_TXBC_TFQS_Pos))
+#define CAN_TXBC_TFQM_Pos 30 /**< \brief (CAN_TXBC) Tx FIFO/Queue Mode */
+#define CAN_TXBC_TFQM (_U_(0x1) << CAN_TXBC_TFQM_Pos)
+#define CAN_TXBC_MASK _U_(0x7F3FFFFF) /**< \brief (CAN_TXBC) MASK Register */
+
+/* -------- CAN_TXFQS : (CAN Offset: 0xC4) (R/ 32) Tx FIFO / Queue Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TFFL:6; /*!< bit: 0.. 5 Tx FIFO Free Level */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t TFGI:5; /*!< bit: 8..12 Tx FIFO Get Index */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t TFQPI:5; /*!< bit: 16..20 Tx FIFO/Queue Put Index */
+ uint32_t TFQF:1; /*!< bit: 21 Tx FIFO/Queue Full */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXFQS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXFQS_OFFSET 0xC4 /**< \brief (CAN_TXFQS offset) Tx FIFO / Queue Status */
+#define CAN_TXFQS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXFQS reset_value) Tx FIFO / Queue Status */
+
+#define CAN_TXFQS_TFFL_Pos 0 /**< \brief (CAN_TXFQS) Tx FIFO Free Level */
+#define CAN_TXFQS_TFFL_Msk (_U_(0x3F) << CAN_TXFQS_TFFL_Pos)
+#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & ((value) << CAN_TXFQS_TFFL_Pos))
+#define CAN_TXFQS_TFGI_Pos 8 /**< \brief (CAN_TXFQS) Tx FIFO Get Index */
+#define CAN_TXFQS_TFGI_Msk (_U_(0x1F) << CAN_TXFQS_TFGI_Pos)
+#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & ((value) << CAN_TXFQS_TFGI_Pos))
+#define CAN_TXFQS_TFQPI_Pos 16 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Put Index */
+#define CAN_TXFQS_TFQPI_Msk (_U_(0x1F) << CAN_TXFQS_TFQPI_Pos)
+#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & ((value) << CAN_TXFQS_TFQPI_Pos))
+#define CAN_TXFQS_TFQF_Pos 21 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Full */
+#define CAN_TXFQS_TFQF (_U_(0x1) << CAN_TXFQS_TFQF_Pos)
+#define CAN_TXFQS_MASK _U_(0x003F1F3F) /**< \brief (CAN_TXFQS) MASK Register */
+
+/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TBDS:3; /*!< bit: 0.. 2 Tx Buffer Data Field Size */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXESC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXESC_OFFSET 0xC8 /**< \brief (CAN_TXESC offset) Tx Buffer Element Size Configuration */
+#define CAN_TXESC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXESC reset_value) Tx Buffer Element Size Configuration */
+
+#define CAN_TXESC_TBDS_Pos 0 /**< \brief (CAN_TXESC) Tx Buffer Data Field Size */
+#define CAN_TXESC_TBDS_Msk (_U_(0x7) << CAN_TXESC_TBDS_Pos)
+#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & ((value) << CAN_TXESC_TBDS_Pos))
+#define CAN_TXESC_TBDS_DATA8_Val _U_(0x0) /**< \brief (CAN_TXESC) 8 byte data field */
+#define CAN_TXESC_TBDS_DATA12_Val _U_(0x1) /**< \brief (CAN_TXESC) 12 byte data field */
+#define CAN_TXESC_TBDS_DATA16_Val _U_(0x2) /**< \brief (CAN_TXESC) 16 byte data field */
+#define CAN_TXESC_TBDS_DATA20_Val _U_(0x3) /**< \brief (CAN_TXESC) 20 byte data field */
+#define CAN_TXESC_TBDS_DATA24_Val _U_(0x4) /**< \brief (CAN_TXESC) 24 byte data field */
+#define CAN_TXESC_TBDS_DATA32_Val _U_(0x5) /**< \brief (CAN_TXESC) 32 byte data field */
+#define CAN_TXESC_TBDS_DATA48_Val _U_(0x6) /**< \brief (CAN_TXESC) 48 byte data field */
+#define CAN_TXESC_TBDS_DATA64_Val _U_(0x7) /**< \brief (CAN_TXESC) 64 byte data field */
+#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos)
+#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos)
+#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos)
+#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos)
+#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos)
+#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos)
+#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos)
+#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos)
+#define CAN_TXESC_MASK _U_(0x00000007) /**< \brief (CAN_TXESC) MASK Register */
+
+/* -------- CAN_TXBRP : (CAN Offset: 0xCC) (R/ 32) Tx Buffer Request Pending -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TRP0:1; /*!< bit: 0 Transmission Request Pending 0 */
+ uint32_t TRP1:1; /*!< bit: 1 Transmission Request Pending 1 */
+ uint32_t TRP2:1; /*!< bit: 2 Transmission Request Pending 2 */
+ uint32_t TRP3:1; /*!< bit: 3 Transmission Request Pending 3 */
+ uint32_t TRP4:1; /*!< bit: 4 Transmission Request Pending 4 */
+ uint32_t TRP5:1; /*!< bit: 5 Transmission Request Pending 5 */
+ uint32_t TRP6:1; /*!< bit: 6 Transmission Request Pending 6 */
+ uint32_t TRP7:1; /*!< bit: 7 Transmission Request Pending 7 */
+ uint32_t TRP8:1; /*!< bit: 8 Transmission Request Pending 8 */
+ uint32_t TRP9:1; /*!< bit: 9 Transmission Request Pending 9 */
+ uint32_t TRP10:1; /*!< bit: 10 Transmission Request Pending 10 */
+ uint32_t TRP11:1; /*!< bit: 11 Transmission Request Pending 11 */
+ uint32_t TRP12:1; /*!< bit: 12 Transmission Request Pending 12 */
+ uint32_t TRP13:1; /*!< bit: 13 Transmission Request Pending 13 */
+ uint32_t TRP14:1; /*!< bit: 14 Transmission Request Pending 14 */
+ uint32_t TRP15:1; /*!< bit: 15 Transmission Request Pending 15 */
+ uint32_t TRP16:1; /*!< bit: 16 Transmission Request Pending 16 */
+ uint32_t TRP17:1; /*!< bit: 17 Transmission Request Pending 17 */
+ uint32_t TRP18:1; /*!< bit: 18 Transmission Request Pending 18 */
+ uint32_t TRP19:1; /*!< bit: 19 Transmission Request Pending 19 */
+ uint32_t TRP20:1; /*!< bit: 20 Transmission Request Pending 20 */
+ uint32_t TRP21:1; /*!< bit: 21 Transmission Request Pending 21 */
+ uint32_t TRP22:1; /*!< bit: 22 Transmission Request Pending 22 */
+ uint32_t TRP23:1; /*!< bit: 23 Transmission Request Pending 23 */
+ uint32_t TRP24:1; /*!< bit: 24 Transmission Request Pending 24 */
+ uint32_t TRP25:1; /*!< bit: 25 Transmission Request Pending 25 */
+ uint32_t TRP26:1; /*!< bit: 26 Transmission Request Pending 26 */
+ uint32_t TRP27:1; /*!< bit: 27 Transmission Request Pending 27 */
+ uint32_t TRP28:1; /*!< bit: 28 Transmission Request Pending 28 */
+ uint32_t TRP29:1; /*!< bit: 29 Transmission Request Pending 29 */
+ uint32_t TRP30:1; /*!< bit: 30 Transmission Request Pending 30 */
+ uint32_t TRP31:1; /*!< bit: 31 Transmission Request Pending 31 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBRP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBRP_OFFSET 0xCC /**< \brief (CAN_TXBRP offset) Tx Buffer Request Pending */
+#define CAN_TXBRP_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBRP reset_value) Tx Buffer Request Pending */
+
+#define CAN_TXBRP_TRP0_Pos 0 /**< \brief (CAN_TXBRP) Transmission Request Pending 0 */
+#define CAN_TXBRP_TRP0 (_U_(0x1) << CAN_TXBRP_TRP0_Pos)
+#define CAN_TXBRP_TRP1_Pos 1 /**< \brief (CAN_TXBRP) Transmission Request Pending 1 */
+#define CAN_TXBRP_TRP1 (_U_(0x1) << CAN_TXBRP_TRP1_Pos)
+#define CAN_TXBRP_TRP2_Pos 2 /**< \brief (CAN_TXBRP) Transmission Request Pending 2 */
+#define CAN_TXBRP_TRP2 (_U_(0x1) << CAN_TXBRP_TRP2_Pos)
+#define CAN_TXBRP_TRP3_Pos 3 /**< \brief (CAN_TXBRP) Transmission Request Pending 3 */
+#define CAN_TXBRP_TRP3 (_U_(0x1) << CAN_TXBRP_TRP3_Pos)
+#define CAN_TXBRP_TRP4_Pos 4 /**< \brief (CAN_TXBRP) Transmission Request Pending 4 */
+#define CAN_TXBRP_TRP4 (_U_(0x1) << CAN_TXBRP_TRP4_Pos)
+#define CAN_TXBRP_TRP5_Pos 5 /**< \brief (CAN_TXBRP) Transmission Request Pending 5 */
+#define CAN_TXBRP_TRP5 (_U_(0x1) << CAN_TXBRP_TRP5_Pos)
+#define CAN_TXBRP_TRP6_Pos 6 /**< \brief (CAN_TXBRP) Transmission Request Pending 6 */
+#define CAN_TXBRP_TRP6 (_U_(0x1) << CAN_TXBRP_TRP6_Pos)
+#define CAN_TXBRP_TRP7_Pos 7 /**< \brief (CAN_TXBRP) Transmission Request Pending 7 */
+#define CAN_TXBRP_TRP7 (_U_(0x1) << CAN_TXBRP_TRP7_Pos)
+#define CAN_TXBRP_TRP8_Pos 8 /**< \brief (CAN_TXBRP) Transmission Request Pending 8 */
+#define CAN_TXBRP_TRP8 (_U_(0x1) << CAN_TXBRP_TRP8_Pos)
+#define CAN_TXBRP_TRP9_Pos 9 /**< \brief (CAN_TXBRP) Transmission Request Pending 9 */
+#define CAN_TXBRP_TRP9 (_U_(0x1) << CAN_TXBRP_TRP9_Pos)
+#define CAN_TXBRP_TRP10_Pos 10 /**< \brief (CAN_TXBRP) Transmission Request Pending 10 */
+#define CAN_TXBRP_TRP10 (_U_(0x1) << CAN_TXBRP_TRP10_Pos)
+#define CAN_TXBRP_TRP11_Pos 11 /**< \brief (CAN_TXBRP) Transmission Request Pending 11 */
+#define CAN_TXBRP_TRP11 (_U_(0x1) << CAN_TXBRP_TRP11_Pos)
+#define CAN_TXBRP_TRP12_Pos 12 /**< \brief (CAN_TXBRP) Transmission Request Pending 12 */
+#define CAN_TXBRP_TRP12 (_U_(0x1) << CAN_TXBRP_TRP12_Pos)
+#define CAN_TXBRP_TRP13_Pos 13 /**< \brief (CAN_TXBRP) Transmission Request Pending 13 */
+#define CAN_TXBRP_TRP13 (_U_(0x1) << CAN_TXBRP_TRP13_Pos)
+#define CAN_TXBRP_TRP14_Pos 14 /**< \brief (CAN_TXBRP) Transmission Request Pending 14 */
+#define CAN_TXBRP_TRP14 (_U_(0x1) << CAN_TXBRP_TRP14_Pos)
+#define CAN_TXBRP_TRP15_Pos 15 /**< \brief (CAN_TXBRP) Transmission Request Pending 15 */
+#define CAN_TXBRP_TRP15 (_U_(0x1) << CAN_TXBRP_TRP15_Pos)
+#define CAN_TXBRP_TRP16_Pos 16 /**< \brief (CAN_TXBRP) Transmission Request Pending 16 */
+#define CAN_TXBRP_TRP16 (_U_(0x1) << CAN_TXBRP_TRP16_Pos)
+#define CAN_TXBRP_TRP17_Pos 17 /**< \brief (CAN_TXBRP) Transmission Request Pending 17 */
+#define CAN_TXBRP_TRP17 (_U_(0x1) << CAN_TXBRP_TRP17_Pos)
+#define CAN_TXBRP_TRP18_Pos 18 /**< \brief (CAN_TXBRP) Transmission Request Pending 18 */
+#define CAN_TXBRP_TRP18 (_U_(0x1) << CAN_TXBRP_TRP18_Pos)
+#define CAN_TXBRP_TRP19_Pos 19 /**< \brief (CAN_TXBRP) Transmission Request Pending 19 */
+#define CAN_TXBRP_TRP19 (_U_(0x1) << CAN_TXBRP_TRP19_Pos)
+#define CAN_TXBRP_TRP20_Pos 20 /**< \brief (CAN_TXBRP) Transmission Request Pending 20 */
+#define CAN_TXBRP_TRP20 (_U_(0x1) << CAN_TXBRP_TRP20_Pos)
+#define CAN_TXBRP_TRP21_Pos 21 /**< \brief (CAN_TXBRP) Transmission Request Pending 21 */
+#define CAN_TXBRP_TRP21 (_U_(0x1) << CAN_TXBRP_TRP21_Pos)
+#define CAN_TXBRP_TRP22_Pos 22 /**< \brief (CAN_TXBRP) Transmission Request Pending 22 */
+#define CAN_TXBRP_TRP22 (_U_(0x1) << CAN_TXBRP_TRP22_Pos)
+#define CAN_TXBRP_TRP23_Pos 23 /**< \brief (CAN_TXBRP) Transmission Request Pending 23 */
+#define CAN_TXBRP_TRP23 (_U_(0x1) << CAN_TXBRP_TRP23_Pos)
+#define CAN_TXBRP_TRP24_Pos 24 /**< \brief (CAN_TXBRP) Transmission Request Pending 24 */
+#define CAN_TXBRP_TRP24 (_U_(0x1) << CAN_TXBRP_TRP24_Pos)
+#define CAN_TXBRP_TRP25_Pos 25 /**< \brief (CAN_TXBRP) Transmission Request Pending 25 */
+#define CAN_TXBRP_TRP25 (_U_(0x1) << CAN_TXBRP_TRP25_Pos)
+#define CAN_TXBRP_TRP26_Pos 26 /**< \brief (CAN_TXBRP) Transmission Request Pending 26 */
+#define CAN_TXBRP_TRP26 (_U_(0x1) << CAN_TXBRP_TRP26_Pos)
+#define CAN_TXBRP_TRP27_Pos 27 /**< \brief (CAN_TXBRP) Transmission Request Pending 27 */
+#define CAN_TXBRP_TRP27 (_U_(0x1) << CAN_TXBRP_TRP27_Pos)
+#define CAN_TXBRP_TRP28_Pos 28 /**< \brief (CAN_TXBRP) Transmission Request Pending 28 */
+#define CAN_TXBRP_TRP28 (_U_(0x1) << CAN_TXBRP_TRP28_Pos)
+#define CAN_TXBRP_TRP29_Pos 29 /**< \brief (CAN_TXBRP) Transmission Request Pending 29 */
+#define CAN_TXBRP_TRP29 (_U_(0x1) << CAN_TXBRP_TRP29_Pos)
+#define CAN_TXBRP_TRP30_Pos 30 /**< \brief (CAN_TXBRP) Transmission Request Pending 30 */
+#define CAN_TXBRP_TRP30 (_U_(0x1) << CAN_TXBRP_TRP30_Pos)
+#define CAN_TXBRP_TRP31_Pos 31 /**< \brief (CAN_TXBRP) Transmission Request Pending 31 */
+#define CAN_TXBRP_TRP31 (_U_(0x1) << CAN_TXBRP_TRP31_Pos)
+#define CAN_TXBRP_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBRP) MASK Register */
+
+/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t AR0:1; /*!< bit: 0 Add Request 0 */
+ uint32_t AR1:1; /*!< bit: 1 Add Request 1 */
+ uint32_t AR2:1; /*!< bit: 2 Add Request 2 */
+ uint32_t AR3:1; /*!< bit: 3 Add Request 3 */
+ uint32_t AR4:1; /*!< bit: 4 Add Request 4 */
+ uint32_t AR5:1; /*!< bit: 5 Add Request 5 */
+ uint32_t AR6:1; /*!< bit: 6 Add Request 6 */
+ uint32_t AR7:1; /*!< bit: 7 Add Request 7 */
+ uint32_t AR8:1; /*!< bit: 8 Add Request 8 */
+ uint32_t AR9:1; /*!< bit: 9 Add Request 9 */
+ uint32_t AR10:1; /*!< bit: 10 Add Request 10 */
+ uint32_t AR11:1; /*!< bit: 11 Add Request 11 */
+ uint32_t AR12:1; /*!< bit: 12 Add Request 12 */
+ uint32_t AR13:1; /*!< bit: 13 Add Request 13 */
+ uint32_t AR14:1; /*!< bit: 14 Add Request 14 */
+ uint32_t AR15:1; /*!< bit: 15 Add Request 15 */
+ uint32_t AR16:1; /*!< bit: 16 Add Request 16 */
+ uint32_t AR17:1; /*!< bit: 17 Add Request 17 */
+ uint32_t AR18:1; /*!< bit: 18 Add Request 18 */
+ uint32_t AR19:1; /*!< bit: 19 Add Request 19 */
+ uint32_t AR20:1; /*!< bit: 20 Add Request 20 */
+ uint32_t AR21:1; /*!< bit: 21 Add Request 21 */
+ uint32_t AR22:1; /*!< bit: 22 Add Request 22 */
+ uint32_t AR23:1; /*!< bit: 23 Add Request 23 */
+ uint32_t AR24:1; /*!< bit: 24 Add Request 24 */
+ uint32_t AR25:1; /*!< bit: 25 Add Request 25 */
+ uint32_t AR26:1; /*!< bit: 26 Add Request 26 */
+ uint32_t AR27:1; /*!< bit: 27 Add Request 27 */
+ uint32_t AR28:1; /*!< bit: 28 Add Request 28 */
+ uint32_t AR29:1; /*!< bit: 29 Add Request 29 */
+ uint32_t AR30:1; /*!< bit: 30 Add Request 30 */
+ uint32_t AR31:1; /*!< bit: 31 Add Request 31 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBAR_OFFSET 0xD0 /**< \brief (CAN_TXBAR offset) Tx Buffer Add Request */
+#define CAN_TXBAR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBAR reset_value) Tx Buffer Add Request */
+
+#define CAN_TXBAR_AR0_Pos 0 /**< \brief (CAN_TXBAR) Add Request 0 */
+#define CAN_TXBAR_AR0 (_U_(0x1) << CAN_TXBAR_AR0_Pos)
+#define CAN_TXBAR_AR1_Pos 1 /**< \brief (CAN_TXBAR) Add Request 1 */
+#define CAN_TXBAR_AR1 (_U_(0x1) << CAN_TXBAR_AR1_Pos)
+#define CAN_TXBAR_AR2_Pos 2 /**< \brief (CAN_TXBAR) Add Request 2 */
+#define CAN_TXBAR_AR2 (_U_(0x1) << CAN_TXBAR_AR2_Pos)
+#define CAN_TXBAR_AR3_Pos 3 /**< \brief (CAN_TXBAR) Add Request 3 */
+#define CAN_TXBAR_AR3 (_U_(0x1) << CAN_TXBAR_AR3_Pos)
+#define CAN_TXBAR_AR4_Pos 4 /**< \brief (CAN_TXBAR) Add Request 4 */
+#define CAN_TXBAR_AR4 (_U_(0x1) << CAN_TXBAR_AR4_Pos)
+#define CAN_TXBAR_AR5_Pos 5 /**< \brief (CAN_TXBAR) Add Request 5 */
+#define CAN_TXBAR_AR5 (_U_(0x1) << CAN_TXBAR_AR5_Pos)
+#define CAN_TXBAR_AR6_Pos 6 /**< \brief (CAN_TXBAR) Add Request 6 */
+#define CAN_TXBAR_AR6 (_U_(0x1) << CAN_TXBAR_AR6_Pos)
+#define CAN_TXBAR_AR7_Pos 7 /**< \brief (CAN_TXBAR) Add Request 7 */
+#define CAN_TXBAR_AR7 (_U_(0x1) << CAN_TXBAR_AR7_Pos)
+#define CAN_TXBAR_AR8_Pos 8 /**< \brief (CAN_TXBAR) Add Request 8 */
+#define CAN_TXBAR_AR8 (_U_(0x1) << CAN_TXBAR_AR8_Pos)
+#define CAN_TXBAR_AR9_Pos 9 /**< \brief (CAN_TXBAR) Add Request 9 */
+#define CAN_TXBAR_AR9 (_U_(0x1) << CAN_TXBAR_AR9_Pos)
+#define CAN_TXBAR_AR10_Pos 10 /**< \brief (CAN_TXBAR) Add Request 10 */
+#define CAN_TXBAR_AR10 (_U_(0x1) << CAN_TXBAR_AR10_Pos)
+#define CAN_TXBAR_AR11_Pos 11 /**< \brief (CAN_TXBAR) Add Request 11 */
+#define CAN_TXBAR_AR11 (_U_(0x1) << CAN_TXBAR_AR11_Pos)
+#define CAN_TXBAR_AR12_Pos 12 /**< \brief (CAN_TXBAR) Add Request 12 */
+#define CAN_TXBAR_AR12 (_U_(0x1) << CAN_TXBAR_AR12_Pos)
+#define CAN_TXBAR_AR13_Pos 13 /**< \brief (CAN_TXBAR) Add Request 13 */
+#define CAN_TXBAR_AR13 (_U_(0x1) << CAN_TXBAR_AR13_Pos)
+#define CAN_TXBAR_AR14_Pos 14 /**< \brief (CAN_TXBAR) Add Request 14 */
+#define CAN_TXBAR_AR14 (_U_(0x1) << CAN_TXBAR_AR14_Pos)
+#define CAN_TXBAR_AR15_Pos 15 /**< \brief (CAN_TXBAR) Add Request 15 */
+#define CAN_TXBAR_AR15 (_U_(0x1) << CAN_TXBAR_AR15_Pos)
+#define CAN_TXBAR_AR16_Pos 16 /**< \brief (CAN_TXBAR) Add Request 16 */
+#define CAN_TXBAR_AR16 (_U_(0x1) << CAN_TXBAR_AR16_Pos)
+#define CAN_TXBAR_AR17_Pos 17 /**< \brief (CAN_TXBAR) Add Request 17 */
+#define CAN_TXBAR_AR17 (_U_(0x1) << CAN_TXBAR_AR17_Pos)
+#define CAN_TXBAR_AR18_Pos 18 /**< \brief (CAN_TXBAR) Add Request 18 */
+#define CAN_TXBAR_AR18 (_U_(0x1) << CAN_TXBAR_AR18_Pos)
+#define CAN_TXBAR_AR19_Pos 19 /**< \brief (CAN_TXBAR) Add Request 19 */
+#define CAN_TXBAR_AR19 (_U_(0x1) << CAN_TXBAR_AR19_Pos)
+#define CAN_TXBAR_AR20_Pos 20 /**< \brief (CAN_TXBAR) Add Request 20 */
+#define CAN_TXBAR_AR20 (_U_(0x1) << CAN_TXBAR_AR20_Pos)
+#define CAN_TXBAR_AR21_Pos 21 /**< \brief (CAN_TXBAR) Add Request 21 */
+#define CAN_TXBAR_AR21 (_U_(0x1) << CAN_TXBAR_AR21_Pos)
+#define CAN_TXBAR_AR22_Pos 22 /**< \brief (CAN_TXBAR) Add Request 22 */
+#define CAN_TXBAR_AR22 (_U_(0x1) << CAN_TXBAR_AR22_Pos)
+#define CAN_TXBAR_AR23_Pos 23 /**< \brief (CAN_TXBAR) Add Request 23 */
+#define CAN_TXBAR_AR23 (_U_(0x1) << CAN_TXBAR_AR23_Pos)
+#define CAN_TXBAR_AR24_Pos 24 /**< \brief (CAN_TXBAR) Add Request 24 */
+#define CAN_TXBAR_AR24 (_U_(0x1) << CAN_TXBAR_AR24_Pos)
+#define CAN_TXBAR_AR25_Pos 25 /**< \brief (CAN_TXBAR) Add Request 25 */
+#define CAN_TXBAR_AR25 (_U_(0x1) << CAN_TXBAR_AR25_Pos)
+#define CAN_TXBAR_AR26_Pos 26 /**< \brief (CAN_TXBAR) Add Request 26 */
+#define CAN_TXBAR_AR26 (_U_(0x1) << CAN_TXBAR_AR26_Pos)
+#define CAN_TXBAR_AR27_Pos 27 /**< \brief (CAN_TXBAR) Add Request 27 */
+#define CAN_TXBAR_AR27 (_U_(0x1) << CAN_TXBAR_AR27_Pos)
+#define CAN_TXBAR_AR28_Pos 28 /**< \brief (CAN_TXBAR) Add Request 28 */
+#define CAN_TXBAR_AR28 (_U_(0x1) << CAN_TXBAR_AR28_Pos)
+#define CAN_TXBAR_AR29_Pos 29 /**< \brief (CAN_TXBAR) Add Request 29 */
+#define CAN_TXBAR_AR29 (_U_(0x1) << CAN_TXBAR_AR29_Pos)
+#define CAN_TXBAR_AR30_Pos 30 /**< \brief (CAN_TXBAR) Add Request 30 */
+#define CAN_TXBAR_AR30 (_U_(0x1) << CAN_TXBAR_AR30_Pos)
+#define CAN_TXBAR_AR31_Pos 31 /**< \brief (CAN_TXBAR) Add Request 31 */
+#define CAN_TXBAR_AR31 (_U_(0x1) << CAN_TXBAR_AR31_Pos)
+#define CAN_TXBAR_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBAR) MASK Register */
+
+/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CR0:1; /*!< bit: 0 Cancellation Request 0 */
+ uint32_t CR1:1; /*!< bit: 1 Cancellation Request 1 */
+ uint32_t CR2:1; /*!< bit: 2 Cancellation Request 2 */
+ uint32_t CR3:1; /*!< bit: 3 Cancellation Request 3 */
+ uint32_t CR4:1; /*!< bit: 4 Cancellation Request 4 */
+ uint32_t CR5:1; /*!< bit: 5 Cancellation Request 5 */
+ uint32_t CR6:1; /*!< bit: 6 Cancellation Request 6 */
+ uint32_t CR7:1; /*!< bit: 7 Cancellation Request 7 */
+ uint32_t CR8:1; /*!< bit: 8 Cancellation Request 8 */
+ uint32_t CR9:1; /*!< bit: 9 Cancellation Request 9 */
+ uint32_t CR10:1; /*!< bit: 10 Cancellation Request 10 */
+ uint32_t CR11:1; /*!< bit: 11 Cancellation Request 11 */
+ uint32_t CR12:1; /*!< bit: 12 Cancellation Request 12 */
+ uint32_t CR13:1; /*!< bit: 13 Cancellation Request 13 */
+ uint32_t CR14:1; /*!< bit: 14 Cancellation Request 14 */
+ uint32_t CR15:1; /*!< bit: 15 Cancellation Request 15 */
+ uint32_t CR16:1; /*!< bit: 16 Cancellation Request 16 */
+ uint32_t CR17:1; /*!< bit: 17 Cancellation Request 17 */
+ uint32_t CR18:1; /*!< bit: 18 Cancellation Request 18 */
+ uint32_t CR19:1; /*!< bit: 19 Cancellation Request 19 */
+ uint32_t CR20:1; /*!< bit: 20 Cancellation Request 20 */
+ uint32_t CR21:1; /*!< bit: 21 Cancellation Request 21 */
+ uint32_t CR22:1; /*!< bit: 22 Cancellation Request 22 */
+ uint32_t CR23:1; /*!< bit: 23 Cancellation Request 23 */
+ uint32_t CR24:1; /*!< bit: 24 Cancellation Request 24 */
+ uint32_t CR25:1; /*!< bit: 25 Cancellation Request 25 */
+ uint32_t CR26:1; /*!< bit: 26 Cancellation Request 26 */
+ uint32_t CR27:1; /*!< bit: 27 Cancellation Request 27 */
+ uint32_t CR28:1; /*!< bit: 28 Cancellation Request 28 */
+ uint32_t CR29:1; /*!< bit: 29 Cancellation Request 29 */
+ uint32_t CR30:1; /*!< bit: 30 Cancellation Request 30 */
+ uint32_t CR31:1; /*!< bit: 31 Cancellation Request 31 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBCR_OFFSET 0xD4 /**< \brief (CAN_TXBCR offset) Tx Buffer Cancellation Request */
+#define CAN_TXBCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCR reset_value) Tx Buffer Cancellation Request */
+
+#define CAN_TXBCR_CR0_Pos 0 /**< \brief (CAN_TXBCR) Cancellation Request 0 */
+#define CAN_TXBCR_CR0 (_U_(0x1) << CAN_TXBCR_CR0_Pos)
+#define CAN_TXBCR_CR1_Pos 1 /**< \brief (CAN_TXBCR) Cancellation Request 1 */
+#define CAN_TXBCR_CR1 (_U_(0x1) << CAN_TXBCR_CR1_Pos)
+#define CAN_TXBCR_CR2_Pos 2 /**< \brief (CAN_TXBCR) Cancellation Request 2 */
+#define CAN_TXBCR_CR2 (_U_(0x1) << CAN_TXBCR_CR2_Pos)
+#define CAN_TXBCR_CR3_Pos 3 /**< \brief (CAN_TXBCR) Cancellation Request 3 */
+#define CAN_TXBCR_CR3 (_U_(0x1) << CAN_TXBCR_CR3_Pos)
+#define CAN_TXBCR_CR4_Pos 4 /**< \brief (CAN_TXBCR) Cancellation Request 4 */
+#define CAN_TXBCR_CR4 (_U_(0x1) << CAN_TXBCR_CR4_Pos)
+#define CAN_TXBCR_CR5_Pos 5 /**< \brief (CAN_TXBCR) Cancellation Request 5 */
+#define CAN_TXBCR_CR5 (_U_(0x1) << CAN_TXBCR_CR5_Pos)
+#define CAN_TXBCR_CR6_Pos 6 /**< \brief (CAN_TXBCR) Cancellation Request 6 */
+#define CAN_TXBCR_CR6 (_U_(0x1) << CAN_TXBCR_CR6_Pos)
+#define CAN_TXBCR_CR7_Pos 7 /**< \brief (CAN_TXBCR) Cancellation Request 7 */
+#define CAN_TXBCR_CR7 (_U_(0x1) << CAN_TXBCR_CR7_Pos)
+#define CAN_TXBCR_CR8_Pos 8 /**< \brief (CAN_TXBCR) Cancellation Request 8 */
+#define CAN_TXBCR_CR8 (_U_(0x1) << CAN_TXBCR_CR8_Pos)
+#define CAN_TXBCR_CR9_Pos 9 /**< \brief (CAN_TXBCR) Cancellation Request 9 */
+#define CAN_TXBCR_CR9 (_U_(0x1) << CAN_TXBCR_CR9_Pos)
+#define CAN_TXBCR_CR10_Pos 10 /**< \brief (CAN_TXBCR) Cancellation Request 10 */
+#define CAN_TXBCR_CR10 (_U_(0x1) << CAN_TXBCR_CR10_Pos)
+#define CAN_TXBCR_CR11_Pos 11 /**< \brief (CAN_TXBCR) Cancellation Request 11 */
+#define CAN_TXBCR_CR11 (_U_(0x1) << CAN_TXBCR_CR11_Pos)
+#define CAN_TXBCR_CR12_Pos 12 /**< \brief (CAN_TXBCR) Cancellation Request 12 */
+#define CAN_TXBCR_CR12 (_U_(0x1) << CAN_TXBCR_CR12_Pos)
+#define CAN_TXBCR_CR13_Pos 13 /**< \brief (CAN_TXBCR) Cancellation Request 13 */
+#define CAN_TXBCR_CR13 (_U_(0x1) << CAN_TXBCR_CR13_Pos)
+#define CAN_TXBCR_CR14_Pos 14 /**< \brief (CAN_TXBCR) Cancellation Request 14 */
+#define CAN_TXBCR_CR14 (_U_(0x1) << CAN_TXBCR_CR14_Pos)
+#define CAN_TXBCR_CR15_Pos 15 /**< \brief (CAN_TXBCR) Cancellation Request 15 */
+#define CAN_TXBCR_CR15 (_U_(0x1) << CAN_TXBCR_CR15_Pos)
+#define CAN_TXBCR_CR16_Pos 16 /**< \brief (CAN_TXBCR) Cancellation Request 16 */
+#define CAN_TXBCR_CR16 (_U_(0x1) << CAN_TXBCR_CR16_Pos)
+#define CAN_TXBCR_CR17_Pos 17 /**< \brief (CAN_TXBCR) Cancellation Request 17 */
+#define CAN_TXBCR_CR17 (_U_(0x1) << CAN_TXBCR_CR17_Pos)
+#define CAN_TXBCR_CR18_Pos 18 /**< \brief (CAN_TXBCR) Cancellation Request 18 */
+#define CAN_TXBCR_CR18 (_U_(0x1) << CAN_TXBCR_CR18_Pos)
+#define CAN_TXBCR_CR19_Pos 19 /**< \brief (CAN_TXBCR) Cancellation Request 19 */
+#define CAN_TXBCR_CR19 (_U_(0x1) << CAN_TXBCR_CR19_Pos)
+#define CAN_TXBCR_CR20_Pos 20 /**< \brief (CAN_TXBCR) Cancellation Request 20 */
+#define CAN_TXBCR_CR20 (_U_(0x1) << CAN_TXBCR_CR20_Pos)
+#define CAN_TXBCR_CR21_Pos 21 /**< \brief (CAN_TXBCR) Cancellation Request 21 */
+#define CAN_TXBCR_CR21 (_U_(0x1) << CAN_TXBCR_CR21_Pos)
+#define CAN_TXBCR_CR22_Pos 22 /**< \brief (CAN_TXBCR) Cancellation Request 22 */
+#define CAN_TXBCR_CR22 (_U_(0x1) << CAN_TXBCR_CR22_Pos)
+#define CAN_TXBCR_CR23_Pos 23 /**< \brief (CAN_TXBCR) Cancellation Request 23 */
+#define CAN_TXBCR_CR23 (_U_(0x1) << CAN_TXBCR_CR23_Pos)
+#define CAN_TXBCR_CR24_Pos 24 /**< \brief (CAN_TXBCR) Cancellation Request 24 */
+#define CAN_TXBCR_CR24 (_U_(0x1) << CAN_TXBCR_CR24_Pos)
+#define CAN_TXBCR_CR25_Pos 25 /**< \brief (CAN_TXBCR) Cancellation Request 25 */
+#define CAN_TXBCR_CR25 (_U_(0x1) << CAN_TXBCR_CR25_Pos)
+#define CAN_TXBCR_CR26_Pos 26 /**< \brief (CAN_TXBCR) Cancellation Request 26 */
+#define CAN_TXBCR_CR26 (_U_(0x1) << CAN_TXBCR_CR26_Pos)
+#define CAN_TXBCR_CR27_Pos 27 /**< \brief (CAN_TXBCR) Cancellation Request 27 */
+#define CAN_TXBCR_CR27 (_U_(0x1) << CAN_TXBCR_CR27_Pos)
+#define CAN_TXBCR_CR28_Pos 28 /**< \brief (CAN_TXBCR) Cancellation Request 28 */
+#define CAN_TXBCR_CR28 (_U_(0x1) << CAN_TXBCR_CR28_Pos)
+#define CAN_TXBCR_CR29_Pos 29 /**< \brief (CAN_TXBCR) Cancellation Request 29 */
+#define CAN_TXBCR_CR29 (_U_(0x1) << CAN_TXBCR_CR29_Pos)
+#define CAN_TXBCR_CR30_Pos 30 /**< \brief (CAN_TXBCR) Cancellation Request 30 */
+#define CAN_TXBCR_CR30 (_U_(0x1) << CAN_TXBCR_CR30_Pos)
+#define CAN_TXBCR_CR31_Pos 31 /**< \brief (CAN_TXBCR) Cancellation Request 31 */
+#define CAN_TXBCR_CR31 (_U_(0x1) << CAN_TXBCR_CR31_Pos)
+#define CAN_TXBCR_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCR) MASK Register */
+
+/* -------- CAN_TXBTO : (CAN Offset: 0xD8) (R/ 32) Tx Buffer Transmission Occurred -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TO0:1; /*!< bit: 0 Transmission Occurred 0 */
+ uint32_t TO1:1; /*!< bit: 1 Transmission Occurred 1 */
+ uint32_t TO2:1; /*!< bit: 2 Transmission Occurred 2 */
+ uint32_t TO3:1; /*!< bit: 3 Transmission Occurred 3 */
+ uint32_t TO4:1; /*!< bit: 4 Transmission Occurred 4 */
+ uint32_t TO5:1; /*!< bit: 5 Transmission Occurred 5 */
+ uint32_t TO6:1; /*!< bit: 6 Transmission Occurred 6 */
+ uint32_t TO7:1; /*!< bit: 7 Transmission Occurred 7 */
+ uint32_t TO8:1; /*!< bit: 8 Transmission Occurred 8 */
+ uint32_t TO9:1; /*!< bit: 9 Transmission Occurred 9 */
+ uint32_t TO10:1; /*!< bit: 10 Transmission Occurred 10 */
+ uint32_t TO11:1; /*!< bit: 11 Transmission Occurred 11 */
+ uint32_t TO12:1; /*!< bit: 12 Transmission Occurred 12 */
+ uint32_t TO13:1; /*!< bit: 13 Transmission Occurred 13 */
+ uint32_t TO14:1; /*!< bit: 14 Transmission Occurred 14 */
+ uint32_t TO15:1; /*!< bit: 15 Transmission Occurred 15 */
+ uint32_t TO16:1; /*!< bit: 16 Transmission Occurred 16 */
+ uint32_t TO17:1; /*!< bit: 17 Transmission Occurred 17 */
+ uint32_t TO18:1; /*!< bit: 18 Transmission Occurred 18 */
+ uint32_t TO19:1; /*!< bit: 19 Transmission Occurred 19 */
+ uint32_t TO20:1; /*!< bit: 20 Transmission Occurred 20 */
+ uint32_t TO21:1; /*!< bit: 21 Transmission Occurred 21 */
+ uint32_t TO22:1; /*!< bit: 22 Transmission Occurred 22 */
+ uint32_t TO23:1; /*!< bit: 23 Transmission Occurred 23 */
+ uint32_t TO24:1; /*!< bit: 24 Transmission Occurred 24 */
+ uint32_t TO25:1; /*!< bit: 25 Transmission Occurred 25 */
+ uint32_t TO26:1; /*!< bit: 26 Transmission Occurred 26 */
+ uint32_t TO27:1; /*!< bit: 27 Transmission Occurred 27 */
+ uint32_t TO28:1; /*!< bit: 28 Transmission Occurred 28 */
+ uint32_t TO29:1; /*!< bit: 29 Transmission Occurred 29 */
+ uint32_t TO30:1; /*!< bit: 30 Transmission Occurred 30 */
+ uint32_t TO31:1; /*!< bit: 31 Transmission Occurred 31 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBTO_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBTO_OFFSET 0xD8 /**< \brief (CAN_TXBTO offset) Tx Buffer Transmission Occurred */
+#define CAN_TXBTO_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBTO reset_value) Tx Buffer Transmission Occurred */
+
+#define CAN_TXBTO_TO0_Pos 0 /**< \brief (CAN_TXBTO) Transmission Occurred 0 */
+#define CAN_TXBTO_TO0 (_U_(0x1) << CAN_TXBTO_TO0_Pos)
+#define CAN_TXBTO_TO1_Pos 1 /**< \brief (CAN_TXBTO) Transmission Occurred 1 */
+#define CAN_TXBTO_TO1 (_U_(0x1) << CAN_TXBTO_TO1_Pos)
+#define CAN_TXBTO_TO2_Pos 2 /**< \brief (CAN_TXBTO) Transmission Occurred 2 */
+#define CAN_TXBTO_TO2 (_U_(0x1) << CAN_TXBTO_TO2_Pos)
+#define CAN_TXBTO_TO3_Pos 3 /**< \brief (CAN_TXBTO) Transmission Occurred 3 */
+#define CAN_TXBTO_TO3 (_U_(0x1) << CAN_TXBTO_TO3_Pos)
+#define CAN_TXBTO_TO4_Pos 4 /**< \brief (CAN_TXBTO) Transmission Occurred 4 */
+#define CAN_TXBTO_TO4 (_U_(0x1) << CAN_TXBTO_TO4_Pos)
+#define CAN_TXBTO_TO5_Pos 5 /**< \brief (CAN_TXBTO) Transmission Occurred 5 */
+#define CAN_TXBTO_TO5 (_U_(0x1) << CAN_TXBTO_TO5_Pos)
+#define CAN_TXBTO_TO6_Pos 6 /**< \brief (CAN_TXBTO) Transmission Occurred 6 */
+#define CAN_TXBTO_TO6 (_U_(0x1) << CAN_TXBTO_TO6_Pos)
+#define CAN_TXBTO_TO7_Pos 7 /**< \brief (CAN_TXBTO) Transmission Occurred 7 */
+#define CAN_TXBTO_TO7 (_U_(0x1) << CAN_TXBTO_TO7_Pos)
+#define CAN_TXBTO_TO8_Pos 8 /**< \brief (CAN_TXBTO) Transmission Occurred 8 */
+#define CAN_TXBTO_TO8 (_U_(0x1) << CAN_TXBTO_TO8_Pos)
+#define CAN_TXBTO_TO9_Pos 9 /**< \brief (CAN_TXBTO) Transmission Occurred 9 */
+#define CAN_TXBTO_TO9 (_U_(0x1) << CAN_TXBTO_TO9_Pos)
+#define CAN_TXBTO_TO10_Pos 10 /**< \brief (CAN_TXBTO) Transmission Occurred 10 */
+#define CAN_TXBTO_TO10 (_U_(0x1) << CAN_TXBTO_TO10_Pos)
+#define CAN_TXBTO_TO11_Pos 11 /**< \brief (CAN_TXBTO) Transmission Occurred 11 */
+#define CAN_TXBTO_TO11 (_U_(0x1) << CAN_TXBTO_TO11_Pos)
+#define CAN_TXBTO_TO12_Pos 12 /**< \brief (CAN_TXBTO) Transmission Occurred 12 */
+#define CAN_TXBTO_TO12 (_U_(0x1) << CAN_TXBTO_TO12_Pos)
+#define CAN_TXBTO_TO13_Pos 13 /**< \brief (CAN_TXBTO) Transmission Occurred 13 */
+#define CAN_TXBTO_TO13 (_U_(0x1) << CAN_TXBTO_TO13_Pos)
+#define CAN_TXBTO_TO14_Pos 14 /**< \brief (CAN_TXBTO) Transmission Occurred 14 */
+#define CAN_TXBTO_TO14 (_U_(0x1) << CAN_TXBTO_TO14_Pos)
+#define CAN_TXBTO_TO15_Pos 15 /**< \brief (CAN_TXBTO) Transmission Occurred 15 */
+#define CAN_TXBTO_TO15 (_U_(0x1) << CAN_TXBTO_TO15_Pos)
+#define CAN_TXBTO_TO16_Pos 16 /**< \brief (CAN_TXBTO) Transmission Occurred 16 */
+#define CAN_TXBTO_TO16 (_U_(0x1) << CAN_TXBTO_TO16_Pos)
+#define CAN_TXBTO_TO17_Pos 17 /**< \brief (CAN_TXBTO) Transmission Occurred 17 */
+#define CAN_TXBTO_TO17 (_U_(0x1) << CAN_TXBTO_TO17_Pos)
+#define CAN_TXBTO_TO18_Pos 18 /**< \brief (CAN_TXBTO) Transmission Occurred 18 */
+#define CAN_TXBTO_TO18 (_U_(0x1) << CAN_TXBTO_TO18_Pos)
+#define CAN_TXBTO_TO19_Pos 19 /**< \brief (CAN_TXBTO) Transmission Occurred 19 */
+#define CAN_TXBTO_TO19 (_U_(0x1) << CAN_TXBTO_TO19_Pos)
+#define CAN_TXBTO_TO20_Pos 20 /**< \brief (CAN_TXBTO) Transmission Occurred 20 */
+#define CAN_TXBTO_TO20 (_U_(0x1) << CAN_TXBTO_TO20_Pos)
+#define CAN_TXBTO_TO21_Pos 21 /**< \brief (CAN_TXBTO) Transmission Occurred 21 */
+#define CAN_TXBTO_TO21 (_U_(0x1) << CAN_TXBTO_TO21_Pos)
+#define CAN_TXBTO_TO22_Pos 22 /**< \brief (CAN_TXBTO) Transmission Occurred 22 */
+#define CAN_TXBTO_TO22 (_U_(0x1) << CAN_TXBTO_TO22_Pos)
+#define CAN_TXBTO_TO23_Pos 23 /**< \brief (CAN_TXBTO) Transmission Occurred 23 */
+#define CAN_TXBTO_TO23 (_U_(0x1) << CAN_TXBTO_TO23_Pos)
+#define CAN_TXBTO_TO24_Pos 24 /**< \brief (CAN_TXBTO) Transmission Occurred 24 */
+#define CAN_TXBTO_TO24 (_U_(0x1) << CAN_TXBTO_TO24_Pos)
+#define CAN_TXBTO_TO25_Pos 25 /**< \brief (CAN_TXBTO) Transmission Occurred 25 */
+#define CAN_TXBTO_TO25 (_U_(0x1) << CAN_TXBTO_TO25_Pos)
+#define CAN_TXBTO_TO26_Pos 26 /**< \brief (CAN_TXBTO) Transmission Occurred 26 */
+#define CAN_TXBTO_TO26 (_U_(0x1) << CAN_TXBTO_TO26_Pos)
+#define CAN_TXBTO_TO27_Pos 27 /**< \brief (CAN_TXBTO) Transmission Occurred 27 */
+#define CAN_TXBTO_TO27 (_U_(0x1) << CAN_TXBTO_TO27_Pos)
+#define CAN_TXBTO_TO28_Pos 28 /**< \brief (CAN_TXBTO) Transmission Occurred 28 */
+#define CAN_TXBTO_TO28 (_U_(0x1) << CAN_TXBTO_TO28_Pos)
+#define CAN_TXBTO_TO29_Pos 29 /**< \brief (CAN_TXBTO) Transmission Occurred 29 */
+#define CAN_TXBTO_TO29 (_U_(0x1) << CAN_TXBTO_TO29_Pos)
+#define CAN_TXBTO_TO30_Pos 30 /**< \brief (CAN_TXBTO) Transmission Occurred 30 */
+#define CAN_TXBTO_TO30 (_U_(0x1) << CAN_TXBTO_TO30_Pos)
+#define CAN_TXBTO_TO31_Pos 31 /**< \brief (CAN_TXBTO) Transmission Occurred 31 */
+#define CAN_TXBTO_TO31 (_U_(0x1) << CAN_TXBTO_TO31_Pos)
+#define CAN_TXBTO_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBTO) MASK Register */
+
+/* -------- CAN_TXBCF : (CAN Offset: 0xDC) (R/ 32) Tx Buffer Cancellation Finished -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CF0:1; /*!< bit: 0 Tx Buffer Cancellation Finished 0 */
+ uint32_t CF1:1; /*!< bit: 1 Tx Buffer Cancellation Finished 1 */
+ uint32_t CF2:1; /*!< bit: 2 Tx Buffer Cancellation Finished 2 */
+ uint32_t CF3:1; /*!< bit: 3 Tx Buffer Cancellation Finished 3 */
+ uint32_t CF4:1; /*!< bit: 4 Tx Buffer Cancellation Finished 4 */
+ uint32_t CF5:1; /*!< bit: 5 Tx Buffer Cancellation Finished 5 */
+ uint32_t CF6:1; /*!< bit: 6 Tx Buffer Cancellation Finished 6 */
+ uint32_t CF7:1; /*!< bit: 7 Tx Buffer Cancellation Finished 7 */
+ uint32_t CF8:1; /*!< bit: 8 Tx Buffer Cancellation Finished 8 */
+ uint32_t CF9:1; /*!< bit: 9 Tx Buffer Cancellation Finished 9 */
+ uint32_t CF10:1; /*!< bit: 10 Tx Buffer Cancellation Finished 10 */
+ uint32_t CF11:1; /*!< bit: 11 Tx Buffer Cancellation Finished 11 */
+ uint32_t CF12:1; /*!< bit: 12 Tx Buffer Cancellation Finished 12 */
+ uint32_t CF13:1; /*!< bit: 13 Tx Buffer Cancellation Finished 13 */
+ uint32_t CF14:1; /*!< bit: 14 Tx Buffer Cancellation Finished 14 */
+ uint32_t CF15:1; /*!< bit: 15 Tx Buffer Cancellation Finished 15 */
+ uint32_t CF16:1; /*!< bit: 16 Tx Buffer Cancellation Finished 16 */
+ uint32_t CF17:1; /*!< bit: 17 Tx Buffer Cancellation Finished 17 */
+ uint32_t CF18:1; /*!< bit: 18 Tx Buffer Cancellation Finished 18 */
+ uint32_t CF19:1; /*!< bit: 19 Tx Buffer Cancellation Finished 19 */
+ uint32_t CF20:1; /*!< bit: 20 Tx Buffer Cancellation Finished 20 */
+ uint32_t CF21:1; /*!< bit: 21 Tx Buffer Cancellation Finished 21 */
+ uint32_t CF22:1; /*!< bit: 22 Tx Buffer Cancellation Finished 22 */
+ uint32_t CF23:1; /*!< bit: 23 Tx Buffer Cancellation Finished 23 */
+ uint32_t CF24:1; /*!< bit: 24 Tx Buffer Cancellation Finished 24 */
+ uint32_t CF25:1; /*!< bit: 25 Tx Buffer Cancellation Finished 25 */
+ uint32_t CF26:1; /*!< bit: 26 Tx Buffer Cancellation Finished 26 */
+ uint32_t CF27:1; /*!< bit: 27 Tx Buffer Cancellation Finished 27 */
+ uint32_t CF28:1; /*!< bit: 28 Tx Buffer Cancellation Finished 28 */
+ uint32_t CF29:1; /*!< bit: 29 Tx Buffer Cancellation Finished 29 */
+ uint32_t CF30:1; /*!< bit: 30 Tx Buffer Cancellation Finished 30 */
+ uint32_t CF31:1; /*!< bit: 31 Tx Buffer Cancellation Finished 31 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBCF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBCF_OFFSET 0xDC /**< \brief (CAN_TXBCF offset) Tx Buffer Cancellation Finished */
+#define CAN_TXBCF_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCF reset_value) Tx Buffer Cancellation Finished */
+
+#define CAN_TXBCF_CF0_Pos 0 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 0 */
+#define CAN_TXBCF_CF0 (_U_(0x1) << CAN_TXBCF_CF0_Pos)
+#define CAN_TXBCF_CF1_Pos 1 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 1 */
+#define CAN_TXBCF_CF1 (_U_(0x1) << CAN_TXBCF_CF1_Pos)
+#define CAN_TXBCF_CF2_Pos 2 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 2 */
+#define CAN_TXBCF_CF2 (_U_(0x1) << CAN_TXBCF_CF2_Pos)
+#define CAN_TXBCF_CF3_Pos 3 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 3 */
+#define CAN_TXBCF_CF3 (_U_(0x1) << CAN_TXBCF_CF3_Pos)
+#define CAN_TXBCF_CF4_Pos 4 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 4 */
+#define CAN_TXBCF_CF4 (_U_(0x1) << CAN_TXBCF_CF4_Pos)
+#define CAN_TXBCF_CF5_Pos 5 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 5 */
+#define CAN_TXBCF_CF5 (_U_(0x1) << CAN_TXBCF_CF5_Pos)
+#define CAN_TXBCF_CF6_Pos 6 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 6 */
+#define CAN_TXBCF_CF6 (_U_(0x1) << CAN_TXBCF_CF6_Pos)
+#define CAN_TXBCF_CF7_Pos 7 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 7 */
+#define CAN_TXBCF_CF7 (_U_(0x1) << CAN_TXBCF_CF7_Pos)
+#define CAN_TXBCF_CF8_Pos 8 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 8 */
+#define CAN_TXBCF_CF8 (_U_(0x1) << CAN_TXBCF_CF8_Pos)
+#define CAN_TXBCF_CF9_Pos 9 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 9 */
+#define CAN_TXBCF_CF9 (_U_(0x1) << CAN_TXBCF_CF9_Pos)
+#define CAN_TXBCF_CF10_Pos 10 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 10 */
+#define CAN_TXBCF_CF10 (_U_(0x1) << CAN_TXBCF_CF10_Pos)
+#define CAN_TXBCF_CF11_Pos 11 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 11 */
+#define CAN_TXBCF_CF11 (_U_(0x1) << CAN_TXBCF_CF11_Pos)
+#define CAN_TXBCF_CF12_Pos 12 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 12 */
+#define CAN_TXBCF_CF12 (_U_(0x1) << CAN_TXBCF_CF12_Pos)
+#define CAN_TXBCF_CF13_Pos 13 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 13 */
+#define CAN_TXBCF_CF13 (_U_(0x1) << CAN_TXBCF_CF13_Pos)
+#define CAN_TXBCF_CF14_Pos 14 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 14 */
+#define CAN_TXBCF_CF14 (_U_(0x1) << CAN_TXBCF_CF14_Pos)
+#define CAN_TXBCF_CF15_Pos 15 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 15 */
+#define CAN_TXBCF_CF15 (_U_(0x1) << CAN_TXBCF_CF15_Pos)
+#define CAN_TXBCF_CF16_Pos 16 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 16 */
+#define CAN_TXBCF_CF16 (_U_(0x1) << CAN_TXBCF_CF16_Pos)
+#define CAN_TXBCF_CF17_Pos 17 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 17 */
+#define CAN_TXBCF_CF17 (_U_(0x1) << CAN_TXBCF_CF17_Pos)
+#define CAN_TXBCF_CF18_Pos 18 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 18 */
+#define CAN_TXBCF_CF18 (_U_(0x1) << CAN_TXBCF_CF18_Pos)
+#define CAN_TXBCF_CF19_Pos 19 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 19 */
+#define CAN_TXBCF_CF19 (_U_(0x1) << CAN_TXBCF_CF19_Pos)
+#define CAN_TXBCF_CF20_Pos 20 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 20 */
+#define CAN_TXBCF_CF20 (_U_(0x1) << CAN_TXBCF_CF20_Pos)
+#define CAN_TXBCF_CF21_Pos 21 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 21 */
+#define CAN_TXBCF_CF21 (_U_(0x1) << CAN_TXBCF_CF21_Pos)
+#define CAN_TXBCF_CF22_Pos 22 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 22 */
+#define CAN_TXBCF_CF22 (_U_(0x1) << CAN_TXBCF_CF22_Pos)
+#define CAN_TXBCF_CF23_Pos 23 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 23 */
+#define CAN_TXBCF_CF23 (_U_(0x1) << CAN_TXBCF_CF23_Pos)
+#define CAN_TXBCF_CF24_Pos 24 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 24 */
+#define CAN_TXBCF_CF24 (_U_(0x1) << CAN_TXBCF_CF24_Pos)
+#define CAN_TXBCF_CF25_Pos 25 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 25 */
+#define CAN_TXBCF_CF25 (_U_(0x1) << CAN_TXBCF_CF25_Pos)
+#define CAN_TXBCF_CF26_Pos 26 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 26 */
+#define CAN_TXBCF_CF26 (_U_(0x1) << CAN_TXBCF_CF26_Pos)
+#define CAN_TXBCF_CF27_Pos 27 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 27 */
+#define CAN_TXBCF_CF27 (_U_(0x1) << CAN_TXBCF_CF27_Pos)
+#define CAN_TXBCF_CF28_Pos 28 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 28 */
+#define CAN_TXBCF_CF28 (_U_(0x1) << CAN_TXBCF_CF28_Pos)
+#define CAN_TXBCF_CF29_Pos 29 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 29 */
+#define CAN_TXBCF_CF29 (_U_(0x1) << CAN_TXBCF_CF29_Pos)
+#define CAN_TXBCF_CF30_Pos 30 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 30 */
+#define CAN_TXBCF_CF30 (_U_(0x1) << CAN_TXBCF_CF30_Pos)
+#define CAN_TXBCF_CF31_Pos 31 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 31 */
+#define CAN_TXBCF_CF31 (_U_(0x1) << CAN_TXBCF_CF31_Pos)
+#define CAN_TXBCF_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCF) MASK Register */
+
+/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TIE0:1; /*!< bit: 0 Transmission Interrupt Enable 0 */
+ uint32_t TIE1:1; /*!< bit: 1 Transmission Interrupt Enable 1 */
+ uint32_t TIE2:1; /*!< bit: 2 Transmission Interrupt Enable 2 */
+ uint32_t TIE3:1; /*!< bit: 3 Transmission Interrupt Enable 3 */
+ uint32_t TIE4:1; /*!< bit: 4 Transmission Interrupt Enable 4 */
+ uint32_t TIE5:1; /*!< bit: 5 Transmission Interrupt Enable 5 */
+ uint32_t TIE6:1; /*!< bit: 6 Transmission Interrupt Enable 6 */
+ uint32_t TIE7:1; /*!< bit: 7 Transmission Interrupt Enable 7 */
+ uint32_t TIE8:1; /*!< bit: 8 Transmission Interrupt Enable 8 */
+ uint32_t TIE9:1; /*!< bit: 9 Transmission Interrupt Enable 9 */
+ uint32_t TIE10:1; /*!< bit: 10 Transmission Interrupt Enable 10 */
+ uint32_t TIE11:1; /*!< bit: 11 Transmission Interrupt Enable 11 */
+ uint32_t TIE12:1; /*!< bit: 12 Transmission Interrupt Enable 12 */
+ uint32_t TIE13:1; /*!< bit: 13 Transmission Interrupt Enable 13 */
+ uint32_t TIE14:1; /*!< bit: 14 Transmission Interrupt Enable 14 */
+ uint32_t TIE15:1; /*!< bit: 15 Transmission Interrupt Enable 15 */
+ uint32_t TIE16:1; /*!< bit: 16 Transmission Interrupt Enable 16 */
+ uint32_t TIE17:1; /*!< bit: 17 Transmission Interrupt Enable 17 */
+ uint32_t TIE18:1; /*!< bit: 18 Transmission Interrupt Enable 18 */
+ uint32_t TIE19:1; /*!< bit: 19 Transmission Interrupt Enable 19 */
+ uint32_t TIE20:1; /*!< bit: 20 Transmission Interrupt Enable 20 */
+ uint32_t TIE21:1; /*!< bit: 21 Transmission Interrupt Enable 21 */
+ uint32_t TIE22:1; /*!< bit: 22 Transmission Interrupt Enable 22 */
+ uint32_t TIE23:1; /*!< bit: 23 Transmission Interrupt Enable 23 */
+ uint32_t TIE24:1; /*!< bit: 24 Transmission Interrupt Enable 24 */
+ uint32_t TIE25:1; /*!< bit: 25 Transmission Interrupt Enable 25 */
+ uint32_t TIE26:1; /*!< bit: 26 Transmission Interrupt Enable 26 */
+ uint32_t TIE27:1; /*!< bit: 27 Transmission Interrupt Enable 27 */
+ uint32_t TIE28:1; /*!< bit: 28 Transmission Interrupt Enable 28 */
+ uint32_t TIE29:1; /*!< bit: 29 Transmission Interrupt Enable 29 */
+ uint32_t TIE30:1; /*!< bit: 30 Transmission Interrupt Enable 30 */
+ uint32_t TIE31:1; /*!< bit: 31 Transmission Interrupt Enable 31 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBTIE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBTIE_OFFSET 0xE0 /**< \brief (CAN_TXBTIE offset) Tx Buffer Transmission Interrupt Enable */
+#define CAN_TXBTIE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBTIE reset_value) Tx Buffer Transmission Interrupt Enable */
+
+#define CAN_TXBTIE_TIE0_Pos 0 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 0 */
+#define CAN_TXBTIE_TIE0 (_U_(0x1) << CAN_TXBTIE_TIE0_Pos)
+#define CAN_TXBTIE_TIE1_Pos 1 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 1 */
+#define CAN_TXBTIE_TIE1 (_U_(0x1) << CAN_TXBTIE_TIE1_Pos)
+#define CAN_TXBTIE_TIE2_Pos 2 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 2 */
+#define CAN_TXBTIE_TIE2 (_U_(0x1) << CAN_TXBTIE_TIE2_Pos)
+#define CAN_TXBTIE_TIE3_Pos 3 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 3 */
+#define CAN_TXBTIE_TIE3 (_U_(0x1) << CAN_TXBTIE_TIE3_Pos)
+#define CAN_TXBTIE_TIE4_Pos 4 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 4 */
+#define CAN_TXBTIE_TIE4 (_U_(0x1) << CAN_TXBTIE_TIE4_Pos)
+#define CAN_TXBTIE_TIE5_Pos 5 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 5 */
+#define CAN_TXBTIE_TIE5 (_U_(0x1) << CAN_TXBTIE_TIE5_Pos)
+#define CAN_TXBTIE_TIE6_Pos 6 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 6 */
+#define CAN_TXBTIE_TIE6 (_U_(0x1) << CAN_TXBTIE_TIE6_Pos)
+#define CAN_TXBTIE_TIE7_Pos 7 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 7 */
+#define CAN_TXBTIE_TIE7 (_U_(0x1) << CAN_TXBTIE_TIE7_Pos)
+#define CAN_TXBTIE_TIE8_Pos 8 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 8 */
+#define CAN_TXBTIE_TIE8 (_U_(0x1) << CAN_TXBTIE_TIE8_Pos)
+#define CAN_TXBTIE_TIE9_Pos 9 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 9 */
+#define CAN_TXBTIE_TIE9 (_U_(0x1) << CAN_TXBTIE_TIE9_Pos)
+#define CAN_TXBTIE_TIE10_Pos 10 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 10 */
+#define CAN_TXBTIE_TIE10 (_U_(0x1) << CAN_TXBTIE_TIE10_Pos)
+#define CAN_TXBTIE_TIE11_Pos 11 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 11 */
+#define CAN_TXBTIE_TIE11 (_U_(0x1) << CAN_TXBTIE_TIE11_Pos)
+#define CAN_TXBTIE_TIE12_Pos 12 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 12 */
+#define CAN_TXBTIE_TIE12 (_U_(0x1) << CAN_TXBTIE_TIE12_Pos)
+#define CAN_TXBTIE_TIE13_Pos 13 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 13 */
+#define CAN_TXBTIE_TIE13 (_U_(0x1) << CAN_TXBTIE_TIE13_Pos)
+#define CAN_TXBTIE_TIE14_Pos 14 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 14 */
+#define CAN_TXBTIE_TIE14 (_U_(0x1) << CAN_TXBTIE_TIE14_Pos)
+#define CAN_TXBTIE_TIE15_Pos 15 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 15 */
+#define CAN_TXBTIE_TIE15 (_U_(0x1) << CAN_TXBTIE_TIE15_Pos)
+#define CAN_TXBTIE_TIE16_Pos 16 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 16 */
+#define CAN_TXBTIE_TIE16 (_U_(0x1) << CAN_TXBTIE_TIE16_Pos)
+#define CAN_TXBTIE_TIE17_Pos 17 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 17 */
+#define CAN_TXBTIE_TIE17 (_U_(0x1) << CAN_TXBTIE_TIE17_Pos)
+#define CAN_TXBTIE_TIE18_Pos 18 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 18 */
+#define CAN_TXBTIE_TIE18 (_U_(0x1) << CAN_TXBTIE_TIE18_Pos)
+#define CAN_TXBTIE_TIE19_Pos 19 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 19 */
+#define CAN_TXBTIE_TIE19 (_U_(0x1) << CAN_TXBTIE_TIE19_Pos)
+#define CAN_TXBTIE_TIE20_Pos 20 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 20 */
+#define CAN_TXBTIE_TIE20 (_U_(0x1) << CAN_TXBTIE_TIE20_Pos)
+#define CAN_TXBTIE_TIE21_Pos 21 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 21 */
+#define CAN_TXBTIE_TIE21 (_U_(0x1) << CAN_TXBTIE_TIE21_Pos)
+#define CAN_TXBTIE_TIE22_Pos 22 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 22 */
+#define CAN_TXBTIE_TIE22 (_U_(0x1) << CAN_TXBTIE_TIE22_Pos)
+#define CAN_TXBTIE_TIE23_Pos 23 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 23 */
+#define CAN_TXBTIE_TIE23 (_U_(0x1) << CAN_TXBTIE_TIE23_Pos)
+#define CAN_TXBTIE_TIE24_Pos 24 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 24 */
+#define CAN_TXBTIE_TIE24 (_U_(0x1) << CAN_TXBTIE_TIE24_Pos)
+#define CAN_TXBTIE_TIE25_Pos 25 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 25 */
+#define CAN_TXBTIE_TIE25 (_U_(0x1) << CAN_TXBTIE_TIE25_Pos)
+#define CAN_TXBTIE_TIE26_Pos 26 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 26 */
+#define CAN_TXBTIE_TIE26 (_U_(0x1) << CAN_TXBTIE_TIE26_Pos)
+#define CAN_TXBTIE_TIE27_Pos 27 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 27 */
+#define CAN_TXBTIE_TIE27 (_U_(0x1) << CAN_TXBTIE_TIE27_Pos)
+#define CAN_TXBTIE_TIE28_Pos 28 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 28 */
+#define CAN_TXBTIE_TIE28 (_U_(0x1) << CAN_TXBTIE_TIE28_Pos)
+#define CAN_TXBTIE_TIE29_Pos 29 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 29 */
+#define CAN_TXBTIE_TIE29 (_U_(0x1) << CAN_TXBTIE_TIE29_Pos)
+#define CAN_TXBTIE_TIE30_Pos 30 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 30 */
+#define CAN_TXBTIE_TIE30 (_U_(0x1) << CAN_TXBTIE_TIE30_Pos)
+#define CAN_TXBTIE_TIE31_Pos 31 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 31 */
+#define CAN_TXBTIE_TIE31 (_U_(0x1) << CAN_TXBTIE_TIE31_Pos)
+#define CAN_TXBTIE_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBTIE) MASK Register */
+
+/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CFIE0:1; /*!< bit: 0 Cancellation Finished Interrupt Enable 0 */
+ uint32_t CFIE1:1; /*!< bit: 1 Cancellation Finished Interrupt Enable 1 */
+ uint32_t CFIE2:1; /*!< bit: 2 Cancellation Finished Interrupt Enable 2 */
+ uint32_t CFIE3:1; /*!< bit: 3 Cancellation Finished Interrupt Enable 3 */
+ uint32_t CFIE4:1; /*!< bit: 4 Cancellation Finished Interrupt Enable 4 */
+ uint32_t CFIE5:1; /*!< bit: 5 Cancellation Finished Interrupt Enable 5 */
+ uint32_t CFIE6:1; /*!< bit: 6 Cancellation Finished Interrupt Enable 6 */
+ uint32_t CFIE7:1; /*!< bit: 7 Cancellation Finished Interrupt Enable 7 */
+ uint32_t CFIE8:1; /*!< bit: 8 Cancellation Finished Interrupt Enable 8 */
+ uint32_t CFIE9:1; /*!< bit: 9 Cancellation Finished Interrupt Enable 9 */
+ uint32_t CFIE10:1; /*!< bit: 10 Cancellation Finished Interrupt Enable 10 */
+ uint32_t CFIE11:1; /*!< bit: 11 Cancellation Finished Interrupt Enable 11 */
+ uint32_t CFIE12:1; /*!< bit: 12 Cancellation Finished Interrupt Enable 12 */
+ uint32_t CFIE13:1; /*!< bit: 13 Cancellation Finished Interrupt Enable 13 */
+ uint32_t CFIE14:1; /*!< bit: 14 Cancellation Finished Interrupt Enable 14 */
+ uint32_t CFIE15:1; /*!< bit: 15 Cancellation Finished Interrupt Enable 15 */
+ uint32_t CFIE16:1; /*!< bit: 16 Cancellation Finished Interrupt Enable 16 */
+ uint32_t CFIE17:1; /*!< bit: 17 Cancellation Finished Interrupt Enable 17 */
+ uint32_t CFIE18:1; /*!< bit: 18 Cancellation Finished Interrupt Enable 18 */
+ uint32_t CFIE19:1; /*!< bit: 19 Cancellation Finished Interrupt Enable 19 */
+ uint32_t CFIE20:1; /*!< bit: 20 Cancellation Finished Interrupt Enable 20 */
+ uint32_t CFIE21:1; /*!< bit: 21 Cancellation Finished Interrupt Enable 21 */
+ uint32_t CFIE22:1; /*!< bit: 22 Cancellation Finished Interrupt Enable 22 */
+ uint32_t CFIE23:1; /*!< bit: 23 Cancellation Finished Interrupt Enable 23 */
+ uint32_t CFIE24:1; /*!< bit: 24 Cancellation Finished Interrupt Enable 24 */
+ uint32_t CFIE25:1; /*!< bit: 25 Cancellation Finished Interrupt Enable 25 */
+ uint32_t CFIE26:1; /*!< bit: 26 Cancellation Finished Interrupt Enable 26 */
+ uint32_t CFIE27:1; /*!< bit: 27 Cancellation Finished Interrupt Enable 27 */
+ uint32_t CFIE28:1; /*!< bit: 28 Cancellation Finished Interrupt Enable 28 */
+ uint32_t CFIE29:1; /*!< bit: 29 Cancellation Finished Interrupt Enable 29 */
+ uint32_t CFIE30:1; /*!< bit: 30 Cancellation Finished Interrupt Enable 30 */
+ uint32_t CFIE31:1; /*!< bit: 31 Cancellation Finished Interrupt Enable 31 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBCIE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBCIE_OFFSET 0xE4 /**< \brief (CAN_TXBCIE offset) Tx Buffer Cancellation Finished Interrupt Enable */
+#define CAN_TXBCIE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCIE reset_value) Tx Buffer Cancellation Finished Interrupt Enable */
+
+#define CAN_TXBCIE_CFIE0_Pos 0 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 */
+#define CAN_TXBCIE_CFIE0 (_U_(0x1) << CAN_TXBCIE_CFIE0_Pos)
+#define CAN_TXBCIE_CFIE1_Pos 1 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 */
+#define CAN_TXBCIE_CFIE1 (_U_(0x1) << CAN_TXBCIE_CFIE1_Pos)
+#define CAN_TXBCIE_CFIE2_Pos 2 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 */
+#define CAN_TXBCIE_CFIE2 (_U_(0x1) << CAN_TXBCIE_CFIE2_Pos)
+#define CAN_TXBCIE_CFIE3_Pos 3 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 */
+#define CAN_TXBCIE_CFIE3 (_U_(0x1) << CAN_TXBCIE_CFIE3_Pos)
+#define CAN_TXBCIE_CFIE4_Pos 4 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 */
+#define CAN_TXBCIE_CFIE4 (_U_(0x1) << CAN_TXBCIE_CFIE4_Pos)
+#define CAN_TXBCIE_CFIE5_Pos 5 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 */
+#define CAN_TXBCIE_CFIE5 (_U_(0x1) << CAN_TXBCIE_CFIE5_Pos)
+#define CAN_TXBCIE_CFIE6_Pos 6 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 */
+#define CAN_TXBCIE_CFIE6 (_U_(0x1) << CAN_TXBCIE_CFIE6_Pos)
+#define CAN_TXBCIE_CFIE7_Pos 7 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 */
+#define CAN_TXBCIE_CFIE7 (_U_(0x1) << CAN_TXBCIE_CFIE7_Pos)
+#define CAN_TXBCIE_CFIE8_Pos 8 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 */
+#define CAN_TXBCIE_CFIE8 (_U_(0x1) << CAN_TXBCIE_CFIE8_Pos)
+#define CAN_TXBCIE_CFIE9_Pos 9 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 */
+#define CAN_TXBCIE_CFIE9 (_U_(0x1) << CAN_TXBCIE_CFIE9_Pos)
+#define CAN_TXBCIE_CFIE10_Pos 10 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 */
+#define CAN_TXBCIE_CFIE10 (_U_(0x1) << CAN_TXBCIE_CFIE10_Pos)
+#define CAN_TXBCIE_CFIE11_Pos 11 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 */
+#define CAN_TXBCIE_CFIE11 (_U_(0x1) << CAN_TXBCIE_CFIE11_Pos)
+#define CAN_TXBCIE_CFIE12_Pos 12 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 */
+#define CAN_TXBCIE_CFIE12 (_U_(0x1) << CAN_TXBCIE_CFIE12_Pos)
+#define CAN_TXBCIE_CFIE13_Pos 13 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 */
+#define CAN_TXBCIE_CFIE13 (_U_(0x1) << CAN_TXBCIE_CFIE13_Pos)
+#define CAN_TXBCIE_CFIE14_Pos 14 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 */
+#define CAN_TXBCIE_CFIE14 (_U_(0x1) << CAN_TXBCIE_CFIE14_Pos)
+#define CAN_TXBCIE_CFIE15_Pos 15 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 */
+#define CAN_TXBCIE_CFIE15 (_U_(0x1) << CAN_TXBCIE_CFIE15_Pos)
+#define CAN_TXBCIE_CFIE16_Pos 16 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 */
+#define CAN_TXBCIE_CFIE16 (_U_(0x1) << CAN_TXBCIE_CFIE16_Pos)
+#define CAN_TXBCIE_CFIE17_Pos 17 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 */
+#define CAN_TXBCIE_CFIE17 (_U_(0x1) << CAN_TXBCIE_CFIE17_Pos)
+#define CAN_TXBCIE_CFIE18_Pos 18 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 */
+#define CAN_TXBCIE_CFIE18 (_U_(0x1) << CAN_TXBCIE_CFIE18_Pos)
+#define CAN_TXBCIE_CFIE19_Pos 19 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 */
+#define CAN_TXBCIE_CFIE19 (_U_(0x1) << CAN_TXBCIE_CFIE19_Pos)
+#define CAN_TXBCIE_CFIE20_Pos 20 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 */
+#define CAN_TXBCIE_CFIE20 (_U_(0x1) << CAN_TXBCIE_CFIE20_Pos)
+#define CAN_TXBCIE_CFIE21_Pos 21 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 */
+#define CAN_TXBCIE_CFIE21 (_U_(0x1) << CAN_TXBCIE_CFIE21_Pos)
+#define CAN_TXBCIE_CFIE22_Pos 22 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 */
+#define CAN_TXBCIE_CFIE22 (_U_(0x1) << CAN_TXBCIE_CFIE22_Pos)
+#define CAN_TXBCIE_CFIE23_Pos 23 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 */
+#define CAN_TXBCIE_CFIE23 (_U_(0x1) << CAN_TXBCIE_CFIE23_Pos)
+#define CAN_TXBCIE_CFIE24_Pos 24 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 */
+#define CAN_TXBCIE_CFIE24 (_U_(0x1) << CAN_TXBCIE_CFIE24_Pos)
+#define CAN_TXBCIE_CFIE25_Pos 25 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 */
+#define CAN_TXBCIE_CFIE25 (_U_(0x1) << CAN_TXBCIE_CFIE25_Pos)
+#define CAN_TXBCIE_CFIE26_Pos 26 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 */
+#define CAN_TXBCIE_CFIE26 (_U_(0x1) << CAN_TXBCIE_CFIE26_Pos)
+#define CAN_TXBCIE_CFIE27_Pos 27 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 */
+#define CAN_TXBCIE_CFIE27 (_U_(0x1) << CAN_TXBCIE_CFIE27_Pos)
+#define CAN_TXBCIE_CFIE28_Pos 28 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 */
+#define CAN_TXBCIE_CFIE28 (_U_(0x1) << CAN_TXBCIE_CFIE28_Pos)
+#define CAN_TXBCIE_CFIE29_Pos 29 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 */
+#define CAN_TXBCIE_CFIE29 (_U_(0x1) << CAN_TXBCIE_CFIE29_Pos)
+#define CAN_TXBCIE_CFIE30_Pos 30 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 */
+#define CAN_TXBCIE_CFIE30 (_U_(0x1) << CAN_TXBCIE_CFIE30_Pos)
+#define CAN_TXBCIE_CFIE31_Pos 31 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 */
+#define CAN_TXBCIE_CFIE31 (_U_(0x1) << CAN_TXBCIE_CFIE31_Pos)
+#define CAN_TXBCIE_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCIE) MASK Register */
+
+/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EFSA:16; /*!< bit: 0..15 Event FIFO Start Address */
+ uint32_t EFS:6; /*!< bit: 16..21 Event FIFO Size */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t EFWM:6; /*!< bit: 24..29 Event FIFO Watermark */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXEFC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXEFC_OFFSET 0xF0 /**< \brief (CAN_TXEFC offset) Tx Event FIFO Configuration */
+#define CAN_TXEFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFC reset_value) Tx Event FIFO Configuration */
+
+#define CAN_TXEFC_EFSA_Pos 0 /**< \brief (CAN_TXEFC) Event FIFO Start Address */
+#define CAN_TXEFC_EFSA_Msk (_U_(0xFFFF) << CAN_TXEFC_EFSA_Pos)
+#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & ((value) << CAN_TXEFC_EFSA_Pos))
+#define CAN_TXEFC_EFS_Pos 16 /**< \brief (CAN_TXEFC) Event FIFO Size */
+#define CAN_TXEFC_EFS_Msk (_U_(0x3F) << CAN_TXEFC_EFS_Pos)
+#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & ((value) << CAN_TXEFC_EFS_Pos))
+#define CAN_TXEFC_EFWM_Pos 24 /**< \brief (CAN_TXEFC) Event FIFO Watermark */
+#define CAN_TXEFC_EFWM_Msk (_U_(0x3F) << CAN_TXEFC_EFWM_Pos)
+#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & ((value) << CAN_TXEFC_EFWM_Pos))
+#define CAN_TXEFC_MASK _U_(0x3F3FFFFF) /**< \brief (CAN_TXEFC) MASK Register */
+
+/* -------- CAN_TXEFS : (CAN Offset: 0xF4) (R/ 32) Tx Event FIFO Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EFFL:6; /*!< bit: 0.. 5 Event FIFO Fill Level */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t EFGI:5; /*!< bit: 8..12 Event FIFO Get Index */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t EFPI:5; /*!< bit: 16..20 Event FIFO Put Index */
+ uint32_t :3; /*!< bit: 21..23 Reserved */
+ uint32_t EFF:1; /*!< bit: 24 Event FIFO Full */
+ uint32_t TEFL:1; /*!< bit: 25 Tx Event FIFO Element Lost */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXEFS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXEFS_OFFSET 0xF4 /**< \brief (CAN_TXEFS offset) Tx Event FIFO Status */
+#define CAN_TXEFS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFS reset_value) Tx Event FIFO Status */
+
+#define CAN_TXEFS_EFFL_Pos 0 /**< \brief (CAN_TXEFS) Event FIFO Fill Level */
+#define CAN_TXEFS_EFFL_Msk (_U_(0x3F) << CAN_TXEFS_EFFL_Pos)
+#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & ((value) << CAN_TXEFS_EFFL_Pos))
+#define CAN_TXEFS_EFGI_Pos 8 /**< \brief (CAN_TXEFS) Event FIFO Get Index */
+#define CAN_TXEFS_EFGI_Msk (_U_(0x1F) << CAN_TXEFS_EFGI_Pos)
+#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & ((value) << CAN_TXEFS_EFGI_Pos))
+#define CAN_TXEFS_EFPI_Pos 16 /**< \brief (CAN_TXEFS) Event FIFO Put Index */
+#define CAN_TXEFS_EFPI_Msk (_U_(0x1F) << CAN_TXEFS_EFPI_Pos)
+#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & ((value) << CAN_TXEFS_EFPI_Pos))
+#define CAN_TXEFS_EFF_Pos 24 /**< \brief (CAN_TXEFS) Event FIFO Full */
+#define CAN_TXEFS_EFF (_U_(0x1) << CAN_TXEFS_EFF_Pos)
+#define CAN_TXEFS_TEFL_Pos 25 /**< \brief (CAN_TXEFS) Tx Event FIFO Element Lost */
+#define CAN_TXEFS_TEFL (_U_(0x1) << CAN_TXEFS_TEFL_Pos)
+#define CAN_TXEFS_MASK _U_(0x031F1F3F) /**< \brief (CAN_TXEFS) MASK Register */
+
+/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EFAI:5; /*!< bit: 0.. 4 Event FIFO Acknowledge Index */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXEFA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXEFA_OFFSET 0xF8 /**< \brief (CAN_TXEFA offset) Tx Event FIFO Acknowledge */
+#define CAN_TXEFA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFA reset_value) Tx Event FIFO Acknowledge */
+
+#define CAN_TXEFA_EFAI_Pos 0 /**< \brief (CAN_TXEFA) Event FIFO Acknowledge Index */
+#define CAN_TXEFA_EFAI_Msk (_U_(0x1F) << CAN_TXEFA_EFAI_Pos)
+#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & ((value) << CAN_TXEFA_EFAI_Pos))
+#define CAN_TXEFA_MASK _U_(0x0000001F) /**< \brief (CAN_TXEFA) MASK Register */
+
+/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ID:29; /*!< bit: 0..28 Identifier */
+ uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
+ uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
+ uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXBE_0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXBE_0_OFFSET 0x00 /**< \brief (CAN_RXBE_0 offset) Rx Buffer Element 0 */
+#define CAN_RXBE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_0 reset_value) Rx Buffer Element 0 */
+
+#define CAN_RXBE_0_ID_Pos 0 /**< \brief (CAN_RXBE_0) Identifier */
+#define CAN_RXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos)
+#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & ((value) << CAN_RXBE_0_ID_Pos))
+#define CAN_RXBE_0_RTR_Pos 29 /**< \brief (CAN_RXBE_0) Remote Transmission Request */
+#define CAN_RXBE_0_RTR (_U_(0x1) << CAN_RXBE_0_RTR_Pos)
+#define CAN_RXBE_0_XTD_Pos 30 /**< \brief (CAN_RXBE_0) Extended Identifier */
+#define CAN_RXBE_0_XTD (_U_(0x1) << CAN_RXBE_0_XTD_Pos)
+#define CAN_RXBE_0_ESI_Pos 31 /**< \brief (CAN_RXBE_0) Error State Indicator */
+#define CAN_RXBE_0_ESI (_U_(0x1) << CAN_RXBE_0_ESI_Pos)
+#define CAN_RXBE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXBE_0) MASK Register */
+
+/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */
+ uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
+ uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
+ uint32_t FDF:1; /*!< bit: 21 FD Format */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */
+ uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXBE_1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXBE_1_OFFSET 0x04 /**< \brief (CAN_RXBE_1 offset) Rx Buffer Element 1 */
+#define CAN_RXBE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_1 reset_value) Rx Buffer Element 1 */
+
+#define CAN_RXBE_1_RXTS_Pos 0 /**< \brief (CAN_RXBE_1) Rx Timestamp */
+#define CAN_RXBE_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXBE_1_RXTS_Pos)
+#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & ((value) << CAN_RXBE_1_RXTS_Pos))
+#define CAN_RXBE_1_DLC_Pos 16 /**< \brief (CAN_RXBE_1) Data Length Code */
+#define CAN_RXBE_1_DLC_Msk (_U_(0xF) << CAN_RXBE_1_DLC_Pos)
+#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & ((value) << CAN_RXBE_1_DLC_Pos))
+#define CAN_RXBE_1_BRS_Pos 20 /**< \brief (CAN_RXBE_1) Bit Rate Search */
+#define CAN_RXBE_1_BRS (_U_(0x1) << CAN_RXBE_1_BRS_Pos)
+#define CAN_RXBE_1_FDF_Pos 21 /**< \brief (CAN_RXBE_1) FD Format */
+#define CAN_RXBE_1_FDF (_U_(0x1) << CAN_RXBE_1_FDF_Pos)
+#define CAN_RXBE_1_FIDX_Pos 24 /**< \brief (CAN_RXBE_1) Filter Index */
+#define CAN_RXBE_1_FIDX_Msk (_U_(0x7F) << CAN_RXBE_1_FIDX_Pos)
+#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & ((value) << CAN_RXBE_1_FIDX_Pos))
+#define CAN_RXBE_1_ANMF_Pos 31 /**< \brief (CAN_RXBE_1) Accepted Non-matching Frame */
+#define CAN_RXBE_1_ANMF (_U_(0x1) << CAN_RXBE_1_ANMF_Pos)
+#define CAN_RXBE_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXBE_1) MASK Register */
+
+/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
+ uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
+ uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
+ uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXBE_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXBE_DATA_OFFSET 0x08 /**< \brief (CAN_RXBE_DATA offset) Rx Buffer Element Data */
+#define CAN_RXBE_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_DATA reset_value) Rx Buffer Element Data */
+
+#define CAN_RXBE_DATA_DB0_Pos 0 /**< \brief (CAN_RXBE_DATA) Data Byte 0 */
+#define CAN_RXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB0_Pos)
+#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & ((value) << CAN_RXBE_DATA_DB0_Pos))
+#define CAN_RXBE_DATA_DB1_Pos 8 /**< \brief (CAN_RXBE_DATA) Data Byte 1 */
+#define CAN_RXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB1_Pos)
+#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & ((value) << CAN_RXBE_DATA_DB1_Pos))
+#define CAN_RXBE_DATA_DB2_Pos 16 /**< \brief (CAN_RXBE_DATA) Data Byte 2 */
+#define CAN_RXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB2_Pos)
+#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & ((value) << CAN_RXBE_DATA_DB2_Pos))
+#define CAN_RXBE_DATA_DB3_Pos 24 /**< \brief (CAN_RXBE_DATA) Data Byte 3 */
+#define CAN_RXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB3_Pos)
+#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & ((value) << CAN_RXBE_DATA_DB3_Pos))
+#define CAN_RXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXBE_DATA) MASK Register */
+
+/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ID:29; /*!< bit: 0..28 Identifier */
+ uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
+ uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
+ uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF0E_0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF0E_0_OFFSET 0x00 /**< \brief (CAN_RXF0E_0 offset) Rx FIFO 0 Element 0 */
+#define CAN_RXF0E_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_0 reset_value) Rx FIFO 0 Element 0 */
+
+#define CAN_RXF0E_0_ID_Pos 0 /**< \brief (CAN_RXF0E_0) Identifier */
+#define CAN_RXF0E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos)
+#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & ((value) << CAN_RXF0E_0_ID_Pos))
+#define CAN_RXF0E_0_RTR_Pos 29 /**< \brief (CAN_RXF0E_0) Remote Transmission Request */
+#define CAN_RXF0E_0_RTR (_U_(0x1) << CAN_RXF0E_0_RTR_Pos)
+#define CAN_RXF0E_0_XTD_Pos 30 /**< \brief (CAN_RXF0E_0) Extended Identifier */
+#define CAN_RXF0E_0_XTD (_U_(0x1) << CAN_RXF0E_0_XTD_Pos)
+#define CAN_RXF0E_0_ESI_Pos 31 /**< \brief (CAN_RXF0E_0) Error State Indicator */
+#define CAN_RXF0E_0_ESI (_U_(0x1) << CAN_RXF0E_0_ESI_Pos)
+#define CAN_RXF0E_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF0E_0) MASK Register */
+
+/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */
+ uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
+ uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
+ uint32_t FDF:1; /*!< bit: 21 FD Format */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */
+ uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF0E_1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF0E_1_OFFSET 0x04 /**< \brief (CAN_RXF0E_1 offset) Rx FIFO 0 Element 1 */
+#define CAN_RXF0E_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_1 reset_value) Rx FIFO 0 Element 1 */
+
+#define CAN_RXF0E_1_RXTS_Pos 0 /**< \brief (CAN_RXF0E_1) Rx Timestamp */
+#define CAN_RXF0E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos)
+#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & ((value) << CAN_RXF0E_1_RXTS_Pos))
+#define CAN_RXF0E_1_DLC_Pos 16 /**< \brief (CAN_RXF0E_1) Data Length Code */
+#define CAN_RXF0E_1_DLC_Msk (_U_(0xF) << CAN_RXF0E_1_DLC_Pos)
+#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & ((value) << CAN_RXF0E_1_DLC_Pos))
+#define CAN_RXF0E_1_BRS_Pos 20 /**< \brief (CAN_RXF0E_1) Bit Rate Search */
+#define CAN_RXF0E_1_BRS (_U_(0x1) << CAN_RXF0E_1_BRS_Pos)
+#define CAN_RXF0E_1_FDF_Pos 21 /**< \brief (CAN_RXF0E_1) FD Format */
+#define CAN_RXF0E_1_FDF (_U_(0x1) << CAN_RXF0E_1_FDF_Pos)
+#define CAN_RXF0E_1_FIDX_Pos 24 /**< \brief (CAN_RXF0E_1) Filter Index */
+#define CAN_RXF0E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF0E_1_FIDX_Pos)
+#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & ((value) << CAN_RXF0E_1_FIDX_Pos))
+#define CAN_RXF0E_1_ANMF_Pos 31 /**< \brief (CAN_RXF0E_1) Accepted Non-matching Frame */
+#define CAN_RXF0E_1_ANMF (_U_(0x1) << CAN_RXF0E_1_ANMF_Pos)
+#define CAN_RXF0E_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXF0E_1) MASK Register */
+
+/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
+ uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
+ uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
+ uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF0E_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF0E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF0E_DATA offset) Rx FIFO 0 Element Data */
+#define CAN_RXF0E_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_DATA reset_value) Rx FIFO 0 Element Data */
+
+#define CAN_RXF0E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF0E_DATA) Data Byte 0 */
+#define CAN_RXF0E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB0_Pos)
+#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & ((value) << CAN_RXF0E_DATA_DB0_Pos))
+#define CAN_RXF0E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF0E_DATA) Data Byte 1 */
+#define CAN_RXF0E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB1_Pos)
+#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & ((value) << CAN_RXF0E_DATA_DB1_Pos))
+#define CAN_RXF0E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF0E_DATA) Data Byte 2 */
+#define CAN_RXF0E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB2_Pos)
+#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & ((value) << CAN_RXF0E_DATA_DB2_Pos))
+#define CAN_RXF0E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF0E_DATA) Data Byte 3 */
+#define CAN_RXF0E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB3_Pos)
+#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & ((value) << CAN_RXF0E_DATA_DB3_Pos))
+#define CAN_RXF0E_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF0E_DATA) MASK Register */
+
+/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ID:29; /*!< bit: 0..28 Identifier */
+ uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
+ uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
+ uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF1E_0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF1E_0_OFFSET 0x00 /**< \brief (CAN_RXF1E_0 offset) Rx FIFO 1 Element 0 */
+#define CAN_RXF1E_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_0 reset_value) Rx FIFO 1 Element 0 */
+
+#define CAN_RXF1E_0_ID_Pos 0 /**< \brief (CAN_RXF1E_0) Identifier */
+#define CAN_RXF1E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos)
+#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & ((value) << CAN_RXF1E_0_ID_Pos))
+#define CAN_RXF1E_0_RTR_Pos 29 /**< \brief (CAN_RXF1E_0) Remote Transmission Request */
+#define CAN_RXF1E_0_RTR (_U_(0x1) << CAN_RXF1E_0_RTR_Pos)
+#define CAN_RXF1E_0_XTD_Pos 30 /**< \brief (CAN_RXF1E_0) Extended Identifier */
+#define CAN_RXF1E_0_XTD (_U_(0x1) << CAN_RXF1E_0_XTD_Pos)
+#define CAN_RXF1E_0_ESI_Pos 31 /**< \brief (CAN_RXF1E_0) Error State Indicator */
+#define CAN_RXF1E_0_ESI (_U_(0x1) << CAN_RXF1E_0_ESI_Pos)
+#define CAN_RXF1E_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF1E_0) MASK Register */
+
+/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */
+ uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
+ uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
+ uint32_t FDF:1; /*!< bit: 21 FD Format */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */
+ uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF1E_1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF1E_1_OFFSET 0x04 /**< \brief (CAN_RXF1E_1 offset) Rx FIFO 1 Element 1 */
+#define CAN_RXF1E_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_1 reset_value) Rx FIFO 1 Element 1 */
+
+#define CAN_RXF1E_1_RXTS_Pos 0 /**< \brief (CAN_RXF1E_1) Rx Timestamp */
+#define CAN_RXF1E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos)
+#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & ((value) << CAN_RXF1E_1_RXTS_Pos))
+#define CAN_RXF1E_1_DLC_Pos 16 /**< \brief (CAN_RXF1E_1) Data Length Code */
+#define CAN_RXF1E_1_DLC_Msk (_U_(0xF) << CAN_RXF1E_1_DLC_Pos)
+#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & ((value) << CAN_RXF1E_1_DLC_Pos))
+#define CAN_RXF1E_1_BRS_Pos 20 /**< \brief (CAN_RXF1E_1) Bit Rate Search */
+#define CAN_RXF1E_1_BRS (_U_(0x1) << CAN_RXF1E_1_BRS_Pos)
+#define CAN_RXF1E_1_FDF_Pos 21 /**< \brief (CAN_RXF1E_1) FD Format */
+#define CAN_RXF1E_1_FDF (_U_(0x1) << CAN_RXF1E_1_FDF_Pos)
+#define CAN_RXF1E_1_FIDX_Pos 24 /**< \brief (CAN_RXF1E_1) Filter Index */
+#define CAN_RXF1E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF1E_1_FIDX_Pos)
+#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & ((value) << CAN_RXF1E_1_FIDX_Pos))
+#define CAN_RXF1E_1_ANMF_Pos 31 /**< \brief (CAN_RXF1E_1) Accepted Non-matching Frame */
+#define CAN_RXF1E_1_ANMF (_U_(0x1) << CAN_RXF1E_1_ANMF_Pos)
+#define CAN_RXF1E_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXF1E_1) MASK Register */
+
+/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
+ uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
+ uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
+ uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF1E_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF1E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF1E_DATA offset) Rx FIFO 1 Element Data */
+#define CAN_RXF1E_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_DATA reset_value) Rx FIFO 1 Element Data */
+
+#define CAN_RXF1E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF1E_DATA) Data Byte 0 */
+#define CAN_RXF1E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB0_Pos)
+#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & ((value) << CAN_RXF1E_DATA_DB0_Pos))
+#define CAN_RXF1E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF1E_DATA) Data Byte 1 */
+#define CAN_RXF1E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB1_Pos)
+#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & ((value) << CAN_RXF1E_DATA_DB1_Pos))
+#define CAN_RXF1E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF1E_DATA) Data Byte 2 */
+#define CAN_RXF1E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB2_Pos)
+#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & ((value) << CAN_RXF1E_DATA_DB2_Pos))
+#define CAN_RXF1E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF1E_DATA) Data Byte 3 */
+#define CAN_RXF1E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB3_Pos)
+#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & ((value) << CAN_RXF1E_DATA_DB3_Pos))
+#define CAN_RXF1E_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF1E_DATA) MASK Register */
+
+/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SFID2:11; /*!< bit: 0..10 Standard Filter ID 2 */
+ uint32_t :5; /*!< bit: 11..15 Reserved */
+ uint32_t SFID1:11; /*!< bit: 16..26 Standard Filter ID 1 */
+ uint32_t SFEC:3; /*!< bit: 27..29 Standard Filter Element Configuration */
+ uint32_t SFT:2; /*!< bit: 30..31 Standard Filter Type */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_SIDFE_0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_SIDFE_0_OFFSET 0x00 /**< \brief (CAN_SIDFE_0 offset) Standard Message ID Filter Element */
+#define CAN_SIDFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFE_0 reset_value) Standard Message ID Filter Element */
+
+#define CAN_SIDFE_0_SFID2_Pos 0 /**< \brief (CAN_SIDFE_0) Standard Filter ID 2 */
+#define CAN_SIDFE_0_SFID2_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID2_Pos)
+#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & ((value) << CAN_SIDFE_0_SFID2_Pos))
+#define CAN_SIDFE_0_SFID1_Pos 16 /**< \brief (CAN_SIDFE_0) Standard Filter ID 1 */
+#define CAN_SIDFE_0_SFID1_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID1_Pos)
+#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & ((value) << CAN_SIDFE_0_SFID1_Pos))
+#define CAN_SIDFE_0_SFEC_Pos 27 /**< \brief (CAN_SIDFE_0) Standard Filter Element Configuration */
+#define CAN_SIDFE_0_SFEC_Msk (_U_(0x7) << CAN_SIDFE_0_SFEC_Pos)
+#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & ((value) << CAN_SIDFE_0_SFEC_Pos))
+#define CAN_SIDFE_0_SFEC_DISABLE_Val _U_(0x0) /**< \brief (CAN_SIDFE_0) Disable filter element */
+#define CAN_SIDFE_0_SFEC_STF0M_Val _U_(0x1) /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */
+#define CAN_SIDFE_0_SFEC_STF1M_Val _U_(0x2) /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */
+#define CAN_SIDFE_0_SFEC_REJECT_Val _U_(0x3) /**< \brief (CAN_SIDFE_0) Reject ID if filter match */
+#define CAN_SIDFE_0_SFEC_PRIORITY_Val _U_(0x4) /**< \brief (CAN_SIDFE_0) Set priority if filter match */
+#define CAN_SIDFE_0_SFEC_PRIF0M_Val _U_(0x5) /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */
+#define CAN_SIDFE_0_SFEC_PRIF1M_Val _U_(0x6) /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */
+#define CAN_SIDFE_0_SFEC_STRXBUF_Val _U_(0x7) /**< \brief (CAN_SIDFE_0) Store into Rx Buffer */
+#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos)
+#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos)
+#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos)
+#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos)
+#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos)
+#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos)
+#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos)
+#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos)
+#define CAN_SIDFE_0_SFT_Pos 30 /**< \brief (CAN_SIDFE_0) Standard Filter Type */
+#define CAN_SIDFE_0_SFT_Msk (_U_(0x3) << CAN_SIDFE_0_SFT_Pos)
+#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & ((value) << CAN_SIDFE_0_SFT_Pos))
+#define CAN_SIDFE_0_SFT_RANGE_Val _U_(0x0) /**< \brief (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */
+#define CAN_SIDFE_0_SFT_DUAL_Val _U_(0x1) /**< \brief (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */
+#define CAN_SIDFE_0_SFT_CLASSIC_Val _U_(0x2) /**< \brief (CAN_SIDFE_0) Classic filter */
+#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos)
+#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos)
+#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos)
+#define CAN_SIDFE_0_MASK _U_(0xFFFF07FF) /**< \brief (CAN_SIDFE_0) MASK Register */
+
+/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ID:29; /*!< bit: 0..28 Identifier */
+ uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
+ uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
+ uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBE_0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBE_0_OFFSET 0x00 /**< \brief (CAN_TXBE_0 offset) Tx Buffer Element 0 */
+#define CAN_TXBE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_0 reset_value) Tx Buffer Element 0 */
+
+#define CAN_TXBE_0_ID_Pos 0 /**< \brief (CAN_TXBE_0) Identifier */
+#define CAN_TXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos)
+#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & ((value) << CAN_TXBE_0_ID_Pos))
+#define CAN_TXBE_0_RTR_Pos 29 /**< \brief (CAN_TXBE_0) Remote Transmission Request */
+#define CAN_TXBE_0_RTR (_U_(0x1) << CAN_TXBE_0_RTR_Pos)
+#define CAN_TXBE_0_XTD_Pos 30 /**< \brief (CAN_TXBE_0) Extended Identifier */
+#define CAN_TXBE_0_XTD (_U_(0x1) << CAN_TXBE_0_XTD_Pos)
+#define CAN_TXBE_0_ESI_Pos 31 /**< \brief (CAN_TXBE_0) Error State Indicator */
+#define CAN_TXBE_0_ESI (_U_(0x1) << CAN_TXBE_0_ESI_Pos)
+#define CAN_TXBE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBE_0) MASK Register */
+
+/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t DLC:4; /*!< bit: 16..19 Identifier */
+ uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
+ uint32_t FDF:1; /*!< bit: 21 FD Format */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t EFC:1; /*!< bit: 23 Event FIFO Control */
+ uint32_t MM:8; /*!< bit: 24..31 Message Marker */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBE_1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBE_1_OFFSET 0x04 /**< \brief (CAN_TXBE_1 offset) Tx Buffer Element 1 */
+#define CAN_TXBE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_1 reset_value) Tx Buffer Element 1 */
+
+#define CAN_TXBE_1_DLC_Pos 16 /**< \brief (CAN_TXBE_1) Identifier */
+#define CAN_TXBE_1_DLC_Msk (_U_(0xF) << CAN_TXBE_1_DLC_Pos)
+#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & ((value) << CAN_TXBE_1_DLC_Pos))
+#define CAN_TXBE_1_BRS_Pos 20 /**< \brief (CAN_TXBE_1) Bit Rate Search */
+#define CAN_TXBE_1_BRS (_U_(0x1) << CAN_TXBE_1_BRS_Pos)
+#define CAN_TXBE_1_FDF_Pos 21 /**< \brief (CAN_TXBE_1) FD Format */
+#define CAN_TXBE_1_FDF (_U_(0x1) << CAN_TXBE_1_FDF_Pos)
+#define CAN_TXBE_1_EFC_Pos 23 /**< \brief (CAN_TXBE_1) Event FIFO Control */
+#define CAN_TXBE_1_EFC (_U_(0x1) << CAN_TXBE_1_EFC_Pos)
+#define CAN_TXBE_1_MM_Pos 24 /**< \brief (CAN_TXBE_1) Message Marker */
+#define CAN_TXBE_1_MM_Msk (_U_(0xFF) << CAN_TXBE_1_MM_Pos)
+#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & ((value) << CAN_TXBE_1_MM_Pos))
+#define CAN_TXBE_1_MASK _U_(0xFFBF0000) /**< \brief (CAN_TXBE_1) MASK Register */
+
+/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
+ uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
+ uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
+ uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBE_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBE_DATA_OFFSET 0x08 /**< \brief (CAN_TXBE_DATA offset) Tx Buffer Element Data */
+#define CAN_TXBE_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_DATA reset_value) Tx Buffer Element Data */
+
+#define CAN_TXBE_DATA_DB0_Pos 0 /**< \brief (CAN_TXBE_DATA) Data Byte 0 */
+#define CAN_TXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB0_Pos)
+#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & ((value) << CAN_TXBE_DATA_DB0_Pos))
+#define CAN_TXBE_DATA_DB1_Pos 8 /**< \brief (CAN_TXBE_DATA) Data Byte 1 */
+#define CAN_TXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB1_Pos)
+#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & ((value) << CAN_TXBE_DATA_DB1_Pos))
+#define CAN_TXBE_DATA_DB2_Pos 16 /**< \brief (CAN_TXBE_DATA) Data Byte 2 */
+#define CAN_TXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB2_Pos)
+#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & ((value) << CAN_TXBE_DATA_DB2_Pos))
+#define CAN_TXBE_DATA_DB3_Pos 24 /**< \brief (CAN_TXBE_DATA) Data Byte 3 */
+#define CAN_TXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB3_Pos)
+#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & ((value) << CAN_TXBE_DATA_DB3_Pos))
+#define CAN_TXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBE_DATA) MASK Register */
+
+/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ID:29; /*!< bit: 0..28 Identifier */
+ uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
+ uint32_t XTD:1; /*!< bit: 30 Extended Indentifier */
+ uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXEFE_0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXEFE_0_OFFSET 0x00 /**< \brief (CAN_TXEFE_0 offset) Tx Event FIFO Element 0 */
+#define CAN_TXEFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFE_0 reset_value) Tx Event FIFO Element 0 */
+
+#define CAN_TXEFE_0_ID_Pos 0 /**< \brief (CAN_TXEFE_0) Identifier */
+#define CAN_TXEFE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos)
+#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & ((value) << CAN_TXEFE_0_ID_Pos))
+#define CAN_TXEFE_0_RTR_Pos 29 /**< \brief (CAN_TXEFE_0) Remote Transmission Request */
+#define CAN_TXEFE_0_RTR (_U_(0x1) << CAN_TXEFE_0_RTR_Pos)
+#define CAN_TXEFE_0_XTD_Pos 30 /**< \brief (CAN_TXEFE_0) Extended Indentifier */
+#define CAN_TXEFE_0_XTD (_U_(0x1) << CAN_TXEFE_0_XTD_Pos)
+#define CAN_TXEFE_0_ESI_Pos 31 /**< \brief (CAN_TXEFE_0) Error State Indicator */
+#define CAN_TXEFE_0_ESI (_U_(0x1) << CAN_TXEFE_0_ESI_Pos)
+#define CAN_TXEFE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXEFE_0) MASK Register */
+
+/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TXTS:16; /*!< bit: 0..15 Tx Timestamp */
+ uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
+ uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
+ uint32_t FDF:1; /*!< bit: 21 FD Format */
+ uint32_t ET:2; /*!< bit: 22..23 Event Type */
+ uint32_t MM:8; /*!< bit: 24..31 Message Marker */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXEFE_1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXEFE_1_OFFSET 0x04 /**< \brief (CAN_TXEFE_1 offset) Tx Event FIFO Element 1 */
+#define CAN_TXEFE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFE_1 reset_value) Tx Event FIFO Element 1 */
+
+#define CAN_TXEFE_1_TXTS_Pos 0 /**< \brief (CAN_TXEFE_1) Tx Timestamp */
+#define CAN_TXEFE_1_TXTS_Msk (_U_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos)
+#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & ((value) << CAN_TXEFE_1_TXTS_Pos))
+#define CAN_TXEFE_1_DLC_Pos 16 /**< \brief (CAN_TXEFE_1) Data Length Code */
+#define CAN_TXEFE_1_DLC_Msk (_U_(0xF) << CAN_TXEFE_1_DLC_Pos)
+#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & ((value) << CAN_TXEFE_1_DLC_Pos))
+#define CAN_TXEFE_1_BRS_Pos 20 /**< \brief (CAN_TXEFE_1) Bit Rate Search */
+#define CAN_TXEFE_1_BRS (_U_(0x1) << CAN_TXEFE_1_BRS_Pos)
+#define CAN_TXEFE_1_FDF_Pos 21 /**< \brief (CAN_TXEFE_1) FD Format */
+#define CAN_TXEFE_1_FDF (_U_(0x1) << CAN_TXEFE_1_FDF_Pos)
+#define CAN_TXEFE_1_ET_Pos 22 /**< \brief (CAN_TXEFE_1) Event Type */
+#define CAN_TXEFE_1_ET_Msk (_U_(0x3) << CAN_TXEFE_1_ET_Pos)
+#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & ((value) << CAN_TXEFE_1_ET_Pos))
+#define CAN_TXEFE_1_ET_TXE_Val _U_(0x1) /**< \brief (CAN_TXEFE_1) Tx event */
+#define CAN_TXEFE_1_ET_TXC_Val _U_(0x2) /**< \brief (CAN_TXEFE_1) Transmission in spite of cancellation */
+#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos)
+#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos)
+#define CAN_TXEFE_1_MM_Pos 24 /**< \brief (CAN_TXEFE_1) Message Marker */
+#define CAN_TXEFE_1_MM_Msk (_U_(0xFF) << CAN_TXEFE_1_MM_Pos)
+#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & ((value) << CAN_TXEFE_1_MM_Pos))
+#define CAN_TXEFE_1_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXEFE_1) MASK Register */
+
+/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EFID1:29; /*!< bit: 0..28 Extended Filter ID 1 */
+ uint32_t EFEC:3; /*!< bit: 29..31 Extended Filter Element Configuration */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_XIDFE_0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_XIDFE_0_OFFSET 0x00 /**< \brief (CAN_XIDFE_0 offset) Extended Message ID Filter Element 0 */
+#define CAN_XIDFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFE_0 reset_value) Extended Message ID Filter Element 0 */
+
+#define CAN_XIDFE_0_EFID1_Pos 0 /**< \brief (CAN_XIDFE_0) Extended Filter ID 1 */
+#define CAN_XIDFE_0_EFID1_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos)
+#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & ((value) << CAN_XIDFE_0_EFID1_Pos))
+#define CAN_XIDFE_0_EFEC_Pos 29 /**< \brief (CAN_XIDFE_0) Extended Filter Element Configuration */
+#define CAN_XIDFE_0_EFEC_Msk (_U_(0x7) << CAN_XIDFE_0_EFEC_Pos)
+#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & ((value) << CAN_XIDFE_0_EFEC_Pos))
+#define CAN_XIDFE_0_EFEC_DISABLE_Val _U_(0x0) /**< \brief (CAN_XIDFE_0) Disable filter element */
+#define CAN_XIDFE_0_EFEC_STF0M_Val _U_(0x1) /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */
+#define CAN_XIDFE_0_EFEC_STF1M_Val _U_(0x2) /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */
+#define CAN_XIDFE_0_EFEC_REJECT_Val _U_(0x3) /**< \brief (CAN_XIDFE_0) Reject ID if filter match */
+#define CAN_XIDFE_0_EFEC_PRIORITY_Val _U_(0x4) /**< \brief (CAN_XIDFE_0) Set priority if filter match */
+#define CAN_XIDFE_0_EFEC_PRIF0M_Val _U_(0x5) /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */
+#define CAN_XIDFE_0_EFEC_PRIF1M_Val _U_(0x6) /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */
+#define CAN_XIDFE_0_EFEC_STRXBUF_Val _U_(0x7) /**< \brief (CAN_XIDFE_0) Store into Rx Buffer */
+#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos)
+#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos)
+#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos)
+#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos)
+#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos)
+#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos)
+#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos)
+#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos)
+#define CAN_XIDFE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_XIDFE_0) MASK Register */
+
+/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EFID2:29; /*!< bit: 0..28 Extended Filter ID 2 */
+ uint32_t :1; /*!< bit: 29 Reserved */
+ uint32_t EFT:2; /*!< bit: 30..31 Extended Filter Type */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_XIDFE_1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_XIDFE_1_OFFSET 0x04 /**< \brief (CAN_XIDFE_1 offset) Extended Message ID Filter Element 1 */
+#define CAN_XIDFE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFE_1 reset_value) Extended Message ID Filter Element 1 */
+
+#define CAN_XIDFE_1_EFID2_Pos 0 /**< \brief (CAN_XIDFE_1) Extended Filter ID 2 */
+#define CAN_XIDFE_1_EFID2_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos)
+#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & ((value) << CAN_XIDFE_1_EFID2_Pos))
+#define CAN_XIDFE_1_EFT_Pos 30 /**< \brief (CAN_XIDFE_1) Extended Filter Type */
+#define CAN_XIDFE_1_EFT_Msk (_U_(0x3) << CAN_XIDFE_1_EFT_Pos)
+#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & ((value) << CAN_XIDFE_1_EFT_Pos))
+#define CAN_XIDFE_1_EFT_RANGEM_Val _U_(0x0) /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */
+#define CAN_XIDFE_1_EFT_DUAL_Val _U_(0x1) /**< \brief (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */
+#define CAN_XIDFE_1_EFT_CLASSIC_Val _U_(0x2) /**< \brief (CAN_XIDFE_1) Classic filter */
+#define CAN_XIDFE_1_EFT_RANGE_Val _U_(0x3) /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */
+#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos)
+#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos)
+#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos)
+#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos)
+#define CAN_XIDFE_1_MASK _U_(0xDFFFFFFF) /**< \brief (CAN_XIDFE_1) MASK Register */
+
+/** \brief CAN APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __I CAN_CREL_Type CREL; /**< \brief Offset: 0x00 (R/ 32) Core Release */
+ __I CAN_ENDN_Type ENDN; /**< \brief Offset: 0x04 (R/ 32) Endian */
+ __IO CAN_MRCFG_Type MRCFG; /**< \brief Offset: 0x08 (R/W 32) Message RAM Configuration */
+ __IO CAN_DBTP_Type DBTP; /**< \brief Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */
+ __IO CAN_TEST_Type TEST; /**< \brief Offset: 0x10 (R/W 32) Test */
+ __IO CAN_RWD_Type RWD; /**< \brief Offset: 0x14 (R/W 32) RAM Watchdog */
+ __IO CAN_CCCR_Type CCCR; /**< \brief Offset: 0x18 (R/W 32) CC Control */
+ __IO CAN_NBTP_Type NBTP; /**< \brief Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */
+ __IO CAN_TSCC_Type TSCC; /**< \brief Offset: 0x20 (R/W 32) Timestamp Counter Configuration */
+ __I CAN_TSCV_Type TSCV; /**< \brief Offset: 0x24 (R/ 32) Timestamp Counter Value */
+ __IO CAN_TOCC_Type TOCC; /**< \brief Offset: 0x28 (R/W 32) Timeout Counter Configuration */
+ __IO CAN_TOCV_Type TOCV; /**< \brief Offset: 0x2C (R/W 32) Timeout Counter Value */
+ RoReg8 Reserved1[0x10];
+ __I CAN_ECR_Type ECR; /**< \brief Offset: 0x40 (R/ 32) Error Counter */
+ __I CAN_PSR_Type PSR; /**< \brief Offset: 0x44 (R/ 32) Protocol Status */
+ __IO CAN_TDCR_Type TDCR; /**< \brief Offset: 0x48 (R/W 32) Extended ID Filter Configuration */
+ RoReg8 Reserved2[0x4];
+ __IO CAN_IR_Type IR; /**< \brief Offset: 0x50 (R/W 32) Interrupt */
+ __IO CAN_IE_Type IE; /**< \brief Offset: 0x54 (R/W 32) Interrupt Enable */
+ __IO CAN_ILS_Type ILS; /**< \brief Offset: 0x58 (R/W 32) Interrupt Line Select */
+ __IO CAN_ILE_Type ILE; /**< \brief Offset: 0x5C (R/W 32) Interrupt Line Enable */
+ RoReg8 Reserved3[0x20];
+ __IO CAN_GFC_Type GFC; /**< \brief Offset: 0x80 (R/W 32) Global Filter Configuration */
+ __IO CAN_SIDFC_Type SIDFC; /**< \brief Offset: 0x84 (R/W 32) Standard ID Filter Configuration */
+ __IO CAN_XIDFC_Type XIDFC; /**< \brief Offset: 0x88 (R/W 32) Extended ID Filter Configuration */
+ RoReg8 Reserved4[0x4];
+ __IO CAN_XIDAM_Type XIDAM; /**< \brief Offset: 0x90 (R/W 32) Extended ID AND Mask */
+ __I CAN_HPMS_Type HPMS; /**< \brief Offset: 0x94 (R/ 32) High Priority Message Status */
+ __IO CAN_NDAT1_Type NDAT1; /**< \brief Offset: 0x98 (R/W 32) New Data 1 */
+ __IO CAN_NDAT2_Type NDAT2; /**< \brief Offset: 0x9C (R/W 32) New Data 2 */
+ __IO CAN_RXF0C_Type RXF0C; /**< \brief Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */
+ __I CAN_RXF0S_Type RXF0S; /**< \brief Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */
+ __IO CAN_RXF0A_Type RXF0A; /**< \brief Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */
+ __IO CAN_RXBC_Type RXBC; /**< \brief Offset: 0xAC (R/W 32) Rx Buffer Configuration */
+ __IO CAN_RXF1C_Type RXF1C; /**< \brief Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */
+ __I CAN_RXF1S_Type RXF1S; /**< \brief Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */
+ __IO CAN_RXF1A_Type RXF1A; /**< \brief Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */
+ __IO CAN_RXESC_Type RXESC; /**< \brief Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */
+ __IO CAN_TXBC_Type TXBC; /**< \brief Offset: 0xC0 (R/W 32) Tx Buffer Configuration */
+ __I CAN_TXFQS_Type TXFQS; /**< \brief Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */
+ __IO CAN_TXESC_Type TXESC; /**< \brief Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */
+ __I CAN_TXBRP_Type TXBRP; /**< \brief Offset: 0xCC (R/ 32) Tx Buffer Request Pending */
+ __IO CAN_TXBAR_Type TXBAR; /**< \brief Offset: 0xD0 (R/W 32) Tx Buffer Add Request */
+ __IO CAN_TXBCR_Type TXBCR; /**< \brief Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */
+ __I CAN_TXBTO_Type TXBTO; /**< \brief Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */
+ __I CAN_TXBCF_Type TXBCF; /**< \brief Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */
+ __IO CAN_TXBTIE_Type TXBTIE; /**< \brief Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */
+ __IO CAN_TXBCIE_Type TXBCIE; /**< \brief Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */
+ RoReg8 Reserved5[0x8];
+ __IO CAN_TXEFC_Type TXEFC; /**< \brief Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */
+ __I CAN_TXEFS_Type TXEFS; /**< \brief Offset: 0xF4 (R/ 32) Tx Event FIFO Status */
+ __IO CAN_TXEFA_Type TXEFA; /**< \brief Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */
+} Can;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief CAN Mram_rxbe hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO CAN_RXBE_0_Type RXBE_0; /**< \brief Offset: 0x00 (R/W 32) Rx Buffer Element 0 */
+ __IO CAN_RXBE_1_Type RXBE_1; /**< \brief Offset: 0x04 (R/W 32) Rx Buffer Element 1 */
+ __IO CAN_RXBE_DATA_Type RXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx Buffer Element Data */
+} CanMramRxbe
+#ifdef __GNUC__
+ __attribute__ ((aligned (4)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief CAN Mram_rxf0e hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO CAN_RXF0E_0_Type RXF0E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */
+ __IO CAN_RXF0E_1_Type RXF0E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */
+ __IO CAN_RXF0E_DATA_Type RXF0E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */
+} CanMramRxf0e
+#ifdef __GNUC__
+ __attribute__ ((aligned (4)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief CAN Mram_rxf1e hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO CAN_RXF1E_0_Type RXF1E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */
+ __IO CAN_RXF1E_1_Type RXF1E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */
+ __IO CAN_RXF1E_DATA_Type RXF1E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */
+} CanMramRxf1e
+#ifdef __GNUC__
+ __attribute__ ((aligned (4)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief CAN Mram_sidfe hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO CAN_SIDFE_0_Type SIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Standard Message ID Filter Element */
+} CanMramSidfe
+#ifdef __GNUC__
+ __attribute__ ((aligned (4)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief CAN Mram_txbe hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO CAN_TXBE_0_Type TXBE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Buffer Element 0 */
+ __IO CAN_TXBE_1_Type TXBE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Buffer Element 1 */
+ __IO CAN_TXBE_DATA_Type TXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Tx Buffer Element Data */
+} CanMramTxbe
+#ifdef __GNUC__
+ __attribute__ ((aligned (4)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief CAN Mram_txefe hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO CAN_TXEFE_0_Type TXEFE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */
+ __IO CAN_TXEFE_1_Type TXEFE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */
+} CanMramTxefe
+#ifdef __GNUC__
+ __attribute__ ((aligned (4)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief CAN Mram_xifde hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO CAN_XIDFE_0_Type XIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */
+ __IO CAN_XIDFE_1_Type XIDFE_1; /**< \brief Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */
+} CanMramXifde
+#ifdef __GNUC__
+ __attribute__ ((aligned (4)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_CAN_MRAM_RXBE
+#define SECTION_CAN_MRAM_RXF0E
+#define SECTION_CAN_MRAM_RXF1E
+#define SECTION_CAN_MRAM_SIDFE
+#define SECTION_CAN_MRAM_TXBE
+#define SECTION_CAN_MRAM_TXEFE
+#define SECTION_CAN_MRAM_XIFDE
+
+/*@}*/
+
+#endif /* _SAME54_CAN_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/ccl.h b/sysmoOCTSIM/include/component/ccl.h
index aa7f5f6..b5dbb9a 100644
--- a/sysmoOCTSIM/include/component/ccl.h
+++ b/sysmoOCTSIM/include/component/ccl.h
@@ -1,228 +1,228 @@
-/**
- * \file
- *
- * \brief Component description for CCL
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_CCL_COMPONENT_
-#define _SAME54_CCL_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR CCL */
-/* ========================================================================== */
-/** \addtogroup SAME54_CCL Configurable Custom Logic */
-/*@{*/
-
-#define CCL_U2225
-#define REV_CCL 0x110
-
-/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} CCL_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */
-#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */
-
-#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */
-#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos)
-#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */
-#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos)
-#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run in Standby */
-#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos)
-#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */
-
-/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} CCL_SEQCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */
-#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */
-
-#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */
-#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos)
-#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos))
-#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */
-#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */
-#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */
-#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */
-#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */
-#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos)
-#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos)
-#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos)
-#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos)
-#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos)
-#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */
-
-/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */
- uint32_t :2; /*!< bit: 2.. 3 Reserved */
- uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */
- uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */
- uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */
- uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */
- uint32_t INVEI:1; /*!< bit: 20 Inverted Event Input Enable */
- uint32_t LUTEI:1; /*!< bit: 21 LUT Event Input Enable */
- uint32_t LUTEO:1; /*!< bit: 22 LUT Event Output Enable */
- uint32_t :1; /*!< bit: 23 Reserved */
- uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CCL_LUTCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */
-#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */
-
-#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */
-#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos)
-#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */
-#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos)
-#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos))
-#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */
-#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */
-#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */
-#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos)
-#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos)
-#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos)
-#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */
-#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos)
-#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */
-#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos))
-#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
-#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
-#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
-#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
-#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
-#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
-#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
-#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
-#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
-#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
-#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */
-#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos))
-#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
-#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
-#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
-#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
-#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
-#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
-#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
-#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
-#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
-#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
-#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */
-#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos))
-#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
-#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
-#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
-#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
-#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
-#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
-#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
-#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
-#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
-#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
-#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */
-#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos)
-#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */
-#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos)
-#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */
-#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos)
-#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */
-#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos)
-#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos))
-#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */
-
-/** \brief CCL hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
- RoReg8 Reserved1[0x3];
- __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */
- RoReg8 Reserved2[0x2];
- __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */
-} Ccl;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_CCL_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for CCL
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_CCL_COMPONENT_
+#define _SAME54_CCL_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR CCL */
+/* ========================================================================== */
+/** \addtogroup SAME54_CCL Configurable Custom Logic */
+/*@{*/
+
+#define CCL_U2225
+#define REV_CCL 0x110
+
+/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} CCL_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */
+#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */
+
+#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */
+#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos)
+#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */
+#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos)
+#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run in Standby */
+#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos)
+#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */
+
+/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} CCL_SEQCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */
+#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */
+
+#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */
+#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos))
+#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */
+#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */
+#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */
+#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */
+#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */
+#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */
+
+/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */
+ uint32_t :2; /*!< bit: 2.. 3 Reserved */
+ uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */
+ uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */
+ uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */
+ uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */
+ uint32_t INVEI:1; /*!< bit: 20 Inverted Event Input Enable */
+ uint32_t LUTEI:1; /*!< bit: 21 LUT Event Input Enable */
+ uint32_t LUTEO:1; /*!< bit: 22 LUT Event Output Enable */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CCL_LUTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */
+#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */
+
+#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */
+#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos)
+#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */
+#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos)
+#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos))
+#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */
+#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */
+#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */
+#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos)
+#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos)
+#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos)
+#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */
+#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos)
+#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */
+#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos))
+#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
+#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
+#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
+#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
+#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
+#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
+#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
+#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
+#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
+#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
+#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */
+#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos))
+#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
+#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
+#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
+#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
+#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
+#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
+#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
+#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
+#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
+#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
+#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */
+#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos))
+#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
+#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
+#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
+#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
+#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
+#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
+#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
+#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
+#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
+#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
+#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */
+#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos)
+#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */
+#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos)
+#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */
+#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos)
+#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */
+#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos)
+#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos))
+#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */
+
+/** \brief CCL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
+ RoReg8 Reserved1[0x3];
+ __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */
+ RoReg8 Reserved2[0x2];
+ __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */
+} Ccl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_CCL_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/cmcc.h b/sysmoOCTSIM/include/component/cmcc.h
index 78bf82a..55799b5 100644
--- a/sysmoOCTSIM/include/component/cmcc.h
+++ b/sysmoOCTSIM/include/component/cmcc.h
@@ -1,357 +1,357 @@
-/**
- * \file
- *
- * \brief Component description for CMCC
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_CMCC_COMPONENT_
-#define _SAME54_CMCC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR CMCC */
-/* ========================================================================== */
-/** \addtogroup SAME54_CMCC Cortex M Cache Controller */
-/*@{*/
-
-#define CMCC_U2015
-#define REV_CMCC 0x600
-
-/* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/ 32) Cache Type Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t GCLK:1; /*!< bit: 1 dynamic Clock Gating supported */
- uint32_t :2; /*!< bit: 2.. 3 Reserved */
- uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */
- uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */
- uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */
- uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */
- uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */
- uint32_t :18; /*!< bit: 14..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_TYPE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_TYPE_OFFSET 0x00 /**< \brief (CMCC_TYPE offset) Cache Type Register */
-#define CMCC_TYPE_RESETVALUE _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */
-
-#define CMCC_TYPE_GCLK_Pos 1 /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */
-#define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos)
-#define CMCC_TYPE_RRP_Pos 4 /**< \brief (CMCC_TYPE) Round Robin Policy supported */
-#define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos)
-#define CMCC_TYPE_WAYNUM_Pos 5 /**< \brief (CMCC_TYPE) Number of Way */
-#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos)
-#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos))
-#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */
-#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */
-#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */
-#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos)
-#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos)
-#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos)
-#define CMCC_TYPE_LCKDOWN_Pos 7 /**< \brief (CMCC_TYPE) Lock Down supported */
-#define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos)
-#define CMCC_TYPE_CSIZE_Pos 8 /**< \brief (CMCC_TYPE) Cache Size */
-#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos))
-#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */
-#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */
-#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */
-#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */
-#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */
-#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */
-#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */
-#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CLSIZE_Pos 11 /**< \brief (CMCC_TYPE) Cache Line Size */
-#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos))
-#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */
-#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */
-#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */
-#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */
-#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */
-#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */
-#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_MASK _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */
-
-/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ICDIS:1; /*!< bit: 1 Instruction Cache Disable */
- uint32_t DCDIS:1; /*!< bit: 2 Data Cache Disable */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t CSIZESW:3; /*!< bit: 4.. 6 Cache size configured by software */
- uint32_t :25; /*!< bit: 7..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_CFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_CFG_OFFSET 0x04 /**< \brief (CMCC_CFG offset) Cache Configuration Register */
-#define CMCC_CFG_RESETVALUE _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */
-
-#define CMCC_CFG_ICDIS_Pos 1 /**< \brief (CMCC_CFG) Instruction Cache Disable */
-#define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos)
-#define CMCC_CFG_DCDIS_Pos 2 /**< \brief (CMCC_CFG) Data Cache Disable */
-#define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos)
-#define CMCC_CFG_CSIZESW_Pos 4 /**< \brief (CMCC_CFG) Cache size configured by software */
-#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos))
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_MASK _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */
-
-/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CEN:1; /*!< bit: 0 Cache Controller Enable */
- uint32_t :31; /*!< bit: 1..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_CTRL_OFFSET 0x08 /**< \brief (CMCC_CTRL offset) Cache Control Register */
-#define CMCC_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */
-
-#define CMCC_CTRL_CEN_Pos 0 /**< \brief (CMCC_CTRL) Cache Controller Enable */
-#define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos)
-#define CMCC_CTRL_MASK _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */
-
-/* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */
- uint32_t :31; /*!< bit: 1..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_SR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_SR_OFFSET 0x0C /**< \brief (CMCC_SR offset) Cache Status Register */
-#define CMCC_SR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */
-
-#define CMCC_SR_CSTS_Pos 0 /**< \brief (CMCC_SR) Cache Controller Status */
-#define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos)
-#define CMCC_SR_MASK _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */
-
-/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t LCKWAY:4; /*!< bit: 0.. 3 Lockdown way Register */
- uint32_t :28; /*!< bit: 4..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_LCKWAY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_LCKWAY_OFFSET 0x10 /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */
-#define CMCC_LCKWAY_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */
-
-#define CMCC_LCKWAY_LCKWAY_Pos 0 /**< \brief (CMCC_LCKWAY) Lockdown way Register */
-#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos)
-#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos))
-#define CMCC_LCKWAY_MASK _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */
-
-/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t INVALL:1; /*!< bit: 0 Cache Controller invalidate All */
- uint32_t :31; /*!< bit: 1..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_MAINT0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_MAINT0_OFFSET 0x20 /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */
-#define CMCC_MAINT0_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */
-
-#define CMCC_MAINT0_INVALL_Pos 0 /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */
-#define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos)
-#define CMCC_MAINT0_MASK _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */
-
-/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :4; /*!< bit: 0.. 3 Reserved */
- uint32_t INDEX:8; /*!< bit: 4..11 Invalidate Index */
- uint32_t :16; /*!< bit: 12..27 Reserved */
- uint32_t WAY:4; /*!< bit: 28..31 Invalidate Way */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_MAINT1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_MAINT1_OFFSET 0x24 /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */
-#define CMCC_MAINT1_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */
-
-#define CMCC_MAINT1_INDEX_Pos 4 /**< \brief (CMCC_MAINT1) Invalidate Index */
-#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos)
-#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos))
-#define CMCC_MAINT1_WAY_Pos 28 /**< \brief (CMCC_MAINT1) Invalidate Way */
-#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos)
-#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos))
-#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */
-#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */
-#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */
-#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */
-#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos)
-#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos)
-#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos)
-#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos)
-#define CMCC_MAINT1_MASK _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */
-
-/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_MCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_MCFG_OFFSET 0x28 /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */
-#define CMCC_MCFG_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */
-
-#define CMCC_MCFG_MODE_Pos 0 /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */
-#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos)
-#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos))
-#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< \brief (CMCC_MCFG) cycle counter */
-#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */
-#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< \brief (CMCC_MCFG) data hit counter */
-#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos)
-#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
-#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
-#define CMCC_MCFG_MASK _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */
-
-/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t MENABLE:1; /*!< bit: 0 Cache Controller Monitor Enable */
- uint32_t :31; /*!< bit: 1..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_MEN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_MEN_OFFSET 0x2C /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */
-#define CMCC_MEN_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */
-
-#define CMCC_MEN_MENABLE_Pos 0 /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */
-#define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos)
-#define CMCC_MEN_MASK _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */
-
-/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Cache Controller Software Reset */
- uint32_t :31; /*!< bit: 1..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_MCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_MCTRL_OFFSET 0x30 /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */
-#define CMCC_MCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */
-
-#define CMCC_MCTRL_SWRST_Pos 0 /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */
-#define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos)
-#define CMCC_MCTRL_MASK _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */
-
-/* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EVENT_CNT:32; /*!< bit: 0..31 Monitor Event Counter */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_MSR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_MSR_OFFSET 0x34 /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */
-#define CMCC_MSR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */
-
-#define CMCC_MSR_EVENT_CNT_Pos 0 /**< \brief (CMCC_MSR) Monitor Event Counter */
-#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos)
-#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos))
-#define CMCC_MSR_MASK _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */
-
-/** \brief CMCC APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __I CMCC_TYPE_Type TYPE; /**< \brief Offset: 0x00 (R/ 32) Cache Type Register */
- __IO CMCC_CFG_Type CFG; /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */
- __O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */
- __I CMCC_SR_Type SR; /**< \brief Offset: 0x0C (R/ 32) Cache Status Register */
- __IO CMCC_LCKWAY_Type LCKWAY; /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */
- RoReg8 Reserved1[0xC];
- __O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */
- __O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */
- __IO CMCC_MCFG_Type MCFG; /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */
- __IO CMCC_MEN_Type MEN; /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */
- __O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */
- __I CMCC_MSR_Type MSR; /**< \brief Offset: 0x34 (R/ 32) Cache Monitor Status Register */
-} Cmcc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_CMCC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for CMCC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_CMCC_COMPONENT_
+#define _SAME54_CMCC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR CMCC */
+/* ========================================================================== */
+/** \addtogroup SAME54_CMCC Cortex M Cache Controller */
+/*@{*/
+
+#define CMCC_U2015
+#define REV_CMCC 0x600
+
+/* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/ 32) Cache Type Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t GCLK:1; /*!< bit: 1 dynamic Clock Gating supported */
+ uint32_t :2; /*!< bit: 2.. 3 Reserved */
+ uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */
+ uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */
+ uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */
+ uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */
+ uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */
+ uint32_t :18; /*!< bit: 14..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_TYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_TYPE_OFFSET 0x00 /**< \brief (CMCC_TYPE offset) Cache Type Register */
+#define CMCC_TYPE_RESETVALUE _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */
+
+#define CMCC_TYPE_GCLK_Pos 1 /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */
+#define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos)
+#define CMCC_TYPE_RRP_Pos 4 /**< \brief (CMCC_TYPE) Round Robin Policy supported */
+#define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos)
+#define CMCC_TYPE_WAYNUM_Pos 5 /**< \brief (CMCC_TYPE) Number of Way */
+#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos)
+#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos))
+#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */
+#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */
+#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */
+#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos)
+#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos)
+#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos)
+#define CMCC_TYPE_LCKDOWN_Pos 7 /**< \brief (CMCC_TYPE) Lock Down supported */
+#define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos)
+#define CMCC_TYPE_CSIZE_Pos 8 /**< \brief (CMCC_TYPE) Cache Size */
+#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos))
+#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */
+#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */
+#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */
+#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */
+#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */
+#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */
+#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */
+#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CLSIZE_Pos 11 /**< \brief (CMCC_TYPE) Cache Line Size */
+#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos))
+#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */
+#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */
+#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */
+#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */
+#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */
+#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */
+#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_MASK _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */
+
+/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ICDIS:1; /*!< bit: 1 Instruction Cache Disable */
+ uint32_t DCDIS:1; /*!< bit: 2 Data Cache Disable */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t CSIZESW:3; /*!< bit: 4.. 6 Cache size configured by software */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_CFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_CFG_OFFSET 0x04 /**< \brief (CMCC_CFG offset) Cache Configuration Register */
+#define CMCC_CFG_RESETVALUE _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */
+
+#define CMCC_CFG_ICDIS_Pos 1 /**< \brief (CMCC_CFG) Instruction Cache Disable */
+#define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos)
+#define CMCC_CFG_DCDIS_Pos 2 /**< \brief (CMCC_CFG) Data Cache Disable */
+#define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos)
+#define CMCC_CFG_CSIZESW_Pos 4 /**< \brief (CMCC_CFG) Cache size configured by software */
+#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos))
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_MASK _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */
+
+/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CEN:1; /*!< bit: 0 Cache Controller Enable */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_CTRL_OFFSET 0x08 /**< \brief (CMCC_CTRL offset) Cache Control Register */
+#define CMCC_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */
+
+#define CMCC_CTRL_CEN_Pos 0 /**< \brief (CMCC_CTRL) Cache Controller Enable */
+#define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos)
+#define CMCC_CTRL_MASK _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */
+
+/* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_SR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_SR_OFFSET 0x0C /**< \brief (CMCC_SR offset) Cache Status Register */
+#define CMCC_SR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */
+
+#define CMCC_SR_CSTS_Pos 0 /**< \brief (CMCC_SR) Cache Controller Status */
+#define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos)
+#define CMCC_SR_MASK _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */
+
+/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LCKWAY:4; /*!< bit: 0.. 3 Lockdown way Register */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_LCKWAY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_LCKWAY_OFFSET 0x10 /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */
+#define CMCC_LCKWAY_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */
+
+#define CMCC_LCKWAY_LCKWAY_Pos 0 /**< \brief (CMCC_LCKWAY) Lockdown way Register */
+#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos)
+#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos))
+#define CMCC_LCKWAY_MASK _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */
+
+/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t INVALL:1; /*!< bit: 0 Cache Controller invalidate All */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_MAINT0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_MAINT0_OFFSET 0x20 /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */
+#define CMCC_MAINT0_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */
+
+#define CMCC_MAINT0_INVALL_Pos 0 /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */
+#define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos)
+#define CMCC_MAINT0_MASK _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */
+
+/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :4; /*!< bit: 0.. 3 Reserved */
+ uint32_t INDEX:8; /*!< bit: 4..11 Invalidate Index */
+ uint32_t :16; /*!< bit: 12..27 Reserved */
+ uint32_t WAY:4; /*!< bit: 28..31 Invalidate Way */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_MAINT1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_MAINT1_OFFSET 0x24 /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */
+#define CMCC_MAINT1_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */
+
+#define CMCC_MAINT1_INDEX_Pos 4 /**< \brief (CMCC_MAINT1) Invalidate Index */
+#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos)
+#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos))
+#define CMCC_MAINT1_WAY_Pos 28 /**< \brief (CMCC_MAINT1) Invalidate Way */
+#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos)
+#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos))
+#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */
+#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */
+#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */
+#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */
+#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos)
+#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos)
+#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos)
+#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos)
+#define CMCC_MAINT1_MASK _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */
+
+/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_MCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_MCFG_OFFSET 0x28 /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */
+#define CMCC_MCFG_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */
+
+#define CMCC_MCFG_MODE_Pos 0 /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */
+#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos)
+#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos))
+#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< \brief (CMCC_MCFG) cycle counter */
+#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */
+#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< \brief (CMCC_MCFG) data hit counter */
+#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos)
+#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
+#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
+#define CMCC_MCFG_MASK _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */
+
+/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MENABLE:1; /*!< bit: 0 Cache Controller Monitor Enable */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_MEN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_MEN_OFFSET 0x2C /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */
+#define CMCC_MEN_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */
+
+#define CMCC_MEN_MENABLE_Pos 0 /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */
+#define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos)
+#define CMCC_MEN_MASK _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */
+
+/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Cache Controller Software Reset */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_MCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_MCTRL_OFFSET 0x30 /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */
+#define CMCC_MCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */
+
+#define CMCC_MCTRL_SWRST_Pos 0 /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */
+#define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos)
+#define CMCC_MCTRL_MASK _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */
+
+/* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EVENT_CNT:32; /*!< bit: 0..31 Monitor Event Counter */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_MSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_MSR_OFFSET 0x34 /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */
+#define CMCC_MSR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */
+
+#define CMCC_MSR_EVENT_CNT_Pos 0 /**< \brief (CMCC_MSR) Monitor Event Counter */
+#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos)
+#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos))
+#define CMCC_MSR_MASK _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */
+
+/** \brief CMCC APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __I CMCC_TYPE_Type TYPE; /**< \brief Offset: 0x00 (R/ 32) Cache Type Register */
+ __IO CMCC_CFG_Type CFG; /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */
+ __O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */
+ __I CMCC_SR_Type SR; /**< \brief Offset: 0x0C (R/ 32) Cache Status Register */
+ __IO CMCC_LCKWAY_Type LCKWAY; /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */
+ RoReg8 Reserved1[0xC];
+ __O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */
+ __O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */
+ __IO CMCC_MCFG_Type MCFG; /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */
+ __IO CMCC_MEN_Type MEN; /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */
+ __O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */
+ __I CMCC_MSR_Type MSR; /**< \brief Offset: 0x34 (R/ 32) Cache Monitor Status Register */
+} Cmcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_CMCC_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/dac.h b/sysmoOCTSIM/include/component/dac.h
index 20820ca..60f28c0 100644
--- a/sysmoOCTSIM/include/component/dac.h
+++ b/sysmoOCTSIM/include/component/dac.h
@@ -1,544 +1,544 @@
-/**
- * \file
- *
- * \brief Component description for DAC
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_DAC_COMPONENT_
-#define _SAME54_DAC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR DAC */
-/* ========================================================================== */
-/** \addtogroup SAME54_DAC Digital-to-Analog Converter */
-/*@{*/
-
-#define DAC_U2502
-#define REV_DAC 0x100
-
-/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DAC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */
-#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */
-
-#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */
-#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos)
-#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */
-#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos)
-#define DAC_CTRLA_MASK _U_(0x03) /**< \brief (DAC_CTRLA) MASK Register */
-
-/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */
- uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DAC_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */
-#define DAC_CTRLB_RESETVALUE _U_(0x02) /**< \brief (DAC_CTRLB reset_value) Control B */
-
-#define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */
-#define DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos)
-#define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */
-#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
-#define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */
-#define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< \brief (DAC_CTRLB) Analog supply */
-#define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference buffered */
-#define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */
-#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_MASK _U_(0x07) /**< \brief (DAC_CTRLB) MASK Register */
-
-/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */
- uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */
- uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */
- uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */
- uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */
- uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */
- uint8_t RESRDYEO0:1; /*!< bit: 6 Result Ready Event Output 0 */
- uint8_t RESRDYEO1:1; /*!< bit: 7 Result Ready Event Output 1 */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */
- uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */
- uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */
- uint8_t RESRDYEO:2; /*!< bit: 6.. 7 Result Ready Event Output x */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} DAC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */
-#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */
-
-#define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */
-#define DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos)
-#define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */
-#define DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos)
-#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */
-#define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos)
-#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos))
-#define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */
-#define DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos)
-#define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */
-#define DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos)
-#define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */
-#define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos)
-#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos))
-#define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */
-#define DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos)
-#define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */
-#define DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos)
-#define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */
-#define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos)
-#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos))
-#define DAC_EVCTRL_RESRDYEO0_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output 0 */
-#define DAC_EVCTRL_RESRDYEO0 (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos)
-#define DAC_EVCTRL_RESRDYEO1_Pos 7 /**< \brief (DAC_EVCTRL) Result Ready Event Output 1 */
-#define DAC_EVCTRL_RESRDYEO1 (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos)
-#define DAC_EVCTRL_RESRDYEO_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output x */
-#define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos)
-#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos))
-#define DAC_EVCTRL_MASK _U_(0xFF) /**< \brief (DAC_EVCTRL) MASK Register */
-
-/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */
- uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */
- uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */
- uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */
- uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */
- uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */
- uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */
- uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */
- uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */
- uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */
- uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} DAC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
-#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun 0 Interrupt Enable */
-#define DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos)
-#define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun 1 Interrupt Enable */
-#define DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos)
-#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun x Interrupt Enable */
-#define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos)
-#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos))
-#define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */
-#define DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos)
-#define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */
-#define DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos)
-#define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */
-#define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos)
-#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos))
-#define DAC_INTENCLR_RESRDY0_Pos 4 /**< \brief (DAC_INTENCLR) Result 0 Ready Interrupt Enable */
-#define DAC_INTENCLR_RESRDY0 (_U_(1) << DAC_INTENCLR_RESRDY0_Pos)
-#define DAC_INTENCLR_RESRDY1_Pos 5 /**< \brief (DAC_INTENCLR) Result 1 Ready Interrupt Enable */
-#define DAC_INTENCLR_RESRDY1 (_U_(1) << DAC_INTENCLR_RESRDY1_Pos)
-#define DAC_INTENCLR_RESRDY_Pos 4 /**< \brief (DAC_INTENCLR) Result x Ready Interrupt Enable */
-#define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos)
-#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos))
-#define DAC_INTENCLR_OVERRUN0_Pos 6 /**< \brief (DAC_INTENCLR) Overrun 0 Interrupt Enable */
-#define DAC_INTENCLR_OVERRUN0 (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos)
-#define DAC_INTENCLR_OVERRUN1_Pos 7 /**< \brief (DAC_INTENCLR) Overrun 1 Interrupt Enable */
-#define DAC_INTENCLR_OVERRUN1 (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos)
-#define DAC_INTENCLR_OVERRUN_Pos 6 /**< \brief (DAC_INTENCLR) Overrun x Interrupt Enable */
-#define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos)
-#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos))
-#define DAC_INTENCLR_MASK _U_(0xFF) /**< \brief (DAC_INTENCLR) MASK Register */
-
-/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */
- uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */
- uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */
- uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */
- uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */
- uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */
- uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */
- uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */
- uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */
- uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */
- uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} DAC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
-#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
-
-#define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun 0 Interrupt Enable */
-#define DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos)
-#define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun 1 Interrupt Enable */
-#define DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos)
-#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun x Interrupt Enable */
-#define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos)
-#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos))
-#define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */
-#define DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos)
-#define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */
-#define DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos)
-#define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */
-#define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos)
-#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos))
-#define DAC_INTENSET_RESRDY0_Pos 4 /**< \brief (DAC_INTENSET) Result 0 Ready Interrupt Enable */
-#define DAC_INTENSET_RESRDY0 (_U_(1) << DAC_INTENSET_RESRDY0_Pos)
-#define DAC_INTENSET_RESRDY1_Pos 5 /**< \brief (DAC_INTENSET) Result 1 Ready Interrupt Enable */
-#define DAC_INTENSET_RESRDY1 (_U_(1) << DAC_INTENSET_RESRDY1_Pos)
-#define DAC_INTENSET_RESRDY_Pos 4 /**< \brief (DAC_INTENSET) Result x Ready Interrupt Enable */
-#define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos)
-#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos))
-#define DAC_INTENSET_OVERRUN0_Pos 6 /**< \brief (DAC_INTENSET) Overrun 0 Interrupt Enable */
-#define DAC_INTENSET_OVERRUN0 (_U_(1) << DAC_INTENSET_OVERRUN0_Pos)
-#define DAC_INTENSET_OVERRUN1_Pos 7 /**< \brief (DAC_INTENSET) Overrun 1 Interrupt Enable */
-#define DAC_INTENSET_OVERRUN1 (_U_(1) << DAC_INTENSET_OVERRUN1_Pos)
-#define DAC_INTENSET_OVERRUN_Pos 6 /**< \brief (DAC_INTENSET) Overrun x Interrupt Enable */
-#define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos)
-#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos))
-#define DAC_INTENSET_MASK _U_(0xFF) /**< \brief (DAC_INTENSET) MASK Register */
-
-/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t UNDERRUN0:1; /*!< bit: 0 Result 0 Underrun */
- __I uint8_t UNDERRUN1:1; /*!< bit: 1 Result 1 Underrun */
- __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */
- __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */
- __I uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready */
- __I uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready */
- __I uint8_t OVERRUN0:1; /*!< bit: 6 Result 0 Overrun */
- __I uint8_t OVERRUN1:1; /*!< bit: 7 Result 1 Overrun */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Result x Underrun */
- __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */
- __I uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready */
- __I uint8_t OVERRUN:2; /*!< bit: 6.. 7 Result x Overrun */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} DAC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) Result 0 Underrun */
-#define DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos)
-#define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) Result 1 Underrun */
-#define DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos)
-#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Result x Underrun */
-#define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos)
-#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos))
-#define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */
-#define DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos)
-#define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */
-#define DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos)
-#define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */
-#define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos)
-#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos))
-#define DAC_INTFLAG_RESRDY0_Pos 4 /**< \brief (DAC_INTFLAG) Result 0 Ready */
-#define DAC_INTFLAG_RESRDY0 (_U_(1) << DAC_INTFLAG_RESRDY0_Pos)
-#define DAC_INTFLAG_RESRDY1_Pos 5 /**< \brief (DAC_INTFLAG) Result 1 Ready */
-#define DAC_INTFLAG_RESRDY1 (_U_(1) << DAC_INTFLAG_RESRDY1_Pos)
-#define DAC_INTFLAG_RESRDY_Pos 4 /**< \brief (DAC_INTFLAG) Result x Ready */
-#define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos)
-#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos))
-#define DAC_INTFLAG_OVERRUN0_Pos 6 /**< \brief (DAC_INTFLAG) Result 0 Overrun */
-#define DAC_INTFLAG_OVERRUN0 (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos)
-#define DAC_INTFLAG_OVERRUN1_Pos 7 /**< \brief (DAC_INTFLAG) Result 1 Overrun */
-#define DAC_INTFLAG_OVERRUN1 (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos)
-#define DAC_INTFLAG_OVERRUN_Pos 6 /**< \brief (DAC_INTFLAG) Result x Overrun */
-#define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos)
-#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos))
-#define DAC_INTFLAG_MASK _U_(0xFF) /**< \brief (DAC_INTFLAG) MASK Register */
-
-/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */
- uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */
- uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */
- uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */
- uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} DAC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */
-#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */
-
-#define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */
-#define DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos)
-#define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */
-#define DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos)
-#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */
-#define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos)
-#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos))
-#define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */
-#define DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos)
-#define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */
-#define DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos)
-#define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */
-#define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos)
-#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos))
-#define DAC_STATUS_MASK _U_(0x0F) /**< \brief (DAC_STATUS) MASK Register */
-
-/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */
- uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */
- uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */
- uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */
- uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */
- uint32_t :26; /*!< bit: 6..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */
- uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */
- uint32_t :26; /*!< bit: 6..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} DAC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */
-#define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */
-
-#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */
-#define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos)
-#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */
-#define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos)
-#define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */
-#define DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos)
-#define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */
-#define DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos)
-#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */
-#define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos)
-#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos))
-#define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */
-#define DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos)
-#define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */
-#define DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos)
-#define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */
-#define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos)
-#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos))
-#define DAC_SYNCBUSY_MASK _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */
-
-/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */
- uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */
- uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */
- uint16_t :1; /*!< bit: 4 Reserved */
- uint16_t FEXT:1; /*!< bit: 5 Standalone Filter */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */
- uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */
- uint16_t :1; /*!< bit: 12 Reserved */
- uint16_t OSR:3; /*!< bit: 13..15 Sampling Rate */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} DAC_DACCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */
-#define DAC_DACCTRL_RESETVALUE _U_(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */
-
-#define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */
-#define DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos)
-#define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */
-#define DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos)
-#define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */
-#define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos)
-#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos))
-#define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */
-#define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS) */
-#define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */
-#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos)
-#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos)
-#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos)
-#define DAC_DACCTRL_FEXT_Pos 5 /**< \brief (DAC_DACCTRL) Standalone Filter */
-#define DAC_DACCTRL_FEXT (_U_(0x1) << DAC_DACCTRL_FEXT_Pos)
-#define DAC_DACCTRL_RUNSTDBY_Pos 6 /**< \brief (DAC_DACCTRL) Run in Standby */
-#define DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos)
-#define DAC_DACCTRL_DITHER_Pos 7 /**< \brief (DAC_DACCTRL) Dithering Mode */
-#define DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos)
-#define DAC_DACCTRL_REFRESH_Pos 8 /**< \brief (DAC_DACCTRL) Refresh period */
-#define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos)
-#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos))
-#define DAC_DACCTRL_OSR_Pos 13 /**< \brief (DAC_DACCTRL) Sampling Rate */
-#define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos)
-#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos))
-#define DAC_DACCTRL_MASK _U_(0xEFEF) /**< \brief (DAC_DACCTRL) MASK Register */
-
-/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t DATA:16; /*!< bit: 0..15 DAC0 Data */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} DAC_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_DATA_OFFSET 0x10 /**< \brief (DAC_DATA offset) DAC n Data */
-#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */
-
-#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) DAC0 Data */
-#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos)
-#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
-#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */
-
-/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t DATABUF:16; /*!< bit: 0..15 DAC0 Data Buffer */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} DAC_DATABUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_DATABUF_OFFSET 0x14 /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */
-#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */
-
-#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) DAC0 Data Buffer */
-#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos)
-#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
-#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */
-
-/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DAC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_DBGCTRL_OFFSET 0x18 /**< \brief (DAC_DBGCTRL offset) Debug Control */
-#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */
-
-#define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */
-#define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos)
-#define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */
-
-/* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/ 16) Filter Result -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t RESULT:16; /*!< bit: 0..15 Filter Result */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} DAC_RESULT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_RESULT_OFFSET 0x1C /**< \brief (DAC_RESULT offset) Filter Result */
-#define DAC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (DAC_RESULT reset_value) Filter Result */
-
-#define DAC_RESULT_RESULT_Pos 0 /**< \brief (DAC_RESULT) Filter Result */
-#define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos)
-#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos))
-#define DAC_RESULT_MASK _U_(0xFFFF) /**< \brief (DAC_RESULT) MASK Register */
-
-/** \brief DAC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
- __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */
- __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */
- RoReg8 Reserved1[0x1];
- __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
- __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
- __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
- __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */
- __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
- __IO DAC_DACCTRL_Type DACCTRL[2]; /**< \brief Offset: 0x0C (R/W 16) DAC n Control */
- __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */
- __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */
- __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x18 (R/W 8) Debug Control */
- RoReg8 Reserved2[0x3];
- __I DAC_RESULT_Type RESULT[2]; /**< \brief Offset: 0x1C (R/ 16) Filter Result */
-} Dac;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_DAC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for DAC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_DAC_COMPONENT_
+#define _SAME54_DAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR DAC */
+/* ========================================================================== */
+/** \addtogroup SAME54_DAC Digital-to-Analog Converter */
+/*@{*/
+
+#define DAC_U2502
+#define REV_DAC 0x100
+
+/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */
+#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */
+
+#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */
+#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos)
+#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */
+#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos)
+#define DAC_CTRLA_MASK _U_(0x03) /**< \brief (DAC_CTRLA) MASK Register */
+
+/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */
+ uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */
+#define DAC_CTRLB_RESETVALUE _U_(0x02) /**< \brief (DAC_CTRLB reset_value) Control B */
+
+#define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */
+#define DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos)
+#define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */
+#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
+#define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */
+#define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< \brief (DAC_CTRLB) Analog supply */
+#define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference buffered */
+#define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */
+#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_MASK _U_(0x07) /**< \brief (DAC_CTRLB) MASK Register */
+
+/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */
+ uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */
+ uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */
+ uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */
+ uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */
+ uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */
+ uint8_t RESRDYEO0:1; /*!< bit: 6 Result Ready Event Output 0 */
+ uint8_t RESRDYEO1:1; /*!< bit: 7 Result Ready Event Output 1 */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */
+ uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */
+ uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */
+ uint8_t RESRDYEO:2; /*!< bit: 6.. 7 Result Ready Event Output x */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */
+#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */
+
+#define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */
+#define DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos)
+#define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */
+#define DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos)
+#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */
+#define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos)
+#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos))
+#define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */
+#define DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos)
+#define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */
+#define DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos)
+#define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */
+#define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos)
+#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos))
+#define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */
+#define DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos)
+#define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */
+#define DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos)
+#define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */
+#define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos)
+#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos))
+#define DAC_EVCTRL_RESRDYEO0_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output 0 */
+#define DAC_EVCTRL_RESRDYEO0 (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos)
+#define DAC_EVCTRL_RESRDYEO1_Pos 7 /**< \brief (DAC_EVCTRL) Result Ready Event Output 1 */
+#define DAC_EVCTRL_RESRDYEO1 (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos)
+#define DAC_EVCTRL_RESRDYEO_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output x */
+#define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos)
+#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos))
+#define DAC_EVCTRL_MASK _U_(0xFF) /**< \brief (DAC_EVCTRL) MASK Register */
+
+/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */
+ uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */
+ uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */
+ uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */
+ uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */
+ uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */
+ uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */
+ uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */
+ uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */
+ uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */
+ uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
+#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun 0 Interrupt Enable */
+#define DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos)
+#define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun 1 Interrupt Enable */
+#define DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos)
+#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun x Interrupt Enable */
+#define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos)
+#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos))
+#define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos)
+#define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos)
+#define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos)
+#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos))
+#define DAC_INTENCLR_RESRDY0_Pos 4 /**< \brief (DAC_INTENCLR) Result 0 Ready Interrupt Enable */
+#define DAC_INTENCLR_RESRDY0 (_U_(1) << DAC_INTENCLR_RESRDY0_Pos)
+#define DAC_INTENCLR_RESRDY1_Pos 5 /**< \brief (DAC_INTENCLR) Result 1 Ready Interrupt Enable */
+#define DAC_INTENCLR_RESRDY1 (_U_(1) << DAC_INTENCLR_RESRDY1_Pos)
+#define DAC_INTENCLR_RESRDY_Pos 4 /**< \brief (DAC_INTENCLR) Result x Ready Interrupt Enable */
+#define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos)
+#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos))
+#define DAC_INTENCLR_OVERRUN0_Pos 6 /**< \brief (DAC_INTENCLR) Overrun 0 Interrupt Enable */
+#define DAC_INTENCLR_OVERRUN0 (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos)
+#define DAC_INTENCLR_OVERRUN1_Pos 7 /**< \brief (DAC_INTENCLR) Overrun 1 Interrupt Enable */
+#define DAC_INTENCLR_OVERRUN1 (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos)
+#define DAC_INTENCLR_OVERRUN_Pos 6 /**< \brief (DAC_INTENCLR) Overrun x Interrupt Enable */
+#define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos)
+#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos))
+#define DAC_INTENCLR_MASK _U_(0xFF) /**< \brief (DAC_INTENCLR) MASK Register */
+
+/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */
+ uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */
+ uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */
+ uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */
+ uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */
+ uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */
+ uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */
+ uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */
+ uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */
+ uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */
+ uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
+#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
+
+#define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun 0 Interrupt Enable */
+#define DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos)
+#define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun 1 Interrupt Enable */
+#define DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos)
+#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun x Interrupt Enable */
+#define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos)
+#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos))
+#define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos)
+#define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos)
+#define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos)
+#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos))
+#define DAC_INTENSET_RESRDY0_Pos 4 /**< \brief (DAC_INTENSET) Result 0 Ready Interrupt Enable */
+#define DAC_INTENSET_RESRDY0 (_U_(1) << DAC_INTENSET_RESRDY0_Pos)
+#define DAC_INTENSET_RESRDY1_Pos 5 /**< \brief (DAC_INTENSET) Result 1 Ready Interrupt Enable */
+#define DAC_INTENSET_RESRDY1 (_U_(1) << DAC_INTENSET_RESRDY1_Pos)
+#define DAC_INTENSET_RESRDY_Pos 4 /**< \brief (DAC_INTENSET) Result x Ready Interrupt Enable */
+#define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos)
+#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos))
+#define DAC_INTENSET_OVERRUN0_Pos 6 /**< \brief (DAC_INTENSET) Overrun 0 Interrupt Enable */
+#define DAC_INTENSET_OVERRUN0 (_U_(1) << DAC_INTENSET_OVERRUN0_Pos)
+#define DAC_INTENSET_OVERRUN1_Pos 7 /**< \brief (DAC_INTENSET) Overrun 1 Interrupt Enable */
+#define DAC_INTENSET_OVERRUN1 (_U_(1) << DAC_INTENSET_OVERRUN1_Pos)
+#define DAC_INTENSET_OVERRUN_Pos 6 /**< \brief (DAC_INTENSET) Overrun x Interrupt Enable */
+#define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos)
+#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos))
+#define DAC_INTENSET_MASK _U_(0xFF) /**< \brief (DAC_INTENSET) MASK Register */
+
+/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t UNDERRUN0:1; /*!< bit: 0 Result 0 Underrun */
+ __I uint8_t UNDERRUN1:1; /*!< bit: 1 Result 1 Underrun */
+ __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */
+ __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */
+ __I uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready */
+ __I uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready */
+ __I uint8_t OVERRUN0:1; /*!< bit: 6 Result 0 Overrun */
+ __I uint8_t OVERRUN1:1; /*!< bit: 7 Result 1 Overrun */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Result x Underrun */
+ __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */
+ __I uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready */
+ __I uint8_t OVERRUN:2; /*!< bit: 6.. 7 Result x Overrun */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) Result 0 Underrun */
+#define DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos)
+#define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) Result 1 Underrun */
+#define DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos)
+#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Result x Underrun */
+#define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos)
+#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos))
+#define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */
+#define DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos)
+#define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */
+#define DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos)
+#define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */
+#define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos)
+#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos))
+#define DAC_INTFLAG_RESRDY0_Pos 4 /**< \brief (DAC_INTFLAG) Result 0 Ready */
+#define DAC_INTFLAG_RESRDY0 (_U_(1) << DAC_INTFLAG_RESRDY0_Pos)
+#define DAC_INTFLAG_RESRDY1_Pos 5 /**< \brief (DAC_INTFLAG) Result 1 Ready */
+#define DAC_INTFLAG_RESRDY1 (_U_(1) << DAC_INTFLAG_RESRDY1_Pos)
+#define DAC_INTFLAG_RESRDY_Pos 4 /**< \brief (DAC_INTFLAG) Result x Ready */
+#define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos)
+#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos))
+#define DAC_INTFLAG_OVERRUN0_Pos 6 /**< \brief (DAC_INTFLAG) Result 0 Overrun */
+#define DAC_INTFLAG_OVERRUN0 (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos)
+#define DAC_INTFLAG_OVERRUN1_Pos 7 /**< \brief (DAC_INTFLAG) Result 1 Overrun */
+#define DAC_INTFLAG_OVERRUN1 (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos)
+#define DAC_INTFLAG_OVERRUN_Pos 6 /**< \brief (DAC_INTFLAG) Result x Overrun */
+#define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos)
+#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos))
+#define DAC_INTFLAG_MASK _U_(0xFF) /**< \brief (DAC_INTFLAG) MASK Register */
+
+/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */
+ uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */
+ uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */
+ uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */
+ uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */
+#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */
+
+#define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */
+#define DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos)
+#define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */
+#define DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos)
+#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */
+#define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos)
+#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos))
+#define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */
+#define DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos)
+#define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */
+#define DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos)
+#define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */
+#define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos)
+#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos))
+#define DAC_STATUS_MASK _U_(0x0F) /**< \brief (DAC_STATUS) MASK Register */
+
+/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */
+ uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */
+ uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */
+ uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */
+ uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */
+ uint32_t :26; /*!< bit: 6..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */
+ uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */
+ uint32_t :26; /*!< bit: 6..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DAC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */
+#define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */
+#define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos)
+#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */
+#define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos)
+#define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */
+#define DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos)
+#define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */
+#define DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos)
+#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */
+#define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos)
+#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos))
+#define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */
+#define DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos)
+#define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */
+#define DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos)
+#define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */
+#define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos)
+#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos))
+#define DAC_SYNCBUSY_MASK _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */
+
+/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */
+ uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */
+ uint16_t :1; /*!< bit: 4 Reserved */
+ uint16_t FEXT:1; /*!< bit: 5 Standalone Filter */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */
+ uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */
+ uint16_t :1; /*!< bit: 12 Reserved */
+ uint16_t OSR:3; /*!< bit: 13..15 Sampling Rate */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DAC_DACCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */
+#define DAC_DACCTRL_RESETVALUE _U_(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */
+
+#define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */
+#define DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos)
+#define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */
+#define DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos)
+#define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */
+#define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos)
+#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos))
+#define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */
+#define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS) */
+#define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */
+#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos)
+#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos)
+#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos)
+#define DAC_DACCTRL_FEXT_Pos 5 /**< \brief (DAC_DACCTRL) Standalone Filter */
+#define DAC_DACCTRL_FEXT (_U_(0x1) << DAC_DACCTRL_FEXT_Pos)
+#define DAC_DACCTRL_RUNSTDBY_Pos 6 /**< \brief (DAC_DACCTRL) Run in Standby */
+#define DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos)
+#define DAC_DACCTRL_DITHER_Pos 7 /**< \brief (DAC_DACCTRL) Dithering Mode */
+#define DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos)
+#define DAC_DACCTRL_REFRESH_Pos 8 /**< \brief (DAC_DACCTRL) Refresh period */
+#define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos)
+#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos))
+#define DAC_DACCTRL_OSR_Pos 13 /**< \brief (DAC_DACCTRL) Sampling Rate */
+#define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos)
+#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos))
+#define DAC_DACCTRL_MASK _U_(0xEFEF) /**< \brief (DAC_DACCTRL) MASK Register */
+
+/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DATA:16; /*!< bit: 0..15 DAC0 Data */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DAC_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATA_OFFSET 0x10 /**< \brief (DAC_DATA offset) DAC n Data */
+#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */
+
+#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) DAC0 Data */
+#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos)
+#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
+#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */
+
+/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DATABUF:16; /*!< bit: 0..15 DAC0 Data Buffer */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DAC_DATABUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATABUF_OFFSET 0x14 /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */
+#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */
+
+#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) DAC0 Data Buffer */
+#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos)
+#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
+#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */
+
+/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DBGCTRL_OFFSET 0x18 /**< \brief (DAC_DBGCTRL offset) Debug Control */
+#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */
+
+#define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */
+#define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos)
+#define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */
+
+/* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/ 16) Filter Result -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RESULT:16; /*!< bit: 0..15 Filter Result */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DAC_RESULT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_RESULT_OFFSET 0x1C /**< \brief (DAC_RESULT offset) Filter Result */
+#define DAC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (DAC_RESULT reset_value) Filter Result */
+
+#define DAC_RESULT_RESULT_Pos 0 /**< \brief (DAC_RESULT) Filter Result */
+#define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos)
+#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos))
+#define DAC_RESULT_MASK _U_(0xFFFF) /**< \brief (DAC_RESULT) MASK Register */
+
+/** \brief DAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */
+ __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */
+ RoReg8 Reserved1[0x1];
+ __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
+ __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
+ __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
+ __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */
+ __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
+ __IO DAC_DACCTRL_Type DACCTRL[2]; /**< \brief Offset: 0x0C (R/W 16) DAC n Control */
+ __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */
+ __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */
+ __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x18 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x3];
+ __I DAC_RESULT_Type RESULT[2]; /**< \brief Offset: 0x1C (R/ 16) Filter Result */
+} Dac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_DAC_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/dmac.h b/sysmoOCTSIM/include/component/dmac.h
index f3f9f5b..a611b79 100644
--- a/sysmoOCTSIM/include/component/dmac.h
+++ b/sysmoOCTSIM/include/component/dmac.h
@@ -1,1416 +1,1416 @@
-/**
- * \file
- *
- * \brief Component description for DMAC
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_DMAC_COMPONENT_
-#define _SAME54_DMAC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR DMAC */
-/* ========================================================================== */
-/** \addtogroup SAME54_DMAC Direct Memory Access Controller */
-/*@{*/
-
-#define DMAC_U2503
-#define REV_DMAC 0x101
-
-/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
- uint16_t :6; /*!< bit: 2.. 7 Reserved */
- uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
- uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
- uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
- uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t :8; /*!< bit: 0.. 7 Reserved */
- uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} DMAC_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */
-#define DMAC_CTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */
-
-#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */
-#define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos)
-#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */
-#define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos)
-#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
-#define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos)
-#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
-#define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos)
-#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
-#define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos)
-#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
-#define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos)
-#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */
-#define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos)
-#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
-#define DMAC_CTRL_MASK _U_(0x0F03) /**< \brief (DMAC_CTRL) MASK Register */
-
-/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
- uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
- uint16_t :4; /*!< bit: 4.. 7 Reserved */
- uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
- uint16_t CRCMODE:2; /*!< bit: 14..15 CRC Operating Mode */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} DMAC_CRCCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */
-#define DMAC_CRCCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
-
-#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
-#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
-#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
-#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */
-#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */
-#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */
-#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
-#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
-#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
-#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
-#define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos)
-#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
-#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
-#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
-#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
-#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
-#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */
-#define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos)
-#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
-#define DMAC_CRCCTRL_CRCSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC Disabled */
-#define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */
-#define DMAC_CRCCTRL_CRCSRC_DISABLE (DMAC_CRCCTRL_CRCSRC_DISABLE_Val << DMAC_CRCCTRL_CRCSRC_Pos)
-#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos)
-#define DMAC_CRCCTRL_CRCMODE_Pos 14 /**< \brief (DMAC_CRCCTRL) CRC Operating Mode */
-#define DMAC_CRCCTRL_CRCMODE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCMODE_Pos)
-#define DMAC_CRCCTRL_CRCMODE(value) (DMAC_CRCCTRL_CRCMODE_Msk & ((value) << DMAC_CRCCTRL_CRCMODE_Pos))
-#define DMAC_CRCCTRL_CRCMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) Default operating mode */
-#define DMAC_CRCCTRL_CRCMODE_CRCMON_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) Memory CRC monitor operating mode */
-#define DMAC_CRCCTRL_CRCMODE_CRCGEN_Val _U_(0x3) /**< \brief (DMAC_CRCCTRL) Memory CRC generation operating mode */
-#define DMAC_CRCCTRL_CRCMODE_DEFAULT (DMAC_CRCCTRL_CRCMODE_DEFAULT_Val << DMAC_CRCCTRL_CRCMODE_Pos)
-#define DMAC_CRCCTRL_CRCMODE_CRCMON (DMAC_CRCCTRL_CRCMODE_CRCMON_Val << DMAC_CRCCTRL_CRCMODE_Pos)
-#define DMAC_CRCCTRL_CRCMODE_CRCGEN (DMAC_CRCCTRL_CRCMODE_CRCGEN_Val << DMAC_CRCCTRL_CRCMODE_Pos)
-#define DMAC_CRCCTRL_MASK _U_(0xFF0F) /**< \brief (DMAC_CRCCTRL) MASK Register */
-
-/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_CRCDATAIN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
-#define DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
-
-#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
-#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos)
-#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
-#define DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */
-
-/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_CRCCHKSUM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
-#define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
-
-#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
-#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
-#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
-#define DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */
-
-/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
- uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
- uint8_t CRCERR:1; /*!< bit: 2 CRC Error */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DMAC_CRCSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
-#define DMAC_CRCSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
-
-#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
-#define DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos)
-#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */
-#define DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos)
-#define DMAC_CRCSTATUS_CRCERR_Pos 2 /**< \brief (DMAC_CRCSTATUS) CRC Error */
-#define DMAC_CRCSTATUS_CRCERR (_U_(0x1) << DMAC_CRCSTATUS_CRCERR_Pos)
-#define DMAC_CRCSTATUS_MASK _U_(0x07) /**< \brief (DMAC_CRCSTATUS) MASK Register */
-
-/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DMAC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */
-#define DMAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
-
-#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */
-#define DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos)
-#define DMAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */
-
-/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
- uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
- uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
- uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
- uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
- uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
- uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
- uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
- uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
- uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
- uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
- uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
- uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */
- uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */
- uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */
- uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */
- uint32_t SWTRIG16:1; /*!< bit: 16 Channel 16 Software Trigger */
- uint32_t SWTRIG17:1; /*!< bit: 17 Channel 17 Software Trigger */
- uint32_t SWTRIG18:1; /*!< bit: 18 Channel 18 Software Trigger */
- uint32_t SWTRIG19:1; /*!< bit: 19 Channel 19 Software Trigger */
- uint32_t SWTRIG20:1; /*!< bit: 20 Channel 20 Software Trigger */
- uint32_t SWTRIG21:1; /*!< bit: 21 Channel 21 Software Trigger */
- uint32_t SWTRIG22:1; /*!< bit: 22 Channel 22 Software Trigger */
- uint32_t SWTRIG23:1; /*!< bit: 23 Channel 23 Software Trigger */
- uint32_t SWTRIG24:1; /*!< bit: 24 Channel 24 Software Trigger */
- uint32_t SWTRIG25:1; /*!< bit: 25 Channel 25 Software Trigger */
- uint32_t SWTRIG26:1; /*!< bit: 26 Channel 26 Software Trigger */
- uint32_t SWTRIG27:1; /*!< bit: 27 Channel 27 Software Trigger */
- uint32_t SWTRIG28:1; /*!< bit: 28 Channel 28 Software Trigger */
- uint32_t SWTRIG29:1; /*!< bit: 29 Channel 29 Software Trigger */
- uint32_t SWTRIG30:1; /*!< bit: 30 Channel 30 Software Trigger */
- uint32_t SWTRIG31:1; /*!< bit: 31 Channel 31 Software Trigger */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t SWTRIG:32; /*!< bit: 0..31 Channel x Software Trigger */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_SWTRIGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
-#define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
-
-#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12 /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG12 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG12_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13 /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG13 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG13_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14 /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG14 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG14_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15 /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG15 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG15_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG16_Pos 16 /**< \brief (DMAC_SWTRIGCTRL) Channel 16 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG16 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG16_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG17_Pos 17 /**< \brief (DMAC_SWTRIGCTRL) Channel 17 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG17 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG17_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG18_Pos 18 /**< \brief (DMAC_SWTRIGCTRL) Channel 18 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG18 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG18_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG19_Pos 19 /**< \brief (DMAC_SWTRIGCTRL) Channel 19 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG19 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG19_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG20_Pos 20 /**< \brief (DMAC_SWTRIGCTRL) Channel 20 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG20 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG20_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG21_Pos 21 /**< \brief (DMAC_SWTRIGCTRL) Channel 21 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG21 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG21_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG22_Pos 22 /**< \brief (DMAC_SWTRIGCTRL) Channel 22 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG22 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG22_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG23_Pos 23 /**< \brief (DMAC_SWTRIGCTRL) Channel 23 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG23 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG23_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG24_Pos 24 /**< \brief (DMAC_SWTRIGCTRL) Channel 24 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG24 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG24_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG25_Pos 25 /**< \brief (DMAC_SWTRIGCTRL) Channel 25 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG25 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG25_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG26_Pos 26 /**< \brief (DMAC_SWTRIGCTRL) Channel 26 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG26 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG26_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG27_Pos 27 /**< \brief (DMAC_SWTRIGCTRL) Channel 27 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG27 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG27_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG28_Pos 28 /**< \brief (DMAC_SWTRIGCTRL) Channel 28 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG28 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG28_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG29_Pos 29 /**< \brief (DMAC_SWTRIGCTRL) Channel 29 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG29 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG29_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG30_Pos 30 /**< \brief (DMAC_SWTRIGCTRL) Channel 30 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG30 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG30_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG31_Pos 31 /**< \brief (DMAC_SWTRIGCTRL) Channel 31 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG31 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG31_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFFFFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
-#define DMAC_SWTRIGCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
-
-/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t LVLPRI0:5; /*!< bit: 0.. 4 Level 0 Channel Priority Number */
- uint32_t QOS0:2; /*!< bit: 5.. 6 Level 0 Quality of Service */
- uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
- uint32_t LVLPRI1:5; /*!< bit: 8..12 Level 1 Channel Priority Number */
- uint32_t QOS1:2; /*!< bit: 13..14 Level 1 Quality of Service */
- uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
- uint32_t LVLPRI2:5; /*!< bit: 16..20 Level 2 Channel Priority Number */
- uint32_t QOS2:2; /*!< bit: 21..22 Level 2 Quality of Service */
- uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
- uint32_t LVLPRI3:5; /*!< bit: 24..28 Level 3 Channel Priority Number */
- uint32_t QOS3:2; /*!< bit: 29..30 Level 3 Quality of Service */
- uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_PRICTRL0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
-#define DMAC_PRICTRL0_RESETVALUE _U_(0x40404040) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
-
-#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI0_Pos)
-#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
-#define DMAC_PRICTRL0_QOS0_Pos 5 /**< \brief (DMAC_PRICTRL0) Level 0 Quality of Service */
-#define DMAC_PRICTRL0_QOS0_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS0_Pos)
-#define DMAC_PRICTRL0_QOS0(value) (DMAC_PRICTRL0_QOS0_Msk & ((value) << DMAC_PRICTRL0_QOS0_Pos))
-#define DMAC_PRICTRL0_QOS0_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
-#define DMAC_PRICTRL0_QOS0_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
-#define DMAC_PRICTRL0_QOS0_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
-#define DMAC_PRICTRL0_QOS0_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
-#define DMAC_PRICTRL0_QOS0_REGULAR (DMAC_PRICTRL0_QOS0_REGULAR_Val << DMAC_PRICTRL0_QOS0_Pos)
-#define DMAC_PRICTRL0_QOS0_SHORTAGE (DMAC_PRICTRL0_QOS0_SHORTAGE_Val << DMAC_PRICTRL0_QOS0_Pos)
-#define DMAC_PRICTRL0_QOS0_SENSITIVE (DMAC_PRICTRL0_QOS0_SENSITIVE_Val << DMAC_PRICTRL0_QOS0_Pos)
-#define DMAC_PRICTRL0_QOS0_CRITICAL (DMAC_PRICTRL0_QOS0_CRITICAL_Val << DMAC_PRICTRL0_QOS0_Pos)
-#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos)
-#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI1_Pos)
-#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
-#define DMAC_PRICTRL0_QOS1_Pos 13 /**< \brief (DMAC_PRICTRL0) Level 1 Quality of Service */
-#define DMAC_PRICTRL0_QOS1_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS1_Pos)
-#define DMAC_PRICTRL0_QOS1(value) (DMAC_PRICTRL0_QOS1_Msk & ((value) << DMAC_PRICTRL0_QOS1_Pos))
-#define DMAC_PRICTRL0_QOS1_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
-#define DMAC_PRICTRL0_QOS1_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
-#define DMAC_PRICTRL0_QOS1_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
-#define DMAC_PRICTRL0_QOS1_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
-#define DMAC_PRICTRL0_QOS1_REGULAR (DMAC_PRICTRL0_QOS1_REGULAR_Val << DMAC_PRICTRL0_QOS1_Pos)
-#define DMAC_PRICTRL0_QOS1_SHORTAGE (DMAC_PRICTRL0_QOS1_SHORTAGE_Val << DMAC_PRICTRL0_QOS1_Pos)
-#define DMAC_PRICTRL0_QOS1_SENSITIVE (DMAC_PRICTRL0_QOS1_SENSITIVE_Val << DMAC_PRICTRL0_QOS1_Pos)
-#define DMAC_PRICTRL0_QOS1_CRITICAL (DMAC_PRICTRL0_QOS1_CRITICAL_Val << DMAC_PRICTRL0_QOS1_Pos)
-#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos)
-#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI2_Pos)
-#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
-#define DMAC_PRICTRL0_QOS2_Pos 21 /**< \brief (DMAC_PRICTRL0) Level 2 Quality of Service */
-#define DMAC_PRICTRL0_QOS2_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS2_Pos)
-#define DMAC_PRICTRL0_QOS2(value) (DMAC_PRICTRL0_QOS2_Msk & ((value) << DMAC_PRICTRL0_QOS2_Pos))
-#define DMAC_PRICTRL0_QOS2_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
-#define DMAC_PRICTRL0_QOS2_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
-#define DMAC_PRICTRL0_QOS2_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
-#define DMAC_PRICTRL0_QOS2_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
-#define DMAC_PRICTRL0_QOS2_REGULAR (DMAC_PRICTRL0_QOS2_REGULAR_Val << DMAC_PRICTRL0_QOS2_Pos)
-#define DMAC_PRICTRL0_QOS2_SHORTAGE (DMAC_PRICTRL0_QOS2_SHORTAGE_Val << DMAC_PRICTRL0_QOS2_Pos)
-#define DMAC_PRICTRL0_QOS2_SENSITIVE (DMAC_PRICTRL0_QOS2_SENSITIVE_Val << DMAC_PRICTRL0_QOS2_Pos)
-#define DMAC_PRICTRL0_QOS2_CRITICAL (DMAC_PRICTRL0_QOS2_CRITICAL_Val << DMAC_PRICTRL0_QOS2_Pos)
-#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos)
-#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI3_Pos)
-#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
-#define DMAC_PRICTRL0_QOS3_Pos 29 /**< \brief (DMAC_PRICTRL0) Level 3 Quality of Service */
-#define DMAC_PRICTRL0_QOS3_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS3_Pos)
-#define DMAC_PRICTRL0_QOS3(value) (DMAC_PRICTRL0_QOS3_Msk & ((value) << DMAC_PRICTRL0_QOS3_Pos))
-#define DMAC_PRICTRL0_QOS3_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
-#define DMAC_PRICTRL0_QOS3_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
-#define DMAC_PRICTRL0_QOS3_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
-#define DMAC_PRICTRL0_QOS3_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
-#define DMAC_PRICTRL0_QOS3_REGULAR (DMAC_PRICTRL0_QOS3_REGULAR_Val << DMAC_PRICTRL0_QOS3_Pos)
-#define DMAC_PRICTRL0_QOS3_SHORTAGE (DMAC_PRICTRL0_QOS3_SHORTAGE_Val << DMAC_PRICTRL0_QOS3_Pos)
-#define DMAC_PRICTRL0_QOS3_SENSITIVE (DMAC_PRICTRL0_QOS3_SENSITIVE_Val << DMAC_PRICTRL0_QOS3_Pos)
-#define DMAC_PRICTRL0_QOS3_CRITICAL (DMAC_PRICTRL0_QOS3_CRITICAL_Val << DMAC_PRICTRL0_QOS3_Pos)
-#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos)
-#define DMAC_PRICTRL0_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PRICTRL0) MASK Register */
-
-/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t ID:5; /*!< bit: 0.. 4 Channel ID */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t TERR:1; /*!< bit: 8 Transfer Error */
- uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
- uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
- uint16_t :1; /*!< bit: 11 Reserved */
- uint16_t CRCERR:1; /*!< bit: 12 CRC Error */
- uint16_t FERR:1; /*!< bit: 13 Fetch Error */
- uint16_t BUSY:1; /*!< bit: 14 Busy */
- uint16_t PEND:1; /*!< bit: 15 Pending */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} DMAC_INTPEND_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
-#define DMAC_INTPEND_RESETVALUE _U_(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
-
-#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */
-#define DMAC_INTPEND_ID_Msk (_U_(0x1F) << DMAC_INTPEND_ID_Pos)
-#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
-#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */
-#define DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos)
-#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */
-#define DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos)
-#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */
-#define DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos)
-#define DMAC_INTPEND_CRCERR_Pos 12 /**< \brief (DMAC_INTPEND) CRC Error */
-#define DMAC_INTPEND_CRCERR (_U_(0x1) << DMAC_INTPEND_CRCERR_Pos)
-#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */
-#define DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos)
-#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */
-#define DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos)
-#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */
-#define DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos)
-#define DMAC_INTPEND_MASK _U_(0xF71F) /**< \brief (DMAC_INTPEND) MASK Register */
-
-/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
- uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
- uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
- uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
- uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
- uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
- uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
- uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
- uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
- uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
- uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
- uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
- uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */
- uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */
- uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */
- uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */
- uint32_t CHINT16:1; /*!< bit: 16 Channel 16 Pending Interrupt */
- uint32_t CHINT17:1; /*!< bit: 17 Channel 17 Pending Interrupt */
- uint32_t CHINT18:1; /*!< bit: 18 Channel 18 Pending Interrupt */
- uint32_t CHINT19:1; /*!< bit: 19 Channel 19 Pending Interrupt */
- uint32_t CHINT20:1; /*!< bit: 20 Channel 20 Pending Interrupt */
- uint32_t CHINT21:1; /*!< bit: 21 Channel 21 Pending Interrupt */
- uint32_t CHINT22:1; /*!< bit: 22 Channel 22 Pending Interrupt */
- uint32_t CHINT23:1; /*!< bit: 23 Channel 23 Pending Interrupt */
- uint32_t CHINT24:1; /*!< bit: 24 Channel 24 Pending Interrupt */
- uint32_t CHINT25:1; /*!< bit: 25 Channel 25 Pending Interrupt */
- uint32_t CHINT26:1; /*!< bit: 26 Channel 26 Pending Interrupt */
- uint32_t CHINT27:1; /*!< bit: 27 Channel 27 Pending Interrupt */
- uint32_t CHINT28:1; /*!< bit: 28 Channel 28 Pending Interrupt */
- uint32_t CHINT29:1; /*!< bit: 29 Channel 29 Pending Interrupt */
- uint32_t CHINT30:1; /*!< bit: 30 Channel 30 Pending Interrupt */
- uint32_t CHINT31:1; /*!< bit: 31 Channel 31 Pending Interrupt */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t CHINT:32; /*!< bit: 0..31 Channel x Pending Interrupt */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_INTSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
-#define DMAC_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
-
-#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos)
-#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos)
-#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos)
-#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos)
-#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos)
-#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos)
-#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos)
-#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos)
-#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos)
-#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos)
-#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos)
-#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos)
-#define DMAC_INTSTATUS_CHINT12_Pos 12 /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT12 (_U_(1) << DMAC_INTSTATUS_CHINT12_Pos)
-#define DMAC_INTSTATUS_CHINT13_Pos 13 /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT13 (_U_(1) << DMAC_INTSTATUS_CHINT13_Pos)
-#define DMAC_INTSTATUS_CHINT14_Pos 14 /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT14 (_U_(1) << DMAC_INTSTATUS_CHINT14_Pos)
-#define DMAC_INTSTATUS_CHINT15_Pos 15 /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT15 (_U_(1) << DMAC_INTSTATUS_CHINT15_Pos)
-#define DMAC_INTSTATUS_CHINT16_Pos 16 /**< \brief (DMAC_INTSTATUS) Channel 16 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT16 (_U_(1) << DMAC_INTSTATUS_CHINT16_Pos)
-#define DMAC_INTSTATUS_CHINT17_Pos 17 /**< \brief (DMAC_INTSTATUS) Channel 17 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT17 (_U_(1) << DMAC_INTSTATUS_CHINT17_Pos)
-#define DMAC_INTSTATUS_CHINT18_Pos 18 /**< \brief (DMAC_INTSTATUS) Channel 18 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT18 (_U_(1) << DMAC_INTSTATUS_CHINT18_Pos)
-#define DMAC_INTSTATUS_CHINT19_Pos 19 /**< \brief (DMAC_INTSTATUS) Channel 19 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT19 (_U_(1) << DMAC_INTSTATUS_CHINT19_Pos)
-#define DMAC_INTSTATUS_CHINT20_Pos 20 /**< \brief (DMAC_INTSTATUS) Channel 20 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT20 (_U_(1) << DMAC_INTSTATUS_CHINT20_Pos)
-#define DMAC_INTSTATUS_CHINT21_Pos 21 /**< \brief (DMAC_INTSTATUS) Channel 21 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT21 (_U_(1) << DMAC_INTSTATUS_CHINT21_Pos)
-#define DMAC_INTSTATUS_CHINT22_Pos 22 /**< \brief (DMAC_INTSTATUS) Channel 22 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT22 (_U_(1) << DMAC_INTSTATUS_CHINT22_Pos)
-#define DMAC_INTSTATUS_CHINT23_Pos 23 /**< \brief (DMAC_INTSTATUS) Channel 23 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT23 (_U_(1) << DMAC_INTSTATUS_CHINT23_Pos)
-#define DMAC_INTSTATUS_CHINT24_Pos 24 /**< \brief (DMAC_INTSTATUS) Channel 24 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT24 (_U_(1) << DMAC_INTSTATUS_CHINT24_Pos)
-#define DMAC_INTSTATUS_CHINT25_Pos 25 /**< \brief (DMAC_INTSTATUS) Channel 25 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT25 (_U_(1) << DMAC_INTSTATUS_CHINT25_Pos)
-#define DMAC_INTSTATUS_CHINT26_Pos 26 /**< \brief (DMAC_INTSTATUS) Channel 26 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT26 (_U_(1) << DMAC_INTSTATUS_CHINT26_Pos)
-#define DMAC_INTSTATUS_CHINT27_Pos 27 /**< \brief (DMAC_INTSTATUS) Channel 27 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT27 (_U_(1) << DMAC_INTSTATUS_CHINT27_Pos)
-#define DMAC_INTSTATUS_CHINT28_Pos 28 /**< \brief (DMAC_INTSTATUS) Channel 28 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT28 (_U_(1) << DMAC_INTSTATUS_CHINT28_Pos)
-#define DMAC_INTSTATUS_CHINT29_Pos 29 /**< \brief (DMAC_INTSTATUS) Channel 29 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT29 (_U_(1) << DMAC_INTSTATUS_CHINT29_Pos)
-#define DMAC_INTSTATUS_CHINT30_Pos 30 /**< \brief (DMAC_INTSTATUS) Channel 30 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT30 (_U_(1) << DMAC_INTSTATUS_CHINT30_Pos)
-#define DMAC_INTSTATUS_CHINT31_Pos 31 /**< \brief (DMAC_INTSTATUS) Channel 31 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT31 (_U_(1) << DMAC_INTSTATUS_CHINT31_Pos)
-#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFFFFFFF) << DMAC_INTSTATUS_CHINT_Pos)
-#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
-#define DMAC_INTSTATUS_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */
-
-/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
- uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
- uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
- uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
- uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
- uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
- uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
- uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
- uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
- uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
- uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
- uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
- uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */
- uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */
- uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */
- uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */
- uint32_t BUSYCH16:1; /*!< bit: 16 Busy Channel 16 */
- uint32_t BUSYCH17:1; /*!< bit: 17 Busy Channel 17 */
- uint32_t BUSYCH18:1; /*!< bit: 18 Busy Channel 18 */
- uint32_t BUSYCH19:1; /*!< bit: 19 Busy Channel 19 */
- uint32_t BUSYCH20:1; /*!< bit: 20 Busy Channel 20 */
- uint32_t BUSYCH21:1; /*!< bit: 21 Busy Channel 21 */
- uint32_t BUSYCH22:1; /*!< bit: 22 Busy Channel 22 */
- uint32_t BUSYCH23:1; /*!< bit: 23 Busy Channel 23 */
- uint32_t BUSYCH24:1; /*!< bit: 24 Busy Channel 24 */
- uint32_t BUSYCH25:1; /*!< bit: 25 Busy Channel 25 */
- uint32_t BUSYCH26:1; /*!< bit: 26 Busy Channel 26 */
- uint32_t BUSYCH27:1; /*!< bit: 27 Busy Channel 27 */
- uint32_t BUSYCH28:1; /*!< bit: 28 Busy Channel 28 */
- uint32_t BUSYCH29:1; /*!< bit: 29 Busy Channel 29 */
- uint32_t BUSYCH30:1; /*!< bit: 30 Busy Channel 30 */
- uint32_t BUSYCH31:1; /*!< bit: 31 Busy Channel 31 */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t BUSYCH:32; /*!< bit: 0..31 Busy Channel x */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_BUSYCH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */
-#define DMAC_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
-
-#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
-#define DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos)
-#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
-#define DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos)
-#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
-#define DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos)
-#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
-#define DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos)
-#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
-#define DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos)
-#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
-#define DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos)
-#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
-#define DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos)
-#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
-#define DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos)
-#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
-#define DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos)
-#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
-#define DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos)
-#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
-#define DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos)
-#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
-#define DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos)
-#define DMAC_BUSYCH_BUSYCH12_Pos 12 /**< \brief (DMAC_BUSYCH) Busy Channel 12 */
-#define DMAC_BUSYCH_BUSYCH12 (_U_(1) << DMAC_BUSYCH_BUSYCH12_Pos)
-#define DMAC_BUSYCH_BUSYCH13_Pos 13 /**< \brief (DMAC_BUSYCH) Busy Channel 13 */
-#define DMAC_BUSYCH_BUSYCH13 (_U_(1) << DMAC_BUSYCH_BUSYCH13_Pos)
-#define DMAC_BUSYCH_BUSYCH14_Pos 14 /**< \brief (DMAC_BUSYCH) Busy Channel 14 */
-#define DMAC_BUSYCH_BUSYCH14 (_U_(1) << DMAC_BUSYCH_BUSYCH14_Pos)
-#define DMAC_BUSYCH_BUSYCH15_Pos 15 /**< \brief (DMAC_BUSYCH) Busy Channel 15 */
-#define DMAC_BUSYCH_BUSYCH15 (_U_(1) << DMAC_BUSYCH_BUSYCH15_Pos)
-#define DMAC_BUSYCH_BUSYCH16_Pos 16 /**< \brief (DMAC_BUSYCH) Busy Channel 16 */
-#define DMAC_BUSYCH_BUSYCH16 (_U_(1) << DMAC_BUSYCH_BUSYCH16_Pos)
-#define DMAC_BUSYCH_BUSYCH17_Pos 17 /**< \brief (DMAC_BUSYCH) Busy Channel 17 */
-#define DMAC_BUSYCH_BUSYCH17 (_U_(1) << DMAC_BUSYCH_BUSYCH17_Pos)
-#define DMAC_BUSYCH_BUSYCH18_Pos 18 /**< \brief (DMAC_BUSYCH) Busy Channel 18 */
-#define DMAC_BUSYCH_BUSYCH18 (_U_(1) << DMAC_BUSYCH_BUSYCH18_Pos)
-#define DMAC_BUSYCH_BUSYCH19_Pos 19 /**< \brief (DMAC_BUSYCH) Busy Channel 19 */
-#define DMAC_BUSYCH_BUSYCH19 (_U_(1) << DMAC_BUSYCH_BUSYCH19_Pos)
-#define DMAC_BUSYCH_BUSYCH20_Pos 20 /**< \brief (DMAC_BUSYCH) Busy Channel 20 */
-#define DMAC_BUSYCH_BUSYCH20 (_U_(1) << DMAC_BUSYCH_BUSYCH20_Pos)
-#define DMAC_BUSYCH_BUSYCH21_Pos 21 /**< \brief (DMAC_BUSYCH) Busy Channel 21 */
-#define DMAC_BUSYCH_BUSYCH21 (_U_(1) << DMAC_BUSYCH_BUSYCH21_Pos)
-#define DMAC_BUSYCH_BUSYCH22_Pos 22 /**< \brief (DMAC_BUSYCH) Busy Channel 22 */
-#define DMAC_BUSYCH_BUSYCH22 (_U_(1) << DMAC_BUSYCH_BUSYCH22_Pos)
-#define DMAC_BUSYCH_BUSYCH23_Pos 23 /**< \brief (DMAC_BUSYCH) Busy Channel 23 */
-#define DMAC_BUSYCH_BUSYCH23 (_U_(1) << DMAC_BUSYCH_BUSYCH23_Pos)
-#define DMAC_BUSYCH_BUSYCH24_Pos 24 /**< \brief (DMAC_BUSYCH) Busy Channel 24 */
-#define DMAC_BUSYCH_BUSYCH24 (_U_(1) << DMAC_BUSYCH_BUSYCH24_Pos)
-#define DMAC_BUSYCH_BUSYCH25_Pos 25 /**< \brief (DMAC_BUSYCH) Busy Channel 25 */
-#define DMAC_BUSYCH_BUSYCH25 (_U_(1) << DMAC_BUSYCH_BUSYCH25_Pos)
-#define DMAC_BUSYCH_BUSYCH26_Pos 26 /**< \brief (DMAC_BUSYCH) Busy Channel 26 */
-#define DMAC_BUSYCH_BUSYCH26 (_U_(1) << DMAC_BUSYCH_BUSYCH26_Pos)
-#define DMAC_BUSYCH_BUSYCH27_Pos 27 /**< \brief (DMAC_BUSYCH) Busy Channel 27 */
-#define DMAC_BUSYCH_BUSYCH27 (_U_(1) << DMAC_BUSYCH_BUSYCH27_Pos)
-#define DMAC_BUSYCH_BUSYCH28_Pos 28 /**< \brief (DMAC_BUSYCH) Busy Channel 28 */
-#define DMAC_BUSYCH_BUSYCH28 (_U_(1) << DMAC_BUSYCH_BUSYCH28_Pos)
-#define DMAC_BUSYCH_BUSYCH29_Pos 29 /**< \brief (DMAC_BUSYCH) Busy Channel 29 */
-#define DMAC_BUSYCH_BUSYCH29 (_U_(1) << DMAC_BUSYCH_BUSYCH29_Pos)
-#define DMAC_BUSYCH_BUSYCH30_Pos 30 /**< \brief (DMAC_BUSYCH) Busy Channel 30 */
-#define DMAC_BUSYCH_BUSYCH30 (_U_(1) << DMAC_BUSYCH_BUSYCH30_Pos)
-#define DMAC_BUSYCH_BUSYCH31_Pos 31 /**< \brief (DMAC_BUSYCH) Busy Channel 31 */
-#define DMAC_BUSYCH_BUSYCH31 (_U_(1) << DMAC_BUSYCH_BUSYCH31_Pos)
-#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */
-#define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFFFFFFF) << DMAC_BUSYCH_BUSYCH_Pos)
-#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
-#define DMAC_BUSYCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BUSYCH) MASK Register */
-
-/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
- uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
- uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
- uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
- uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
- uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
- uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
- uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
- uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
- uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
- uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
- uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
- uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */
- uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */
- uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */
- uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */
- uint32_t PENDCH16:1; /*!< bit: 16 Pending Channel 16 */
- uint32_t PENDCH17:1; /*!< bit: 17 Pending Channel 17 */
- uint32_t PENDCH18:1; /*!< bit: 18 Pending Channel 18 */
- uint32_t PENDCH19:1; /*!< bit: 19 Pending Channel 19 */
- uint32_t PENDCH20:1; /*!< bit: 20 Pending Channel 20 */
- uint32_t PENDCH21:1; /*!< bit: 21 Pending Channel 21 */
- uint32_t PENDCH22:1; /*!< bit: 22 Pending Channel 22 */
- uint32_t PENDCH23:1; /*!< bit: 23 Pending Channel 23 */
- uint32_t PENDCH24:1; /*!< bit: 24 Pending Channel 24 */
- uint32_t PENDCH25:1; /*!< bit: 25 Pending Channel 25 */
- uint32_t PENDCH26:1; /*!< bit: 26 Pending Channel 26 */
- uint32_t PENDCH27:1; /*!< bit: 27 Pending Channel 27 */
- uint32_t PENDCH28:1; /*!< bit: 28 Pending Channel 28 */
- uint32_t PENDCH29:1; /*!< bit: 29 Pending Channel 29 */
- uint32_t PENDCH30:1; /*!< bit: 30 Pending Channel 30 */
- uint32_t PENDCH31:1; /*!< bit: 31 Pending Channel 31 */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t PENDCH:32; /*!< bit: 0..31 Pending Channel x */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_PENDCH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */
-#define DMAC_PENDCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
-
-#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */
-#define DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos)
-#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */
-#define DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos)
-#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */
-#define DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos)
-#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */
-#define DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos)
-#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */
-#define DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos)
-#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */
-#define DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos)
-#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */
-#define DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos)
-#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */
-#define DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos)
-#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */
-#define DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos)
-#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */
-#define DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos)
-#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */
-#define DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos)
-#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */
-#define DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos)
-#define DMAC_PENDCH_PENDCH12_Pos 12 /**< \brief (DMAC_PENDCH) Pending Channel 12 */
-#define DMAC_PENDCH_PENDCH12 (_U_(1) << DMAC_PENDCH_PENDCH12_Pos)
-#define DMAC_PENDCH_PENDCH13_Pos 13 /**< \brief (DMAC_PENDCH) Pending Channel 13 */
-#define DMAC_PENDCH_PENDCH13 (_U_(1) << DMAC_PENDCH_PENDCH13_Pos)
-#define DMAC_PENDCH_PENDCH14_Pos 14 /**< \brief (DMAC_PENDCH) Pending Channel 14 */
-#define DMAC_PENDCH_PENDCH14 (_U_(1) << DMAC_PENDCH_PENDCH14_Pos)
-#define DMAC_PENDCH_PENDCH15_Pos 15 /**< \brief (DMAC_PENDCH) Pending Channel 15 */
-#define DMAC_PENDCH_PENDCH15 (_U_(1) << DMAC_PENDCH_PENDCH15_Pos)
-#define DMAC_PENDCH_PENDCH16_Pos 16 /**< \brief (DMAC_PENDCH) Pending Channel 16 */
-#define DMAC_PENDCH_PENDCH16 (_U_(1) << DMAC_PENDCH_PENDCH16_Pos)
-#define DMAC_PENDCH_PENDCH17_Pos 17 /**< \brief (DMAC_PENDCH) Pending Channel 17 */
-#define DMAC_PENDCH_PENDCH17 (_U_(1) << DMAC_PENDCH_PENDCH17_Pos)
-#define DMAC_PENDCH_PENDCH18_Pos 18 /**< \brief (DMAC_PENDCH) Pending Channel 18 */
-#define DMAC_PENDCH_PENDCH18 (_U_(1) << DMAC_PENDCH_PENDCH18_Pos)
-#define DMAC_PENDCH_PENDCH19_Pos 19 /**< \brief (DMAC_PENDCH) Pending Channel 19 */
-#define DMAC_PENDCH_PENDCH19 (_U_(1) << DMAC_PENDCH_PENDCH19_Pos)
-#define DMAC_PENDCH_PENDCH20_Pos 20 /**< \brief (DMAC_PENDCH) Pending Channel 20 */
-#define DMAC_PENDCH_PENDCH20 (_U_(1) << DMAC_PENDCH_PENDCH20_Pos)
-#define DMAC_PENDCH_PENDCH21_Pos 21 /**< \brief (DMAC_PENDCH) Pending Channel 21 */
-#define DMAC_PENDCH_PENDCH21 (_U_(1) << DMAC_PENDCH_PENDCH21_Pos)
-#define DMAC_PENDCH_PENDCH22_Pos 22 /**< \brief (DMAC_PENDCH) Pending Channel 22 */
-#define DMAC_PENDCH_PENDCH22 (_U_(1) << DMAC_PENDCH_PENDCH22_Pos)
-#define DMAC_PENDCH_PENDCH23_Pos 23 /**< \brief (DMAC_PENDCH) Pending Channel 23 */
-#define DMAC_PENDCH_PENDCH23 (_U_(1) << DMAC_PENDCH_PENDCH23_Pos)
-#define DMAC_PENDCH_PENDCH24_Pos 24 /**< \brief (DMAC_PENDCH) Pending Channel 24 */
-#define DMAC_PENDCH_PENDCH24 (_U_(1) << DMAC_PENDCH_PENDCH24_Pos)
-#define DMAC_PENDCH_PENDCH25_Pos 25 /**< \brief (DMAC_PENDCH) Pending Channel 25 */
-#define DMAC_PENDCH_PENDCH25 (_U_(1) << DMAC_PENDCH_PENDCH25_Pos)
-#define DMAC_PENDCH_PENDCH26_Pos 26 /**< \brief (DMAC_PENDCH) Pending Channel 26 */
-#define DMAC_PENDCH_PENDCH26 (_U_(1) << DMAC_PENDCH_PENDCH26_Pos)
-#define DMAC_PENDCH_PENDCH27_Pos 27 /**< \brief (DMAC_PENDCH) Pending Channel 27 */
-#define DMAC_PENDCH_PENDCH27 (_U_(1) << DMAC_PENDCH_PENDCH27_Pos)
-#define DMAC_PENDCH_PENDCH28_Pos 28 /**< \brief (DMAC_PENDCH) Pending Channel 28 */
-#define DMAC_PENDCH_PENDCH28 (_U_(1) << DMAC_PENDCH_PENDCH28_Pos)
-#define DMAC_PENDCH_PENDCH29_Pos 29 /**< \brief (DMAC_PENDCH) Pending Channel 29 */
-#define DMAC_PENDCH_PENDCH29 (_U_(1) << DMAC_PENDCH_PENDCH29_Pos)
-#define DMAC_PENDCH_PENDCH30_Pos 30 /**< \brief (DMAC_PENDCH) Pending Channel 30 */
-#define DMAC_PENDCH_PENDCH30 (_U_(1) << DMAC_PENDCH_PENDCH30_Pos)
-#define DMAC_PENDCH_PENDCH31_Pos 31 /**< \brief (DMAC_PENDCH) Pending Channel 31 */
-#define DMAC_PENDCH_PENDCH31 (_U_(1) << DMAC_PENDCH_PENDCH31_Pos)
-#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */
-#define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFFFFFFF) << DMAC_PENDCH_PENDCH_Pos)
-#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
-#define DMAC_PENDCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PENDCH) MASK Register */
-
-/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
- uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
- uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
- uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
- uint32_t :2; /*!< bit: 13..14 Reserved */
- uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
- uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
- uint32_t :28; /*!< bit: 4..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_ACTIVE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
-#define DMAC_ACTIVE_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
-
-#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos)
-#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos)
-#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos)
-#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos)
-#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos)
-#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
-#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */
-#define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos)
-#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
-#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */
-#define DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos)
-#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
-#define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos)
-#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
-#define DMAC_ACTIVE_MASK _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */
-
-/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_BASEADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
-#define DMAC_BASEADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
-
-#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
-#define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos)
-#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
-#define DMAC_BASEADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */
-
-/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_WRBADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
-#define DMAC_WRBADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
-
-#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
-#define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos)
-#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
-#define DMAC_WRBADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */
-
-/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 32) CHANNEL Channel n Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Channel Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Channel Enable */
- uint32_t :4; /*!< bit: 2.. 5 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Channel Run in Standby */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t TRIGSRC:7; /*!< bit: 8..14 Trigger Source */
- uint32_t :5; /*!< bit: 15..19 Reserved */
- uint32_t TRIGACT:2; /*!< bit: 20..21 Trigger Action */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t BURSTLEN:4; /*!< bit: 24..27 Burst Length */
- uint32_t THRESHOLD:2; /*!< bit: 28..29 FIFO Threshold */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_CHCTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel n Control A */
-#define DMAC_CHCTRLA_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CHCTRLA reset_value) Channel n Control A */
-
-#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
-#define DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos)
-#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */
-#define DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos)
-#define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel Run in Standby */
-#define DMAC_CHCTRLA_RUNSTDBY (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos)
-#define DMAC_CHCTRLA_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLA) Trigger Source */
-#define DMAC_CHCTRLA_TRIGSRC_Msk (_U_(0x7F) << DMAC_CHCTRLA_TRIGSRC_Pos)
-#define DMAC_CHCTRLA_TRIGSRC(value) (DMAC_CHCTRLA_TRIGSRC_Msk & ((value) << DMAC_CHCTRLA_TRIGSRC_Pos))
-#define DMAC_CHCTRLA_TRIGSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Only software/event triggers */
-#define DMAC_CHCTRLA_TRIGSRC_DISABLE (DMAC_CHCTRLA_TRIGSRC_DISABLE_Val << DMAC_CHCTRLA_TRIGSRC_Pos)
-#define DMAC_CHCTRLA_TRIGACT_Pos 20 /**< \brief (DMAC_CHCTRLA) Trigger Action */
-#define DMAC_CHCTRLA_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLA_TRIGACT_Pos)
-#define DMAC_CHCTRLA_TRIGACT(value) (DMAC_CHCTRLA_TRIGACT_Msk & ((value) << DMAC_CHCTRLA_TRIGACT_Pos))
-#define DMAC_CHCTRLA_TRIGACT_BLOCK_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) One trigger required for each block transfer */
-#define DMAC_CHCTRLA_TRIGACT_BURST_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) One trigger required for each burst transfer */
-#define DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) One trigger required for each transaction */
-#define DMAC_CHCTRLA_TRIGACT_BLOCK (DMAC_CHCTRLA_TRIGACT_BLOCK_Val << DMAC_CHCTRLA_TRIGACT_Pos)
-#define DMAC_CHCTRLA_TRIGACT_BURST (DMAC_CHCTRLA_TRIGACT_BURST_Val << DMAC_CHCTRLA_TRIGACT_Pos)
-#define DMAC_CHCTRLA_TRIGACT_TRANSACTION (DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLA_TRIGACT_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_Pos 24 /**< \brief (DMAC_CHCTRLA) Burst Length */
-#define DMAC_CHCTRLA_BURSTLEN_Msk (_U_(0xF) << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN(value) (DMAC_CHCTRLA_BURSTLEN_Msk & ((value) << DMAC_CHCTRLA_BURSTLEN_Pos))
-#define DMAC_CHCTRLA_BURSTLEN_SINGLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Single-beat burst length */
-#define DMAC_CHCTRLA_BURSTLEN_2BEAT_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) 2-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_3BEAT_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) 3-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_4BEAT_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) 4-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_5BEAT_Val _U_(0x4) /**< \brief (DMAC_CHCTRLA) 5-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_6BEAT_Val _U_(0x5) /**< \brief (DMAC_CHCTRLA) 6-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_7BEAT_Val _U_(0x6) /**< \brief (DMAC_CHCTRLA) 7-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_8BEAT_Val _U_(0x7) /**< \brief (DMAC_CHCTRLA) 8-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_9BEAT_Val _U_(0x8) /**< \brief (DMAC_CHCTRLA) 9-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_10BEAT_Val _U_(0x9) /**< \brief (DMAC_CHCTRLA) 10-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_11BEAT_Val _U_(0xA) /**< \brief (DMAC_CHCTRLA) 11-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_12BEAT_Val _U_(0xB) /**< \brief (DMAC_CHCTRLA) 12-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_13BEAT_Val _U_(0xC) /**< \brief (DMAC_CHCTRLA) 13-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_14BEAT_Val _U_(0xD) /**< \brief (DMAC_CHCTRLA) 14-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_15BEAT_Val _U_(0xE) /**< \brief (DMAC_CHCTRLA) 15-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_16BEAT_Val _U_(0xF) /**< \brief (DMAC_CHCTRLA) 16-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_SINGLE (DMAC_CHCTRLA_BURSTLEN_SINGLE_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_2BEAT (DMAC_CHCTRLA_BURSTLEN_2BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_3BEAT (DMAC_CHCTRLA_BURSTLEN_3BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_4BEAT (DMAC_CHCTRLA_BURSTLEN_4BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_5BEAT (DMAC_CHCTRLA_BURSTLEN_5BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_6BEAT (DMAC_CHCTRLA_BURSTLEN_6BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_7BEAT (DMAC_CHCTRLA_BURSTLEN_7BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_8BEAT (DMAC_CHCTRLA_BURSTLEN_8BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_9BEAT (DMAC_CHCTRLA_BURSTLEN_9BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_10BEAT (DMAC_CHCTRLA_BURSTLEN_10BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_11BEAT (DMAC_CHCTRLA_BURSTLEN_11BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_12BEAT (DMAC_CHCTRLA_BURSTLEN_12BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_13BEAT (DMAC_CHCTRLA_BURSTLEN_13BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_14BEAT (DMAC_CHCTRLA_BURSTLEN_14BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_15BEAT (DMAC_CHCTRLA_BURSTLEN_15BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_16BEAT (DMAC_CHCTRLA_BURSTLEN_16BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_THRESHOLD_Pos 28 /**< \brief (DMAC_CHCTRLA) FIFO Threshold */
-#define DMAC_CHCTRLA_THRESHOLD_Msk (_U_(0x3) << DMAC_CHCTRLA_THRESHOLD_Pos)
-#define DMAC_CHCTRLA_THRESHOLD(value) (DMAC_CHCTRLA_THRESHOLD_Msk & ((value) << DMAC_CHCTRLA_THRESHOLD_Pos))
-#define DMAC_CHCTRLA_THRESHOLD_1BEAT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Destination write starts after each beat source address read */
-#define DMAC_CHCTRLA_THRESHOLD_2BEATS_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) Destination write starts after 2-beats source address read */
-#define DMAC_CHCTRLA_THRESHOLD_4BEATS_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) Destination write starts after 4-beats source address read */
-#define DMAC_CHCTRLA_THRESHOLD_8BEATS_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) Destination write starts after 8-beats source address read */
-#define DMAC_CHCTRLA_THRESHOLD_1BEAT (DMAC_CHCTRLA_THRESHOLD_1BEAT_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
-#define DMAC_CHCTRLA_THRESHOLD_2BEATS (DMAC_CHCTRLA_THRESHOLD_2BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
-#define DMAC_CHCTRLA_THRESHOLD_4BEATS (DMAC_CHCTRLA_THRESHOLD_4BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
-#define DMAC_CHCTRLA_THRESHOLD_8BEATS (DMAC_CHCTRLA_THRESHOLD_8BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
-#define DMAC_CHCTRLA_MASK _U_(0x3F307F43) /**< \brief (DMAC_CHCTRLA) MASK Register */
-
-/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 8) CHANNEL Channel n Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t CMD:2; /*!< bit: 0.. 1 Software Command */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DMAC_CHCTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel n Control B */
-#define DMAC_CHCTRLB_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHCTRLB reset_value) Channel n Control B */
-
-#define DMAC_CHCTRLB_CMD_Pos 0 /**< \brief (DMAC_CHCTRLB) Software Command */
-#define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos)
-#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
-#define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */
-#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
-#define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */
-#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos)
-#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos)
-#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos)
-#define DMAC_CHCTRLB_MASK _U_(0x03) /**< \brief (DMAC_CHCTRLB) MASK Register */
-
-/* -------- DMAC_CHPRILVL : (DMAC Offset: 0x45) (R/W 8) CHANNEL Channel n Priority Level -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t PRILVL:2; /*!< bit: 0.. 1 Channel Priority Level */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DMAC_CHPRILVL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHPRILVL_OFFSET 0x45 /**< \brief (DMAC_CHPRILVL offset) Channel n Priority Level */
-#define DMAC_CHPRILVL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHPRILVL reset_value) Channel n Priority Level */
-
-#define DMAC_CHPRILVL_PRILVL_Pos 0 /**< \brief (DMAC_CHPRILVL) Channel Priority Level */
-#define DMAC_CHPRILVL_PRILVL_Msk (_U_(0x3) << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL(value) (DMAC_CHPRILVL_PRILVL_Msk & ((value) << DMAC_CHPRILVL_PRILVL_Pos))
-#define DMAC_CHPRILVL_PRILVL_LVL0_Val _U_(0x0) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 0 (Lowest Level) */
-#define DMAC_CHPRILVL_PRILVL_LVL1_Val _U_(0x1) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 1 */
-#define DMAC_CHPRILVL_PRILVL_LVL2_Val _U_(0x2) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 2 */
-#define DMAC_CHPRILVL_PRILVL_LVL3_Val _U_(0x3) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 3 */
-#define DMAC_CHPRILVL_PRILVL_LVL4_Val _U_(0x4) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 4 */
-#define DMAC_CHPRILVL_PRILVL_LVL5_Val _U_(0x5) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 5 */
-#define DMAC_CHPRILVL_PRILVL_LVL6_Val _U_(0x6) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 6 */
-#define DMAC_CHPRILVL_PRILVL_LVL7_Val _U_(0x7) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 7 (Highest Level) */
-#define DMAC_CHPRILVL_PRILVL_LVL0 (DMAC_CHPRILVL_PRILVL_LVL0_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL1 (DMAC_CHPRILVL_PRILVL_LVL1_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL2 (DMAC_CHPRILVL_PRILVL_LVL2_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL3 (DMAC_CHPRILVL_PRILVL_LVL3_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL4 (DMAC_CHPRILVL_PRILVL_LVL4_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL5 (DMAC_CHPRILVL_PRILVL_LVL5_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL6 (DMAC_CHPRILVL_PRILVL_LVL6_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL7 (DMAC_CHPRILVL_PRILVL_LVL7_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_MASK _U_(0x03) /**< \brief (DMAC_CHPRILVL) MASK Register */
-
-/* -------- DMAC_CHEVCTRL : (DMAC Offset: 0x46) (R/W 8) CHANNEL Channel n Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t EVACT:3; /*!< bit: 0.. 2 Channel Event Input Action */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t EVOMODE:2; /*!< bit: 4.. 5 Channel Event Output Mode */
- uint8_t EVIE:1; /*!< bit: 6 Channel Event Input Enable */
- uint8_t EVOE:1; /*!< bit: 7 Channel Event Output Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DMAC_CHEVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHEVCTRL_OFFSET 0x46 /**< \brief (DMAC_CHEVCTRL offset) Channel n Event Control */
-#define DMAC_CHEVCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHEVCTRL reset_value) Channel n Event Control */
-
-#define DMAC_CHEVCTRL_EVACT_Pos 0 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Action */
-#define DMAC_CHEVCTRL_EVACT_Msk (_U_(0x7) << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT(value) (DMAC_CHEVCTRL_EVACT_Msk & ((value) << DMAC_CHEVCTRL_EVACT_Pos))
-#define DMAC_CHEVCTRL_EVACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) No action */
-#define DMAC_CHEVCTRL_EVACT_TRIG_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Transfer and periodic transfer trigger */
-#define DMAC_CHEVCTRL_EVACT_CTRIG_Val _U_(0x2) /**< \brief (DMAC_CHEVCTRL) Conditional transfer trigger */
-#define DMAC_CHEVCTRL_EVACT_CBLOCK_Val _U_(0x3) /**< \brief (DMAC_CHEVCTRL) Conditional block transfer */
-#define DMAC_CHEVCTRL_EVACT_SUSPEND_Val _U_(0x4) /**< \brief (DMAC_CHEVCTRL) Channel suspend operation */
-#define DMAC_CHEVCTRL_EVACT_RESUME_Val _U_(0x5) /**< \brief (DMAC_CHEVCTRL) Channel resume operation */
-#define DMAC_CHEVCTRL_EVACT_SSKIP_Val _U_(0x6) /**< \brief (DMAC_CHEVCTRL) Skip next block suspend action */
-#define DMAC_CHEVCTRL_EVACT_INCPRI_Val _U_(0x7) /**< \brief (DMAC_CHEVCTRL) Increase priority */
-#define DMAC_CHEVCTRL_EVACT_NOACT (DMAC_CHEVCTRL_EVACT_NOACT_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_TRIG (DMAC_CHEVCTRL_EVACT_TRIG_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_CTRIG (DMAC_CHEVCTRL_EVACT_CTRIG_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_CBLOCK (DMAC_CHEVCTRL_EVACT_CBLOCK_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_SUSPEND (DMAC_CHEVCTRL_EVACT_SUSPEND_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_RESUME (DMAC_CHEVCTRL_EVACT_RESUME_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_SSKIP (DMAC_CHEVCTRL_EVACT_SSKIP_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_INCPRI (DMAC_CHEVCTRL_EVACT_INCPRI_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVOMODE_Pos 4 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Mode */
-#define DMAC_CHEVCTRL_EVOMODE_Msk (_U_(0x3) << DMAC_CHEVCTRL_EVOMODE_Pos)
-#define DMAC_CHEVCTRL_EVOMODE(value) (DMAC_CHEVCTRL_EVOMODE_Msk & ((value) << DMAC_CHEVCTRL_EVOMODE_Pos))
-#define DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) Block event output selection. Refer to BTCTRL.EVOSEL for available selections. */
-#define DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Ongoing trigger action */
-#define DMAC_CHEVCTRL_EVOMODE_DEFAULT (DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val << DMAC_CHEVCTRL_EVOMODE_Pos)
-#define DMAC_CHEVCTRL_EVOMODE_TRIGACT (DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val << DMAC_CHEVCTRL_EVOMODE_Pos)
-#define DMAC_CHEVCTRL_EVIE_Pos 6 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Enable */
-#define DMAC_CHEVCTRL_EVIE (_U_(0x1) << DMAC_CHEVCTRL_EVIE_Pos)
-#define DMAC_CHEVCTRL_EVOE_Pos 7 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Enable */
-#define DMAC_CHEVCTRL_EVOE (_U_(0x1) << DMAC_CHEVCTRL_EVOE_Pos)
-#define DMAC_CHEVCTRL_MASK _U_(0xF7) /**< \brief (DMAC_CHEVCTRL) MASK Register */
-
-/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
- uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
- uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DMAC_CHINTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel n Interrupt Enable Clear */
-#define DMAC_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */
-
-#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */
-#define DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos)
-#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */
-#define DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos)
-#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
-#define DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos)
-#define DMAC_CHINTENCLR_MASK _U_(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */
-
-/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
- uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
- uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DMAC_CHINTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel n Interrupt Enable Set */
-#define DMAC_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel n Interrupt Enable Set */
-
-#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */
-#define DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos)
-#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */
-#define DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos)
-#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
-#define DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos)
-#define DMAC_CHINTENSET_MASK _U_(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */
-
-/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
- __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
- __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
- __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DMAC_CHINTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */
-#define DMAC_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */
-
-#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */
-#define DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos)
-#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */
-#define DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos)
-#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
-#define DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos)
-#define DMAC_CHINTFLAG_MASK _U_(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */
-
-/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/W 8) CHANNEL Channel n Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t PEND:1; /*!< bit: 0 Channel Pending */
- uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
- uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */
- uint8_t CRCERR:1; /*!< bit: 3 Channel CRC Error */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DMAC_CHSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel n Status */
-#define DMAC_CHSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel n Status */
-
-#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */
-#define DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos)
-#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */
-#define DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos)
-#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */
-#define DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos)
-#define DMAC_CHSTATUS_CRCERR_Pos 3 /**< \brief (DMAC_CHSTATUS) Channel CRC Error */
-#define DMAC_CHSTATUS_CRCERR (_U_(0x1) << DMAC_CHSTATUS_CRCERR_Pos)
-#define DMAC_CHSTATUS_MASK _U_(0x0F) /**< \brief (DMAC_CHSTATUS) MASK Register */
-
-/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
- uint16_t EVOSEL:2; /*!< bit: 1.. 2 Block Event Output Selection */
- uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
- uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
- uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
- uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
- uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} DMAC_BTCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
-#define DMAC_BTCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
-
-#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */
-#define DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos)
-#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Block Event Output Selection */
-#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos)
-#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
-#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */
-#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Block event strobe */
-#define DMAC_BTCTRL_EVOSEL_BURST_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Burst event strobe */
-#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
-#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos)
-#define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos)
-#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */
-#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
-#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */
-#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */
-#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
-#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
-#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */
-#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos)
-#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
-#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */
-#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */
-#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */
-#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
-#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
-#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
-#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
-#define DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos)
-#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
-#define DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos)
-#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */
-#define DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos)
-#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
-#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
-#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos)
-#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos)
-#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
-#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
-#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 1 */
-#define DMAC_BTCTRL_STEPSIZE_X2_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 2 */
-#define DMAC_BTCTRL_STEPSIZE_X4_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 4 */
-#define DMAC_BTCTRL_STEPSIZE_X8_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 8 */
-#define DMAC_BTCTRL_STEPSIZE_X16_Val _U_(0x4) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 16 */
-#define DMAC_BTCTRL_STEPSIZE_X32_Val _U_(0x5) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 32 */
-#define DMAC_BTCTRL_STEPSIZE_X64_Val _U_(0x6) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 64 */
-#define DMAC_BTCTRL_STEPSIZE_X128_Val _U_(0x7) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 128 */
-#define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_MASK _U_(0xFF1F) /**< \brief (DMAC_BTCTRL) MASK Register */
-
-/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} DMAC_BTCNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_BTCNT_OFFSET 0x02 /**< \brief (DMAC_BTCNT offset) Block Transfer Count */
-#define DMAC_BTCNT_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCNT reset_value) Block Transfer Count */
-
-#define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */
-#define DMAC_BTCNT_BTCNT_Msk (_U_(0xFFFF) << DMAC_BTCNT_BTCNT_Pos)
-#define DMAC_BTCNT_BTCNT(value) (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
-#define DMAC_BTCNT_MASK _U_(0xFFFF) /**< \brief (DMAC_BTCNT) MASK Register */
-
-/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_SRCADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_SRCADDR_OFFSET 0x04 /**< \brief (DMAC_SRCADDR offset) Block Transfer Source Address */
-#define DMAC_SRCADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SRCADDR reset_value) Block Transfer Source Address */
-
-#define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */
-#define DMAC_SRCADDR_SRCADDR_Msk (_U_(0xFFFFFFFF) << DMAC_SRCADDR_SRCADDR_Pos)
-#define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
-#define DMAC_SRCADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_SRCADDR) MASK Register */
-
-/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct { // CRC mode
- uint32_t CHKINIT:32; /*!< bit: 0..31 CRC Checksum Initial Value */
- } CRC; /*!< Structure used for CRC */
- struct {
- uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_DSTADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_DSTADDR_OFFSET 0x08 /**< \brief (DMAC_DSTADDR offset) Block Transfer Destination Address */
-
-// CRC mode
-#define DMAC_DSTADDR_CRC_CHKINIT_Pos 0 /**< \brief (DMAC_DSTADDR_CRC) CRC Checksum Initial Value */
-#define DMAC_DSTADDR_CRC_CHKINIT_Msk (_U_(0xFFFFFFFF) << DMAC_DSTADDR_CRC_CHKINIT_Pos)
-#define DMAC_DSTADDR_CRC_CHKINIT(value) (DMAC_DSTADDR_CRC_CHKINIT_Msk & ((value) << DMAC_DSTADDR_CRC_CHKINIT_Pos))
-#define DMAC_DSTADDR_CRC_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_DSTADDR_CRC) MASK Register */
-
-#define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
-#define DMAC_DSTADDR_DSTADDR_Msk (_U_(0xFFFFFFFF) << DMAC_DSTADDR_DSTADDR_Pos)
-#define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
-#define DMAC_DSTADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_DSTADDR) MASK Register */
-
-/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_DESCADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_DESCADDR_OFFSET 0x0C /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */
-
-#define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
-#define DMAC_DESCADDR_DESCADDR_Msk (_U_(0xFFFFFFFF) << DMAC_DESCADDR_DESCADDR_Pos)
-#define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
-#define DMAC_DESCADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_DESCADDR) MASK Register */
-
-/** \brief DmacChannel hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x00 (R/W 32) Channel n Control A */
- __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x04 (R/W 8) Channel n Control B */
- __IO DMAC_CHPRILVL_Type CHPRILVL; /**< \brief Offset: 0x05 (R/W 8) Channel n Priority Level */
- __IO DMAC_CHEVCTRL_Type CHEVCTRL; /**< \brief Offset: 0x06 (R/W 8) Channel n Event Control */
- RoReg8 Reserved1[0x5];
- __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x0C (R/W 8) Channel n Interrupt Enable Clear */
- __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x0D (R/W 8) Channel n Interrupt Enable Set */
- __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x0E (R/W 8) Channel n Interrupt Flag Status and Clear */
- __IO DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0F (R/W 8) Channel n Status */
-} DmacChannel;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief DMAC APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
- __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
- __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
- __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
- __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
- __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
- RoReg8 Reserved1[0x2];
- __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
- __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
- RoReg8 Reserved2[0x8];
- __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
- RoReg8 Reserved3[0x2];
- __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
- __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
- __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
- __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
- __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
- __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
- RoReg8 Reserved4[0x4];
- DmacChannel Channel[32]; /**< \brief Offset: 0x40 DmacChannel groups [CH_NUM] */
-} Dmac;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief DMAC Descriptor SRAM registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
- __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
- __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
- __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
- __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
-} DmacDescriptor
-#ifdef __GNUC__
- __attribute__ ((aligned (8)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#ifdef __GNUC__
- #define SECTION_DMAC_DESCRIPTOR __attribute__ ((section(".hsram")))
-#elif defined(__ICCARM__)
- #define SECTION_DMAC_DESCRIPTOR @".hsram"
-#endif
-
-/*@}*/
-
-#endif /* _SAME54_DMAC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for DMAC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_DMAC_COMPONENT_
+#define _SAME54_DMAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR DMAC */
+/* ========================================================================== */
+/** \addtogroup SAME54_DMAC Direct Memory Access Controller */
+/*@{*/
+
+#define DMAC_U2503
+#define REV_DMAC 0x101
+
+/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
+ uint16_t :6; /*!< bit: 2.. 7 Reserved */
+ uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
+ uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
+ uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
+ uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :8; /*!< bit: 0.. 7 Reserved */
+ uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */
+#define DMAC_CTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */
+
+#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */
+#define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos)
+#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */
+#define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos)
+#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
+#define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos)
+#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
+#define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos)
+#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
+#define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos)
+#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
+#define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos)
+#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */
+#define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos)
+#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
+#define DMAC_CTRL_MASK _U_(0x0F03) /**< \brief (DMAC_CTRL) MASK Register */
+
+/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
+ uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
+ uint16_t CRCMODE:2; /*!< bit: 14..15 CRC Operating Mode */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_CRCCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */
+#define DMAC_CRCCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
+
+#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
+#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
+#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */
+#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */
+#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */
+#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
+#define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
+#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
+#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
+#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */
+#define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
+#define DMAC_CRCCTRL_CRCSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC Disabled */
+#define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */
+#define DMAC_CRCCTRL_CRCSRC_DISABLE (DMAC_CRCCTRL_CRCSRC_DISABLE_Val << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCMODE_Pos 14 /**< \brief (DMAC_CRCCTRL) CRC Operating Mode */
+#define DMAC_CRCCTRL_CRCMODE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCMODE_Pos)
+#define DMAC_CRCCTRL_CRCMODE(value) (DMAC_CRCCTRL_CRCMODE_Msk & ((value) << DMAC_CRCCTRL_CRCMODE_Pos))
+#define DMAC_CRCCTRL_CRCMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) Default operating mode */
+#define DMAC_CRCCTRL_CRCMODE_CRCMON_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) Memory CRC monitor operating mode */
+#define DMAC_CRCCTRL_CRCMODE_CRCGEN_Val _U_(0x3) /**< \brief (DMAC_CRCCTRL) Memory CRC generation operating mode */
+#define DMAC_CRCCTRL_CRCMODE_DEFAULT (DMAC_CRCCTRL_CRCMODE_DEFAULT_Val << DMAC_CRCCTRL_CRCMODE_Pos)
+#define DMAC_CRCCTRL_CRCMODE_CRCMON (DMAC_CRCCTRL_CRCMODE_CRCMON_Val << DMAC_CRCCTRL_CRCMODE_Pos)
+#define DMAC_CRCCTRL_CRCMODE_CRCGEN (DMAC_CRCCTRL_CRCMODE_CRCGEN_Val << DMAC_CRCCTRL_CRCMODE_Pos)
+#define DMAC_CRCCTRL_MASK _U_(0xFF0F) /**< \brief (DMAC_CRCCTRL) MASK Register */
+
+/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_CRCDATAIN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
+#define DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
+
+#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
+#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos)
+#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
+#define DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */
+
+/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_CRCCHKSUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
+#define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
+
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
+#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
+#define DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */
+
+/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
+ uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
+ uint8_t CRCERR:1; /*!< bit: 2 CRC Error */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CRCSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
+#define DMAC_CRCSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
+
+#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
+#define DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos)
+#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */
+#define DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos)
+#define DMAC_CRCSTATUS_CRCERR_Pos 2 /**< \brief (DMAC_CRCSTATUS) CRC Error */
+#define DMAC_CRCSTATUS_CRCERR (_U_(0x1) << DMAC_CRCSTATUS_CRCERR_Pos)
+#define DMAC_CRCSTATUS_MASK _U_(0x07) /**< \brief (DMAC_CRCSTATUS) MASK Register */
+
+/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */
+#define DMAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
+
+#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */
+#define DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos)
+#define DMAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */
+
+/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
+ uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
+ uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
+ uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
+ uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
+ uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
+ uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
+ uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
+ uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
+ uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
+ uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
+ uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
+ uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */
+ uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */
+ uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */
+ uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */
+ uint32_t SWTRIG16:1; /*!< bit: 16 Channel 16 Software Trigger */
+ uint32_t SWTRIG17:1; /*!< bit: 17 Channel 17 Software Trigger */
+ uint32_t SWTRIG18:1; /*!< bit: 18 Channel 18 Software Trigger */
+ uint32_t SWTRIG19:1; /*!< bit: 19 Channel 19 Software Trigger */
+ uint32_t SWTRIG20:1; /*!< bit: 20 Channel 20 Software Trigger */
+ uint32_t SWTRIG21:1; /*!< bit: 21 Channel 21 Software Trigger */
+ uint32_t SWTRIG22:1; /*!< bit: 22 Channel 22 Software Trigger */
+ uint32_t SWTRIG23:1; /*!< bit: 23 Channel 23 Software Trigger */
+ uint32_t SWTRIG24:1; /*!< bit: 24 Channel 24 Software Trigger */
+ uint32_t SWTRIG25:1; /*!< bit: 25 Channel 25 Software Trigger */
+ uint32_t SWTRIG26:1; /*!< bit: 26 Channel 26 Software Trigger */
+ uint32_t SWTRIG27:1; /*!< bit: 27 Channel 27 Software Trigger */
+ uint32_t SWTRIG28:1; /*!< bit: 28 Channel 28 Software Trigger */
+ uint32_t SWTRIG29:1; /*!< bit: 29 Channel 29 Software Trigger */
+ uint32_t SWTRIG30:1; /*!< bit: 30 Channel 30 Software Trigger */
+ uint32_t SWTRIG31:1; /*!< bit: 31 Channel 31 Software Trigger */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t SWTRIG:32; /*!< bit: 0..31 Channel x Software Trigger */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_SWTRIGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
+#define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
+
+#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12 /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG12 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG12_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13 /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG13 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG13_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14 /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG14 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG14_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15 /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG15 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG15_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG16_Pos 16 /**< \brief (DMAC_SWTRIGCTRL) Channel 16 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG16 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG16_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG17_Pos 17 /**< \brief (DMAC_SWTRIGCTRL) Channel 17 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG17 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG17_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG18_Pos 18 /**< \brief (DMAC_SWTRIGCTRL) Channel 18 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG18 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG18_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG19_Pos 19 /**< \brief (DMAC_SWTRIGCTRL) Channel 19 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG19 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG19_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG20_Pos 20 /**< \brief (DMAC_SWTRIGCTRL) Channel 20 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG20 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG20_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG21_Pos 21 /**< \brief (DMAC_SWTRIGCTRL) Channel 21 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG21 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG21_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG22_Pos 22 /**< \brief (DMAC_SWTRIGCTRL) Channel 22 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG22 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG22_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG23_Pos 23 /**< \brief (DMAC_SWTRIGCTRL) Channel 23 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG23 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG23_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG24_Pos 24 /**< \brief (DMAC_SWTRIGCTRL) Channel 24 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG24 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG24_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG25_Pos 25 /**< \brief (DMAC_SWTRIGCTRL) Channel 25 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG25 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG25_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG26_Pos 26 /**< \brief (DMAC_SWTRIGCTRL) Channel 26 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG26 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG26_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG27_Pos 27 /**< \brief (DMAC_SWTRIGCTRL) Channel 27 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG27 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG27_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG28_Pos 28 /**< \brief (DMAC_SWTRIGCTRL) Channel 28 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG28 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG28_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG29_Pos 29 /**< \brief (DMAC_SWTRIGCTRL) Channel 29 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG29 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG29_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG30_Pos 30 /**< \brief (DMAC_SWTRIGCTRL) Channel 30 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG30 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG30_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG31_Pos 31 /**< \brief (DMAC_SWTRIGCTRL) Channel 31 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG31 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG31_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFFFFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
+#define DMAC_SWTRIGCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
+
+/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LVLPRI0:5; /*!< bit: 0.. 4 Level 0 Channel Priority Number */
+ uint32_t QOS0:2; /*!< bit: 5.. 6 Level 0 Quality of Service */
+ uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI1:5; /*!< bit: 8..12 Level 1 Channel Priority Number */
+ uint32_t QOS1:2; /*!< bit: 13..14 Level 1 Quality of Service */
+ uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI2:5; /*!< bit: 16..20 Level 2 Channel Priority Number */
+ uint32_t QOS2:2; /*!< bit: 21..22 Level 2 Quality of Service */
+ uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI3:5; /*!< bit: 24..28 Level 3 Channel Priority Number */
+ uint32_t QOS3:2; /*!< bit: 29..30 Level 3 Quality of Service */
+ uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_PRICTRL0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
+#define DMAC_PRICTRL0_RESETVALUE _U_(0x40404040) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
+
+#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI0_Pos)
+#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
+#define DMAC_PRICTRL0_QOS0_Pos 5 /**< \brief (DMAC_PRICTRL0) Level 0 Quality of Service */
+#define DMAC_PRICTRL0_QOS0_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS0_Pos)
+#define DMAC_PRICTRL0_QOS0(value) (DMAC_PRICTRL0_QOS0_Msk & ((value) << DMAC_PRICTRL0_QOS0_Pos))
+#define DMAC_PRICTRL0_QOS0_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
+#define DMAC_PRICTRL0_QOS0_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
+#define DMAC_PRICTRL0_QOS0_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
+#define DMAC_PRICTRL0_QOS0_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
+#define DMAC_PRICTRL0_QOS0_REGULAR (DMAC_PRICTRL0_QOS0_REGULAR_Val << DMAC_PRICTRL0_QOS0_Pos)
+#define DMAC_PRICTRL0_QOS0_SHORTAGE (DMAC_PRICTRL0_QOS0_SHORTAGE_Val << DMAC_PRICTRL0_QOS0_Pos)
+#define DMAC_PRICTRL0_QOS0_SENSITIVE (DMAC_PRICTRL0_QOS0_SENSITIVE_Val << DMAC_PRICTRL0_QOS0_Pos)
+#define DMAC_PRICTRL0_QOS0_CRITICAL (DMAC_PRICTRL0_QOS0_CRITICAL_Val << DMAC_PRICTRL0_QOS0_Pos)
+#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos)
+#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI1_Pos)
+#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
+#define DMAC_PRICTRL0_QOS1_Pos 13 /**< \brief (DMAC_PRICTRL0) Level 1 Quality of Service */
+#define DMAC_PRICTRL0_QOS1_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS1_Pos)
+#define DMAC_PRICTRL0_QOS1(value) (DMAC_PRICTRL0_QOS1_Msk & ((value) << DMAC_PRICTRL0_QOS1_Pos))
+#define DMAC_PRICTRL0_QOS1_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
+#define DMAC_PRICTRL0_QOS1_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
+#define DMAC_PRICTRL0_QOS1_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
+#define DMAC_PRICTRL0_QOS1_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
+#define DMAC_PRICTRL0_QOS1_REGULAR (DMAC_PRICTRL0_QOS1_REGULAR_Val << DMAC_PRICTRL0_QOS1_Pos)
+#define DMAC_PRICTRL0_QOS1_SHORTAGE (DMAC_PRICTRL0_QOS1_SHORTAGE_Val << DMAC_PRICTRL0_QOS1_Pos)
+#define DMAC_PRICTRL0_QOS1_SENSITIVE (DMAC_PRICTRL0_QOS1_SENSITIVE_Val << DMAC_PRICTRL0_QOS1_Pos)
+#define DMAC_PRICTRL0_QOS1_CRITICAL (DMAC_PRICTRL0_QOS1_CRITICAL_Val << DMAC_PRICTRL0_QOS1_Pos)
+#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos)
+#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI2_Pos)
+#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
+#define DMAC_PRICTRL0_QOS2_Pos 21 /**< \brief (DMAC_PRICTRL0) Level 2 Quality of Service */
+#define DMAC_PRICTRL0_QOS2_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS2_Pos)
+#define DMAC_PRICTRL0_QOS2(value) (DMAC_PRICTRL0_QOS2_Msk & ((value) << DMAC_PRICTRL0_QOS2_Pos))
+#define DMAC_PRICTRL0_QOS2_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
+#define DMAC_PRICTRL0_QOS2_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
+#define DMAC_PRICTRL0_QOS2_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
+#define DMAC_PRICTRL0_QOS2_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
+#define DMAC_PRICTRL0_QOS2_REGULAR (DMAC_PRICTRL0_QOS2_REGULAR_Val << DMAC_PRICTRL0_QOS2_Pos)
+#define DMAC_PRICTRL0_QOS2_SHORTAGE (DMAC_PRICTRL0_QOS2_SHORTAGE_Val << DMAC_PRICTRL0_QOS2_Pos)
+#define DMAC_PRICTRL0_QOS2_SENSITIVE (DMAC_PRICTRL0_QOS2_SENSITIVE_Val << DMAC_PRICTRL0_QOS2_Pos)
+#define DMAC_PRICTRL0_QOS2_CRITICAL (DMAC_PRICTRL0_QOS2_CRITICAL_Val << DMAC_PRICTRL0_QOS2_Pos)
+#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos)
+#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI3_Pos)
+#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
+#define DMAC_PRICTRL0_QOS3_Pos 29 /**< \brief (DMAC_PRICTRL0) Level 3 Quality of Service */
+#define DMAC_PRICTRL0_QOS3_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS3_Pos)
+#define DMAC_PRICTRL0_QOS3(value) (DMAC_PRICTRL0_QOS3_Msk & ((value) << DMAC_PRICTRL0_QOS3_Pos))
+#define DMAC_PRICTRL0_QOS3_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
+#define DMAC_PRICTRL0_QOS3_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
+#define DMAC_PRICTRL0_QOS3_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
+#define DMAC_PRICTRL0_QOS3_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
+#define DMAC_PRICTRL0_QOS3_REGULAR (DMAC_PRICTRL0_QOS3_REGULAR_Val << DMAC_PRICTRL0_QOS3_Pos)
+#define DMAC_PRICTRL0_QOS3_SHORTAGE (DMAC_PRICTRL0_QOS3_SHORTAGE_Val << DMAC_PRICTRL0_QOS3_Pos)
+#define DMAC_PRICTRL0_QOS3_SENSITIVE (DMAC_PRICTRL0_QOS3_SENSITIVE_Val << DMAC_PRICTRL0_QOS3_Pos)
+#define DMAC_PRICTRL0_QOS3_CRITICAL (DMAC_PRICTRL0_QOS3_CRITICAL_Val << DMAC_PRICTRL0_QOS3_Pos)
+#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos)
+#define DMAC_PRICTRL0_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PRICTRL0) MASK Register */
+
+/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ID:5; /*!< bit: 0.. 4 Channel ID */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t TERR:1; /*!< bit: 8 Transfer Error */
+ uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
+ uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t CRCERR:1; /*!< bit: 12 CRC Error */
+ uint16_t FERR:1; /*!< bit: 13 Fetch Error */
+ uint16_t BUSY:1; /*!< bit: 14 Busy */
+ uint16_t PEND:1; /*!< bit: 15 Pending */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_INTPEND_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
+#define DMAC_INTPEND_RESETVALUE _U_(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
+
+#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */
+#define DMAC_INTPEND_ID_Msk (_U_(0x1F) << DMAC_INTPEND_ID_Pos)
+#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
+#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */
+#define DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos)
+#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */
+#define DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos)
+#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */
+#define DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos)
+#define DMAC_INTPEND_CRCERR_Pos 12 /**< \brief (DMAC_INTPEND) CRC Error */
+#define DMAC_INTPEND_CRCERR (_U_(0x1) << DMAC_INTPEND_CRCERR_Pos)
+#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */
+#define DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos)
+#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */
+#define DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos)
+#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */
+#define DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos)
+#define DMAC_INTPEND_MASK _U_(0xF71F) /**< \brief (DMAC_INTPEND) MASK Register */
+
+/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
+ uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
+ uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
+ uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
+ uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
+ uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
+ uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
+ uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
+ uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
+ uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
+ uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
+ uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
+ uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */
+ uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */
+ uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */
+ uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */
+ uint32_t CHINT16:1; /*!< bit: 16 Channel 16 Pending Interrupt */
+ uint32_t CHINT17:1; /*!< bit: 17 Channel 17 Pending Interrupt */
+ uint32_t CHINT18:1; /*!< bit: 18 Channel 18 Pending Interrupt */
+ uint32_t CHINT19:1; /*!< bit: 19 Channel 19 Pending Interrupt */
+ uint32_t CHINT20:1; /*!< bit: 20 Channel 20 Pending Interrupt */
+ uint32_t CHINT21:1; /*!< bit: 21 Channel 21 Pending Interrupt */
+ uint32_t CHINT22:1; /*!< bit: 22 Channel 22 Pending Interrupt */
+ uint32_t CHINT23:1; /*!< bit: 23 Channel 23 Pending Interrupt */
+ uint32_t CHINT24:1; /*!< bit: 24 Channel 24 Pending Interrupt */
+ uint32_t CHINT25:1; /*!< bit: 25 Channel 25 Pending Interrupt */
+ uint32_t CHINT26:1; /*!< bit: 26 Channel 26 Pending Interrupt */
+ uint32_t CHINT27:1; /*!< bit: 27 Channel 27 Pending Interrupt */
+ uint32_t CHINT28:1; /*!< bit: 28 Channel 28 Pending Interrupt */
+ uint32_t CHINT29:1; /*!< bit: 29 Channel 29 Pending Interrupt */
+ uint32_t CHINT30:1; /*!< bit: 30 Channel 30 Pending Interrupt */
+ uint32_t CHINT31:1; /*!< bit: 31 Channel 31 Pending Interrupt */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t CHINT:32; /*!< bit: 0..31 Channel x Pending Interrupt */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_INTSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
+#define DMAC_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
+
+#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos)
+#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos)
+#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos)
+#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos)
+#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos)
+#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos)
+#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos)
+#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos)
+#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos)
+#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos)
+#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos)
+#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos)
+#define DMAC_INTSTATUS_CHINT12_Pos 12 /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT12 (_U_(1) << DMAC_INTSTATUS_CHINT12_Pos)
+#define DMAC_INTSTATUS_CHINT13_Pos 13 /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT13 (_U_(1) << DMAC_INTSTATUS_CHINT13_Pos)
+#define DMAC_INTSTATUS_CHINT14_Pos 14 /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT14 (_U_(1) << DMAC_INTSTATUS_CHINT14_Pos)
+#define DMAC_INTSTATUS_CHINT15_Pos 15 /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT15 (_U_(1) << DMAC_INTSTATUS_CHINT15_Pos)
+#define DMAC_INTSTATUS_CHINT16_Pos 16 /**< \brief (DMAC_INTSTATUS) Channel 16 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT16 (_U_(1) << DMAC_INTSTATUS_CHINT16_Pos)
+#define DMAC_INTSTATUS_CHINT17_Pos 17 /**< \brief (DMAC_INTSTATUS) Channel 17 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT17 (_U_(1) << DMAC_INTSTATUS_CHINT17_Pos)
+#define DMAC_INTSTATUS_CHINT18_Pos 18 /**< \brief (DMAC_INTSTATUS) Channel 18 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT18 (_U_(1) << DMAC_INTSTATUS_CHINT18_Pos)
+#define DMAC_INTSTATUS_CHINT19_Pos 19 /**< \brief (DMAC_INTSTATUS) Channel 19 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT19 (_U_(1) << DMAC_INTSTATUS_CHINT19_Pos)
+#define DMAC_INTSTATUS_CHINT20_Pos 20 /**< \brief (DMAC_INTSTATUS) Channel 20 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT20 (_U_(1) << DMAC_INTSTATUS_CHINT20_Pos)
+#define DMAC_INTSTATUS_CHINT21_Pos 21 /**< \brief (DMAC_INTSTATUS) Channel 21 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT21 (_U_(1) << DMAC_INTSTATUS_CHINT21_Pos)
+#define DMAC_INTSTATUS_CHINT22_Pos 22 /**< \brief (DMAC_INTSTATUS) Channel 22 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT22 (_U_(1) << DMAC_INTSTATUS_CHINT22_Pos)
+#define DMAC_INTSTATUS_CHINT23_Pos 23 /**< \brief (DMAC_INTSTATUS) Channel 23 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT23 (_U_(1) << DMAC_INTSTATUS_CHINT23_Pos)
+#define DMAC_INTSTATUS_CHINT24_Pos 24 /**< \brief (DMAC_INTSTATUS) Channel 24 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT24 (_U_(1) << DMAC_INTSTATUS_CHINT24_Pos)
+#define DMAC_INTSTATUS_CHINT25_Pos 25 /**< \brief (DMAC_INTSTATUS) Channel 25 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT25 (_U_(1) << DMAC_INTSTATUS_CHINT25_Pos)
+#define DMAC_INTSTATUS_CHINT26_Pos 26 /**< \brief (DMAC_INTSTATUS) Channel 26 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT26 (_U_(1) << DMAC_INTSTATUS_CHINT26_Pos)
+#define DMAC_INTSTATUS_CHINT27_Pos 27 /**< \brief (DMAC_INTSTATUS) Channel 27 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT27 (_U_(1) << DMAC_INTSTATUS_CHINT27_Pos)
+#define DMAC_INTSTATUS_CHINT28_Pos 28 /**< \brief (DMAC_INTSTATUS) Channel 28 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT28 (_U_(1) << DMAC_INTSTATUS_CHINT28_Pos)
+#define DMAC_INTSTATUS_CHINT29_Pos 29 /**< \brief (DMAC_INTSTATUS) Channel 29 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT29 (_U_(1) << DMAC_INTSTATUS_CHINT29_Pos)
+#define DMAC_INTSTATUS_CHINT30_Pos 30 /**< \brief (DMAC_INTSTATUS) Channel 30 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT30 (_U_(1) << DMAC_INTSTATUS_CHINT30_Pos)
+#define DMAC_INTSTATUS_CHINT31_Pos 31 /**< \brief (DMAC_INTSTATUS) Channel 31 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT31 (_U_(1) << DMAC_INTSTATUS_CHINT31_Pos)
+#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFFFFFFF) << DMAC_INTSTATUS_CHINT_Pos)
+#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
+#define DMAC_INTSTATUS_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */
+
+/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
+ uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
+ uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
+ uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
+ uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
+ uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
+ uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
+ uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
+ uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
+ uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
+ uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
+ uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
+ uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */
+ uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */
+ uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */
+ uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */
+ uint32_t BUSYCH16:1; /*!< bit: 16 Busy Channel 16 */
+ uint32_t BUSYCH17:1; /*!< bit: 17 Busy Channel 17 */
+ uint32_t BUSYCH18:1; /*!< bit: 18 Busy Channel 18 */
+ uint32_t BUSYCH19:1; /*!< bit: 19 Busy Channel 19 */
+ uint32_t BUSYCH20:1; /*!< bit: 20 Busy Channel 20 */
+ uint32_t BUSYCH21:1; /*!< bit: 21 Busy Channel 21 */
+ uint32_t BUSYCH22:1; /*!< bit: 22 Busy Channel 22 */
+ uint32_t BUSYCH23:1; /*!< bit: 23 Busy Channel 23 */
+ uint32_t BUSYCH24:1; /*!< bit: 24 Busy Channel 24 */
+ uint32_t BUSYCH25:1; /*!< bit: 25 Busy Channel 25 */
+ uint32_t BUSYCH26:1; /*!< bit: 26 Busy Channel 26 */
+ uint32_t BUSYCH27:1; /*!< bit: 27 Busy Channel 27 */
+ uint32_t BUSYCH28:1; /*!< bit: 28 Busy Channel 28 */
+ uint32_t BUSYCH29:1; /*!< bit: 29 Busy Channel 29 */
+ uint32_t BUSYCH30:1; /*!< bit: 30 Busy Channel 30 */
+ uint32_t BUSYCH31:1; /*!< bit: 31 Busy Channel 31 */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t BUSYCH:32; /*!< bit: 0..31 Busy Channel x */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_BUSYCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */
+#define DMAC_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
+
+#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
+#define DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos)
+#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
+#define DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos)
+#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
+#define DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos)
+#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
+#define DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos)
+#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
+#define DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos)
+#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
+#define DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos)
+#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
+#define DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos)
+#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
+#define DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos)
+#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
+#define DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos)
+#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
+#define DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos)
+#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
+#define DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos)
+#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
+#define DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos)
+#define DMAC_BUSYCH_BUSYCH12_Pos 12 /**< \brief (DMAC_BUSYCH) Busy Channel 12 */
+#define DMAC_BUSYCH_BUSYCH12 (_U_(1) << DMAC_BUSYCH_BUSYCH12_Pos)
+#define DMAC_BUSYCH_BUSYCH13_Pos 13 /**< \brief (DMAC_BUSYCH) Busy Channel 13 */
+#define DMAC_BUSYCH_BUSYCH13 (_U_(1) << DMAC_BUSYCH_BUSYCH13_Pos)
+#define DMAC_BUSYCH_BUSYCH14_Pos 14 /**< \brief (DMAC_BUSYCH) Busy Channel 14 */
+#define DMAC_BUSYCH_BUSYCH14 (_U_(1) << DMAC_BUSYCH_BUSYCH14_Pos)
+#define DMAC_BUSYCH_BUSYCH15_Pos 15 /**< \brief (DMAC_BUSYCH) Busy Channel 15 */
+#define DMAC_BUSYCH_BUSYCH15 (_U_(1) << DMAC_BUSYCH_BUSYCH15_Pos)
+#define DMAC_BUSYCH_BUSYCH16_Pos 16 /**< \brief (DMAC_BUSYCH) Busy Channel 16 */
+#define DMAC_BUSYCH_BUSYCH16 (_U_(1) << DMAC_BUSYCH_BUSYCH16_Pos)
+#define DMAC_BUSYCH_BUSYCH17_Pos 17 /**< \brief (DMAC_BUSYCH) Busy Channel 17 */
+#define DMAC_BUSYCH_BUSYCH17 (_U_(1) << DMAC_BUSYCH_BUSYCH17_Pos)
+#define DMAC_BUSYCH_BUSYCH18_Pos 18 /**< \brief (DMAC_BUSYCH) Busy Channel 18 */
+#define DMAC_BUSYCH_BUSYCH18 (_U_(1) << DMAC_BUSYCH_BUSYCH18_Pos)
+#define DMAC_BUSYCH_BUSYCH19_Pos 19 /**< \brief (DMAC_BUSYCH) Busy Channel 19 */
+#define DMAC_BUSYCH_BUSYCH19 (_U_(1) << DMAC_BUSYCH_BUSYCH19_Pos)
+#define DMAC_BUSYCH_BUSYCH20_Pos 20 /**< \brief (DMAC_BUSYCH) Busy Channel 20 */
+#define DMAC_BUSYCH_BUSYCH20 (_U_(1) << DMAC_BUSYCH_BUSYCH20_Pos)
+#define DMAC_BUSYCH_BUSYCH21_Pos 21 /**< \brief (DMAC_BUSYCH) Busy Channel 21 */
+#define DMAC_BUSYCH_BUSYCH21 (_U_(1) << DMAC_BUSYCH_BUSYCH21_Pos)
+#define DMAC_BUSYCH_BUSYCH22_Pos 22 /**< \brief (DMAC_BUSYCH) Busy Channel 22 */
+#define DMAC_BUSYCH_BUSYCH22 (_U_(1) << DMAC_BUSYCH_BUSYCH22_Pos)
+#define DMAC_BUSYCH_BUSYCH23_Pos 23 /**< \brief (DMAC_BUSYCH) Busy Channel 23 */
+#define DMAC_BUSYCH_BUSYCH23 (_U_(1) << DMAC_BUSYCH_BUSYCH23_Pos)
+#define DMAC_BUSYCH_BUSYCH24_Pos 24 /**< \brief (DMAC_BUSYCH) Busy Channel 24 */
+#define DMAC_BUSYCH_BUSYCH24 (_U_(1) << DMAC_BUSYCH_BUSYCH24_Pos)
+#define DMAC_BUSYCH_BUSYCH25_Pos 25 /**< \brief (DMAC_BUSYCH) Busy Channel 25 */
+#define DMAC_BUSYCH_BUSYCH25 (_U_(1) << DMAC_BUSYCH_BUSYCH25_Pos)
+#define DMAC_BUSYCH_BUSYCH26_Pos 26 /**< \brief (DMAC_BUSYCH) Busy Channel 26 */
+#define DMAC_BUSYCH_BUSYCH26 (_U_(1) << DMAC_BUSYCH_BUSYCH26_Pos)
+#define DMAC_BUSYCH_BUSYCH27_Pos 27 /**< \brief (DMAC_BUSYCH) Busy Channel 27 */
+#define DMAC_BUSYCH_BUSYCH27 (_U_(1) << DMAC_BUSYCH_BUSYCH27_Pos)
+#define DMAC_BUSYCH_BUSYCH28_Pos 28 /**< \brief (DMAC_BUSYCH) Busy Channel 28 */
+#define DMAC_BUSYCH_BUSYCH28 (_U_(1) << DMAC_BUSYCH_BUSYCH28_Pos)
+#define DMAC_BUSYCH_BUSYCH29_Pos 29 /**< \brief (DMAC_BUSYCH) Busy Channel 29 */
+#define DMAC_BUSYCH_BUSYCH29 (_U_(1) << DMAC_BUSYCH_BUSYCH29_Pos)
+#define DMAC_BUSYCH_BUSYCH30_Pos 30 /**< \brief (DMAC_BUSYCH) Busy Channel 30 */
+#define DMAC_BUSYCH_BUSYCH30 (_U_(1) << DMAC_BUSYCH_BUSYCH30_Pos)
+#define DMAC_BUSYCH_BUSYCH31_Pos 31 /**< \brief (DMAC_BUSYCH) Busy Channel 31 */
+#define DMAC_BUSYCH_BUSYCH31 (_U_(1) << DMAC_BUSYCH_BUSYCH31_Pos)
+#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */
+#define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFFFFFFF) << DMAC_BUSYCH_BUSYCH_Pos)
+#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
+#define DMAC_BUSYCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BUSYCH) MASK Register */
+
+/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
+ uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
+ uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
+ uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
+ uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
+ uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
+ uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
+ uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
+ uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
+ uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
+ uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
+ uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
+ uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */
+ uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */
+ uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */
+ uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */
+ uint32_t PENDCH16:1; /*!< bit: 16 Pending Channel 16 */
+ uint32_t PENDCH17:1; /*!< bit: 17 Pending Channel 17 */
+ uint32_t PENDCH18:1; /*!< bit: 18 Pending Channel 18 */
+ uint32_t PENDCH19:1; /*!< bit: 19 Pending Channel 19 */
+ uint32_t PENDCH20:1; /*!< bit: 20 Pending Channel 20 */
+ uint32_t PENDCH21:1; /*!< bit: 21 Pending Channel 21 */
+ uint32_t PENDCH22:1; /*!< bit: 22 Pending Channel 22 */
+ uint32_t PENDCH23:1; /*!< bit: 23 Pending Channel 23 */
+ uint32_t PENDCH24:1; /*!< bit: 24 Pending Channel 24 */
+ uint32_t PENDCH25:1; /*!< bit: 25 Pending Channel 25 */
+ uint32_t PENDCH26:1; /*!< bit: 26 Pending Channel 26 */
+ uint32_t PENDCH27:1; /*!< bit: 27 Pending Channel 27 */
+ uint32_t PENDCH28:1; /*!< bit: 28 Pending Channel 28 */
+ uint32_t PENDCH29:1; /*!< bit: 29 Pending Channel 29 */
+ uint32_t PENDCH30:1; /*!< bit: 30 Pending Channel 30 */
+ uint32_t PENDCH31:1; /*!< bit: 31 Pending Channel 31 */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t PENDCH:32; /*!< bit: 0..31 Pending Channel x */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_PENDCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */
+#define DMAC_PENDCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
+
+#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */
+#define DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos)
+#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */
+#define DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos)
+#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */
+#define DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos)
+#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */
+#define DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos)
+#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */
+#define DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos)
+#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */
+#define DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos)
+#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */
+#define DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos)
+#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */
+#define DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos)
+#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */
+#define DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos)
+#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */
+#define DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos)
+#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */
+#define DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos)
+#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */
+#define DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos)
+#define DMAC_PENDCH_PENDCH12_Pos 12 /**< \brief (DMAC_PENDCH) Pending Channel 12 */
+#define DMAC_PENDCH_PENDCH12 (_U_(1) << DMAC_PENDCH_PENDCH12_Pos)
+#define DMAC_PENDCH_PENDCH13_Pos 13 /**< \brief (DMAC_PENDCH) Pending Channel 13 */
+#define DMAC_PENDCH_PENDCH13 (_U_(1) << DMAC_PENDCH_PENDCH13_Pos)
+#define DMAC_PENDCH_PENDCH14_Pos 14 /**< \brief (DMAC_PENDCH) Pending Channel 14 */
+#define DMAC_PENDCH_PENDCH14 (_U_(1) << DMAC_PENDCH_PENDCH14_Pos)
+#define DMAC_PENDCH_PENDCH15_Pos 15 /**< \brief (DMAC_PENDCH) Pending Channel 15 */
+#define DMAC_PENDCH_PENDCH15 (_U_(1) << DMAC_PENDCH_PENDCH15_Pos)
+#define DMAC_PENDCH_PENDCH16_Pos 16 /**< \brief (DMAC_PENDCH) Pending Channel 16 */
+#define DMAC_PENDCH_PENDCH16 (_U_(1) << DMAC_PENDCH_PENDCH16_Pos)
+#define DMAC_PENDCH_PENDCH17_Pos 17 /**< \brief (DMAC_PENDCH) Pending Channel 17 */
+#define DMAC_PENDCH_PENDCH17 (_U_(1) << DMAC_PENDCH_PENDCH17_Pos)
+#define DMAC_PENDCH_PENDCH18_Pos 18 /**< \brief (DMAC_PENDCH) Pending Channel 18 */
+#define DMAC_PENDCH_PENDCH18 (_U_(1) << DMAC_PENDCH_PENDCH18_Pos)
+#define DMAC_PENDCH_PENDCH19_Pos 19 /**< \brief (DMAC_PENDCH) Pending Channel 19 */
+#define DMAC_PENDCH_PENDCH19 (_U_(1) << DMAC_PENDCH_PENDCH19_Pos)
+#define DMAC_PENDCH_PENDCH20_Pos 20 /**< \brief (DMAC_PENDCH) Pending Channel 20 */
+#define DMAC_PENDCH_PENDCH20 (_U_(1) << DMAC_PENDCH_PENDCH20_Pos)
+#define DMAC_PENDCH_PENDCH21_Pos 21 /**< \brief (DMAC_PENDCH) Pending Channel 21 */
+#define DMAC_PENDCH_PENDCH21 (_U_(1) << DMAC_PENDCH_PENDCH21_Pos)
+#define DMAC_PENDCH_PENDCH22_Pos 22 /**< \brief (DMAC_PENDCH) Pending Channel 22 */
+#define DMAC_PENDCH_PENDCH22 (_U_(1) << DMAC_PENDCH_PENDCH22_Pos)
+#define DMAC_PENDCH_PENDCH23_Pos 23 /**< \brief (DMAC_PENDCH) Pending Channel 23 */
+#define DMAC_PENDCH_PENDCH23 (_U_(1) << DMAC_PENDCH_PENDCH23_Pos)
+#define DMAC_PENDCH_PENDCH24_Pos 24 /**< \brief (DMAC_PENDCH) Pending Channel 24 */
+#define DMAC_PENDCH_PENDCH24 (_U_(1) << DMAC_PENDCH_PENDCH24_Pos)
+#define DMAC_PENDCH_PENDCH25_Pos 25 /**< \brief (DMAC_PENDCH) Pending Channel 25 */
+#define DMAC_PENDCH_PENDCH25 (_U_(1) << DMAC_PENDCH_PENDCH25_Pos)
+#define DMAC_PENDCH_PENDCH26_Pos 26 /**< \brief (DMAC_PENDCH) Pending Channel 26 */
+#define DMAC_PENDCH_PENDCH26 (_U_(1) << DMAC_PENDCH_PENDCH26_Pos)
+#define DMAC_PENDCH_PENDCH27_Pos 27 /**< \brief (DMAC_PENDCH) Pending Channel 27 */
+#define DMAC_PENDCH_PENDCH27 (_U_(1) << DMAC_PENDCH_PENDCH27_Pos)
+#define DMAC_PENDCH_PENDCH28_Pos 28 /**< \brief (DMAC_PENDCH) Pending Channel 28 */
+#define DMAC_PENDCH_PENDCH28 (_U_(1) << DMAC_PENDCH_PENDCH28_Pos)
+#define DMAC_PENDCH_PENDCH29_Pos 29 /**< \brief (DMAC_PENDCH) Pending Channel 29 */
+#define DMAC_PENDCH_PENDCH29 (_U_(1) << DMAC_PENDCH_PENDCH29_Pos)
+#define DMAC_PENDCH_PENDCH30_Pos 30 /**< \brief (DMAC_PENDCH) Pending Channel 30 */
+#define DMAC_PENDCH_PENDCH30 (_U_(1) << DMAC_PENDCH_PENDCH30_Pos)
+#define DMAC_PENDCH_PENDCH31_Pos 31 /**< \brief (DMAC_PENDCH) Pending Channel 31 */
+#define DMAC_PENDCH_PENDCH31 (_U_(1) << DMAC_PENDCH_PENDCH31_Pos)
+#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */
+#define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFFFFFFF) << DMAC_PENDCH_PENDCH_Pos)
+#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
+#define DMAC_PENDCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PENDCH) MASK Register */
+
+/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
+ uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
+ uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
+ uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
+ uint32_t :2; /*!< bit: 13..14 Reserved */
+ uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
+ uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_ACTIVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
+#define DMAC_ACTIVE_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
+
+#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos)
+#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos)
+#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos)
+#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos)
+#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos)
+#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
+#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */
+#define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos)
+#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
+#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */
+#define DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos)
+#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
+#define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos)
+#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
+#define DMAC_ACTIVE_MASK _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */
+
+/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_BASEADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
+#define DMAC_BASEADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
+
+#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
+#define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos)
+#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
+#define DMAC_BASEADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */
+
+/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_WRBADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
+#define DMAC_WRBADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
+
+#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
+#define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos)
+#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
+#define DMAC_WRBADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */
+
+/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 32) CHANNEL Channel n Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Channel Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Channel Enable */
+ uint32_t :4; /*!< bit: 2.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Channel Run in Standby */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t TRIGSRC:7; /*!< bit: 8..14 Trigger Source */
+ uint32_t :5; /*!< bit: 15..19 Reserved */
+ uint32_t TRIGACT:2; /*!< bit: 20..21 Trigger Action */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t BURSTLEN:4; /*!< bit: 24..27 Burst Length */
+ uint32_t THRESHOLD:2; /*!< bit: 28..29 FIFO Threshold */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_CHCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel n Control A */
+#define DMAC_CHCTRLA_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CHCTRLA reset_value) Channel n Control A */
+
+#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
+#define DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos)
+#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */
+#define DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos)
+#define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel Run in Standby */
+#define DMAC_CHCTRLA_RUNSTDBY (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos)
+#define DMAC_CHCTRLA_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLA) Trigger Source */
+#define DMAC_CHCTRLA_TRIGSRC_Msk (_U_(0x7F) << DMAC_CHCTRLA_TRIGSRC_Pos)
+#define DMAC_CHCTRLA_TRIGSRC(value) (DMAC_CHCTRLA_TRIGSRC_Msk & ((value) << DMAC_CHCTRLA_TRIGSRC_Pos))
+#define DMAC_CHCTRLA_TRIGSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Only software/event triggers */
+#define DMAC_CHCTRLA_TRIGSRC_DISABLE (DMAC_CHCTRLA_TRIGSRC_DISABLE_Val << DMAC_CHCTRLA_TRIGSRC_Pos)
+#define DMAC_CHCTRLA_TRIGACT_Pos 20 /**< \brief (DMAC_CHCTRLA) Trigger Action */
+#define DMAC_CHCTRLA_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLA_TRIGACT_Pos)
+#define DMAC_CHCTRLA_TRIGACT(value) (DMAC_CHCTRLA_TRIGACT_Msk & ((value) << DMAC_CHCTRLA_TRIGACT_Pos))
+#define DMAC_CHCTRLA_TRIGACT_BLOCK_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) One trigger required for each block transfer */
+#define DMAC_CHCTRLA_TRIGACT_BURST_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) One trigger required for each burst transfer */
+#define DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) One trigger required for each transaction */
+#define DMAC_CHCTRLA_TRIGACT_BLOCK (DMAC_CHCTRLA_TRIGACT_BLOCK_Val << DMAC_CHCTRLA_TRIGACT_Pos)
+#define DMAC_CHCTRLA_TRIGACT_BURST (DMAC_CHCTRLA_TRIGACT_BURST_Val << DMAC_CHCTRLA_TRIGACT_Pos)
+#define DMAC_CHCTRLA_TRIGACT_TRANSACTION (DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLA_TRIGACT_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_Pos 24 /**< \brief (DMAC_CHCTRLA) Burst Length */
+#define DMAC_CHCTRLA_BURSTLEN_Msk (_U_(0xF) << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN(value) (DMAC_CHCTRLA_BURSTLEN_Msk & ((value) << DMAC_CHCTRLA_BURSTLEN_Pos))
+#define DMAC_CHCTRLA_BURSTLEN_SINGLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Single-beat burst length */
+#define DMAC_CHCTRLA_BURSTLEN_2BEAT_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) 2-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_3BEAT_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) 3-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_4BEAT_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) 4-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_5BEAT_Val _U_(0x4) /**< \brief (DMAC_CHCTRLA) 5-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_6BEAT_Val _U_(0x5) /**< \brief (DMAC_CHCTRLA) 6-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_7BEAT_Val _U_(0x6) /**< \brief (DMAC_CHCTRLA) 7-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_8BEAT_Val _U_(0x7) /**< \brief (DMAC_CHCTRLA) 8-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_9BEAT_Val _U_(0x8) /**< \brief (DMAC_CHCTRLA) 9-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_10BEAT_Val _U_(0x9) /**< \brief (DMAC_CHCTRLA) 10-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_11BEAT_Val _U_(0xA) /**< \brief (DMAC_CHCTRLA) 11-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_12BEAT_Val _U_(0xB) /**< \brief (DMAC_CHCTRLA) 12-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_13BEAT_Val _U_(0xC) /**< \brief (DMAC_CHCTRLA) 13-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_14BEAT_Val _U_(0xD) /**< \brief (DMAC_CHCTRLA) 14-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_15BEAT_Val _U_(0xE) /**< \brief (DMAC_CHCTRLA) 15-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_16BEAT_Val _U_(0xF) /**< \brief (DMAC_CHCTRLA) 16-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_SINGLE (DMAC_CHCTRLA_BURSTLEN_SINGLE_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_2BEAT (DMAC_CHCTRLA_BURSTLEN_2BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_3BEAT (DMAC_CHCTRLA_BURSTLEN_3BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_4BEAT (DMAC_CHCTRLA_BURSTLEN_4BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_5BEAT (DMAC_CHCTRLA_BURSTLEN_5BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_6BEAT (DMAC_CHCTRLA_BURSTLEN_6BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_7BEAT (DMAC_CHCTRLA_BURSTLEN_7BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_8BEAT (DMAC_CHCTRLA_BURSTLEN_8BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_9BEAT (DMAC_CHCTRLA_BURSTLEN_9BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_10BEAT (DMAC_CHCTRLA_BURSTLEN_10BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_11BEAT (DMAC_CHCTRLA_BURSTLEN_11BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_12BEAT (DMAC_CHCTRLA_BURSTLEN_12BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_13BEAT (DMAC_CHCTRLA_BURSTLEN_13BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_14BEAT (DMAC_CHCTRLA_BURSTLEN_14BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_15BEAT (DMAC_CHCTRLA_BURSTLEN_15BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_16BEAT (DMAC_CHCTRLA_BURSTLEN_16BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_THRESHOLD_Pos 28 /**< \brief (DMAC_CHCTRLA) FIFO Threshold */
+#define DMAC_CHCTRLA_THRESHOLD_Msk (_U_(0x3) << DMAC_CHCTRLA_THRESHOLD_Pos)
+#define DMAC_CHCTRLA_THRESHOLD(value) (DMAC_CHCTRLA_THRESHOLD_Msk & ((value) << DMAC_CHCTRLA_THRESHOLD_Pos))
+#define DMAC_CHCTRLA_THRESHOLD_1BEAT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Destination write starts after each beat source address read */
+#define DMAC_CHCTRLA_THRESHOLD_2BEATS_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) Destination write starts after 2-beats source address read */
+#define DMAC_CHCTRLA_THRESHOLD_4BEATS_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) Destination write starts after 4-beats source address read */
+#define DMAC_CHCTRLA_THRESHOLD_8BEATS_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) Destination write starts after 8-beats source address read */
+#define DMAC_CHCTRLA_THRESHOLD_1BEAT (DMAC_CHCTRLA_THRESHOLD_1BEAT_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
+#define DMAC_CHCTRLA_THRESHOLD_2BEATS (DMAC_CHCTRLA_THRESHOLD_2BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
+#define DMAC_CHCTRLA_THRESHOLD_4BEATS (DMAC_CHCTRLA_THRESHOLD_4BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
+#define DMAC_CHCTRLA_THRESHOLD_8BEATS (DMAC_CHCTRLA_THRESHOLD_8BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
+#define DMAC_CHCTRLA_MASK _U_(0x3F307F43) /**< \brief (DMAC_CHCTRLA) MASK Register */
+
+/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 8) CHANNEL Channel n Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMD:2; /*!< bit: 0.. 1 Software Command */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel n Control B */
+#define DMAC_CHCTRLB_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHCTRLB reset_value) Channel n Control B */
+
+#define DMAC_CHCTRLB_CMD_Pos 0 /**< \brief (DMAC_CHCTRLB) Software Command */
+#define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
+#define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */
+#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_MASK _U_(0x03) /**< \brief (DMAC_CHCTRLB) MASK Register */
+
+/* -------- DMAC_CHPRILVL : (DMAC Offset: 0x45) (R/W 8) CHANNEL Channel n Priority Level -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PRILVL:2; /*!< bit: 0.. 1 Channel Priority Level */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHPRILVL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHPRILVL_OFFSET 0x45 /**< \brief (DMAC_CHPRILVL offset) Channel n Priority Level */
+#define DMAC_CHPRILVL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHPRILVL reset_value) Channel n Priority Level */
+
+#define DMAC_CHPRILVL_PRILVL_Pos 0 /**< \brief (DMAC_CHPRILVL) Channel Priority Level */
+#define DMAC_CHPRILVL_PRILVL_Msk (_U_(0x3) << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL(value) (DMAC_CHPRILVL_PRILVL_Msk & ((value) << DMAC_CHPRILVL_PRILVL_Pos))
+#define DMAC_CHPRILVL_PRILVL_LVL0_Val _U_(0x0) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 0 (Lowest Level) */
+#define DMAC_CHPRILVL_PRILVL_LVL1_Val _U_(0x1) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 1 */
+#define DMAC_CHPRILVL_PRILVL_LVL2_Val _U_(0x2) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 2 */
+#define DMAC_CHPRILVL_PRILVL_LVL3_Val _U_(0x3) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 3 */
+#define DMAC_CHPRILVL_PRILVL_LVL4_Val _U_(0x4) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 4 */
+#define DMAC_CHPRILVL_PRILVL_LVL5_Val _U_(0x5) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 5 */
+#define DMAC_CHPRILVL_PRILVL_LVL6_Val _U_(0x6) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 6 */
+#define DMAC_CHPRILVL_PRILVL_LVL7_Val _U_(0x7) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 7 (Highest Level) */
+#define DMAC_CHPRILVL_PRILVL_LVL0 (DMAC_CHPRILVL_PRILVL_LVL0_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL1 (DMAC_CHPRILVL_PRILVL_LVL1_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL2 (DMAC_CHPRILVL_PRILVL_LVL2_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL3 (DMAC_CHPRILVL_PRILVL_LVL3_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL4 (DMAC_CHPRILVL_PRILVL_LVL4_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL5 (DMAC_CHPRILVL_PRILVL_LVL5_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL6 (DMAC_CHPRILVL_PRILVL_LVL6_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL7 (DMAC_CHPRILVL_PRILVL_LVL7_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_MASK _U_(0x03) /**< \brief (DMAC_CHPRILVL) MASK Register */
+
+/* -------- DMAC_CHEVCTRL : (DMAC Offset: 0x46) (R/W 8) CHANNEL Channel n Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EVACT:3; /*!< bit: 0.. 2 Channel Event Input Action */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t EVOMODE:2; /*!< bit: 4.. 5 Channel Event Output Mode */
+ uint8_t EVIE:1; /*!< bit: 6 Channel Event Input Enable */
+ uint8_t EVOE:1; /*!< bit: 7 Channel Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHEVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHEVCTRL_OFFSET 0x46 /**< \brief (DMAC_CHEVCTRL offset) Channel n Event Control */
+#define DMAC_CHEVCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHEVCTRL reset_value) Channel n Event Control */
+
+#define DMAC_CHEVCTRL_EVACT_Pos 0 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Action */
+#define DMAC_CHEVCTRL_EVACT_Msk (_U_(0x7) << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT(value) (DMAC_CHEVCTRL_EVACT_Msk & ((value) << DMAC_CHEVCTRL_EVACT_Pos))
+#define DMAC_CHEVCTRL_EVACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) No action */
+#define DMAC_CHEVCTRL_EVACT_TRIG_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Transfer and periodic transfer trigger */
+#define DMAC_CHEVCTRL_EVACT_CTRIG_Val _U_(0x2) /**< \brief (DMAC_CHEVCTRL) Conditional transfer trigger */
+#define DMAC_CHEVCTRL_EVACT_CBLOCK_Val _U_(0x3) /**< \brief (DMAC_CHEVCTRL) Conditional block transfer */
+#define DMAC_CHEVCTRL_EVACT_SUSPEND_Val _U_(0x4) /**< \brief (DMAC_CHEVCTRL) Channel suspend operation */
+#define DMAC_CHEVCTRL_EVACT_RESUME_Val _U_(0x5) /**< \brief (DMAC_CHEVCTRL) Channel resume operation */
+#define DMAC_CHEVCTRL_EVACT_SSKIP_Val _U_(0x6) /**< \brief (DMAC_CHEVCTRL) Skip next block suspend action */
+#define DMAC_CHEVCTRL_EVACT_INCPRI_Val _U_(0x7) /**< \brief (DMAC_CHEVCTRL) Increase priority */
+#define DMAC_CHEVCTRL_EVACT_NOACT (DMAC_CHEVCTRL_EVACT_NOACT_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_TRIG (DMAC_CHEVCTRL_EVACT_TRIG_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_CTRIG (DMAC_CHEVCTRL_EVACT_CTRIG_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_CBLOCK (DMAC_CHEVCTRL_EVACT_CBLOCK_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_SUSPEND (DMAC_CHEVCTRL_EVACT_SUSPEND_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_RESUME (DMAC_CHEVCTRL_EVACT_RESUME_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_SSKIP (DMAC_CHEVCTRL_EVACT_SSKIP_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_INCPRI (DMAC_CHEVCTRL_EVACT_INCPRI_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVOMODE_Pos 4 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Mode */
+#define DMAC_CHEVCTRL_EVOMODE_Msk (_U_(0x3) << DMAC_CHEVCTRL_EVOMODE_Pos)
+#define DMAC_CHEVCTRL_EVOMODE(value) (DMAC_CHEVCTRL_EVOMODE_Msk & ((value) << DMAC_CHEVCTRL_EVOMODE_Pos))
+#define DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) Block event output selection. Refer to BTCTRL.EVOSEL for available selections. */
+#define DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Ongoing trigger action */
+#define DMAC_CHEVCTRL_EVOMODE_DEFAULT (DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val << DMAC_CHEVCTRL_EVOMODE_Pos)
+#define DMAC_CHEVCTRL_EVOMODE_TRIGACT (DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val << DMAC_CHEVCTRL_EVOMODE_Pos)
+#define DMAC_CHEVCTRL_EVIE_Pos 6 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Enable */
+#define DMAC_CHEVCTRL_EVIE (_U_(0x1) << DMAC_CHEVCTRL_EVIE_Pos)
+#define DMAC_CHEVCTRL_EVOE_Pos 7 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Enable */
+#define DMAC_CHEVCTRL_EVOE (_U_(0x1) << DMAC_CHEVCTRL_EVOE_Pos)
+#define DMAC_CHEVCTRL_MASK _U_(0xF7) /**< \brief (DMAC_CHEVCTRL) MASK Register */
+
+/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel n Interrupt Enable Clear */
+#define DMAC_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */
+
+#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */
+#define DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos)
+#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos)
+#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos)
+#define DMAC_CHINTENCLR_MASK _U_(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */
+
+/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel n Interrupt Enable Set */
+#define DMAC_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel n Interrupt Enable Set */
+
+#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */
+#define DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos)
+#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos)
+#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos)
+#define DMAC_CHINTENSET_MASK _U_(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */
+
+/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
+ __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
+ __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
+ __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */
+#define DMAC_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */
+
+#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */
+#define DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos)
+#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */
+#define DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos)
+#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
+#define DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos)
+#define DMAC_CHINTFLAG_MASK _U_(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */
+
+/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/W 8) CHANNEL Channel n Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PEND:1; /*!< bit: 0 Channel Pending */
+ uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
+ uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */
+ uint8_t CRCERR:1; /*!< bit: 3 Channel CRC Error */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel n Status */
+#define DMAC_CHSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel n Status */
+
+#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */
+#define DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos)
+#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */
+#define DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos)
+#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */
+#define DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos)
+#define DMAC_CHSTATUS_CRCERR_Pos 3 /**< \brief (DMAC_CHSTATUS) Channel CRC Error */
+#define DMAC_CHSTATUS_CRCERR (_U_(0x1) << DMAC_CHSTATUS_CRCERR_Pos)
+#define DMAC_CHSTATUS_MASK _U_(0x0F) /**< \brief (DMAC_CHSTATUS) MASK Register */
+
+/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
+ uint16_t EVOSEL:2; /*!< bit: 1.. 2 Block Event Output Selection */
+ uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
+ uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
+ uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
+ uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
+ uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_BTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
+#define DMAC_BTCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
+
+#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */
+#define DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos)
+#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Block Event Output Selection */
+#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
+#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */
+#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Block event strobe */
+#define DMAC_BTCTRL_EVOSEL_BURST_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Burst event strobe */
+#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */
+#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
+#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */
+#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */
+#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
+#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
+#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */
+#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
+#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */
+#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */
+#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */
+#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
+#define DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos)
+#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
+#define DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos)
+#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */
+#define DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
+#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
+#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
+#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
+#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 1 */
+#define DMAC_BTCTRL_STEPSIZE_X2_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 2 */
+#define DMAC_BTCTRL_STEPSIZE_X4_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 4 */
+#define DMAC_BTCTRL_STEPSIZE_X8_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 8 */
+#define DMAC_BTCTRL_STEPSIZE_X16_Val _U_(0x4) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 16 */
+#define DMAC_BTCTRL_STEPSIZE_X32_Val _U_(0x5) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 32 */
+#define DMAC_BTCTRL_STEPSIZE_X64_Val _U_(0x6) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 64 */
+#define DMAC_BTCTRL_STEPSIZE_X128_Val _U_(0x7) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 128 */
+#define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_MASK _U_(0xFF1F) /**< \brief (DMAC_BTCTRL) MASK Register */
+
+/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_BTCNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCNT_OFFSET 0x02 /**< \brief (DMAC_BTCNT offset) Block Transfer Count */
+#define DMAC_BTCNT_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCNT reset_value) Block Transfer Count */
+
+#define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */
+#define DMAC_BTCNT_BTCNT_Msk (_U_(0xFFFF) << DMAC_BTCNT_BTCNT_Pos)
+#define DMAC_BTCNT_BTCNT(value) (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
+#define DMAC_BTCNT_MASK _U_(0xFFFF) /**< \brief (DMAC_BTCNT) MASK Register */
+
+/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_SRCADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SRCADDR_OFFSET 0x04 /**< \brief (DMAC_SRCADDR offset) Block Transfer Source Address */
+#define DMAC_SRCADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SRCADDR reset_value) Block Transfer Source Address */
+
+#define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */
+#define DMAC_SRCADDR_SRCADDR_Msk (_U_(0xFFFFFFFF) << DMAC_SRCADDR_SRCADDR_Pos)
+#define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
+#define DMAC_SRCADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_SRCADDR) MASK Register */
+
+/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // CRC mode
+ uint32_t CHKINIT:32; /*!< bit: 0..31 CRC Checksum Initial Value */
+ } CRC; /*!< Structure used for CRC */
+ struct {
+ uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_DSTADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DSTADDR_OFFSET 0x08 /**< \brief (DMAC_DSTADDR offset) Block Transfer Destination Address */
+
+// CRC mode
+#define DMAC_DSTADDR_CRC_CHKINIT_Pos 0 /**< \brief (DMAC_DSTADDR_CRC) CRC Checksum Initial Value */
+#define DMAC_DSTADDR_CRC_CHKINIT_Msk (_U_(0xFFFFFFFF) << DMAC_DSTADDR_CRC_CHKINIT_Pos)
+#define DMAC_DSTADDR_CRC_CHKINIT(value) (DMAC_DSTADDR_CRC_CHKINIT_Msk & ((value) << DMAC_DSTADDR_CRC_CHKINIT_Pos))
+#define DMAC_DSTADDR_CRC_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_DSTADDR_CRC) MASK Register */
+
+#define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
+#define DMAC_DSTADDR_DSTADDR_Msk (_U_(0xFFFFFFFF) << DMAC_DSTADDR_DSTADDR_Pos)
+#define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
+#define DMAC_DSTADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_DSTADDR) MASK Register */
+
+/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_DESCADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DESCADDR_OFFSET 0x0C /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */
+
+#define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
+#define DMAC_DESCADDR_DESCADDR_Msk (_U_(0xFFFFFFFF) << DMAC_DESCADDR_DESCADDR_Pos)
+#define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
+#define DMAC_DESCADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_DESCADDR) MASK Register */
+
+/** \brief DmacChannel hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x00 (R/W 32) Channel n Control A */
+ __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x04 (R/W 8) Channel n Control B */
+ __IO DMAC_CHPRILVL_Type CHPRILVL; /**< \brief Offset: 0x05 (R/W 8) Channel n Priority Level */
+ __IO DMAC_CHEVCTRL_Type CHEVCTRL; /**< \brief Offset: 0x06 (R/W 8) Channel n Event Control */
+ RoReg8 Reserved1[0x5];
+ __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x0C (R/W 8) Channel n Interrupt Enable Clear */
+ __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x0D (R/W 8) Channel n Interrupt Enable Set */
+ __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x0E (R/W 8) Channel n Interrupt Flag Status and Clear */
+ __IO DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0F (R/W 8) Channel n Status */
+} DmacChannel;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief DMAC APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
+ __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
+ __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
+ __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
+ __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
+ __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
+ RoReg8 Reserved1[0x2];
+ __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
+ __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
+ RoReg8 Reserved2[0x8];
+ __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
+ RoReg8 Reserved3[0x2];
+ __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
+ __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
+ __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
+ __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
+ __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
+ __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
+ RoReg8 Reserved4[0x4];
+ DmacChannel Channel[32]; /**< \brief Offset: 0x40 DmacChannel groups [CH_NUM] */
+} Dmac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief DMAC Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
+ __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
+ __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
+ __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
+ __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
+} DmacDescriptor
+#ifdef __GNUC__
+ __attribute__ ((aligned (8)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#ifdef __GNUC__
+ #define SECTION_DMAC_DESCRIPTOR __attribute__ ((section(".hsram")))
+#elif defined(__ICCARM__)
+ #define SECTION_DMAC_DESCRIPTOR @".hsram"
+#endif
+
+/*@}*/
+
+#endif /* _SAME54_DMAC_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/eic.h b/sysmoOCTSIM/include/component/eic.h
index f11bcae..6c184f8 100644
--- a/sysmoOCTSIM/include/component/eic.h
+++ b/sysmoOCTSIM/include/component/eic.h
@@ -1,497 +1,497 @@
-/**
- * \file
- *
- * \brief Component description for EIC
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_EIC_COMPONENT_
-#define _SAME54_EIC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR EIC */
-/* ========================================================================== */
-/** \addtogroup SAME54_EIC External Interrupt Controller */
-/*@{*/
-
-#define EIC_U2254
-#define REV_EIC 0x300
-
-/* -------- EIC_CTRLA : (EIC Offset: 0x00) (R/W 8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t CKSEL:1; /*!< bit: 4 Clock Selection */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} EIC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_CTRLA_OFFSET 0x00 /**< \brief (EIC_CTRLA offset) Control A */
-#define EIC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (EIC_CTRLA reset_value) Control A */
-
-#define EIC_CTRLA_SWRST_Pos 0 /**< \brief (EIC_CTRLA) Software Reset */
-#define EIC_CTRLA_SWRST (_U_(0x1) << EIC_CTRLA_SWRST_Pos)
-#define EIC_CTRLA_ENABLE_Pos 1 /**< \brief (EIC_CTRLA) Enable */
-#define EIC_CTRLA_ENABLE (_U_(0x1) << EIC_CTRLA_ENABLE_Pos)
-#define EIC_CTRLA_CKSEL_Pos 4 /**< \brief (EIC_CTRLA) Clock Selection */
-#define EIC_CTRLA_CKSEL (_U_(0x1) << EIC_CTRLA_CKSEL_Pos)
-#define EIC_CTRLA_MASK _U_(0x13) /**< \brief (EIC_CTRLA) MASK Register */
-
-/* -------- EIC_NMICTRL : (EIC Offset: 0x01) (R/W 8) Non-Maskable Interrupt Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense Configuration */
- uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
- uint8_t NMIASYNCH:1; /*!< bit: 4 Asynchronous Edge Detection Mode */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} EIC_NMICTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_NMICTRL_OFFSET 0x01 /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
-#define EIC_NMICTRL_RESETVALUE _U_(0x00) /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
-
-#define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense Configuration */
-#define EIC_NMICTRL_NMISENSE_Msk (_U_(0x7) << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
-#define EIC_NMICTRL_NMISENSE_NONE_Val _U_(0x0) /**< \brief (EIC_NMICTRL) No detection */
-#define EIC_NMICTRL_NMISENSE_RISE_Val _U_(0x1) /**< \brief (EIC_NMICTRL) Rising-edge detection */
-#define EIC_NMICTRL_NMISENSE_FALL_Val _U_(0x2) /**< \brief (EIC_NMICTRL) Falling-edge detection */
-#define EIC_NMICTRL_NMISENSE_BOTH_Val _U_(0x3) /**< \brief (EIC_NMICTRL) Both-edges detection */
-#define EIC_NMICTRL_NMISENSE_HIGH_Val _U_(0x4) /**< \brief (EIC_NMICTRL) High-level detection */
-#define EIC_NMICTRL_NMISENSE_LOW_Val _U_(0x5) /**< \brief (EIC_NMICTRL) Low-level detection */
-#define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
-#define EIC_NMICTRL_NMIFILTEN (_U_(0x1) << EIC_NMICTRL_NMIFILTEN_Pos)
-#define EIC_NMICTRL_NMIASYNCH_Pos 4 /**< \brief (EIC_NMICTRL) Asynchronous Edge Detection Mode */
-#define EIC_NMICTRL_NMIASYNCH (_U_(0x1) << EIC_NMICTRL_NMIASYNCH_Pos)
-#define EIC_NMICTRL_MASK _U_(0x1F) /**< \brief (EIC_NMICTRL) MASK Register */
-
-/* -------- EIC_NMIFLAG : (EIC Offset: 0x02) (R/W 16) Non-Maskable Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
- uint16_t :15; /*!< bit: 1..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} EIC_NMIFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_NMIFLAG_OFFSET 0x02 /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
-#define EIC_NMIFLAG_RESETVALUE _U_(0x0000) /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
-
-#define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
-#define EIC_NMIFLAG_NMI (_U_(0x1) << EIC_NMIFLAG_NMI_Pos)
-#define EIC_NMIFLAG_MASK _U_(0x0001) /**< \brief (EIC_NMIFLAG) MASK Register */
-
-/* -------- EIC_SYNCBUSY : (EIC Offset: 0x04) (R/ 32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy Status */
- uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy Status */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} EIC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_SYNCBUSY_OFFSET 0x04 /**< \brief (EIC_SYNCBUSY offset) Synchronization Busy */
-#define EIC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (EIC_SYNCBUSY reset_value) Synchronization Busy */
-
-#define EIC_SYNCBUSY_SWRST_Pos 0 /**< \brief (EIC_SYNCBUSY) Software Reset Synchronization Busy Status */
-#define EIC_SYNCBUSY_SWRST (_U_(0x1) << EIC_SYNCBUSY_SWRST_Pos)
-#define EIC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (EIC_SYNCBUSY) Enable Synchronization Busy Status */
-#define EIC_SYNCBUSY_ENABLE (_U_(0x1) << EIC_SYNCBUSY_ENABLE_Pos)
-#define EIC_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (EIC_SYNCBUSY) MASK Register */
-
-/* -------- EIC_EVCTRL : (EIC Offset: 0x08) (R/W 32) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt Event Output Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} EIC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_EVCTRL_OFFSET 0x08 /**< \brief (EIC_EVCTRL offset) Event Control */
-#define EIC_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (EIC_EVCTRL reset_value) Event Control */
-
-#define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO_Msk (_U_(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos)
-#define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
-#define EIC_EVCTRL_MASK _U_(0x0000FFFF) /**< \brief (EIC_EVCTRL) MASK Register */
-
-/* -------- EIC_INTENCLR : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} EIC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_INTENCLR_OFFSET 0x0C /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
-#define EIC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt Enable */
-#define EIC_INTENCLR_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENCLR_EXTINT_Pos)
-#define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
-#define EIC_INTENCLR_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTENCLR) MASK Register */
-
-/* -------- EIC_INTENSET : (EIC Offset: 0x10) (R/W 32) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} EIC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_INTENSET_OFFSET 0x10 /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
-#define EIC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
-
-#define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt Enable */
-#define EIC_INTENSET_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENSET_EXTINT_Pos)
-#define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
-#define EIC_INTENSET_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTENSET) MASK Register */
-
-/* -------- EIC_INTFLAG : (EIC Offset: 0x14) (R/W 32) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt */
- __I uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} EIC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_INTFLAG_OFFSET 0x14 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define EIC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt */
-#define EIC_INTFLAG_EXTINT_Msk (_U_(0xFFFF) << EIC_INTFLAG_EXTINT_Pos)
-#define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
-#define EIC_INTFLAG_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTFLAG) MASK Register */
-
-/* -------- EIC_ASYNCH : (EIC Offset: 0x18) (R/W 32) External Interrupt Asynchronous Mode -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ASYNCH:16; /*!< bit: 0..15 Asynchronous Edge Detection Mode */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} EIC_ASYNCH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_ASYNCH_OFFSET 0x18 /**< \brief (EIC_ASYNCH offset) External Interrupt Asynchronous Mode */
-#define EIC_ASYNCH_RESETVALUE _U_(0x00000000) /**< \brief (EIC_ASYNCH reset_value) External Interrupt Asynchronous Mode */
-
-#define EIC_ASYNCH_ASYNCH_Pos 0 /**< \brief (EIC_ASYNCH) Asynchronous Edge Detection Mode */
-#define EIC_ASYNCH_ASYNCH_Msk (_U_(0xFFFF) << EIC_ASYNCH_ASYNCH_Pos)
-#define EIC_ASYNCH_ASYNCH(value) (EIC_ASYNCH_ASYNCH_Msk & ((value) << EIC_ASYNCH_ASYNCH_Pos))
-#define EIC_ASYNCH_MASK _U_(0x0000FFFF) /**< \brief (EIC_ASYNCH) MASK Register */
-
-/* -------- EIC_CONFIG : (EIC Offset: 0x1C) (R/W 32) External Interrupt Sense Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense Configuration 0 */
- uint32_t FILTEN0:1; /*!< bit: 3 Filter Enable 0 */
- uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense Configuration 1 */
- uint32_t FILTEN1:1; /*!< bit: 7 Filter Enable 1 */
- uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense Configuration 2 */
- uint32_t FILTEN2:1; /*!< bit: 11 Filter Enable 2 */
- uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense Configuration 3 */
- uint32_t FILTEN3:1; /*!< bit: 15 Filter Enable 3 */
- uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense Configuration 4 */
- uint32_t FILTEN4:1; /*!< bit: 19 Filter Enable 4 */
- uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense Configuration 5 */
- uint32_t FILTEN5:1; /*!< bit: 23 Filter Enable 5 */
- uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense Configuration 6 */
- uint32_t FILTEN6:1; /*!< bit: 27 Filter Enable 6 */
- uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense Configuration 7 */
- uint32_t FILTEN7:1; /*!< bit: 31 Filter Enable 7 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} EIC_CONFIG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_CONFIG_OFFSET 0x1C /**< \brief (EIC_CONFIG offset) External Interrupt Sense Configuration */
-#define EIC_CONFIG_RESETVALUE _U_(0x00000000) /**< \brief (EIC_CONFIG reset_value) External Interrupt Sense Configuration */
-
-#define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense Configuration 0 */
-#define EIC_CONFIG_SENSE0_Msk (_U_(0x7) << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
-#define EIC_CONFIG_SENSE0_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
-#define EIC_CONFIG_SENSE0_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
-#define EIC_CONFIG_SENSE0_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
-#define EIC_CONFIG_SENSE0_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
-#define EIC_CONFIG_SENSE0_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
-#define EIC_CONFIG_SENSE0_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter Enable 0 */
-#define EIC_CONFIG_FILTEN0 (_U_(0x1) << EIC_CONFIG_FILTEN0_Pos)
-#define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense Configuration 1 */
-#define EIC_CONFIG_SENSE1_Msk (_U_(0x7) << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
-#define EIC_CONFIG_SENSE1_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
-#define EIC_CONFIG_SENSE1_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
-#define EIC_CONFIG_SENSE1_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
-#define EIC_CONFIG_SENSE1_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
-#define EIC_CONFIG_SENSE1_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
-#define EIC_CONFIG_SENSE1_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter Enable 1 */
-#define EIC_CONFIG_FILTEN1 (_U_(0x1) << EIC_CONFIG_FILTEN1_Pos)
-#define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense Configuration 2 */
-#define EIC_CONFIG_SENSE2_Msk (_U_(0x7) << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
-#define EIC_CONFIG_SENSE2_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
-#define EIC_CONFIG_SENSE2_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
-#define EIC_CONFIG_SENSE2_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
-#define EIC_CONFIG_SENSE2_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
-#define EIC_CONFIG_SENSE2_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
-#define EIC_CONFIG_SENSE2_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter Enable 2 */
-#define EIC_CONFIG_FILTEN2 (_U_(0x1) << EIC_CONFIG_FILTEN2_Pos)
-#define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense Configuration 3 */
-#define EIC_CONFIG_SENSE3_Msk (_U_(0x7) << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
-#define EIC_CONFIG_SENSE3_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
-#define EIC_CONFIG_SENSE3_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
-#define EIC_CONFIG_SENSE3_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
-#define EIC_CONFIG_SENSE3_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
-#define EIC_CONFIG_SENSE3_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
-#define EIC_CONFIG_SENSE3_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter Enable 3 */
-#define EIC_CONFIG_FILTEN3 (_U_(0x1) << EIC_CONFIG_FILTEN3_Pos)
-#define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense Configuration 4 */
-#define EIC_CONFIG_SENSE4_Msk (_U_(0x7) << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_SENSE4(value) (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
-#define EIC_CONFIG_SENSE4_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
-#define EIC_CONFIG_SENSE4_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
-#define EIC_CONFIG_SENSE4_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
-#define EIC_CONFIG_SENSE4_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
-#define EIC_CONFIG_SENSE4_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
-#define EIC_CONFIG_SENSE4_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter Enable 4 */
-#define EIC_CONFIG_FILTEN4 (_U_(0x1) << EIC_CONFIG_FILTEN4_Pos)
-#define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense Configuration 5 */
-#define EIC_CONFIG_SENSE5_Msk (_U_(0x7) << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_SENSE5(value) (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
-#define EIC_CONFIG_SENSE5_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
-#define EIC_CONFIG_SENSE5_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
-#define EIC_CONFIG_SENSE5_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
-#define EIC_CONFIG_SENSE5_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
-#define EIC_CONFIG_SENSE5_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
-#define EIC_CONFIG_SENSE5_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter Enable 5 */
-#define EIC_CONFIG_FILTEN5 (_U_(0x1) << EIC_CONFIG_FILTEN5_Pos)
-#define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense Configuration 6 */
-#define EIC_CONFIG_SENSE6_Msk (_U_(0x7) << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_SENSE6(value) (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
-#define EIC_CONFIG_SENSE6_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
-#define EIC_CONFIG_SENSE6_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
-#define EIC_CONFIG_SENSE6_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
-#define EIC_CONFIG_SENSE6_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
-#define EIC_CONFIG_SENSE6_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
-#define EIC_CONFIG_SENSE6_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter Enable 6 */
-#define EIC_CONFIG_FILTEN6 (_U_(0x1) << EIC_CONFIG_FILTEN6_Pos)
-#define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense Configuration 7 */
-#define EIC_CONFIG_SENSE7_Msk (_U_(0x7) << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_SENSE7(value) (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
-#define EIC_CONFIG_SENSE7_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
-#define EIC_CONFIG_SENSE7_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
-#define EIC_CONFIG_SENSE7_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
-#define EIC_CONFIG_SENSE7_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
-#define EIC_CONFIG_SENSE7_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
-#define EIC_CONFIG_SENSE7_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter Enable 7 */
-#define EIC_CONFIG_FILTEN7 (_U_(0x1) << EIC_CONFIG_FILTEN7_Pos)
-#define EIC_CONFIG_MASK _U_(0xFFFFFFFF) /**< \brief (EIC_CONFIG) MASK Register */
-
-/* -------- EIC_DEBOUNCEN : (EIC Offset: 0x30) (R/W 32) Debouncer Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DEBOUNCEN:16; /*!< bit: 0..15 Debouncer Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} EIC_DEBOUNCEN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_DEBOUNCEN_OFFSET 0x30 /**< \brief (EIC_DEBOUNCEN offset) Debouncer Enable */
-#define EIC_DEBOUNCEN_RESETVALUE _U_(0x00000000) /**< \brief (EIC_DEBOUNCEN reset_value) Debouncer Enable */
-
-#define EIC_DEBOUNCEN_DEBOUNCEN_Pos 0 /**< \brief (EIC_DEBOUNCEN) Debouncer Enable */
-#define EIC_DEBOUNCEN_DEBOUNCEN_Msk (_U_(0xFFFF) << EIC_DEBOUNCEN_DEBOUNCEN_Pos)
-#define EIC_DEBOUNCEN_DEBOUNCEN(value) (EIC_DEBOUNCEN_DEBOUNCEN_Msk & ((value) << EIC_DEBOUNCEN_DEBOUNCEN_Pos))
-#define EIC_DEBOUNCEN_MASK _U_(0x0000FFFF) /**< \brief (EIC_DEBOUNCEN) MASK Register */
-
-/* -------- EIC_DPRESCALER : (EIC Offset: 0x34) (R/W 32) Debouncer Prescaler -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t PRESCALER0:3; /*!< bit: 0.. 2 Debouncer Prescaler */
- uint32_t STATES0:1; /*!< bit: 3 Debouncer number of states */
- uint32_t PRESCALER1:3; /*!< bit: 4.. 6 Debouncer Prescaler */
- uint32_t STATES1:1; /*!< bit: 7 Debouncer number of states */
- uint32_t :8; /*!< bit: 8..15 Reserved */
- uint32_t TICKON:1; /*!< bit: 16 Pin Sampler frequency selection */
- uint32_t :15; /*!< bit: 17..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} EIC_DPRESCALER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_DPRESCALER_OFFSET 0x34 /**< \brief (EIC_DPRESCALER offset) Debouncer Prescaler */
-#define EIC_DPRESCALER_RESETVALUE _U_(0x00000000) /**< \brief (EIC_DPRESCALER reset_value) Debouncer Prescaler */
-
-#define EIC_DPRESCALER_PRESCALER0_Pos 0 /**< \brief (EIC_DPRESCALER) Debouncer Prescaler */
-#define EIC_DPRESCALER_PRESCALER0_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER0_Pos)
-#define EIC_DPRESCALER_PRESCALER0(value) (EIC_DPRESCALER_PRESCALER0_Msk & ((value) << EIC_DPRESCALER_PRESCALER0_Pos))
-#define EIC_DPRESCALER_STATES0_Pos 3 /**< \brief (EIC_DPRESCALER) Debouncer number of states */
-#define EIC_DPRESCALER_STATES0 (_U_(0x1) << EIC_DPRESCALER_STATES0_Pos)
-#define EIC_DPRESCALER_PRESCALER1_Pos 4 /**< \brief (EIC_DPRESCALER) Debouncer Prescaler */
-#define EIC_DPRESCALER_PRESCALER1_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER1_Pos)
-#define EIC_DPRESCALER_PRESCALER1(value) (EIC_DPRESCALER_PRESCALER1_Msk & ((value) << EIC_DPRESCALER_PRESCALER1_Pos))
-#define EIC_DPRESCALER_STATES1_Pos 7 /**< \brief (EIC_DPRESCALER) Debouncer number of states */
-#define EIC_DPRESCALER_STATES1 (_U_(0x1) << EIC_DPRESCALER_STATES1_Pos)
-#define EIC_DPRESCALER_TICKON_Pos 16 /**< \brief (EIC_DPRESCALER) Pin Sampler frequency selection */
-#define EIC_DPRESCALER_TICKON (_U_(0x1) << EIC_DPRESCALER_TICKON_Pos)
-#define EIC_DPRESCALER_MASK _U_(0x000100FF) /**< \brief (EIC_DPRESCALER) MASK Register */
-
-/* -------- EIC_PINSTATE : (EIC Offset: 0x38) (R/ 32) Pin State -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t PINSTATE:16; /*!< bit: 0..15 Pin State */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} EIC_PINSTATE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_PINSTATE_OFFSET 0x38 /**< \brief (EIC_PINSTATE offset) Pin State */
-#define EIC_PINSTATE_RESETVALUE _U_(0x00000000) /**< \brief (EIC_PINSTATE reset_value) Pin State */
-
-#define EIC_PINSTATE_PINSTATE_Pos 0 /**< \brief (EIC_PINSTATE) Pin State */
-#define EIC_PINSTATE_PINSTATE_Msk (_U_(0xFFFF) << EIC_PINSTATE_PINSTATE_Pos)
-#define EIC_PINSTATE_PINSTATE(value) (EIC_PINSTATE_PINSTATE_Msk & ((value) << EIC_PINSTATE_PINSTATE_Pos))
-#define EIC_PINSTATE_MASK _U_(0x0000FFFF) /**< \brief (EIC_PINSTATE) MASK Register */
-
-/** \brief EIC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO EIC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
- __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x01 (R/W 8) Non-Maskable Interrupt Control */
- __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x02 (R/W 16) Non-Maskable Interrupt Flag Status and Clear */
- __I EIC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Synchronization Busy */
- __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x08 (R/W 32) Event Control */
- __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Clear */
- __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Set */
- __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 32) Interrupt Flag Status and Clear */
- __IO EIC_ASYNCH_Type ASYNCH; /**< \brief Offset: 0x18 (R/W 32) External Interrupt Asynchronous Mode */
- __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x1C (R/W 32) External Interrupt Sense Configuration */
- RoReg8 Reserved1[0xC];
- __IO EIC_DEBOUNCEN_Type DEBOUNCEN; /**< \brief Offset: 0x30 (R/W 32) Debouncer Enable */
- __IO EIC_DPRESCALER_Type DPRESCALER; /**< \brief Offset: 0x34 (R/W 32) Debouncer Prescaler */
- __I EIC_PINSTATE_Type PINSTATE; /**< \brief Offset: 0x38 (R/ 32) Pin State */
-} Eic;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_EIC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for EIC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_EIC_COMPONENT_
+#define _SAME54_EIC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR EIC */
+/* ========================================================================== */
+/** \addtogroup SAME54_EIC External Interrupt Controller */
+/*@{*/
+
+#define EIC_U2254
+#define REV_EIC 0x300
+
+/* -------- EIC_CTRLA : (EIC Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t CKSEL:1; /*!< bit: 4 Clock Selection */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EIC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CTRLA_OFFSET 0x00 /**< \brief (EIC_CTRLA offset) Control A */
+#define EIC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (EIC_CTRLA reset_value) Control A */
+
+#define EIC_CTRLA_SWRST_Pos 0 /**< \brief (EIC_CTRLA) Software Reset */
+#define EIC_CTRLA_SWRST (_U_(0x1) << EIC_CTRLA_SWRST_Pos)
+#define EIC_CTRLA_ENABLE_Pos 1 /**< \brief (EIC_CTRLA) Enable */
+#define EIC_CTRLA_ENABLE (_U_(0x1) << EIC_CTRLA_ENABLE_Pos)
+#define EIC_CTRLA_CKSEL_Pos 4 /**< \brief (EIC_CTRLA) Clock Selection */
+#define EIC_CTRLA_CKSEL (_U_(0x1) << EIC_CTRLA_CKSEL_Pos)
+#define EIC_CTRLA_MASK _U_(0x13) /**< \brief (EIC_CTRLA) MASK Register */
+
+/* -------- EIC_NMICTRL : (EIC Offset: 0x01) (R/W 8) Non-Maskable Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense Configuration */
+ uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
+ uint8_t NMIASYNCH:1; /*!< bit: 4 Asynchronous Edge Detection Mode */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EIC_NMICTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMICTRL_OFFSET 0x01 /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
+#define EIC_NMICTRL_RESETVALUE _U_(0x00) /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
+
+#define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense Configuration */
+#define EIC_NMICTRL_NMISENSE_Msk (_U_(0x7) << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
+#define EIC_NMICTRL_NMISENSE_NONE_Val _U_(0x0) /**< \brief (EIC_NMICTRL) No detection */
+#define EIC_NMICTRL_NMISENSE_RISE_Val _U_(0x1) /**< \brief (EIC_NMICTRL) Rising-edge detection */
+#define EIC_NMICTRL_NMISENSE_FALL_Val _U_(0x2) /**< \brief (EIC_NMICTRL) Falling-edge detection */
+#define EIC_NMICTRL_NMISENSE_BOTH_Val _U_(0x3) /**< \brief (EIC_NMICTRL) Both-edges detection */
+#define EIC_NMICTRL_NMISENSE_HIGH_Val _U_(0x4) /**< \brief (EIC_NMICTRL) High-level detection */
+#define EIC_NMICTRL_NMISENSE_LOW_Val _U_(0x5) /**< \brief (EIC_NMICTRL) Low-level detection */
+#define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
+#define EIC_NMICTRL_NMIFILTEN (_U_(0x1) << EIC_NMICTRL_NMIFILTEN_Pos)
+#define EIC_NMICTRL_NMIASYNCH_Pos 4 /**< \brief (EIC_NMICTRL) Asynchronous Edge Detection Mode */
+#define EIC_NMICTRL_NMIASYNCH (_U_(0x1) << EIC_NMICTRL_NMIASYNCH_Pos)
+#define EIC_NMICTRL_MASK _U_(0x1F) /**< \brief (EIC_NMICTRL) MASK Register */
+
+/* -------- EIC_NMIFLAG : (EIC Offset: 0x02) (R/W 16) Non-Maskable Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
+ uint16_t :15; /*!< bit: 1..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} EIC_NMIFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMIFLAG_OFFSET 0x02 /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
+#define EIC_NMIFLAG_RESETVALUE _U_(0x0000) /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
+
+#define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
+#define EIC_NMIFLAG_NMI (_U_(0x1) << EIC_NMIFLAG_NMI_Pos)
+#define EIC_NMIFLAG_MASK _U_(0x0001) /**< \brief (EIC_NMIFLAG) MASK Register */
+
+/* -------- EIC_SYNCBUSY : (EIC Offset: 0x04) (R/ 32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy Status */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy Status */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_SYNCBUSY_OFFSET 0x04 /**< \brief (EIC_SYNCBUSY offset) Synchronization Busy */
+#define EIC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (EIC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define EIC_SYNCBUSY_SWRST_Pos 0 /**< \brief (EIC_SYNCBUSY) Software Reset Synchronization Busy Status */
+#define EIC_SYNCBUSY_SWRST (_U_(0x1) << EIC_SYNCBUSY_SWRST_Pos)
+#define EIC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (EIC_SYNCBUSY) Enable Synchronization Busy Status */
+#define EIC_SYNCBUSY_ENABLE (_U_(0x1) << EIC_SYNCBUSY_ENABLE_Pos)
+#define EIC_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (EIC_SYNCBUSY) MASK Register */
+
+/* -------- EIC_EVCTRL : (EIC Offset: 0x08) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt Event Output Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_EVCTRL_OFFSET 0x08 /**< \brief (EIC_EVCTRL offset) Event Control */
+#define EIC_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (EIC_EVCTRL reset_value) Event Control */
+
+#define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO_Msk (_U_(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos)
+#define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
+#define EIC_EVCTRL_MASK _U_(0x0000FFFF) /**< \brief (EIC_EVCTRL) MASK Register */
+
+/* -------- EIC_INTENCLR : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENCLR_OFFSET 0x0C /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
+#define EIC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt Enable */
+#define EIC_INTENCLR_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENCLR_EXTINT_Pos)
+#define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
+#define EIC_INTENCLR_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTENCLR) MASK Register */
+
+/* -------- EIC_INTENSET : (EIC Offset: 0x10) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENSET_OFFSET 0x10 /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
+#define EIC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
+
+#define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt Enable */
+#define EIC_INTENSET_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENSET_EXTINT_Pos)
+#define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
+#define EIC_INTENSET_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTENSET) MASK Register */
+
+/* -------- EIC_INTFLAG : (EIC Offset: 0x14) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt */
+ __I uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTFLAG_OFFSET 0x14 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EIC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt */
+#define EIC_INTFLAG_EXTINT_Msk (_U_(0xFFFF) << EIC_INTFLAG_EXTINT_Pos)
+#define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
+#define EIC_INTFLAG_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTFLAG) MASK Register */
+
+/* -------- EIC_ASYNCH : (EIC Offset: 0x18) (R/W 32) External Interrupt Asynchronous Mode -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ASYNCH:16; /*!< bit: 0..15 Asynchronous Edge Detection Mode */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_ASYNCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_ASYNCH_OFFSET 0x18 /**< \brief (EIC_ASYNCH offset) External Interrupt Asynchronous Mode */
+#define EIC_ASYNCH_RESETVALUE _U_(0x00000000) /**< \brief (EIC_ASYNCH reset_value) External Interrupt Asynchronous Mode */
+
+#define EIC_ASYNCH_ASYNCH_Pos 0 /**< \brief (EIC_ASYNCH) Asynchronous Edge Detection Mode */
+#define EIC_ASYNCH_ASYNCH_Msk (_U_(0xFFFF) << EIC_ASYNCH_ASYNCH_Pos)
+#define EIC_ASYNCH_ASYNCH(value) (EIC_ASYNCH_ASYNCH_Msk & ((value) << EIC_ASYNCH_ASYNCH_Pos))
+#define EIC_ASYNCH_MASK _U_(0x0000FFFF) /**< \brief (EIC_ASYNCH) MASK Register */
+
+/* -------- EIC_CONFIG : (EIC Offset: 0x1C) (R/W 32) External Interrupt Sense Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense Configuration 0 */
+ uint32_t FILTEN0:1; /*!< bit: 3 Filter Enable 0 */
+ uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense Configuration 1 */
+ uint32_t FILTEN1:1; /*!< bit: 7 Filter Enable 1 */
+ uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense Configuration 2 */
+ uint32_t FILTEN2:1; /*!< bit: 11 Filter Enable 2 */
+ uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense Configuration 3 */
+ uint32_t FILTEN3:1; /*!< bit: 15 Filter Enable 3 */
+ uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense Configuration 4 */
+ uint32_t FILTEN4:1; /*!< bit: 19 Filter Enable 4 */
+ uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense Configuration 5 */
+ uint32_t FILTEN5:1; /*!< bit: 23 Filter Enable 5 */
+ uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense Configuration 6 */
+ uint32_t FILTEN6:1; /*!< bit: 27 Filter Enable 6 */
+ uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense Configuration 7 */
+ uint32_t FILTEN7:1; /*!< bit: 31 Filter Enable 7 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CONFIG_OFFSET 0x1C /**< \brief (EIC_CONFIG offset) External Interrupt Sense Configuration */
+#define EIC_CONFIG_RESETVALUE _U_(0x00000000) /**< \brief (EIC_CONFIG reset_value) External Interrupt Sense Configuration */
+
+#define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense Configuration 0 */
+#define EIC_CONFIG_SENSE0_Msk (_U_(0x7) << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
+#define EIC_CONFIG_SENSE0_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE0_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE0_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE0_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE0_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE0_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter Enable 0 */
+#define EIC_CONFIG_FILTEN0 (_U_(0x1) << EIC_CONFIG_FILTEN0_Pos)
+#define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense Configuration 1 */
+#define EIC_CONFIG_SENSE1_Msk (_U_(0x7) << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
+#define EIC_CONFIG_SENSE1_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE1_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE1_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE1_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE1_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE1_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter Enable 1 */
+#define EIC_CONFIG_FILTEN1 (_U_(0x1) << EIC_CONFIG_FILTEN1_Pos)
+#define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense Configuration 2 */
+#define EIC_CONFIG_SENSE2_Msk (_U_(0x7) << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
+#define EIC_CONFIG_SENSE2_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE2_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE2_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE2_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE2_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE2_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter Enable 2 */
+#define EIC_CONFIG_FILTEN2 (_U_(0x1) << EIC_CONFIG_FILTEN2_Pos)
+#define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense Configuration 3 */
+#define EIC_CONFIG_SENSE3_Msk (_U_(0x7) << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
+#define EIC_CONFIG_SENSE3_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE3_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE3_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE3_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE3_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE3_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter Enable 3 */
+#define EIC_CONFIG_FILTEN3 (_U_(0x1) << EIC_CONFIG_FILTEN3_Pos)
+#define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense Configuration 4 */
+#define EIC_CONFIG_SENSE4_Msk (_U_(0x7) << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4(value) (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
+#define EIC_CONFIG_SENSE4_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE4_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE4_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE4_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE4_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE4_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter Enable 4 */
+#define EIC_CONFIG_FILTEN4 (_U_(0x1) << EIC_CONFIG_FILTEN4_Pos)
+#define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense Configuration 5 */
+#define EIC_CONFIG_SENSE5_Msk (_U_(0x7) << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5(value) (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
+#define EIC_CONFIG_SENSE5_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE5_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE5_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE5_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE5_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE5_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter Enable 5 */
+#define EIC_CONFIG_FILTEN5 (_U_(0x1) << EIC_CONFIG_FILTEN5_Pos)
+#define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense Configuration 6 */
+#define EIC_CONFIG_SENSE6_Msk (_U_(0x7) << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6(value) (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
+#define EIC_CONFIG_SENSE6_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE6_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE6_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE6_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE6_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE6_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter Enable 6 */
+#define EIC_CONFIG_FILTEN6 (_U_(0x1) << EIC_CONFIG_FILTEN6_Pos)
+#define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense Configuration 7 */
+#define EIC_CONFIG_SENSE7_Msk (_U_(0x7) << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7(value) (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
+#define EIC_CONFIG_SENSE7_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE7_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE7_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE7_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE7_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE7_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter Enable 7 */
+#define EIC_CONFIG_FILTEN7 (_U_(0x1) << EIC_CONFIG_FILTEN7_Pos)
+#define EIC_CONFIG_MASK _U_(0xFFFFFFFF) /**< \brief (EIC_CONFIG) MASK Register */
+
+/* -------- EIC_DEBOUNCEN : (EIC Offset: 0x30) (R/W 32) Debouncer Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DEBOUNCEN:16; /*!< bit: 0..15 Debouncer Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_DEBOUNCEN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_DEBOUNCEN_OFFSET 0x30 /**< \brief (EIC_DEBOUNCEN offset) Debouncer Enable */
+#define EIC_DEBOUNCEN_RESETVALUE _U_(0x00000000) /**< \brief (EIC_DEBOUNCEN reset_value) Debouncer Enable */
+
+#define EIC_DEBOUNCEN_DEBOUNCEN_Pos 0 /**< \brief (EIC_DEBOUNCEN) Debouncer Enable */
+#define EIC_DEBOUNCEN_DEBOUNCEN_Msk (_U_(0xFFFF) << EIC_DEBOUNCEN_DEBOUNCEN_Pos)
+#define EIC_DEBOUNCEN_DEBOUNCEN(value) (EIC_DEBOUNCEN_DEBOUNCEN_Msk & ((value) << EIC_DEBOUNCEN_DEBOUNCEN_Pos))
+#define EIC_DEBOUNCEN_MASK _U_(0x0000FFFF) /**< \brief (EIC_DEBOUNCEN) MASK Register */
+
+/* -------- EIC_DPRESCALER : (EIC Offset: 0x34) (R/W 32) Debouncer Prescaler -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PRESCALER0:3; /*!< bit: 0.. 2 Debouncer Prescaler */
+ uint32_t STATES0:1; /*!< bit: 3 Debouncer number of states */
+ uint32_t PRESCALER1:3; /*!< bit: 4.. 6 Debouncer Prescaler */
+ uint32_t STATES1:1; /*!< bit: 7 Debouncer number of states */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t TICKON:1; /*!< bit: 16 Pin Sampler frequency selection */
+ uint32_t :15; /*!< bit: 17..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_DPRESCALER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_DPRESCALER_OFFSET 0x34 /**< \brief (EIC_DPRESCALER offset) Debouncer Prescaler */
+#define EIC_DPRESCALER_RESETVALUE _U_(0x00000000) /**< \brief (EIC_DPRESCALER reset_value) Debouncer Prescaler */
+
+#define EIC_DPRESCALER_PRESCALER0_Pos 0 /**< \brief (EIC_DPRESCALER) Debouncer Prescaler */
+#define EIC_DPRESCALER_PRESCALER0_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER0_Pos)
+#define EIC_DPRESCALER_PRESCALER0(value) (EIC_DPRESCALER_PRESCALER0_Msk & ((value) << EIC_DPRESCALER_PRESCALER0_Pos))
+#define EIC_DPRESCALER_STATES0_Pos 3 /**< \brief (EIC_DPRESCALER) Debouncer number of states */
+#define EIC_DPRESCALER_STATES0 (_U_(0x1) << EIC_DPRESCALER_STATES0_Pos)
+#define EIC_DPRESCALER_PRESCALER1_Pos 4 /**< \brief (EIC_DPRESCALER) Debouncer Prescaler */
+#define EIC_DPRESCALER_PRESCALER1_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER1_Pos)
+#define EIC_DPRESCALER_PRESCALER1(value) (EIC_DPRESCALER_PRESCALER1_Msk & ((value) << EIC_DPRESCALER_PRESCALER1_Pos))
+#define EIC_DPRESCALER_STATES1_Pos 7 /**< \brief (EIC_DPRESCALER) Debouncer number of states */
+#define EIC_DPRESCALER_STATES1 (_U_(0x1) << EIC_DPRESCALER_STATES1_Pos)
+#define EIC_DPRESCALER_TICKON_Pos 16 /**< \brief (EIC_DPRESCALER) Pin Sampler frequency selection */
+#define EIC_DPRESCALER_TICKON (_U_(0x1) << EIC_DPRESCALER_TICKON_Pos)
+#define EIC_DPRESCALER_MASK _U_(0x000100FF) /**< \brief (EIC_DPRESCALER) MASK Register */
+
+/* -------- EIC_PINSTATE : (EIC Offset: 0x38) (R/ 32) Pin State -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PINSTATE:16; /*!< bit: 0..15 Pin State */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_PINSTATE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_PINSTATE_OFFSET 0x38 /**< \brief (EIC_PINSTATE offset) Pin State */
+#define EIC_PINSTATE_RESETVALUE _U_(0x00000000) /**< \brief (EIC_PINSTATE reset_value) Pin State */
+
+#define EIC_PINSTATE_PINSTATE_Pos 0 /**< \brief (EIC_PINSTATE) Pin State */
+#define EIC_PINSTATE_PINSTATE_Msk (_U_(0xFFFF) << EIC_PINSTATE_PINSTATE_Pos)
+#define EIC_PINSTATE_PINSTATE(value) (EIC_PINSTATE_PINSTATE_Msk & ((value) << EIC_PINSTATE_PINSTATE_Pos))
+#define EIC_PINSTATE_MASK _U_(0x0000FFFF) /**< \brief (EIC_PINSTATE) MASK Register */
+
+/** \brief EIC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO EIC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x01 (R/W 8) Non-Maskable Interrupt Control */
+ __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x02 (R/W 16) Non-Maskable Interrupt Flag Status and Clear */
+ __I EIC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Synchronization Busy */
+ __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x08 (R/W 32) Event Control */
+ __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Clear */
+ __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Set */
+ __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 32) Interrupt Flag Status and Clear */
+ __IO EIC_ASYNCH_Type ASYNCH; /**< \brief Offset: 0x18 (R/W 32) External Interrupt Asynchronous Mode */
+ __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x1C (R/W 32) External Interrupt Sense Configuration */
+ RoReg8 Reserved1[0xC];
+ __IO EIC_DEBOUNCEN_Type DEBOUNCEN; /**< \brief Offset: 0x30 (R/W 32) Debouncer Enable */
+ __IO EIC_DPRESCALER_Type DPRESCALER; /**< \brief Offset: 0x34 (R/W 32) Debouncer Prescaler */
+ __I EIC_PINSTATE_Type PINSTATE; /**< \brief Offset: 0x38 (R/ 32) Pin State */
+} Eic;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_EIC_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/evsys.h b/sysmoOCTSIM/include/component/evsys.h
index e78fd4c..a145243 100644
--- a/sysmoOCTSIM/include/component/evsys.h
+++ b/sysmoOCTSIM/include/component/evsys.h
@@ -1,587 +1,587 @@
-/**
- * \file
- *
- * \brief Component description for EVSYS
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_EVSYS_COMPONENT_
-#define _SAME54_EVSYS_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR EVSYS */
-/* ========================================================================== */
-/** \addtogroup SAME54_EVSYS Event System Interface */
-/*@{*/
-
-#define EVSYS_U2504
-#define REV_EVSYS 0x100
-
-/* -------- EVSYS_CTRLA : (EVSYS Offset: 0x000) (R/W 8) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} EVSYS_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_CTRLA_OFFSET 0x000 /**< \brief (EVSYS_CTRLA offset) Control */
-#define EVSYS_CTRLA_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CTRLA reset_value) Control */
-
-#define EVSYS_CTRLA_SWRST_Pos 0 /**< \brief (EVSYS_CTRLA) Software Reset */
-#define EVSYS_CTRLA_SWRST (_U_(0x1) << EVSYS_CTRLA_SWRST_Pos)
-#define EVSYS_CTRLA_MASK _U_(0x01) /**< \brief (EVSYS_CTRLA) MASK Register */
-
-/* -------- EVSYS_SWEVT : (EVSYS Offset: 0x004) ( /W 32) Software Event -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CHANNEL0:1; /*!< bit: 0 Channel 0 Software Selection */
- uint32_t CHANNEL1:1; /*!< bit: 1 Channel 1 Software Selection */
- uint32_t CHANNEL2:1; /*!< bit: 2 Channel 2 Software Selection */
- uint32_t CHANNEL3:1; /*!< bit: 3 Channel 3 Software Selection */
- uint32_t CHANNEL4:1; /*!< bit: 4 Channel 4 Software Selection */
- uint32_t CHANNEL5:1; /*!< bit: 5 Channel 5 Software Selection */
- uint32_t CHANNEL6:1; /*!< bit: 6 Channel 6 Software Selection */
- uint32_t CHANNEL7:1; /*!< bit: 7 Channel 7 Software Selection */
- uint32_t CHANNEL8:1; /*!< bit: 8 Channel 8 Software Selection */
- uint32_t CHANNEL9:1; /*!< bit: 9 Channel 9 Software Selection */
- uint32_t CHANNEL10:1; /*!< bit: 10 Channel 10 Software Selection */
- uint32_t CHANNEL11:1; /*!< bit: 11 Channel 11 Software Selection */
- uint32_t CHANNEL12:1; /*!< bit: 12 Channel 12 Software Selection */
- uint32_t CHANNEL13:1; /*!< bit: 13 Channel 13 Software Selection */
- uint32_t CHANNEL14:1; /*!< bit: 14 Channel 14 Software Selection */
- uint32_t CHANNEL15:1; /*!< bit: 15 Channel 15 Software Selection */
- uint32_t CHANNEL16:1; /*!< bit: 16 Channel 16 Software Selection */
- uint32_t CHANNEL17:1; /*!< bit: 17 Channel 17 Software Selection */
- uint32_t CHANNEL18:1; /*!< bit: 18 Channel 18 Software Selection */
- uint32_t CHANNEL19:1; /*!< bit: 19 Channel 19 Software Selection */
- uint32_t CHANNEL20:1; /*!< bit: 20 Channel 20 Software Selection */
- uint32_t CHANNEL21:1; /*!< bit: 21 Channel 21 Software Selection */
- uint32_t CHANNEL22:1; /*!< bit: 22 Channel 22 Software Selection */
- uint32_t CHANNEL23:1; /*!< bit: 23 Channel 23 Software Selection */
- uint32_t CHANNEL24:1; /*!< bit: 24 Channel 24 Software Selection */
- uint32_t CHANNEL25:1; /*!< bit: 25 Channel 25 Software Selection */
- uint32_t CHANNEL26:1; /*!< bit: 26 Channel 26 Software Selection */
- uint32_t CHANNEL27:1; /*!< bit: 27 Channel 27 Software Selection */
- uint32_t CHANNEL28:1; /*!< bit: 28 Channel 28 Software Selection */
- uint32_t CHANNEL29:1; /*!< bit: 29 Channel 29 Software Selection */
- uint32_t CHANNEL30:1; /*!< bit: 30 Channel 30 Software Selection */
- uint32_t CHANNEL31:1; /*!< bit: 31 Channel 31 Software Selection */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t CHANNEL:32; /*!< bit: 0..31 Channel x Software Selection */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} EVSYS_SWEVT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_SWEVT_OFFSET 0x004 /**< \brief (EVSYS_SWEVT offset) Software Event */
-#define EVSYS_SWEVT_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_SWEVT reset_value) Software Event */
-
-#define EVSYS_SWEVT_CHANNEL0_Pos 0 /**< \brief (EVSYS_SWEVT) Channel 0 Software Selection */
-#define EVSYS_SWEVT_CHANNEL0 (_U_(1) << EVSYS_SWEVT_CHANNEL0_Pos)
-#define EVSYS_SWEVT_CHANNEL1_Pos 1 /**< \brief (EVSYS_SWEVT) Channel 1 Software Selection */
-#define EVSYS_SWEVT_CHANNEL1 (_U_(1) << EVSYS_SWEVT_CHANNEL1_Pos)
-#define EVSYS_SWEVT_CHANNEL2_Pos 2 /**< \brief (EVSYS_SWEVT) Channel 2 Software Selection */
-#define EVSYS_SWEVT_CHANNEL2 (_U_(1) << EVSYS_SWEVT_CHANNEL2_Pos)
-#define EVSYS_SWEVT_CHANNEL3_Pos 3 /**< \brief (EVSYS_SWEVT) Channel 3 Software Selection */
-#define EVSYS_SWEVT_CHANNEL3 (_U_(1) << EVSYS_SWEVT_CHANNEL3_Pos)
-#define EVSYS_SWEVT_CHANNEL4_Pos 4 /**< \brief (EVSYS_SWEVT) Channel 4 Software Selection */
-#define EVSYS_SWEVT_CHANNEL4 (_U_(1) << EVSYS_SWEVT_CHANNEL4_Pos)
-#define EVSYS_SWEVT_CHANNEL5_Pos 5 /**< \brief (EVSYS_SWEVT) Channel 5 Software Selection */
-#define EVSYS_SWEVT_CHANNEL5 (_U_(1) << EVSYS_SWEVT_CHANNEL5_Pos)
-#define EVSYS_SWEVT_CHANNEL6_Pos 6 /**< \brief (EVSYS_SWEVT) Channel 6 Software Selection */
-#define EVSYS_SWEVT_CHANNEL6 (_U_(1) << EVSYS_SWEVT_CHANNEL6_Pos)
-#define EVSYS_SWEVT_CHANNEL7_Pos 7 /**< \brief (EVSYS_SWEVT) Channel 7 Software Selection */
-#define EVSYS_SWEVT_CHANNEL7 (_U_(1) << EVSYS_SWEVT_CHANNEL7_Pos)
-#define EVSYS_SWEVT_CHANNEL8_Pos 8 /**< \brief (EVSYS_SWEVT) Channel 8 Software Selection */
-#define EVSYS_SWEVT_CHANNEL8 (_U_(1) << EVSYS_SWEVT_CHANNEL8_Pos)
-#define EVSYS_SWEVT_CHANNEL9_Pos 9 /**< \brief (EVSYS_SWEVT) Channel 9 Software Selection */
-#define EVSYS_SWEVT_CHANNEL9 (_U_(1) << EVSYS_SWEVT_CHANNEL9_Pos)
-#define EVSYS_SWEVT_CHANNEL10_Pos 10 /**< \brief (EVSYS_SWEVT) Channel 10 Software Selection */
-#define EVSYS_SWEVT_CHANNEL10 (_U_(1) << EVSYS_SWEVT_CHANNEL10_Pos)
-#define EVSYS_SWEVT_CHANNEL11_Pos 11 /**< \brief (EVSYS_SWEVT) Channel 11 Software Selection */
-#define EVSYS_SWEVT_CHANNEL11 (_U_(1) << EVSYS_SWEVT_CHANNEL11_Pos)
-#define EVSYS_SWEVT_CHANNEL12_Pos 12 /**< \brief (EVSYS_SWEVT) Channel 12 Software Selection */
-#define EVSYS_SWEVT_CHANNEL12 (_U_(1) << EVSYS_SWEVT_CHANNEL12_Pos)
-#define EVSYS_SWEVT_CHANNEL13_Pos 13 /**< \brief (EVSYS_SWEVT) Channel 13 Software Selection */
-#define EVSYS_SWEVT_CHANNEL13 (_U_(1) << EVSYS_SWEVT_CHANNEL13_Pos)
-#define EVSYS_SWEVT_CHANNEL14_Pos 14 /**< \brief (EVSYS_SWEVT) Channel 14 Software Selection */
-#define EVSYS_SWEVT_CHANNEL14 (_U_(1) << EVSYS_SWEVT_CHANNEL14_Pos)
-#define EVSYS_SWEVT_CHANNEL15_Pos 15 /**< \brief (EVSYS_SWEVT) Channel 15 Software Selection */
-#define EVSYS_SWEVT_CHANNEL15 (_U_(1) << EVSYS_SWEVT_CHANNEL15_Pos)
-#define EVSYS_SWEVT_CHANNEL16_Pos 16 /**< \brief (EVSYS_SWEVT) Channel 16 Software Selection */
-#define EVSYS_SWEVT_CHANNEL16 (_U_(1) << EVSYS_SWEVT_CHANNEL16_Pos)
-#define EVSYS_SWEVT_CHANNEL17_Pos 17 /**< \brief (EVSYS_SWEVT) Channel 17 Software Selection */
-#define EVSYS_SWEVT_CHANNEL17 (_U_(1) << EVSYS_SWEVT_CHANNEL17_Pos)
-#define EVSYS_SWEVT_CHANNEL18_Pos 18 /**< \brief (EVSYS_SWEVT) Channel 18 Software Selection */
-#define EVSYS_SWEVT_CHANNEL18 (_U_(1) << EVSYS_SWEVT_CHANNEL18_Pos)
-#define EVSYS_SWEVT_CHANNEL19_Pos 19 /**< \brief (EVSYS_SWEVT) Channel 19 Software Selection */
-#define EVSYS_SWEVT_CHANNEL19 (_U_(1) << EVSYS_SWEVT_CHANNEL19_Pos)
-#define EVSYS_SWEVT_CHANNEL20_Pos 20 /**< \brief (EVSYS_SWEVT) Channel 20 Software Selection */
-#define EVSYS_SWEVT_CHANNEL20 (_U_(1) << EVSYS_SWEVT_CHANNEL20_Pos)
-#define EVSYS_SWEVT_CHANNEL21_Pos 21 /**< \brief (EVSYS_SWEVT) Channel 21 Software Selection */
-#define EVSYS_SWEVT_CHANNEL21 (_U_(1) << EVSYS_SWEVT_CHANNEL21_Pos)
-#define EVSYS_SWEVT_CHANNEL22_Pos 22 /**< \brief (EVSYS_SWEVT) Channel 22 Software Selection */
-#define EVSYS_SWEVT_CHANNEL22 (_U_(1) << EVSYS_SWEVT_CHANNEL22_Pos)
-#define EVSYS_SWEVT_CHANNEL23_Pos 23 /**< \brief (EVSYS_SWEVT) Channel 23 Software Selection */
-#define EVSYS_SWEVT_CHANNEL23 (_U_(1) << EVSYS_SWEVT_CHANNEL23_Pos)
-#define EVSYS_SWEVT_CHANNEL24_Pos 24 /**< \brief (EVSYS_SWEVT) Channel 24 Software Selection */
-#define EVSYS_SWEVT_CHANNEL24 (_U_(1) << EVSYS_SWEVT_CHANNEL24_Pos)
-#define EVSYS_SWEVT_CHANNEL25_Pos 25 /**< \brief (EVSYS_SWEVT) Channel 25 Software Selection */
-#define EVSYS_SWEVT_CHANNEL25 (_U_(1) << EVSYS_SWEVT_CHANNEL25_Pos)
-#define EVSYS_SWEVT_CHANNEL26_Pos 26 /**< \brief (EVSYS_SWEVT) Channel 26 Software Selection */
-#define EVSYS_SWEVT_CHANNEL26 (_U_(1) << EVSYS_SWEVT_CHANNEL26_Pos)
-#define EVSYS_SWEVT_CHANNEL27_Pos 27 /**< \brief (EVSYS_SWEVT) Channel 27 Software Selection */
-#define EVSYS_SWEVT_CHANNEL27 (_U_(1) << EVSYS_SWEVT_CHANNEL27_Pos)
-#define EVSYS_SWEVT_CHANNEL28_Pos 28 /**< \brief (EVSYS_SWEVT) Channel 28 Software Selection */
-#define EVSYS_SWEVT_CHANNEL28 (_U_(1) << EVSYS_SWEVT_CHANNEL28_Pos)
-#define EVSYS_SWEVT_CHANNEL29_Pos 29 /**< \brief (EVSYS_SWEVT) Channel 29 Software Selection */
-#define EVSYS_SWEVT_CHANNEL29 (_U_(1) << EVSYS_SWEVT_CHANNEL29_Pos)
-#define EVSYS_SWEVT_CHANNEL30_Pos 30 /**< \brief (EVSYS_SWEVT) Channel 30 Software Selection */
-#define EVSYS_SWEVT_CHANNEL30 (_U_(1) << EVSYS_SWEVT_CHANNEL30_Pos)
-#define EVSYS_SWEVT_CHANNEL31_Pos 31 /**< \brief (EVSYS_SWEVT) Channel 31 Software Selection */
-#define EVSYS_SWEVT_CHANNEL31 (_U_(1) << EVSYS_SWEVT_CHANNEL31_Pos)
-#define EVSYS_SWEVT_CHANNEL_Pos 0 /**< \brief (EVSYS_SWEVT) Channel x Software Selection */
-#define EVSYS_SWEVT_CHANNEL_Msk (_U_(0xFFFFFFFF) << EVSYS_SWEVT_CHANNEL_Pos)
-#define EVSYS_SWEVT_CHANNEL(value) (EVSYS_SWEVT_CHANNEL_Msk & ((value) << EVSYS_SWEVT_CHANNEL_Pos))
-#define EVSYS_SWEVT_MASK _U_(0xFFFFFFFF) /**< \brief (EVSYS_SWEVT) MASK Register */
-
-/* -------- EVSYS_PRICTRL : (EVSYS Offset: 0x008) (R/W 8) Priority Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t PRI:4; /*!< bit: 0.. 3 Channel Priority Number */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t RREN:1; /*!< bit: 7 Round-Robin Scheduling Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} EVSYS_PRICTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_PRICTRL_OFFSET 0x008 /**< \brief (EVSYS_PRICTRL offset) Priority Control */
-#define EVSYS_PRICTRL_RESETVALUE _U_(0x00) /**< \brief (EVSYS_PRICTRL reset_value) Priority Control */
-
-#define EVSYS_PRICTRL_PRI_Pos 0 /**< \brief (EVSYS_PRICTRL) Channel Priority Number */
-#define EVSYS_PRICTRL_PRI_Msk (_U_(0xF) << EVSYS_PRICTRL_PRI_Pos)
-#define EVSYS_PRICTRL_PRI(value) (EVSYS_PRICTRL_PRI_Msk & ((value) << EVSYS_PRICTRL_PRI_Pos))
-#define EVSYS_PRICTRL_RREN_Pos 7 /**< \brief (EVSYS_PRICTRL) Round-Robin Scheduling Enable */
-#define EVSYS_PRICTRL_RREN (_U_(0x1) << EVSYS_PRICTRL_RREN_Pos)
-#define EVSYS_PRICTRL_MASK _U_(0x8F) /**< \brief (EVSYS_PRICTRL) MASK Register */
-
-/* -------- EVSYS_INTPEND : (EVSYS Offset: 0x010) (R/W 16) Channel Pending Interrupt -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
- uint16_t :4; /*!< bit: 4.. 7 Reserved */
- uint16_t OVR:1; /*!< bit: 8 Channel Overrun */
- uint16_t EVD:1; /*!< bit: 9 Channel Event Detected */
- uint16_t :4; /*!< bit: 10..13 Reserved */
- uint16_t READY:1; /*!< bit: 14 Ready */
- uint16_t BUSY:1; /*!< bit: 15 Busy */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} EVSYS_INTPEND_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_INTPEND_OFFSET 0x010 /**< \brief (EVSYS_INTPEND offset) Channel Pending Interrupt */
-#define EVSYS_INTPEND_RESETVALUE _U_(0x4000) /**< \brief (EVSYS_INTPEND reset_value) Channel Pending Interrupt */
-
-#define EVSYS_INTPEND_ID_Pos 0 /**< \brief (EVSYS_INTPEND) Channel ID */
-#define EVSYS_INTPEND_ID_Msk (_U_(0xF) << EVSYS_INTPEND_ID_Pos)
-#define EVSYS_INTPEND_ID(value) (EVSYS_INTPEND_ID_Msk & ((value) << EVSYS_INTPEND_ID_Pos))
-#define EVSYS_INTPEND_OVR_Pos 8 /**< \brief (EVSYS_INTPEND) Channel Overrun */
-#define EVSYS_INTPEND_OVR (_U_(0x1) << EVSYS_INTPEND_OVR_Pos)
-#define EVSYS_INTPEND_EVD_Pos 9 /**< \brief (EVSYS_INTPEND) Channel Event Detected */
-#define EVSYS_INTPEND_EVD (_U_(0x1) << EVSYS_INTPEND_EVD_Pos)
-#define EVSYS_INTPEND_READY_Pos 14 /**< \brief (EVSYS_INTPEND) Ready */
-#define EVSYS_INTPEND_READY (_U_(0x1) << EVSYS_INTPEND_READY_Pos)
-#define EVSYS_INTPEND_BUSY_Pos 15 /**< \brief (EVSYS_INTPEND) Busy */
-#define EVSYS_INTPEND_BUSY (_U_(0x1) << EVSYS_INTPEND_BUSY_Pos)
-#define EVSYS_INTPEND_MASK _U_(0xC30F) /**< \brief (EVSYS_INTPEND) MASK Register */
-
-/* -------- EVSYS_INTSTATUS : (EVSYS Offset: 0x014) (R/ 32) Interrupt Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
- uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
- uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
- uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
- uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
- uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
- uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
- uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
- uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
- uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
- uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
- uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} EVSYS_INTSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_INTSTATUS_OFFSET 0x014 /**< \brief (EVSYS_INTSTATUS offset) Interrupt Status */
-#define EVSYS_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_INTSTATUS reset_value) Interrupt Status */
-
-#define EVSYS_INTSTATUS_CHINT0_Pos 0 /**< \brief (EVSYS_INTSTATUS) Channel 0 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT0 (_U_(1) << EVSYS_INTSTATUS_CHINT0_Pos)
-#define EVSYS_INTSTATUS_CHINT1_Pos 1 /**< \brief (EVSYS_INTSTATUS) Channel 1 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT1 (_U_(1) << EVSYS_INTSTATUS_CHINT1_Pos)
-#define EVSYS_INTSTATUS_CHINT2_Pos 2 /**< \brief (EVSYS_INTSTATUS) Channel 2 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT2 (_U_(1) << EVSYS_INTSTATUS_CHINT2_Pos)
-#define EVSYS_INTSTATUS_CHINT3_Pos 3 /**< \brief (EVSYS_INTSTATUS) Channel 3 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT3 (_U_(1) << EVSYS_INTSTATUS_CHINT3_Pos)
-#define EVSYS_INTSTATUS_CHINT4_Pos 4 /**< \brief (EVSYS_INTSTATUS) Channel 4 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT4 (_U_(1) << EVSYS_INTSTATUS_CHINT4_Pos)
-#define EVSYS_INTSTATUS_CHINT5_Pos 5 /**< \brief (EVSYS_INTSTATUS) Channel 5 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT5 (_U_(1) << EVSYS_INTSTATUS_CHINT5_Pos)
-#define EVSYS_INTSTATUS_CHINT6_Pos 6 /**< \brief (EVSYS_INTSTATUS) Channel 6 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT6 (_U_(1) << EVSYS_INTSTATUS_CHINT6_Pos)
-#define EVSYS_INTSTATUS_CHINT7_Pos 7 /**< \brief (EVSYS_INTSTATUS) Channel 7 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT7 (_U_(1) << EVSYS_INTSTATUS_CHINT7_Pos)
-#define EVSYS_INTSTATUS_CHINT8_Pos 8 /**< \brief (EVSYS_INTSTATUS) Channel 8 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT8 (_U_(1) << EVSYS_INTSTATUS_CHINT8_Pos)
-#define EVSYS_INTSTATUS_CHINT9_Pos 9 /**< \brief (EVSYS_INTSTATUS) Channel 9 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT9 (_U_(1) << EVSYS_INTSTATUS_CHINT9_Pos)
-#define EVSYS_INTSTATUS_CHINT10_Pos 10 /**< \brief (EVSYS_INTSTATUS) Channel 10 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT10 (_U_(1) << EVSYS_INTSTATUS_CHINT10_Pos)
-#define EVSYS_INTSTATUS_CHINT11_Pos 11 /**< \brief (EVSYS_INTSTATUS) Channel 11 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT11 (_U_(1) << EVSYS_INTSTATUS_CHINT11_Pos)
-#define EVSYS_INTSTATUS_CHINT_Pos 0 /**< \brief (EVSYS_INTSTATUS) Channel x Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT_Msk (_U_(0xFFF) << EVSYS_INTSTATUS_CHINT_Pos)
-#define EVSYS_INTSTATUS_CHINT(value) (EVSYS_INTSTATUS_CHINT_Msk & ((value) << EVSYS_INTSTATUS_CHINT_Pos))
-#define EVSYS_INTSTATUS_MASK _U_(0x00000FFF) /**< \brief (EVSYS_INTSTATUS) MASK Register */
-
-/* -------- EVSYS_BUSYCH : (EVSYS Offset: 0x018) (R/ 32) Busy Channels -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
- uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
- uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
- uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
- uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
- uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
- uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
- uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
- uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
- uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
- uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
- uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} EVSYS_BUSYCH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_BUSYCH_OFFSET 0x018 /**< \brief (EVSYS_BUSYCH offset) Busy Channels */
-#define EVSYS_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_BUSYCH reset_value) Busy Channels */
-
-#define EVSYS_BUSYCH_BUSYCH0_Pos 0 /**< \brief (EVSYS_BUSYCH) Busy Channel 0 */
-#define EVSYS_BUSYCH_BUSYCH0 (_U_(1) << EVSYS_BUSYCH_BUSYCH0_Pos)
-#define EVSYS_BUSYCH_BUSYCH1_Pos 1 /**< \brief (EVSYS_BUSYCH) Busy Channel 1 */
-#define EVSYS_BUSYCH_BUSYCH1 (_U_(1) << EVSYS_BUSYCH_BUSYCH1_Pos)
-#define EVSYS_BUSYCH_BUSYCH2_Pos 2 /**< \brief (EVSYS_BUSYCH) Busy Channel 2 */
-#define EVSYS_BUSYCH_BUSYCH2 (_U_(1) << EVSYS_BUSYCH_BUSYCH2_Pos)
-#define EVSYS_BUSYCH_BUSYCH3_Pos 3 /**< \brief (EVSYS_BUSYCH) Busy Channel 3 */
-#define EVSYS_BUSYCH_BUSYCH3 (_U_(1) << EVSYS_BUSYCH_BUSYCH3_Pos)
-#define EVSYS_BUSYCH_BUSYCH4_Pos 4 /**< \brief (EVSYS_BUSYCH) Busy Channel 4 */
-#define EVSYS_BUSYCH_BUSYCH4 (_U_(1) << EVSYS_BUSYCH_BUSYCH4_Pos)
-#define EVSYS_BUSYCH_BUSYCH5_Pos 5 /**< \brief (EVSYS_BUSYCH) Busy Channel 5 */
-#define EVSYS_BUSYCH_BUSYCH5 (_U_(1) << EVSYS_BUSYCH_BUSYCH5_Pos)
-#define EVSYS_BUSYCH_BUSYCH6_Pos 6 /**< \brief (EVSYS_BUSYCH) Busy Channel 6 */
-#define EVSYS_BUSYCH_BUSYCH6 (_U_(1) << EVSYS_BUSYCH_BUSYCH6_Pos)
-#define EVSYS_BUSYCH_BUSYCH7_Pos 7 /**< \brief (EVSYS_BUSYCH) Busy Channel 7 */
-#define EVSYS_BUSYCH_BUSYCH7 (_U_(1) << EVSYS_BUSYCH_BUSYCH7_Pos)
-#define EVSYS_BUSYCH_BUSYCH8_Pos 8 /**< \brief (EVSYS_BUSYCH) Busy Channel 8 */
-#define EVSYS_BUSYCH_BUSYCH8 (_U_(1) << EVSYS_BUSYCH_BUSYCH8_Pos)
-#define EVSYS_BUSYCH_BUSYCH9_Pos 9 /**< \brief (EVSYS_BUSYCH) Busy Channel 9 */
-#define EVSYS_BUSYCH_BUSYCH9 (_U_(1) << EVSYS_BUSYCH_BUSYCH9_Pos)
-#define EVSYS_BUSYCH_BUSYCH10_Pos 10 /**< \brief (EVSYS_BUSYCH) Busy Channel 10 */
-#define EVSYS_BUSYCH_BUSYCH10 (_U_(1) << EVSYS_BUSYCH_BUSYCH10_Pos)
-#define EVSYS_BUSYCH_BUSYCH11_Pos 11 /**< \brief (EVSYS_BUSYCH) Busy Channel 11 */
-#define EVSYS_BUSYCH_BUSYCH11 (_U_(1) << EVSYS_BUSYCH_BUSYCH11_Pos)
-#define EVSYS_BUSYCH_BUSYCH_Pos 0 /**< \brief (EVSYS_BUSYCH) Busy Channel x */
-#define EVSYS_BUSYCH_BUSYCH_Msk (_U_(0xFFF) << EVSYS_BUSYCH_BUSYCH_Pos)
-#define EVSYS_BUSYCH_BUSYCH(value) (EVSYS_BUSYCH_BUSYCH_Msk & ((value) << EVSYS_BUSYCH_BUSYCH_Pos))
-#define EVSYS_BUSYCH_MASK _U_(0x00000FFF) /**< \brief (EVSYS_BUSYCH) MASK Register */
-
-/* -------- EVSYS_READYUSR : (EVSYS Offset: 0x01C) (R/ 32) Ready Users -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t READYUSR0:1; /*!< bit: 0 Ready User for Channel 0 */
- uint32_t READYUSR1:1; /*!< bit: 1 Ready User for Channel 1 */
- uint32_t READYUSR2:1; /*!< bit: 2 Ready User for Channel 2 */
- uint32_t READYUSR3:1; /*!< bit: 3 Ready User for Channel 3 */
- uint32_t READYUSR4:1; /*!< bit: 4 Ready User for Channel 4 */
- uint32_t READYUSR5:1; /*!< bit: 5 Ready User for Channel 5 */
- uint32_t READYUSR6:1; /*!< bit: 6 Ready User for Channel 6 */
- uint32_t READYUSR7:1; /*!< bit: 7 Ready User for Channel 7 */
- uint32_t READYUSR8:1; /*!< bit: 8 Ready User for Channel 8 */
- uint32_t READYUSR9:1; /*!< bit: 9 Ready User for Channel 9 */
- uint32_t READYUSR10:1; /*!< bit: 10 Ready User for Channel 10 */
- uint32_t READYUSR11:1; /*!< bit: 11 Ready User for Channel 11 */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t READYUSR:12; /*!< bit: 0..11 Ready User for Channel x */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} EVSYS_READYUSR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_READYUSR_OFFSET 0x01C /**< \brief (EVSYS_READYUSR offset) Ready Users */
-#define EVSYS_READYUSR_RESETVALUE _U_(0xFFFFFFFF) /**< \brief (EVSYS_READYUSR reset_value) Ready Users */
-
-#define EVSYS_READYUSR_READYUSR0_Pos 0 /**< \brief (EVSYS_READYUSR) Ready User for Channel 0 */
-#define EVSYS_READYUSR_READYUSR0 (_U_(1) << EVSYS_READYUSR_READYUSR0_Pos)
-#define EVSYS_READYUSR_READYUSR1_Pos 1 /**< \brief (EVSYS_READYUSR) Ready User for Channel 1 */
-#define EVSYS_READYUSR_READYUSR1 (_U_(1) << EVSYS_READYUSR_READYUSR1_Pos)
-#define EVSYS_READYUSR_READYUSR2_Pos 2 /**< \brief (EVSYS_READYUSR) Ready User for Channel 2 */
-#define EVSYS_READYUSR_READYUSR2 (_U_(1) << EVSYS_READYUSR_READYUSR2_Pos)
-#define EVSYS_READYUSR_READYUSR3_Pos 3 /**< \brief (EVSYS_READYUSR) Ready User for Channel 3 */
-#define EVSYS_READYUSR_READYUSR3 (_U_(1) << EVSYS_READYUSR_READYUSR3_Pos)
-#define EVSYS_READYUSR_READYUSR4_Pos 4 /**< \brief (EVSYS_READYUSR) Ready User for Channel 4 */
-#define EVSYS_READYUSR_READYUSR4 (_U_(1) << EVSYS_READYUSR_READYUSR4_Pos)
-#define EVSYS_READYUSR_READYUSR5_Pos 5 /**< \brief (EVSYS_READYUSR) Ready User for Channel 5 */
-#define EVSYS_READYUSR_READYUSR5 (_U_(1) << EVSYS_READYUSR_READYUSR5_Pos)
-#define EVSYS_READYUSR_READYUSR6_Pos 6 /**< \brief (EVSYS_READYUSR) Ready User for Channel 6 */
-#define EVSYS_READYUSR_READYUSR6 (_U_(1) << EVSYS_READYUSR_READYUSR6_Pos)
-#define EVSYS_READYUSR_READYUSR7_Pos 7 /**< \brief (EVSYS_READYUSR) Ready User for Channel 7 */
-#define EVSYS_READYUSR_READYUSR7 (_U_(1) << EVSYS_READYUSR_READYUSR7_Pos)
-#define EVSYS_READYUSR_READYUSR8_Pos 8 /**< \brief (EVSYS_READYUSR) Ready User for Channel 8 */
-#define EVSYS_READYUSR_READYUSR8 (_U_(1) << EVSYS_READYUSR_READYUSR8_Pos)
-#define EVSYS_READYUSR_READYUSR9_Pos 9 /**< \brief (EVSYS_READYUSR) Ready User for Channel 9 */
-#define EVSYS_READYUSR_READYUSR9 (_U_(1) << EVSYS_READYUSR_READYUSR9_Pos)
-#define EVSYS_READYUSR_READYUSR10_Pos 10 /**< \brief (EVSYS_READYUSR) Ready User for Channel 10 */
-#define EVSYS_READYUSR_READYUSR10 (_U_(1) << EVSYS_READYUSR_READYUSR10_Pos)
-#define EVSYS_READYUSR_READYUSR11_Pos 11 /**< \brief (EVSYS_READYUSR) Ready User for Channel 11 */
-#define EVSYS_READYUSR_READYUSR11 (_U_(1) << EVSYS_READYUSR_READYUSR11_Pos)
-#define EVSYS_READYUSR_READYUSR_Pos 0 /**< \brief (EVSYS_READYUSR) Ready User for Channel x */
-#define EVSYS_READYUSR_READYUSR_Msk (_U_(0xFFF) << EVSYS_READYUSR_READYUSR_Pos)
-#define EVSYS_READYUSR_READYUSR(value) (EVSYS_READYUSR_READYUSR_Msk & ((value) << EVSYS_READYUSR_READYUSR_Pos))
-#define EVSYS_READYUSR_MASK _U_(0x00000FFF) /**< \brief (EVSYS_READYUSR) MASK Register */
-
-/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x020) (R/W 32) CHANNEL Channel n Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EVGEN:7; /*!< bit: 0.. 6 Event Generator Selection */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t PATH:2; /*!< bit: 8.. 9 Path Selection */
- uint32_t EDGSEL:2; /*!< bit: 10..11 Edge Detection Selection */
- uint32_t :2; /*!< bit: 12..13 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 14 Run in standby */
- uint32_t ONDEMAND:1; /*!< bit: 15 Generic Clock On Demand */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} EVSYS_CHANNEL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_CHANNEL_OFFSET 0x020 /**< \brief (EVSYS_CHANNEL offset) Channel n Control */
-#define EVSYS_CHANNEL_RESETVALUE _U_(0x00008000) /**< \brief (EVSYS_CHANNEL reset_value) Channel n Control */
-
-#define EVSYS_CHANNEL_EVGEN_Pos 0 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
-#define EVSYS_CHANNEL_EVGEN_Msk (_U_(0x7F) << EVSYS_CHANNEL_EVGEN_Pos)
-#define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
-#define EVSYS_CHANNEL_PATH_Pos 8 /**< \brief (EVSYS_CHANNEL) Path Selection */
-#define EVSYS_CHANNEL_PATH_Msk (_U_(0x3) << EVSYS_CHANNEL_PATH_Pos)
-#define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
-#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val _U_(0x0) /**< \brief (EVSYS_CHANNEL) Synchronous path */
-#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _U_(0x1) /**< \brief (EVSYS_CHANNEL) Resynchronized path */
-#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _U_(0x2) /**< \brief (EVSYS_CHANNEL) Asynchronous path */
-#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
-#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
-#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
-#define EVSYS_CHANNEL_EDGSEL_Pos 10 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
-#define EVSYS_CHANNEL_EDGSEL_Msk (_U_(0x3) << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
-#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _U_(0x0) /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
-#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _U_(0x1) /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
-#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _U_(0x2) /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
-#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _U_(0x3) /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
-#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_RUNSTDBY_Pos 14 /**< \brief (EVSYS_CHANNEL) Run in standby */
-#define EVSYS_CHANNEL_RUNSTDBY (_U_(0x1) << EVSYS_CHANNEL_RUNSTDBY_Pos)
-#define EVSYS_CHANNEL_ONDEMAND_Pos 15 /**< \brief (EVSYS_CHANNEL) Generic Clock On Demand */
-#define EVSYS_CHANNEL_ONDEMAND (_U_(0x1) << EVSYS_CHANNEL_ONDEMAND_Pos)
-#define EVSYS_CHANNEL_MASK _U_(0x0000CF7F) /**< \brief (EVSYS_CHANNEL) MASK Register */
-
-/* -------- EVSYS_CHINTENCLR : (EVSYS Offset: 0x024) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t OVR:1; /*!< bit: 0 Channel Overrun Interrupt Disable */
- uint8_t EVD:1; /*!< bit: 1 Channel Event Detected Interrupt Disable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} EVSYS_CHINTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_CHINTENCLR_OFFSET 0x024 /**< \brief (EVSYS_CHINTENCLR offset) Channel n Interrupt Enable Clear */
-#define EVSYS_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */
-
-#define EVSYS_CHINTENCLR_OVR_Pos 0 /**< \brief (EVSYS_CHINTENCLR) Channel Overrun Interrupt Disable */
-#define EVSYS_CHINTENCLR_OVR (_U_(0x1) << EVSYS_CHINTENCLR_OVR_Pos)
-#define EVSYS_CHINTENCLR_EVD_Pos 1 /**< \brief (EVSYS_CHINTENCLR) Channel Event Detected Interrupt Disable */
-#define EVSYS_CHINTENCLR_EVD (_U_(0x1) << EVSYS_CHINTENCLR_EVD_Pos)
-#define EVSYS_CHINTENCLR_MASK _U_(0x03) /**< \brief (EVSYS_CHINTENCLR) MASK Register */
-
-/* -------- EVSYS_CHINTENSET : (EVSYS Offset: 0x025) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t OVR:1; /*!< bit: 0 Channel Overrun Interrupt Enable */
- uint8_t EVD:1; /*!< bit: 1 Channel Event Detected Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} EVSYS_CHINTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_CHINTENSET_OFFSET 0x025 /**< \brief (EVSYS_CHINTENSET offset) Channel n Interrupt Enable Set */
-#define EVSYS_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CHINTENSET reset_value) Channel n Interrupt Enable Set */
-
-#define EVSYS_CHINTENSET_OVR_Pos 0 /**< \brief (EVSYS_CHINTENSET) Channel Overrun Interrupt Enable */
-#define EVSYS_CHINTENSET_OVR (_U_(0x1) << EVSYS_CHINTENSET_OVR_Pos)
-#define EVSYS_CHINTENSET_EVD_Pos 1 /**< \brief (EVSYS_CHINTENSET) Channel Event Detected Interrupt Enable */
-#define EVSYS_CHINTENSET_EVD (_U_(0x1) << EVSYS_CHINTENSET_EVD_Pos)
-#define EVSYS_CHINTENSET_MASK _U_(0x03) /**< \brief (EVSYS_CHINTENSET) MASK Register */
-
-/* -------- EVSYS_CHINTFLAG : (EVSYS Offset: 0x026) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t OVR:1; /*!< bit: 0 Channel Overrun */
- __I uint8_t EVD:1; /*!< bit: 1 Channel Event Detected */
- __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} EVSYS_CHINTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_CHINTFLAG_OFFSET 0x026 /**< \brief (EVSYS_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */
-#define EVSYS_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */
-
-#define EVSYS_CHINTFLAG_OVR_Pos 0 /**< \brief (EVSYS_CHINTFLAG) Channel Overrun */
-#define EVSYS_CHINTFLAG_OVR (_U_(0x1) << EVSYS_CHINTFLAG_OVR_Pos)
-#define EVSYS_CHINTFLAG_EVD_Pos 1 /**< \brief (EVSYS_CHINTFLAG) Channel Event Detected */
-#define EVSYS_CHINTFLAG_EVD (_U_(0x1) << EVSYS_CHINTFLAG_EVD_Pos)
-#define EVSYS_CHINTFLAG_MASK _U_(0x03) /**< \brief (EVSYS_CHINTFLAG) MASK Register */
-
-/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x027) (R/ 8) CHANNEL Channel n Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t RDYUSR:1; /*!< bit: 0 Ready User */
- uint8_t BUSYCH:1; /*!< bit: 1 Busy Channel */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} EVSYS_CHSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_CHSTATUS_OFFSET 0x027 /**< \brief (EVSYS_CHSTATUS offset) Channel n Status */
-#define EVSYS_CHSTATUS_RESETVALUE _U_(0x01) /**< \brief (EVSYS_CHSTATUS reset_value) Channel n Status */
-
-#define EVSYS_CHSTATUS_RDYUSR_Pos 0 /**< \brief (EVSYS_CHSTATUS) Ready User */
-#define EVSYS_CHSTATUS_RDYUSR (_U_(0x1) << EVSYS_CHSTATUS_RDYUSR_Pos)
-#define EVSYS_CHSTATUS_BUSYCH_Pos 1 /**< \brief (EVSYS_CHSTATUS) Busy Channel */
-#define EVSYS_CHSTATUS_BUSYCH (_U_(0x1) << EVSYS_CHSTATUS_BUSYCH_Pos)
-#define EVSYS_CHSTATUS_MASK _U_(0x03) /**< \brief (EVSYS_CHSTATUS) MASK Register */
-
-/* -------- EVSYS_USER : (EVSYS Offset: 0x120) (R/W 32) User Multiplexer n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CHANNEL:6; /*!< bit: 0.. 5 Channel Event Selection */
- uint32_t :26; /*!< bit: 6..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} EVSYS_USER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_USER_OFFSET 0x120 /**< \brief (EVSYS_USER offset) User Multiplexer n */
-#define EVSYS_USER_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_USER reset_value) User Multiplexer n */
-
-#define EVSYS_USER_CHANNEL_Pos 0 /**< \brief (EVSYS_USER) Channel Event Selection */
-#define EVSYS_USER_CHANNEL_Msk (_U_(0x3F) << EVSYS_USER_CHANNEL_Pos)
-#define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
-#define EVSYS_USER_MASK _U_(0x0000003F) /**< \brief (EVSYS_USER) MASK Register */
-
-/** \brief EvsysChannel hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x000 (R/W 32) Channel n Control */
- __IO EVSYS_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x004 (R/W 8) Channel n Interrupt Enable Clear */
- __IO EVSYS_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x005 (R/W 8) Channel n Interrupt Enable Set */
- __IO EVSYS_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x006 (R/W 8) Channel n Interrupt Flag Status and Clear */
- __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x007 (R/ 8) Channel n Status */
-} EvsysChannel;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief EVSYS hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO EVSYS_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control */
- RoReg8 Reserved1[0x3];
- __O EVSYS_SWEVT_Type SWEVT; /**< \brief Offset: 0x004 ( /W 32) Software Event */
- __IO EVSYS_PRICTRL_Type PRICTRL; /**< \brief Offset: 0x008 (R/W 8) Priority Control */
- RoReg8 Reserved2[0x7];
- __IO EVSYS_INTPEND_Type INTPEND; /**< \brief Offset: 0x010 (R/W 16) Channel Pending Interrupt */
- RoReg8 Reserved3[0x2];
- __I EVSYS_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x014 (R/ 32) Interrupt Status */
- __I EVSYS_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x018 (R/ 32) Busy Channels */
- __I EVSYS_READYUSR_Type READYUSR; /**< \brief Offset: 0x01C (R/ 32) Ready Users */
- EvsysChannel Channel[32]; /**< \brief Offset: 0x020 EvsysChannel groups [CHANNELS] */
- __IO EVSYS_USER_Type USER[67]; /**< \brief Offset: 0x120 (R/W 32) User Multiplexer n */
-} Evsys;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_EVSYS_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for EVSYS
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_EVSYS_COMPONENT_
+#define _SAME54_EVSYS_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR EVSYS */
+/* ========================================================================== */
+/** \addtogroup SAME54_EVSYS Event System Interface */
+/*@{*/
+
+#define EVSYS_U2504
+#define REV_EVSYS 0x100
+
+/* -------- EVSYS_CTRLA : (EVSYS Offset: 0x000) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EVSYS_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CTRLA_OFFSET 0x000 /**< \brief (EVSYS_CTRLA offset) Control */
+#define EVSYS_CTRLA_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CTRLA reset_value) Control */
+
+#define EVSYS_CTRLA_SWRST_Pos 0 /**< \brief (EVSYS_CTRLA) Software Reset */
+#define EVSYS_CTRLA_SWRST (_U_(0x1) << EVSYS_CTRLA_SWRST_Pos)
+#define EVSYS_CTRLA_MASK _U_(0x01) /**< \brief (EVSYS_CTRLA) MASK Register */
+
+/* -------- EVSYS_SWEVT : (EVSYS Offset: 0x004) ( /W 32) Software Event -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHANNEL0:1; /*!< bit: 0 Channel 0 Software Selection */
+ uint32_t CHANNEL1:1; /*!< bit: 1 Channel 1 Software Selection */
+ uint32_t CHANNEL2:1; /*!< bit: 2 Channel 2 Software Selection */
+ uint32_t CHANNEL3:1; /*!< bit: 3 Channel 3 Software Selection */
+ uint32_t CHANNEL4:1; /*!< bit: 4 Channel 4 Software Selection */
+ uint32_t CHANNEL5:1; /*!< bit: 5 Channel 5 Software Selection */
+ uint32_t CHANNEL6:1; /*!< bit: 6 Channel 6 Software Selection */
+ uint32_t CHANNEL7:1; /*!< bit: 7 Channel 7 Software Selection */
+ uint32_t CHANNEL8:1; /*!< bit: 8 Channel 8 Software Selection */
+ uint32_t CHANNEL9:1; /*!< bit: 9 Channel 9 Software Selection */
+ uint32_t CHANNEL10:1; /*!< bit: 10 Channel 10 Software Selection */
+ uint32_t CHANNEL11:1; /*!< bit: 11 Channel 11 Software Selection */
+ uint32_t CHANNEL12:1; /*!< bit: 12 Channel 12 Software Selection */
+ uint32_t CHANNEL13:1; /*!< bit: 13 Channel 13 Software Selection */
+ uint32_t CHANNEL14:1; /*!< bit: 14 Channel 14 Software Selection */
+ uint32_t CHANNEL15:1; /*!< bit: 15 Channel 15 Software Selection */
+ uint32_t CHANNEL16:1; /*!< bit: 16 Channel 16 Software Selection */
+ uint32_t CHANNEL17:1; /*!< bit: 17 Channel 17 Software Selection */
+ uint32_t CHANNEL18:1; /*!< bit: 18 Channel 18 Software Selection */
+ uint32_t CHANNEL19:1; /*!< bit: 19 Channel 19 Software Selection */
+ uint32_t CHANNEL20:1; /*!< bit: 20 Channel 20 Software Selection */
+ uint32_t CHANNEL21:1; /*!< bit: 21 Channel 21 Software Selection */
+ uint32_t CHANNEL22:1; /*!< bit: 22 Channel 22 Software Selection */
+ uint32_t CHANNEL23:1; /*!< bit: 23 Channel 23 Software Selection */
+ uint32_t CHANNEL24:1; /*!< bit: 24 Channel 24 Software Selection */
+ uint32_t CHANNEL25:1; /*!< bit: 25 Channel 25 Software Selection */
+ uint32_t CHANNEL26:1; /*!< bit: 26 Channel 26 Software Selection */
+ uint32_t CHANNEL27:1; /*!< bit: 27 Channel 27 Software Selection */
+ uint32_t CHANNEL28:1; /*!< bit: 28 Channel 28 Software Selection */
+ uint32_t CHANNEL29:1; /*!< bit: 29 Channel 29 Software Selection */
+ uint32_t CHANNEL30:1; /*!< bit: 30 Channel 30 Software Selection */
+ uint32_t CHANNEL31:1; /*!< bit: 31 Channel 31 Software Selection */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t CHANNEL:32; /*!< bit: 0..31 Channel x Software Selection */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_SWEVT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_SWEVT_OFFSET 0x004 /**< \brief (EVSYS_SWEVT offset) Software Event */
+#define EVSYS_SWEVT_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_SWEVT reset_value) Software Event */
+
+#define EVSYS_SWEVT_CHANNEL0_Pos 0 /**< \brief (EVSYS_SWEVT) Channel 0 Software Selection */
+#define EVSYS_SWEVT_CHANNEL0 (_U_(1) << EVSYS_SWEVT_CHANNEL0_Pos)
+#define EVSYS_SWEVT_CHANNEL1_Pos 1 /**< \brief (EVSYS_SWEVT) Channel 1 Software Selection */
+#define EVSYS_SWEVT_CHANNEL1 (_U_(1) << EVSYS_SWEVT_CHANNEL1_Pos)
+#define EVSYS_SWEVT_CHANNEL2_Pos 2 /**< \brief (EVSYS_SWEVT) Channel 2 Software Selection */
+#define EVSYS_SWEVT_CHANNEL2 (_U_(1) << EVSYS_SWEVT_CHANNEL2_Pos)
+#define EVSYS_SWEVT_CHANNEL3_Pos 3 /**< \brief (EVSYS_SWEVT) Channel 3 Software Selection */
+#define EVSYS_SWEVT_CHANNEL3 (_U_(1) << EVSYS_SWEVT_CHANNEL3_Pos)
+#define EVSYS_SWEVT_CHANNEL4_Pos 4 /**< \brief (EVSYS_SWEVT) Channel 4 Software Selection */
+#define EVSYS_SWEVT_CHANNEL4 (_U_(1) << EVSYS_SWEVT_CHANNEL4_Pos)
+#define EVSYS_SWEVT_CHANNEL5_Pos 5 /**< \brief (EVSYS_SWEVT) Channel 5 Software Selection */
+#define EVSYS_SWEVT_CHANNEL5 (_U_(1) << EVSYS_SWEVT_CHANNEL5_Pos)
+#define EVSYS_SWEVT_CHANNEL6_Pos 6 /**< \brief (EVSYS_SWEVT) Channel 6 Software Selection */
+#define EVSYS_SWEVT_CHANNEL6 (_U_(1) << EVSYS_SWEVT_CHANNEL6_Pos)
+#define EVSYS_SWEVT_CHANNEL7_Pos 7 /**< \brief (EVSYS_SWEVT) Channel 7 Software Selection */
+#define EVSYS_SWEVT_CHANNEL7 (_U_(1) << EVSYS_SWEVT_CHANNEL7_Pos)
+#define EVSYS_SWEVT_CHANNEL8_Pos 8 /**< \brief (EVSYS_SWEVT) Channel 8 Software Selection */
+#define EVSYS_SWEVT_CHANNEL8 (_U_(1) << EVSYS_SWEVT_CHANNEL8_Pos)
+#define EVSYS_SWEVT_CHANNEL9_Pos 9 /**< \brief (EVSYS_SWEVT) Channel 9 Software Selection */
+#define EVSYS_SWEVT_CHANNEL9 (_U_(1) << EVSYS_SWEVT_CHANNEL9_Pos)
+#define EVSYS_SWEVT_CHANNEL10_Pos 10 /**< \brief (EVSYS_SWEVT) Channel 10 Software Selection */
+#define EVSYS_SWEVT_CHANNEL10 (_U_(1) << EVSYS_SWEVT_CHANNEL10_Pos)
+#define EVSYS_SWEVT_CHANNEL11_Pos 11 /**< \brief (EVSYS_SWEVT) Channel 11 Software Selection */
+#define EVSYS_SWEVT_CHANNEL11 (_U_(1) << EVSYS_SWEVT_CHANNEL11_Pos)
+#define EVSYS_SWEVT_CHANNEL12_Pos 12 /**< \brief (EVSYS_SWEVT) Channel 12 Software Selection */
+#define EVSYS_SWEVT_CHANNEL12 (_U_(1) << EVSYS_SWEVT_CHANNEL12_Pos)
+#define EVSYS_SWEVT_CHANNEL13_Pos 13 /**< \brief (EVSYS_SWEVT) Channel 13 Software Selection */
+#define EVSYS_SWEVT_CHANNEL13 (_U_(1) << EVSYS_SWEVT_CHANNEL13_Pos)
+#define EVSYS_SWEVT_CHANNEL14_Pos 14 /**< \brief (EVSYS_SWEVT) Channel 14 Software Selection */
+#define EVSYS_SWEVT_CHANNEL14 (_U_(1) << EVSYS_SWEVT_CHANNEL14_Pos)
+#define EVSYS_SWEVT_CHANNEL15_Pos 15 /**< \brief (EVSYS_SWEVT) Channel 15 Software Selection */
+#define EVSYS_SWEVT_CHANNEL15 (_U_(1) << EVSYS_SWEVT_CHANNEL15_Pos)
+#define EVSYS_SWEVT_CHANNEL16_Pos 16 /**< \brief (EVSYS_SWEVT) Channel 16 Software Selection */
+#define EVSYS_SWEVT_CHANNEL16 (_U_(1) << EVSYS_SWEVT_CHANNEL16_Pos)
+#define EVSYS_SWEVT_CHANNEL17_Pos 17 /**< \brief (EVSYS_SWEVT) Channel 17 Software Selection */
+#define EVSYS_SWEVT_CHANNEL17 (_U_(1) << EVSYS_SWEVT_CHANNEL17_Pos)
+#define EVSYS_SWEVT_CHANNEL18_Pos 18 /**< \brief (EVSYS_SWEVT) Channel 18 Software Selection */
+#define EVSYS_SWEVT_CHANNEL18 (_U_(1) << EVSYS_SWEVT_CHANNEL18_Pos)
+#define EVSYS_SWEVT_CHANNEL19_Pos 19 /**< \brief (EVSYS_SWEVT) Channel 19 Software Selection */
+#define EVSYS_SWEVT_CHANNEL19 (_U_(1) << EVSYS_SWEVT_CHANNEL19_Pos)
+#define EVSYS_SWEVT_CHANNEL20_Pos 20 /**< \brief (EVSYS_SWEVT) Channel 20 Software Selection */
+#define EVSYS_SWEVT_CHANNEL20 (_U_(1) << EVSYS_SWEVT_CHANNEL20_Pos)
+#define EVSYS_SWEVT_CHANNEL21_Pos 21 /**< \brief (EVSYS_SWEVT) Channel 21 Software Selection */
+#define EVSYS_SWEVT_CHANNEL21 (_U_(1) << EVSYS_SWEVT_CHANNEL21_Pos)
+#define EVSYS_SWEVT_CHANNEL22_Pos 22 /**< \brief (EVSYS_SWEVT) Channel 22 Software Selection */
+#define EVSYS_SWEVT_CHANNEL22 (_U_(1) << EVSYS_SWEVT_CHANNEL22_Pos)
+#define EVSYS_SWEVT_CHANNEL23_Pos 23 /**< \brief (EVSYS_SWEVT) Channel 23 Software Selection */
+#define EVSYS_SWEVT_CHANNEL23 (_U_(1) << EVSYS_SWEVT_CHANNEL23_Pos)
+#define EVSYS_SWEVT_CHANNEL24_Pos 24 /**< \brief (EVSYS_SWEVT) Channel 24 Software Selection */
+#define EVSYS_SWEVT_CHANNEL24 (_U_(1) << EVSYS_SWEVT_CHANNEL24_Pos)
+#define EVSYS_SWEVT_CHANNEL25_Pos 25 /**< \brief (EVSYS_SWEVT) Channel 25 Software Selection */
+#define EVSYS_SWEVT_CHANNEL25 (_U_(1) << EVSYS_SWEVT_CHANNEL25_Pos)
+#define EVSYS_SWEVT_CHANNEL26_Pos 26 /**< \brief (EVSYS_SWEVT) Channel 26 Software Selection */
+#define EVSYS_SWEVT_CHANNEL26 (_U_(1) << EVSYS_SWEVT_CHANNEL26_Pos)
+#define EVSYS_SWEVT_CHANNEL27_Pos 27 /**< \brief (EVSYS_SWEVT) Channel 27 Software Selection */
+#define EVSYS_SWEVT_CHANNEL27 (_U_(1) << EVSYS_SWEVT_CHANNEL27_Pos)
+#define EVSYS_SWEVT_CHANNEL28_Pos 28 /**< \brief (EVSYS_SWEVT) Channel 28 Software Selection */
+#define EVSYS_SWEVT_CHANNEL28 (_U_(1) << EVSYS_SWEVT_CHANNEL28_Pos)
+#define EVSYS_SWEVT_CHANNEL29_Pos 29 /**< \brief (EVSYS_SWEVT) Channel 29 Software Selection */
+#define EVSYS_SWEVT_CHANNEL29 (_U_(1) << EVSYS_SWEVT_CHANNEL29_Pos)
+#define EVSYS_SWEVT_CHANNEL30_Pos 30 /**< \brief (EVSYS_SWEVT) Channel 30 Software Selection */
+#define EVSYS_SWEVT_CHANNEL30 (_U_(1) << EVSYS_SWEVT_CHANNEL30_Pos)
+#define EVSYS_SWEVT_CHANNEL31_Pos 31 /**< \brief (EVSYS_SWEVT) Channel 31 Software Selection */
+#define EVSYS_SWEVT_CHANNEL31 (_U_(1) << EVSYS_SWEVT_CHANNEL31_Pos)
+#define EVSYS_SWEVT_CHANNEL_Pos 0 /**< \brief (EVSYS_SWEVT) Channel x Software Selection */
+#define EVSYS_SWEVT_CHANNEL_Msk (_U_(0xFFFFFFFF) << EVSYS_SWEVT_CHANNEL_Pos)
+#define EVSYS_SWEVT_CHANNEL(value) (EVSYS_SWEVT_CHANNEL_Msk & ((value) << EVSYS_SWEVT_CHANNEL_Pos))
+#define EVSYS_SWEVT_MASK _U_(0xFFFFFFFF) /**< \brief (EVSYS_SWEVT) MASK Register */
+
+/* -------- EVSYS_PRICTRL : (EVSYS Offset: 0x008) (R/W 8) Priority Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PRI:4; /*!< bit: 0.. 3 Channel Priority Number */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t RREN:1; /*!< bit: 7 Round-Robin Scheduling Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EVSYS_PRICTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_PRICTRL_OFFSET 0x008 /**< \brief (EVSYS_PRICTRL offset) Priority Control */
+#define EVSYS_PRICTRL_RESETVALUE _U_(0x00) /**< \brief (EVSYS_PRICTRL reset_value) Priority Control */
+
+#define EVSYS_PRICTRL_PRI_Pos 0 /**< \brief (EVSYS_PRICTRL) Channel Priority Number */
+#define EVSYS_PRICTRL_PRI_Msk (_U_(0xF) << EVSYS_PRICTRL_PRI_Pos)
+#define EVSYS_PRICTRL_PRI(value) (EVSYS_PRICTRL_PRI_Msk & ((value) << EVSYS_PRICTRL_PRI_Pos))
+#define EVSYS_PRICTRL_RREN_Pos 7 /**< \brief (EVSYS_PRICTRL) Round-Robin Scheduling Enable */
+#define EVSYS_PRICTRL_RREN (_U_(0x1) << EVSYS_PRICTRL_RREN_Pos)
+#define EVSYS_PRICTRL_MASK _U_(0x8F) /**< \brief (EVSYS_PRICTRL) MASK Register */
+
+/* -------- EVSYS_INTPEND : (EVSYS Offset: 0x010) (R/W 16) Channel Pending Interrupt -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t OVR:1; /*!< bit: 8 Channel Overrun */
+ uint16_t EVD:1; /*!< bit: 9 Channel Event Detected */
+ uint16_t :4; /*!< bit: 10..13 Reserved */
+ uint16_t READY:1; /*!< bit: 14 Ready */
+ uint16_t BUSY:1; /*!< bit: 15 Busy */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} EVSYS_INTPEND_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTPEND_OFFSET 0x010 /**< \brief (EVSYS_INTPEND offset) Channel Pending Interrupt */
+#define EVSYS_INTPEND_RESETVALUE _U_(0x4000) /**< \brief (EVSYS_INTPEND reset_value) Channel Pending Interrupt */
+
+#define EVSYS_INTPEND_ID_Pos 0 /**< \brief (EVSYS_INTPEND) Channel ID */
+#define EVSYS_INTPEND_ID_Msk (_U_(0xF) << EVSYS_INTPEND_ID_Pos)
+#define EVSYS_INTPEND_ID(value) (EVSYS_INTPEND_ID_Msk & ((value) << EVSYS_INTPEND_ID_Pos))
+#define EVSYS_INTPEND_OVR_Pos 8 /**< \brief (EVSYS_INTPEND) Channel Overrun */
+#define EVSYS_INTPEND_OVR (_U_(0x1) << EVSYS_INTPEND_OVR_Pos)
+#define EVSYS_INTPEND_EVD_Pos 9 /**< \brief (EVSYS_INTPEND) Channel Event Detected */
+#define EVSYS_INTPEND_EVD (_U_(0x1) << EVSYS_INTPEND_EVD_Pos)
+#define EVSYS_INTPEND_READY_Pos 14 /**< \brief (EVSYS_INTPEND) Ready */
+#define EVSYS_INTPEND_READY (_U_(0x1) << EVSYS_INTPEND_READY_Pos)
+#define EVSYS_INTPEND_BUSY_Pos 15 /**< \brief (EVSYS_INTPEND) Busy */
+#define EVSYS_INTPEND_BUSY (_U_(0x1) << EVSYS_INTPEND_BUSY_Pos)
+#define EVSYS_INTPEND_MASK _U_(0xC30F) /**< \brief (EVSYS_INTPEND) MASK Register */
+
+/* -------- EVSYS_INTSTATUS : (EVSYS Offset: 0x014) (R/ 32) Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
+ uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
+ uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
+ uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
+ uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
+ uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
+ uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
+ uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
+ uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
+ uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
+ uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
+ uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_INTSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTSTATUS_OFFSET 0x014 /**< \brief (EVSYS_INTSTATUS offset) Interrupt Status */
+#define EVSYS_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_INTSTATUS reset_value) Interrupt Status */
+
+#define EVSYS_INTSTATUS_CHINT0_Pos 0 /**< \brief (EVSYS_INTSTATUS) Channel 0 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT0 (_U_(1) << EVSYS_INTSTATUS_CHINT0_Pos)
+#define EVSYS_INTSTATUS_CHINT1_Pos 1 /**< \brief (EVSYS_INTSTATUS) Channel 1 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT1 (_U_(1) << EVSYS_INTSTATUS_CHINT1_Pos)
+#define EVSYS_INTSTATUS_CHINT2_Pos 2 /**< \brief (EVSYS_INTSTATUS) Channel 2 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT2 (_U_(1) << EVSYS_INTSTATUS_CHINT2_Pos)
+#define EVSYS_INTSTATUS_CHINT3_Pos 3 /**< \brief (EVSYS_INTSTATUS) Channel 3 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT3 (_U_(1) << EVSYS_INTSTATUS_CHINT3_Pos)
+#define EVSYS_INTSTATUS_CHINT4_Pos 4 /**< \brief (EVSYS_INTSTATUS) Channel 4 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT4 (_U_(1) << EVSYS_INTSTATUS_CHINT4_Pos)
+#define EVSYS_INTSTATUS_CHINT5_Pos 5 /**< \brief (EVSYS_INTSTATUS) Channel 5 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT5 (_U_(1) << EVSYS_INTSTATUS_CHINT5_Pos)
+#define EVSYS_INTSTATUS_CHINT6_Pos 6 /**< \brief (EVSYS_INTSTATUS) Channel 6 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT6 (_U_(1) << EVSYS_INTSTATUS_CHINT6_Pos)
+#define EVSYS_INTSTATUS_CHINT7_Pos 7 /**< \brief (EVSYS_INTSTATUS) Channel 7 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT7 (_U_(1) << EVSYS_INTSTATUS_CHINT7_Pos)
+#define EVSYS_INTSTATUS_CHINT8_Pos 8 /**< \brief (EVSYS_INTSTATUS) Channel 8 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT8 (_U_(1) << EVSYS_INTSTATUS_CHINT8_Pos)
+#define EVSYS_INTSTATUS_CHINT9_Pos 9 /**< \brief (EVSYS_INTSTATUS) Channel 9 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT9 (_U_(1) << EVSYS_INTSTATUS_CHINT9_Pos)
+#define EVSYS_INTSTATUS_CHINT10_Pos 10 /**< \brief (EVSYS_INTSTATUS) Channel 10 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT10 (_U_(1) << EVSYS_INTSTATUS_CHINT10_Pos)
+#define EVSYS_INTSTATUS_CHINT11_Pos 11 /**< \brief (EVSYS_INTSTATUS) Channel 11 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT11 (_U_(1) << EVSYS_INTSTATUS_CHINT11_Pos)
+#define EVSYS_INTSTATUS_CHINT_Pos 0 /**< \brief (EVSYS_INTSTATUS) Channel x Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT_Msk (_U_(0xFFF) << EVSYS_INTSTATUS_CHINT_Pos)
+#define EVSYS_INTSTATUS_CHINT(value) (EVSYS_INTSTATUS_CHINT_Msk & ((value) << EVSYS_INTSTATUS_CHINT_Pos))
+#define EVSYS_INTSTATUS_MASK _U_(0x00000FFF) /**< \brief (EVSYS_INTSTATUS) MASK Register */
+
+/* -------- EVSYS_BUSYCH : (EVSYS Offset: 0x018) (R/ 32) Busy Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
+ uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
+ uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
+ uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
+ uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
+ uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
+ uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
+ uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
+ uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
+ uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
+ uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
+ uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_BUSYCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_BUSYCH_OFFSET 0x018 /**< \brief (EVSYS_BUSYCH offset) Busy Channels */
+#define EVSYS_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_BUSYCH reset_value) Busy Channels */
+
+#define EVSYS_BUSYCH_BUSYCH0_Pos 0 /**< \brief (EVSYS_BUSYCH) Busy Channel 0 */
+#define EVSYS_BUSYCH_BUSYCH0 (_U_(1) << EVSYS_BUSYCH_BUSYCH0_Pos)
+#define EVSYS_BUSYCH_BUSYCH1_Pos 1 /**< \brief (EVSYS_BUSYCH) Busy Channel 1 */
+#define EVSYS_BUSYCH_BUSYCH1 (_U_(1) << EVSYS_BUSYCH_BUSYCH1_Pos)
+#define EVSYS_BUSYCH_BUSYCH2_Pos 2 /**< \brief (EVSYS_BUSYCH) Busy Channel 2 */
+#define EVSYS_BUSYCH_BUSYCH2 (_U_(1) << EVSYS_BUSYCH_BUSYCH2_Pos)
+#define EVSYS_BUSYCH_BUSYCH3_Pos 3 /**< \brief (EVSYS_BUSYCH) Busy Channel 3 */
+#define EVSYS_BUSYCH_BUSYCH3 (_U_(1) << EVSYS_BUSYCH_BUSYCH3_Pos)
+#define EVSYS_BUSYCH_BUSYCH4_Pos 4 /**< \brief (EVSYS_BUSYCH) Busy Channel 4 */
+#define EVSYS_BUSYCH_BUSYCH4 (_U_(1) << EVSYS_BUSYCH_BUSYCH4_Pos)
+#define EVSYS_BUSYCH_BUSYCH5_Pos 5 /**< \brief (EVSYS_BUSYCH) Busy Channel 5 */
+#define EVSYS_BUSYCH_BUSYCH5 (_U_(1) << EVSYS_BUSYCH_BUSYCH5_Pos)
+#define EVSYS_BUSYCH_BUSYCH6_Pos 6 /**< \brief (EVSYS_BUSYCH) Busy Channel 6 */
+#define EVSYS_BUSYCH_BUSYCH6 (_U_(1) << EVSYS_BUSYCH_BUSYCH6_Pos)
+#define EVSYS_BUSYCH_BUSYCH7_Pos 7 /**< \brief (EVSYS_BUSYCH) Busy Channel 7 */
+#define EVSYS_BUSYCH_BUSYCH7 (_U_(1) << EVSYS_BUSYCH_BUSYCH7_Pos)
+#define EVSYS_BUSYCH_BUSYCH8_Pos 8 /**< \brief (EVSYS_BUSYCH) Busy Channel 8 */
+#define EVSYS_BUSYCH_BUSYCH8 (_U_(1) << EVSYS_BUSYCH_BUSYCH8_Pos)
+#define EVSYS_BUSYCH_BUSYCH9_Pos 9 /**< \brief (EVSYS_BUSYCH) Busy Channel 9 */
+#define EVSYS_BUSYCH_BUSYCH9 (_U_(1) << EVSYS_BUSYCH_BUSYCH9_Pos)
+#define EVSYS_BUSYCH_BUSYCH10_Pos 10 /**< \brief (EVSYS_BUSYCH) Busy Channel 10 */
+#define EVSYS_BUSYCH_BUSYCH10 (_U_(1) << EVSYS_BUSYCH_BUSYCH10_Pos)
+#define EVSYS_BUSYCH_BUSYCH11_Pos 11 /**< \brief (EVSYS_BUSYCH) Busy Channel 11 */
+#define EVSYS_BUSYCH_BUSYCH11 (_U_(1) << EVSYS_BUSYCH_BUSYCH11_Pos)
+#define EVSYS_BUSYCH_BUSYCH_Pos 0 /**< \brief (EVSYS_BUSYCH) Busy Channel x */
+#define EVSYS_BUSYCH_BUSYCH_Msk (_U_(0xFFF) << EVSYS_BUSYCH_BUSYCH_Pos)
+#define EVSYS_BUSYCH_BUSYCH(value) (EVSYS_BUSYCH_BUSYCH_Msk & ((value) << EVSYS_BUSYCH_BUSYCH_Pos))
+#define EVSYS_BUSYCH_MASK _U_(0x00000FFF) /**< \brief (EVSYS_BUSYCH) MASK Register */
+
+/* -------- EVSYS_READYUSR : (EVSYS Offset: 0x01C) (R/ 32) Ready Users -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t READYUSR0:1; /*!< bit: 0 Ready User for Channel 0 */
+ uint32_t READYUSR1:1; /*!< bit: 1 Ready User for Channel 1 */
+ uint32_t READYUSR2:1; /*!< bit: 2 Ready User for Channel 2 */
+ uint32_t READYUSR3:1; /*!< bit: 3 Ready User for Channel 3 */
+ uint32_t READYUSR4:1; /*!< bit: 4 Ready User for Channel 4 */
+ uint32_t READYUSR5:1; /*!< bit: 5 Ready User for Channel 5 */
+ uint32_t READYUSR6:1; /*!< bit: 6 Ready User for Channel 6 */
+ uint32_t READYUSR7:1; /*!< bit: 7 Ready User for Channel 7 */
+ uint32_t READYUSR8:1; /*!< bit: 8 Ready User for Channel 8 */
+ uint32_t READYUSR9:1; /*!< bit: 9 Ready User for Channel 9 */
+ uint32_t READYUSR10:1; /*!< bit: 10 Ready User for Channel 10 */
+ uint32_t READYUSR11:1; /*!< bit: 11 Ready User for Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t READYUSR:12; /*!< bit: 0..11 Ready User for Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_READYUSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_READYUSR_OFFSET 0x01C /**< \brief (EVSYS_READYUSR offset) Ready Users */
+#define EVSYS_READYUSR_RESETVALUE _U_(0xFFFFFFFF) /**< \brief (EVSYS_READYUSR reset_value) Ready Users */
+
+#define EVSYS_READYUSR_READYUSR0_Pos 0 /**< \brief (EVSYS_READYUSR) Ready User for Channel 0 */
+#define EVSYS_READYUSR_READYUSR0 (_U_(1) << EVSYS_READYUSR_READYUSR0_Pos)
+#define EVSYS_READYUSR_READYUSR1_Pos 1 /**< \brief (EVSYS_READYUSR) Ready User for Channel 1 */
+#define EVSYS_READYUSR_READYUSR1 (_U_(1) << EVSYS_READYUSR_READYUSR1_Pos)
+#define EVSYS_READYUSR_READYUSR2_Pos 2 /**< \brief (EVSYS_READYUSR) Ready User for Channel 2 */
+#define EVSYS_READYUSR_READYUSR2 (_U_(1) << EVSYS_READYUSR_READYUSR2_Pos)
+#define EVSYS_READYUSR_READYUSR3_Pos 3 /**< \brief (EVSYS_READYUSR) Ready User for Channel 3 */
+#define EVSYS_READYUSR_READYUSR3 (_U_(1) << EVSYS_READYUSR_READYUSR3_Pos)
+#define EVSYS_READYUSR_READYUSR4_Pos 4 /**< \brief (EVSYS_READYUSR) Ready User for Channel 4 */
+#define EVSYS_READYUSR_READYUSR4 (_U_(1) << EVSYS_READYUSR_READYUSR4_Pos)
+#define EVSYS_READYUSR_READYUSR5_Pos 5 /**< \brief (EVSYS_READYUSR) Ready User for Channel 5 */
+#define EVSYS_READYUSR_READYUSR5 (_U_(1) << EVSYS_READYUSR_READYUSR5_Pos)
+#define EVSYS_READYUSR_READYUSR6_Pos 6 /**< \brief (EVSYS_READYUSR) Ready User for Channel 6 */
+#define EVSYS_READYUSR_READYUSR6 (_U_(1) << EVSYS_READYUSR_READYUSR6_Pos)
+#define EVSYS_READYUSR_READYUSR7_Pos 7 /**< \brief (EVSYS_READYUSR) Ready User for Channel 7 */
+#define EVSYS_READYUSR_READYUSR7 (_U_(1) << EVSYS_READYUSR_READYUSR7_Pos)
+#define EVSYS_READYUSR_READYUSR8_Pos 8 /**< \brief (EVSYS_READYUSR) Ready User for Channel 8 */
+#define EVSYS_READYUSR_READYUSR8 (_U_(1) << EVSYS_READYUSR_READYUSR8_Pos)
+#define EVSYS_READYUSR_READYUSR9_Pos 9 /**< \brief (EVSYS_READYUSR) Ready User for Channel 9 */
+#define EVSYS_READYUSR_READYUSR9 (_U_(1) << EVSYS_READYUSR_READYUSR9_Pos)
+#define EVSYS_READYUSR_READYUSR10_Pos 10 /**< \brief (EVSYS_READYUSR) Ready User for Channel 10 */
+#define EVSYS_READYUSR_READYUSR10 (_U_(1) << EVSYS_READYUSR_READYUSR10_Pos)
+#define EVSYS_READYUSR_READYUSR11_Pos 11 /**< \brief (EVSYS_READYUSR) Ready User for Channel 11 */
+#define EVSYS_READYUSR_READYUSR11 (_U_(1) << EVSYS_READYUSR_READYUSR11_Pos)
+#define EVSYS_READYUSR_READYUSR_Pos 0 /**< \brief (EVSYS_READYUSR) Ready User for Channel x */
+#define EVSYS_READYUSR_READYUSR_Msk (_U_(0xFFF) << EVSYS_READYUSR_READYUSR_Pos)
+#define EVSYS_READYUSR_READYUSR(value) (EVSYS_READYUSR_READYUSR_Msk & ((value) << EVSYS_READYUSR_READYUSR_Pos))
+#define EVSYS_READYUSR_MASK _U_(0x00000FFF) /**< \brief (EVSYS_READYUSR) MASK Register */
+
+/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x020) (R/W 32) CHANNEL Channel n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EVGEN:7; /*!< bit: 0.. 6 Event Generator Selection */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t PATH:2; /*!< bit: 8.. 9 Path Selection */
+ uint32_t EDGSEL:2; /*!< bit: 10..11 Edge Detection Selection */
+ uint32_t :2; /*!< bit: 12..13 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 14 Run in standby */
+ uint32_t ONDEMAND:1; /*!< bit: 15 Generic Clock On Demand */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_CHANNEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHANNEL_OFFSET 0x020 /**< \brief (EVSYS_CHANNEL offset) Channel n Control */
+#define EVSYS_CHANNEL_RESETVALUE _U_(0x00008000) /**< \brief (EVSYS_CHANNEL reset_value) Channel n Control */
+
+#define EVSYS_CHANNEL_EVGEN_Pos 0 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
+#define EVSYS_CHANNEL_EVGEN_Msk (_U_(0x7F) << EVSYS_CHANNEL_EVGEN_Pos)
+#define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
+#define EVSYS_CHANNEL_PATH_Pos 8 /**< \brief (EVSYS_CHANNEL) Path Selection */
+#define EVSYS_CHANNEL_PATH_Msk (_U_(0x3) << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
+#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val _U_(0x0) /**< \brief (EVSYS_CHANNEL) Synchronous path */
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _U_(0x1) /**< \brief (EVSYS_CHANNEL) Resynchronized path */
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _U_(0x2) /**< \brief (EVSYS_CHANNEL) Asynchronous path */
+#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_EDGSEL_Pos 10 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
+#define EVSYS_CHANNEL_EDGSEL_Msk (_U_(0x3) << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _U_(0x0) /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _U_(0x1) /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _U_(0x2) /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _U_(0x3) /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_RUNSTDBY_Pos 14 /**< \brief (EVSYS_CHANNEL) Run in standby */
+#define EVSYS_CHANNEL_RUNSTDBY (_U_(0x1) << EVSYS_CHANNEL_RUNSTDBY_Pos)
+#define EVSYS_CHANNEL_ONDEMAND_Pos 15 /**< \brief (EVSYS_CHANNEL) Generic Clock On Demand */
+#define EVSYS_CHANNEL_ONDEMAND (_U_(0x1) << EVSYS_CHANNEL_ONDEMAND_Pos)
+#define EVSYS_CHANNEL_MASK _U_(0x0000CF7F) /**< \brief (EVSYS_CHANNEL) MASK Register */
+
+/* -------- EVSYS_CHINTENCLR : (EVSYS Offset: 0x024) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVR:1; /*!< bit: 0 Channel Overrun Interrupt Disable */
+ uint8_t EVD:1; /*!< bit: 1 Channel Event Detected Interrupt Disable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EVSYS_CHINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHINTENCLR_OFFSET 0x024 /**< \brief (EVSYS_CHINTENCLR offset) Channel n Interrupt Enable Clear */
+#define EVSYS_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */
+
+#define EVSYS_CHINTENCLR_OVR_Pos 0 /**< \brief (EVSYS_CHINTENCLR) Channel Overrun Interrupt Disable */
+#define EVSYS_CHINTENCLR_OVR (_U_(0x1) << EVSYS_CHINTENCLR_OVR_Pos)
+#define EVSYS_CHINTENCLR_EVD_Pos 1 /**< \brief (EVSYS_CHINTENCLR) Channel Event Detected Interrupt Disable */
+#define EVSYS_CHINTENCLR_EVD (_U_(0x1) << EVSYS_CHINTENCLR_EVD_Pos)
+#define EVSYS_CHINTENCLR_MASK _U_(0x03) /**< \brief (EVSYS_CHINTENCLR) MASK Register */
+
+/* -------- EVSYS_CHINTENSET : (EVSYS Offset: 0x025) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVR:1; /*!< bit: 0 Channel Overrun Interrupt Enable */
+ uint8_t EVD:1; /*!< bit: 1 Channel Event Detected Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EVSYS_CHINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHINTENSET_OFFSET 0x025 /**< \brief (EVSYS_CHINTENSET offset) Channel n Interrupt Enable Set */
+#define EVSYS_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CHINTENSET reset_value) Channel n Interrupt Enable Set */
+
+#define EVSYS_CHINTENSET_OVR_Pos 0 /**< \brief (EVSYS_CHINTENSET) Channel Overrun Interrupt Enable */
+#define EVSYS_CHINTENSET_OVR (_U_(0x1) << EVSYS_CHINTENSET_OVR_Pos)
+#define EVSYS_CHINTENSET_EVD_Pos 1 /**< \brief (EVSYS_CHINTENSET) Channel Event Detected Interrupt Enable */
+#define EVSYS_CHINTENSET_EVD (_U_(0x1) << EVSYS_CHINTENSET_EVD_Pos)
+#define EVSYS_CHINTENSET_MASK _U_(0x03) /**< \brief (EVSYS_CHINTENSET) MASK Register */
+
+/* -------- EVSYS_CHINTFLAG : (EVSYS Offset: 0x026) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t OVR:1; /*!< bit: 0 Channel Overrun */
+ __I uint8_t EVD:1; /*!< bit: 1 Channel Event Detected */
+ __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EVSYS_CHINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHINTFLAG_OFFSET 0x026 /**< \brief (EVSYS_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */
+#define EVSYS_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */
+
+#define EVSYS_CHINTFLAG_OVR_Pos 0 /**< \brief (EVSYS_CHINTFLAG) Channel Overrun */
+#define EVSYS_CHINTFLAG_OVR (_U_(0x1) << EVSYS_CHINTFLAG_OVR_Pos)
+#define EVSYS_CHINTFLAG_EVD_Pos 1 /**< \brief (EVSYS_CHINTFLAG) Channel Event Detected */
+#define EVSYS_CHINTFLAG_EVD (_U_(0x1) << EVSYS_CHINTFLAG_EVD_Pos)
+#define EVSYS_CHINTFLAG_MASK _U_(0x03) /**< \brief (EVSYS_CHINTFLAG) MASK Register */
+
+/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x027) (R/ 8) CHANNEL Channel n Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RDYUSR:1; /*!< bit: 0 Ready User */
+ uint8_t BUSYCH:1; /*!< bit: 1 Busy Channel */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EVSYS_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHSTATUS_OFFSET 0x027 /**< \brief (EVSYS_CHSTATUS offset) Channel n Status */
+#define EVSYS_CHSTATUS_RESETVALUE _U_(0x01) /**< \brief (EVSYS_CHSTATUS reset_value) Channel n Status */
+
+#define EVSYS_CHSTATUS_RDYUSR_Pos 0 /**< \brief (EVSYS_CHSTATUS) Ready User */
+#define EVSYS_CHSTATUS_RDYUSR (_U_(0x1) << EVSYS_CHSTATUS_RDYUSR_Pos)
+#define EVSYS_CHSTATUS_BUSYCH_Pos 1 /**< \brief (EVSYS_CHSTATUS) Busy Channel */
+#define EVSYS_CHSTATUS_BUSYCH (_U_(0x1) << EVSYS_CHSTATUS_BUSYCH_Pos)
+#define EVSYS_CHSTATUS_MASK _U_(0x03) /**< \brief (EVSYS_CHSTATUS) MASK Register */
+
+/* -------- EVSYS_USER : (EVSYS Offset: 0x120) (R/W 32) User Multiplexer n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHANNEL:6; /*!< bit: 0.. 5 Channel Event Selection */
+ uint32_t :26; /*!< bit: 6..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_USER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_USER_OFFSET 0x120 /**< \brief (EVSYS_USER offset) User Multiplexer n */
+#define EVSYS_USER_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_USER reset_value) User Multiplexer n */
+
+#define EVSYS_USER_CHANNEL_Pos 0 /**< \brief (EVSYS_USER) Channel Event Selection */
+#define EVSYS_USER_CHANNEL_Msk (_U_(0x3F) << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
+#define EVSYS_USER_MASK _U_(0x0000003F) /**< \brief (EVSYS_USER) MASK Register */
+
+/** \brief EvsysChannel hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x000 (R/W 32) Channel n Control */
+ __IO EVSYS_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x004 (R/W 8) Channel n Interrupt Enable Clear */
+ __IO EVSYS_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x005 (R/W 8) Channel n Interrupt Enable Set */
+ __IO EVSYS_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x006 (R/W 8) Channel n Interrupt Flag Status and Clear */
+ __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x007 (R/ 8) Channel n Status */
+} EvsysChannel;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief EVSYS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO EVSYS_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control */
+ RoReg8 Reserved1[0x3];
+ __O EVSYS_SWEVT_Type SWEVT; /**< \brief Offset: 0x004 ( /W 32) Software Event */
+ __IO EVSYS_PRICTRL_Type PRICTRL; /**< \brief Offset: 0x008 (R/W 8) Priority Control */
+ RoReg8 Reserved2[0x7];
+ __IO EVSYS_INTPEND_Type INTPEND; /**< \brief Offset: 0x010 (R/W 16) Channel Pending Interrupt */
+ RoReg8 Reserved3[0x2];
+ __I EVSYS_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x014 (R/ 32) Interrupt Status */
+ __I EVSYS_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x018 (R/ 32) Busy Channels */
+ __I EVSYS_READYUSR_Type READYUSR; /**< \brief Offset: 0x01C (R/ 32) Ready Users */
+ EvsysChannel Channel[32]; /**< \brief Offset: 0x020 EvsysChannel groups [CHANNELS] */
+ __IO EVSYS_USER_Type USER[67]; /**< \brief Offset: 0x120 (R/W 32) User Multiplexer n */
+} Evsys;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_EVSYS_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/freqm.h b/sysmoOCTSIM/include/component/freqm.h
index 6182fb3..34e62f9 100644
--- a/sysmoOCTSIM/include/component/freqm.h
+++ b/sysmoOCTSIM/include/component/freqm.h
@@ -1,233 +1,233 @@
-/**
- * \file
- *
- * \brief Component description for FREQM
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_FREQM_COMPONENT_
-#define _SAME54_FREQM_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR FREQM */
-/* ========================================================================== */
-/** \addtogroup SAME54_FREQM Frequency Meter */
-/*@{*/
-
-#define FREQM_U2257
-#define REV_FREQM 0x110
-
-/* -------- FREQM_CTRLA : (FREQM Offset: 0x00) (R/W 8) Control A Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} FREQM_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define FREQM_CTRLA_OFFSET 0x00 /**< \brief (FREQM_CTRLA offset) Control A Register */
-#define FREQM_CTRLA_RESETVALUE _U_(0x00) /**< \brief (FREQM_CTRLA reset_value) Control A Register */
-
-#define FREQM_CTRLA_SWRST_Pos 0 /**< \brief (FREQM_CTRLA) Software Reset */
-#define FREQM_CTRLA_SWRST (_U_(0x1) << FREQM_CTRLA_SWRST_Pos)
-#define FREQM_CTRLA_ENABLE_Pos 1 /**< \brief (FREQM_CTRLA) Enable */
-#define FREQM_CTRLA_ENABLE (_U_(0x1) << FREQM_CTRLA_ENABLE_Pos)
-#define FREQM_CTRLA_MASK _U_(0x03) /**< \brief (FREQM_CTRLA) MASK Register */
-
-/* -------- FREQM_CTRLB : (FREQM Offset: 0x01) ( /W 8) Control B Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t START:1; /*!< bit: 0 Start Measurement */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} FREQM_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define FREQM_CTRLB_OFFSET 0x01 /**< \brief (FREQM_CTRLB offset) Control B Register */
-#define FREQM_CTRLB_RESETVALUE _U_(0x00) /**< \brief (FREQM_CTRLB reset_value) Control B Register */
-
-#define FREQM_CTRLB_START_Pos 0 /**< \brief (FREQM_CTRLB) Start Measurement */
-#define FREQM_CTRLB_START (_U_(0x1) << FREQM_CTRLB_START_Pos)
-#define FREQM_CTRLB_MASK _U_(0x01) /**< \brief (FREQM_CTRLB) MASK Register */
-
-/* -------- FREQM_CFGA : (FREQM Offset: 0x02) (R/W 16) Config A register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t REFNUM:8; /*!< bit: 0.. 7 Number of Reference Clock Cycles */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} FREQM_CFGA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define FREQM_CFGA_OFFSET 0x02 /**< \brief (FREQM_CFGA offset) Config A register */
-#define FREQM_CFGA_RESETVALUE _U_(0x0000) /**< \brief (FREQM_CFGA reset_value) Config A register */
-
-#define FREQM_CFGA_REFNUM_Pos 0 /**< \brief (FREQM_CFGA) Number of Reference Clock Cycles */
-#define FREQM_CFGA_REFNUM_Msk (_U_(0xFF) << FREQM_CFGA_REFNUM_Pos)
-#define FREQM_CFGA_REFNUM(value) (FREQM_CFGA_REFNUM_Msk & ((value) << FREQM_CFGA_REFNUM_Pos))
-#define FREQM_CFGA_MASK _U_(0x00FF) /**< \brief (FREQM_CFGA) MASK Register */
-
-/* -------- FREQM_INTENCLR : (FREQM Offset: 0x08) (R/W 8) Interrupt Enable Clear Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DONE:1; /*!< bit: 0 Measurement Done Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} FREQM_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define FREQM_INTENCLR_OFFSET 0x08 /**< \brief (FREQM_INTENCLR offset) Interrupt Enable Clear Register */
-#define FREQM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTENCLR reset_value) Interrupt Enable Clear Register */
-
-#define FREQM_INTENCLR_DONE_Pos 0 /**< \brief (FREQM_INTENCLR) Measurement Done Interrupt Enable */
-#define FREQM_INTENCLR_DONE (_U_(0x1) << FREQM_INTENCLR_DONE_Pos)
-#define FREQM_INTENCLR_MASK _U_(0x01) /**< \brief (FREQM_INTENCLR) MASK Register */
-
-/* -------- FREQM_INTENSET : (FREQM Offset: 0x09) (R/W 8) Interrupt Enable Set Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DONE:1; /*!< bit: 0 Measurement Done Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} FREQM_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define FREQM_INTENSET_OFFSET 0x09 /**< \brief (FREQM_INTENSET offset) Interrupt Enable Set Register */
-#define FREQM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTENSET reset_value) Interrupt Enable Set Register */
-
-#define FREQM_INTENSET_DONE_Pos 0 /**< \brief (FREQM_INTENSET) Measurement Done Interrupt Enable */
-#define FREQM_INTENSET_DONE (_U_(0x1) << FREQM_INTENSET_DONE_Pos)
-#define FREQM_INTENSET_MASK _U_(0x01) /**< \brief (FREQM_INTENSET) MASK Register */
-
-/* -------- FREQM_INTFLAG : (FREQM Offset: 0x0A) (R/W 8) Interrupt Flag Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t DONE:1; /*!< bit: 0 Measurement Done */
- __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} FREQM_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define FREQM_INTFLAG_OFFSET 0x0A /**< \brief (FREQM_INTFLAG offset) Interrupt Flag Register */
-#define FREQM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTFLAG reset_value) Interrupt Flag Register */
-
-#define FREQM_INTFLAG_DONE_Pos 0 /**< \brief (FREQM_INTFLAG) Measurement Done */
-#define FREQM_INTFLAG_DONE (_U_(0x1) << FREQM_INTFLAG_DONE_Pos)
-#define FREQM_INTFLAG_MASK _U_(0x01) /**< \brief (FREQM_INTFLAG) MASK Register */
-
-/* -------- FREQM_STATUS : (FREQM Offset: 0x0B) (R/W 8) Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t BUSY:1; /*!< bit: 0 FREQM Status */
- uint8_t OVF:1; /*!< bit: 1 Sticky Count Value Overflow */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} FREQM_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define FREQM_STATUS_OFFSET 0x0B /**< \brief (FREQM_STATUS offset) Status Register */
-#define FREQM_STATUS_RESETVALUE _U_(0x00) /**< \brief (FREQM_STATUS reset_value) Status Register */
-
-#define FREQM_STATUS_BUSY_Pos 0 /**< \brief (FREQM_STATUS) FREQM Status */
-#define FREQM_STATUS_BUSY (_U_(0x1) << FREQM_STATUS_BUSY_Pos)
-#define FREQM_STATUS_OVF_Pos 1 /**< \brief (FREQM_STATUS) Sticky Count Value Overflow */
-#define FREQM_STATUS_OVF (_U_(0x1) << FREQM_STATUS_OVF_Pos)
-#define FREQM_STATUS_MASK _U_(0x03) /**< \brief (FREQM_STATUS) MASK Register */
-
-/* -------- FREQM_SYNCBUSY : (FREQM Offset: 0x0C) (R/ 32) Synchronization Busy Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} FREQM_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define FREQM_SYNCBUSY_OFFSET 0x0C /**< \brief (FREQM_SYNCBUSY offset) Synchronization Busy Register */
-#define FREQM_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (FREQM_SYNCBUSY reset_value) Synchronization Busy Register */
-
-#define FREQM_SYNCBUSY_SWRST_Pos 0 /**< \brief (FREQM_SYNCBUSY) Software Reset */
-#define FREQM_SYNCBUSY_SWRST (_U_(0x1) << FREQM_SYNCBUSY_SWRST_Pos)
-#define FREQM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (FREQM_SYNCBUSY) Enable */
-#define FREQM_SYNCBUSY_ENABLE (_U_(0x1) << FREQM_SYNCBUSY_ENABLE_Pos)
-#define FREQM_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (FREQM_SYNCBUSY) MASK Register */
-
-/* -------- FREQM_VALUE : (FREQM Offset: 0x10) (R/ 32) Count Value Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t VALUE:24; /*!< bit: 0..23 Measurement Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} FREQM_VALUE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define FREQM_VALUE_OFFSET 0x10 /**< \brief (FREQM_VALUE offset) Count Value Register */
-#define FREQM_VALUE_RESETVALUE _U_(0x00000000) /**< \brief (FREQM_VALUE reset_value) Count Value Register */
-
-#define FREQM_VALUE_VALUE_Pos 0 /**< \brief (FREQM_VALUE) Measurement Value */
-#define FREQM_VALUE_VALUE_Msk (_U_(0xFFFFFF) << FREQM_VALUE_VALUE_Pos)
-#define FREQM_VALUE_VALUE(value) (FREQM_VALUE_VALUE_Msk & ((value) << FREQM_VALUE_VALUE_Pos))
-#define FREQM_VALUE_MASK _U_(0x00FFFFFF) /**< \brief (FREQM_VALUE) MASK Register */
-
-/** \brief FREQM hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO FREQM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A Register */
- __O FREQM_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B Register */
- __IO FREQM_CFGA_Type CFGA; /**< \brief Offset: 0x02 (R/W 16) Config A register */
- RoReg8 Reserved1[0x4];
- __IO FREQM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear Register */
- __IO FREQM_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set Register */
- __IO FREQM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Register */
- __IO FREQM_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status Register */
- __I FREQM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x0C (R/ 32) Synchronization Busy Register */
- __I FREQM_VALUE_Type VALUE; /**< \brief Offset: 0x10 (R/ 32) Count Value Register */
-} Freqm;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_FREQM_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for FREQM
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_FREQM_COMPONENT_
+#define _SAME54_FREQM_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR FREQM */
+/* ========================================================================== */
+/** \addtogroup SAME54_FREQM Frequency Meter */
+/*@{*/
+
+#define FREQM_U2257
+#define REV_FREQM 0x110
+
+/* -------- FREQM_CTRLA : (FREQM Offset: 0x00) (R/W 8) Control A Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} FREQM_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_CTRLA_OFFSET 0x00 /**< \brief (FREQM_CTRLA offset) Control A Register */
+#define FREQM_CTRLA_RESETVALUE _U_(0x00) /**< \brief (FREQM_CTRLA reset_value) Control A Register */
+
+#define FREQM_CTRLA_SWRST_Pos 0 /**< \brief (FREQM_CTRLA) Software Reset */
+#define FREQM_CTRLA_SWRST (_U_(0x1) << FREQM_CTRLA_SWRST_Pos)
+#define FREQM_CTRLA_ENABLE_Pos 1 /**< \brief (FREQM_CTRLA) Enable */
+#define FREQM_CTRLA_ENABLE (_U_(0x1) << FREQM_CTRLA_ENABLE_Pos)
+#define FREQM_CTRLA_MASK _U_(0x03) /**< \brief (FREQM_CTRLA) MASK Register */
+
+/* -------- FREQM_CTRLB : (FREQM Offset: 0x01) ( /W 8) Control B Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t START:1; /*!< bit: 0 Start Measurement */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} FREQM_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_CTRLB_OFFSET 0x01 /**< \brief (FREQM_CTRLB offset) Control B Register */
+#define FREQM_CTRLB_RESETVALUE _U_(0x00) /**< \brief (FREQM_CTRLB reset_value) Control B Register */
+
+#define FREQM_CTRLB_START_Pos 0 /**< \brief (FREQM_CTRLB) Start Measurement */
+#define FREQM_CTRLB_START (_U_(0x1) << FREQM_CTRLB_START_Pos)
+#define FREQM_CTRLB_MASK _U_(0x01) /**< \brief (FREQM_CTRLB) MASK Register */
+
+/* -------- FREQM_CFGA : (FREQM Offset: 0x02) (R/W 16) Config A register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t REFNUM:8; /*!< bit: 0.. 7 Number of Reference Clock Cycles */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} FREQM_CFGA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_CFGA_OFFSET 0x02 /**< \brief (FREQM_CFGA offset) Config A register */
+#define FREQM_CFGA_RESETVALUE _U_(0x0000) /**< \brief (FREQM_CFGA reset_value) Config A register */
+
+#define FREQM_CFGA_REFNUM_Pos 0 /**< \brief (FREQM_CFGA) Number of Reference Clock Cycles */
+#define FREQM_CFGA_REFNUM_Msk (_U_(0xFF) << FREQM_CFGA_REFNUM_Pos)
+#define FREQM_CFGA_REFNUM(value) (FREQM_CFGA_REFNUM_Msk & ((value) << FREQM_CFGA_REFNUM_Pos))
+#define FREQM_CFGA_MASK _U_(0x00FF) /**< \brief (FREQM_CFGA) MASK Register */
+
+/* -------- FREQM_INTENCLR : (FREQM Offset: 0x08) (R/W 8) Interrupt Enable Clear Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DONE:1; /*!< bit: 0 Measurement Done Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} FREQM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_INTENCLR_OFFSET 0x08 /**< \brief (FREQM_INTENCLR offset) Interrupt Enable Clear Register */
+#define FREQM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTENCLR reset_value) Interrupt Enable Clear Register */
+
+#define FREQM_INTENCLR_DONE_Pos 0 /**< \brief (FREQM_INTENCLR) Measurement Done Interrupt Enable */
+#define FREQM_INTENCLR_DONE (_U_(0x1) << FREQM_INTENCLR_DONE_Pos)
+#define FREQM_INTENCLR_MASK _U_(0x01) /**< \brief (FREQM_INTENCLR) MASK Register */
+
+/* -------- FREQM_INTENSET : (FREQM Offset: 0x09) (R/W 8) Interrupt Enable Set Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DONE:1; /*!< bit: 0 Measurement Done Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} FREQM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_INTENSET_OFFSET 0x09 /**< \brief (FREQM_INTENSET offset) Interrupt Enable Set Register */
+#define FREQM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTENSET reset_value) Interrupt Enable Set Register */
+
+#define FREQM_INTENSET_DONE_Pos 0 /**< \brief (FREQM_INTENSET) Measurement Done Interrupt Enable */
+#define FREQM_INTENSET_DONE (_U_(0x1) << FREQM_INTENSET_DONE_Pos)
+#define FREQM_INTENSET_MASK _U_(0x01) /**< \brief (FREQM_INTENSET) MASK Register */
+
+/* -------- FREQM_INTFLAG : (FREQM Offset: 0x0A) (R/W 8) Interrupt Flag Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t DONE:1; /*!< bit: 0 Measurement Done */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} FREQM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_INTFLAG_OFFSET 0x0A /**< \brief (FREQM_INTFLAG offset) Interrupt Flag Register */
+#define FREQM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTFLAG reset_value) Interrupt Flag Register */
+
+#define FREQM_INTFLAG_DONE_Pos 0 /**< \brief (FREQM_INTFLAG) Measurement Done */
+#define FREQM_INTFLAG_DONE (_U_(0x1) << FREQM_INTFLAG_DONE_Pos)
+#define FREQM_INTFLAG_MASK _U_(0x01) /**< \brief (FREQM_INTFLAG) MASK Register */
+
+/* -------- FREQM_STATUS : (FREQM Offset: 0x0B) (R/W 8) Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t BUSY:1; /*!< bit: 0 FREQM Status */
+ uint8_t OVF:1; /*!< bit: 1 Sticky Count Value Overflow */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} FREQM_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_STATUS_OFFSET 0x0B /**< \brief (FREQM_STATUS offset) Status Register */
+#define FREQM_STATUS_RESETVALUE _U_(0x00) /**< \brief (FREQM_STATUS reset_value) Status Register */
+
+#define FREQM_STATUS_BUSY_Pos 0 /**< \brief (FREQM_STATUS) FREQM Status */
+#define FREQM_STATUS_BUSY (_U_(0x1) << FREQM_STATUS_BUSY_Pos)
+#define FREQM_STATUS_OVF_Pos 1 /**< \brief (FREQM_STATUS) Sticky Count Value Overflow */
+#define FREQM_STATUS_OVF (_U_(0x1) << FREQM_STATUS_OVF_Pos)
+#define FREQM_STATUS_MASK _U_(0x03) /**< \brief (FREQM_STATUS) MASK Register */
+
+/* -------- FREQM_SYNCBUSY : (FREQM Offset: 0x0C) (R/ 32) Synchronization Busy Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} FREQM_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_SYNCBUSY_OFFSET 0x0C /**< \brief (FREQM_SYNCBUSY offset) Synchronization Busy Register */
+#define FREQM_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (FREQM_SYNCBUSY reset_value) Synchronization Busy Register */
+
+#define FREQM_SYNCBUSY_SWRST_Pos 0 /**< \brief (FREQM_SYNCBUSY) Software Reset */
+#define FREQM_SYNCBUSY_SWRST (_U_(0x1) << FREQM_SYNCBUSY_SWRST_Pos)
+#define FREQM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (FREQM_SYNCBUSY) Enable */
+#define FREQM_SYNCBUSY_ENABLE (_U_(0x1) << FREQM_SYNCBUSY_ENABLE_Pos)
+#define FREQM_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (FREQM_SYNCBUSY) MASK Register */
+
+/* -------- FREQM_VALUE : (FREQM Offset: 0x10) (R/ 32) Count Value Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t VALUE:24; /*!< bit: 0..23 Measurement Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} FREQM_VALUE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_VALUE_OFFSET 0x10 /**< \brief (FREQM_VALUE offset) Count Value Register */
+#define FREQM_VALUE_RESETVALUE _U_(0x00000000) /**< \brief (FREQM_VALUE reset_value) Count Value Register */
+
+#define FREQM_VALUE_VALUE_Pos 0 /**< \brief (FREQM_VALUE) Measurement Value */
+#define FREQM_VALUE_VALUE_Msk (_U_(0xFFFFFF) << FREQM_VALUE_VALUE_Pos)
+#define FREQM_VALUE_VALUE(value) (FREQM_VALUE_VALUE_Msk & ((value) << FREQM_VALUE_VALUE_Pos))
+#define FREQM_VALUE_MASK _U_(0x00FFFFFF) /**< \brief (FREQM_VALUE) MASK Register */
+
+/** \brief FREQM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO FREQM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A Register */
+ __O FREQM_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B Register */
+ __IO FREQM_CFGA_Type CFGA; /**< \brief Offset: 0x02 (R/W 16) Config A register */
+ RoReg8 Reserved1[0x4];
+ __IO FREQM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear Register */
+ __IO FREQM_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set Register */
+ __IO FREQM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Register */
+ __IO FREQM_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status Register */
+ __I FREQM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x0C (R/ 32) Synchronization Busy Register */
+ __I FREQM_VALUE_Type VALUE; /**< \brief Offset: 0x10 (R/ 32) Count Value Register */
+} Freqm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_FREQM_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/gclk.h b/sysmoOCTSIM/include/component/gclk.h
index e3ee39a..4d8dfc0 100644
--- a/sysmoOCTSIM/include/component/gclk.h
+++ b/sysmoOCTSIM/include/component/gclk.h
@@ -1,272 +1,272 @@
-/**
- * \file
- *
- * \brief Component description for GCLK
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_GCLK_COMPONENT_
-#define _SAME54_GCLK_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR GCLK */
-/* ========================================================================== */
-/** \addtogroup SAME54_GCLK Generic Clock Generator */
-/*@{*/
-
-#define GCLK_U2122
-#define REV_GCLK 0x120
-
-/* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} GCLK_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GCLK_CTRLA_OFFSET 0x00 /**< \brief (GCLK_CTRLA offset) Control */
-#define GCLK_CTRLA_RESETVALUE _U_(0x00) /**< \brief (GCLK_CTRLA reset_value) Control */
-
-#define GCLK_CTRLA_SWRST_Pos 0 /**< \brief (GCLK_CTRLA) Software Reset */
-#define GCLK_CTRLA_SWRST (_U_(0x1) << GCLK_CTRLA_SWRST_Pos)
-#define GCLK_CTRLA_MASK _U_(0x01) /**< \brief (GCLK_CTRLA) MASK Register */
-
-/* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) (R/ 32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchroniation Busy bit */
- uint32_t :1; /*!< bit: 1 Reserved */
- uint32_t GENCTRL0:1; /*!< bit: 2 Generic Clock Generator Control 0 Synchronization Busy bits */
- uint32_t GENCTRL1:1; /*!< bit: 3 Generic Clock Generator Control 1 Synchronization Busy bits */
- uint32_t GENCTRL2:1; /*!< bit: 4 Generic Clock Generator Control 2 Synchronization Busy bits */
- uint32_t GENCTRL3:1; /*!< bit: 5 Generic Clock Generator Control 3 Synchronization Busy bits */
- uint32_t GENCTRL4:1; /*!< bit: 6 Generic Clock Generator Control 4 Synchronization Busy bits */
- uint32_t GENCTRL5:1; /*!< bit: 7 Generic Clock Generator Control 5 Synchronization Busy bits */
- uint32_t GENCTRL6:1; /*!< bit: 8 Generic Clock Generator Control 6 Synchronization Busy bits */
- uint32_t GENCTRL7:1; /*!< bit: 9 Generic Clock Generator Control 7 Synchronization Busy bits */
- uint32_t GENCTRL8:1; /*!< bit: 10 Generic Clock Generator Control 8 Synchronization Busy bits */
- uint32_t GENCTRL9:1; /*!< bit: 11 Generic Clock Generator Control 9 Synchronization Busy bits */
- uint32_t GENCTRL10:1; /*!< bit: 12 Generic Clock Generator Control 10 Synchronization Busy bits */
- uint32_t GENCTRL11:1; /*!< bit: 13 Generic Clock Generator Control 11 Synchronization Busy bits */
- uint32_t :18; /*!< bit: 14..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t GENCTRL:12; /*!< bit: 2..13 Generic Clock Generator Control x Synchronization Busy bits */
- uint32_t :18; /*!< bit: 14..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} GCLK_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GCLK_SYNCBUSY_OFFSET 0x04 /**< \brief (GCLK_SYNCBUSY offset) Synchronization Busy */
-#define GCLK_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_SYNCBUSY reset_value) Synchronization Busy */
-
-#define GCLK_SYNCBUSY_SWRST_Pos 0 /**< \brief (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit */
-#define GCLK_SYNCBUSY_SWRST (_U_(0x1) << GCLK_SYNCBUSY_SWRST_Pos)
-#define GCLK_SYNCBUSY_GENCTRL0_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 0 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL0 (_U_(1) << GCLK_SYNCBUSY_GENCTRL0_Pos)
-#define GCLK_SYNCBUSY_GENCTRL1_Pos 3 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 1 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL1 (_U_(1) << GCLK_SYNCBUSY_GENCTRL1_Pos)
-#define GCLK_SYNCBUSY_GENCTRL2_Pos 4 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 2 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL2 (_U_(1) << GCLK_SYNCBUSY_GENCTRL2_Pos)
-#define GCLK_SYNCBUSY_GENCTRL3_Pos 5 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 3 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL3 (_U_(1) << GCLK_SYNCBUSY_GENCTRL3_Pos)
-#define GCLK_SYNCBUSY_GENCTRL4_Pos 6 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 4 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL4 (_U_(1) << GCLK_SYNCBUSY_GENCTRL4_Pos)
-#define GCLK_SYNCBUSY_GENCTRL5_Pos 7 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 5 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL5 (_U_(1) << GCLK_SYNCBUSY_GENCTRL5_Pos)
-#define GCLK_SYNCBUSY_GENCTRL6_Pos 8 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 6 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL6 (_U_(1) << GCLK_SYNCBUSY_GENCTRL6_Pos)
-#define GCLK_SYNCBUSY_GENCTRL7_Pos 9 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 7 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL7 (_U_(1) << GCLK_SYNCBUSY_GENCTRL7_Pos)
-#define GCLK_SYNCBUSY_GENCTRL8_Pos 10 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 8 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL8 (_U_(1) << GCLK_SYNCBUSY_GENCTRL8_Pos)
-#define GCLK_SYNCBUSY_GENCTRL9_Pos 11 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 9 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL9 (_U_(1) << GCLK_SYNCBUSY_GENCTRL9_Pos)
-#define GCLK_SYNCBUSY_GENCTRL10_Pos 12 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 10 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL10 (_U_(1) << GCLK_SYNCBUSY_GENCTRL10_Pos)
-#define GCLK_SYNCBUSY_GENCTRL11_Pos 13 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 11 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL11 (_U_(1) << GCLK_SYNCBUSY_GENCTRL11_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control x Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL_Msk (_U_(0xFFF) << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL(value) (GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos))
-#define GCLK_SYNCBUSY_GENCTRL_GCLK0_Val _U_(0x1) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 0 */
-#define GCLK_SYNCBUSY_GENCTRL_GCLK1_Val _U_(0x2) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 1 */
-#define GCLK_SYNCBUSY_GENCTRL_GCLK2_Val _U_(0x4) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 2 */
-#define GCLK_SYNCBUSY_GENCTRL_GCLK3_Val _U_(0x8) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 3 */
-#define GCLK_SYNCBUSY_GENCTRL_GCLK4_Val _U_(0x10) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 4 */
-#define GCLK_SYNCBUSY_GENCTRL_GCLK5_Val _U_(0x20) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 5 */
-#define GCLK_SYNCBUSY_GENCTRL_GCLK6_Val _U_(0x40) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 6 */
-#define GCLK_SYNCBUSY_GENCTRL_GCLK7_Val _U_(0x80) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 7 */
-#define GCLK_SYNCBUSY_GENCTRL_GCLK8_Val _U_(0x100) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 8 */
-#define GCLK_SYNCBUSY_GENCTRL_GCLK9_Val _U_(0x200) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 9 */
-#define GCLK_SYNCBUSY_GENCTRL_GCLK10_Val _U_(0x400) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 10 */
-#define GCLK_SYNCBUSY_GENCTRL_GCLK11_Val _U_(0x800) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 11 */
-#define GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK9 (GCLK_SYNCBUSY_GENCTRL_GCLK9_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK10 (GCLK_SYNCBUSY_GENCTRL_GCLK10_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK11 (GCLK_SYNCBUSY_GENCTRL_GCLK11_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_MASK _U_(0x00003FFD) /**< \brief (GCLK_SYNCBUSY) MASK Register */
-
-/* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SRC:4; /*!< bit: 0.. 3 Source Select */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t GENEN:1; /*!< bit: 8 Generic Clock Generator Enable */
- uint32_t IDC:1; /*!< bit: 9 Improve Duty Cycle */
- uint32_t OOV:1; /*!< bit: 10 Output Off Value */
- uint32_t OE:1; /*!< bit: 11 Output Enable */
- uint32_t DIVSEL:1; /*!< bit: 12 Divide Selection */
- uint32_t RUNSTDBY:1; /*!< bit: 13 Run in Standby */
- uint32_t :2; /*!< bit: 14..15 Reserved */
- uint32_t DIV:16; /*!< bit: 16..31 Division Factor */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GCLK_GENCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GCLK_GENCTRL_OFFSET 0x20 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
-#define GCLK_GENCTRL_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
-
-#define GCLK_GENCTRL_SRC_Pos 0 /**< \brief (GCLK_GENCTRL) Source Select */
-#define GCLK_GENCTRL_SRC_Msk (_U_(0xF) << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
-#define GCLK_GENCTRL_SRC_XOSC0_Val _U_(0x0) /**< \brief (GCLK_GENCTRL) XOSC0 oscillator output */
-#define GCLK_GENCTRL_SRC_XOSC1_Val _U_(0x1) /**< \brief (GCLK_GENCTRL) XOSC1 oscillator output */
-#define GCLK_GENCTRL_SRC_GCLKIN_Val _U_(0x2) /**< \brief (GCLK_GENCTRL) Generator input pad */
-#define GCLK_GENCTRL_SRC_GCLKGEN1_Val _U_(0x3) /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
-#define GCLK_GENCTRL_SRC_OSCULP32K_Val _U_(0x4) /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
-#define GCLK_GENCTRL_SRC_XOSC32K_Val _U_(0x5) /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
-#define GCLK_GENCTRL_SRC_DFLL_Val _U_(0x6) /**< \brief (GCLK_GENCTRL) DFLL output */
-#define GCLK_GENCTRL_SRC_DPLL0_Val _U_(0x7) /**< \brief (GCLK_GENCTRL) DPLL0 output */
-#define GCLK_GENCTRL_SRC_DPLL1_Val _U_(0x8) /**< \brief (GCLK_GENCTRL) DPLL1 output */
-#define GCLK_GENCTRL_SRC_XOSC0 (GCLK_GENCTRL_SRC_XOSC0_Val << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_XOSC1 (GCLK_GENCTRL_SRC_XOSC1_Val << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_DFLL (GCLK_GENCTRL_SRC_DFLL_Val << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_DPLL0 (GCLK_GENCTRL_SRC_DPLL0_Val << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_DPLL1 (GCLK_GENCTRL_SRC_DPLL1_Val << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_GENEN_Pos 8 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
-#define GCLK_GENCTRL_GENEN (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos)
-#define GCLK_GENCTRL_IDC_Pos 9 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
-#define GCLK_GENCTRL_IDC (_U_(0x1) << GCLK_GENCTRL_IDC_Pos)
-#define GCLK_GENCTRL_OOV_Pos 10 /**< \brief (GCLK_GENCTRL) Output Off Value */
-#define GCLK_GENCTRL_OOV (_U_(0x1) << GCLK_GENCTRL_OOV_Pos)
-#define GCLK_GENCTRL_OE_Pos 11 /**< \brief (GCLK_GENCTRL) Output Enable */
-#define GCLK_GENCTRL_OE (_U_(0x1) << GCLK_GENCTRL_OE_Pos)
-#define GCLK_GENCTRL_DIVSEL_Pos 12 /**< \brief (GCLK_GENCTRL) Divide Selection */
-#define GCLK_GENCTRL_DIVSEL (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos)
-#define GCLK_GENCTRL_RUNSTDBY_Pos 13 /**< \brief (GCLK_GENCTRL) Run in Standby */
-#define GCLK_GENCTRL_RUNSTDBY (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)
-#define GCLK_GENCTRL_DIV_Pos 16 /**< \brief (GCLK_GENCTRL) Division Factor */
-#define GCLK_GENCTRL_DIV_Msk (_U_(0xFFFF) << GCLK_GENCTRL_DIV_Pos)
-#define GCLK_GENCTRL_DIV(value) (GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos))
-#define GCLK_GENCTRL_MASK _U_(0xFFFF3F0F) /**< \brief (GCLK_GENCTRL) MASK Register */
-
-/* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t GEN:4; /*!< bit: 0.. 3 Generic Clock Generator */
- uint32_t :2; /*!< bit: 4.. 5 Reserved */
- uint32_t CHEN:1; /*!< bit: 6 Channel Enable */
- uint32_t WRTLOCK:1; /*!< bit: 7 Write Lock */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GCLK_PCHCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GCLK_PCHCTRL_OFFSET 0x80 /**< \brief (GCLK_PCHCTRL offset) Peripheral Clock Control */
-#define GCLK_PCHCTRL_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_PCHCTRL reset_value) Peripheral Clock Control */
-
-#define GCLK_PCHCTRL_GEN_Pos 0 /**< \brief (GCLK_PCHCTRL) Generic Clock Generator */
-#define GCLK_PCHCTRL_GEN_Msk (_U_(0xF) << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN(value) (GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos))
-#define GCLK_PCHCTRL_GEN_GCLK0_Val _U_(0x0) /**< \brief (GCLK_PCHCTRL) Generic clock generator 0 */
-#define GCLK_PCHCTRL_GEN_GCLK1_Val _U_(0x1) /**< \brief (GCLK_PCHCTRL) Generic clock generator 1 */
-#define GCLK_PCHCTRL_GEN_GCLK2_Val _U_(0x2) /**< \brief (GCLK_PCHCTRL) Generic clock generator 2 */
-#define GCLK_PCHCTRL_GEN_GCLK3_Val _U_(0x3) /**< \brief (GCLK_PCHCTRL) Generic clock generator 3 */
-#define GCLK_PCHCTRL_GEN_GCLK4_Val _U_(0x4) /**< \brief (GCLK_PCHCTRL) Generic clock generator 4 */
-#define GCLK_PCHCTRL_GEN_GCLK5_Val _U_(0x5) /**< \brief (GCLK_PCHCTRL) Generic clock generator 5 */
-#define GCLK_PCHCTRL_GEN_GCLK6_Val _U_(0x6) /**< \brief (GCLK_PCHCTRL) Generic clock generator 6 */
-#define GCLK_PCHCTRL_GEN_GCLK7_Val _U_(0x7) /**< \brief (GCLK_PCHCTRL) Generic clock generator 7 */
-#define GCLK_PCHCTRL_GEN_GCLK8_Val _U_(0x8) /**< \brief (GCLK_PCHCTRL) Generic clock generator 8 */
-#define GCLK_PCHCTRL_GEN_GCLK9_Val _U_(0x9) /**< \brief (GCLK_PCHCTRL) Generic clock generator 9 */
-#define GCLK_PCHCTRL_GEN_GCLK10_Val _U_(0xA) /**< \brief (GCLK_PCHCTRL) Generic clock generator 10 */
-#define GCLK_PCHCTRL_GEN_GCLK11_Val _U_(0xB) /**< \brief (GCLK_PCHCTRL) Generic clock generator 11 */
-#define GCLK_PCHCTRL_GEN_GCLK0 (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK1 (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK2 (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK3 (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK4 (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK5 (GCLK_PCHCTRL_GEN_GCLK5_Val << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK6 (GCLK_PCHCTRL_GEN_GCLK6_Val << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK7 (GCLK_PCHCTRL_GEN_GCLK7_Val << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK8 (GCLK_PCHCTRL_GEN_GCLK8_Val << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK9 (GCLK_PCHCTRL_GEN_GCLK9_Val << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK10 (GCLK_PCHCTRL_GEN_GCLK10_Val << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK11 (GCLK_PCHCTRL_GEN_GCLK11_Val << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_CHEN_Pos 6 /**< \brief (GCLK_PCHCTRL) Channel Enable */
-#define GCLK_PCHCTRL_CHEN (_U_(0x1) << GCLK_PCHCTRL_CHEN_Pos)
-#define GCLK_PCHCTRL_WRTLOCK_Pos 7 /**< \brief (GCLK_PCHCTRL) Write Lock */
-#define GCLK_PCHCTRL_WRTLOCK (_U_(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos)
-#define GCLK_PCHCTRL_MASK _U_(0x000000CF) /**< \brief (GCLK_PCHCTRL) MASK Register */
-
-/** \brief GCLK hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO GCLK_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */
- RoReg8 Reserved1[0x3];
- __I GCLK_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Synchronization Busy */
- RoReg8 Reserved2[0x18];
- __IO GCLK_GENCTRL_Type GENCTRL[12]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Generator Control */
- RoReg8 Reserved3[0x30];
- __IO GCLK_PCHCTRL_Type PCHCTRL[48]; /**< \brief Offset: 0x80 (R/W 32) Peripheral Clock Control */
-} Gclk;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_GCLK_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for GCLK
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_GCLK_COMPONENT_
+#define _SAME54_GCLK_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR GCLK */
+/* ========================================================================== */
+/** \addtogroup SAME54_GCLK Generic Clock Generator */
+/*@{*/
+
+#define GCLK_U2122
+#define REV_GCLK 0x120
+
+/* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} GCLK_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_CTRLA_OFFSET 0x00 /**< \brief (GCLK_CTRLA offset) Control */
+#define GCLK_CTRLA_RESETVALUE _U_(0x00) /**< \brief (GCLK_CTRLA reset_value) Control */
+
+#define GCLK_CTRLA_SWRST_Pos 0 /**< \brief (GCLK_CTRLA) Software Reset */
+#define GCLK_CTRLA_SWRST (_U_(0x1) << GCLK_CTRLA_SWRST_Pos)
+#define GCLK_CTRLA_MASK _U_(0x01) /**< \brief (GCLK_CTRLA) MASK Register */
+
+/* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) (R/ 32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchroniation Busy bit */
+ uint32_t :1; /*!< bit: 1 Reserved */
+ uint32_t GENCTRL0:1; /*!< bit: 2 Generic Clock Generator Control 0 Synchronization Busy bits */
+ uint32_t GENCTRL1:1; /*!< bit: 3 Generic Clock Generator Control 1 Synchronization Busy bits */
+ uint32_t GENCTRL2:1; /*!< bit: 4 Generic Clock Generator Control 2 Synchronization Busy bits */
+ uint32_t GENCTRL3:1; /*!< bit: 5 Generic Clock Generator Control 3 Synchronization Busy bits */
+ uint32_t GENCTRL4:1; /*!< bit: 6 Generic Clock Generator Control 4 Synchronization Busy bits */
+ uint32_t GENCTRL5:1; /*!< bit: 7 Generic Clock Generator Control 5 Synchronization Busy bits */
+ uint32_t GENCTRL6:1; /*!< bit: 8 Generic Clock Generator Control 6 Synchronization Busy bits */
+ uint32_t GENCTRL7:1; /*!< bit: 9 Generic Clock Generator Control 7 Synchronization Busy bits */
+ uint32_t GENCTRL8:1; /*!< bit: 10 Generic Clock Generator Control 8 Synchronization Busy bits */
+ uint32_t GENCTRL9:1; /*!< bit: 11 Generic Clock Generator Control 9 Synchronization Busy bits */
+ uint32_t GENCTRL10:1; /*!< bit: 12 Generic Clock Generator Control 10 Synchronization Busy bits */
+ uint32_t GENCTRL11:1; /*!< bit: 13 Generic Clock Generator Control 11 Synchronization Busy bits */
+ uint32_t :18; /*!< bit: 14..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t GENCTRL:12; /*!< bit: 2..13 Generic Clock Generator Control x Synchronization Busy bits */
+ uint32_t :18; /*!< bit: 14..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} GCLK_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_SYNCBUSY_OFFSET 0x04 /**< \brief (GCLK_SYNCBUSY offset) Synchronization Busy */
+#define GCLK_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_SYNCBUSY reset_value) Synchronization Busy */
+
+#define GCLK_SYNCBUSY_SWRST_Pos 0 /**< \brief (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit */
+#define GCLK_SYNCBUSY_SWRST (_U_(0x1) << GCLK_SYNCBUSY_SWRST_Pos)
+#define GCLK_SYNCBUSY_GENCTRL0_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 0 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL0 (_U_(1) << GCLK_SYNCBUSY_GENCTRL0_Pos)
+#define GCLK_SYNCBUSY_GENCTRL1_Pos 3 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 1 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL1 (_U_(1) << GCLK_SYNCBUSY_GENCTRL1_Pos)
+#define GCLK_SYNCBUSY_GENCTRL2_Pos 4 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 2 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL2 (_U_(1) << GCLK_SYNCBUSY_GENCTRL2_Pos)
+#define GCLK_SYNCBUSY_GENCTRL3_Pos 5 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 3 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL3 (_U_(1) << GCLK_SYNCBUSY_GENCTRL3_Pos)
+#define GCLK_SYNCBUSY_GENCTRL4_Pos 6 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 4 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL4 (_U_(1) << GCLK_SYNCBUSY_GENCTRL4_Pos)
+#define GCLK_SYNCBUSY_GENCTRL5_Pos 7 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 5 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL5 (_U_(1) << GCLK_SYNCBUSY_GENCTRL5_Pos)
+#define GCLK_SYNCBUSY_GENCTRL6_Pos 8 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 6 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL6 (_U_(1) << GCLK_SYNCBUSY_GENCTRL6_Pos)
+#define GCLK_SYNCBUSY_GENCTRL7_Pos 9 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 7 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL7 (_U_(1) << GCLK_SYNCBUSY_GENCTRL7_Pos)
+#define GCLK_SYNCBUSY_GENCTRL8_Pos 10 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 8 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL8 (_U_(1) << GCLK_SYNCBUSY_GENCTRL8_Pos)
+#define GCLK_SYNCBUSY_GENCTRL9_Pos 11 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 9 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL9 (_U_(1) << GCLK_SYNCBUSY_GENCTRL9_Pos)
+#define GCLK_SYNCBUSY_GENCTRL10_Pos 12 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 10 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL10 (_U_(1) << GCLK_SYNCBUSY_GENCTRL10_Pos)
+#define GCLK_SYNCBUSY_GENCTRL11_Pos 13 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 11 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL11 (_U_(1) << GCLK_SYNCBUSY_GENCTRL11_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control x Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL_Msk (_U_(0xFFF) << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL(value) (GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos))
+#define GCLK_SYNCBUSY_GENCTRL_GCLK0_Val _U_(0x1) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 0 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK1_Val _U_(0x2) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 1 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK2_Val _U_(0x4) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 2 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK3_Val _U_(0x8) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 3 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK4_Val _U_(0x10) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 4 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK5_Val _U_(0x20) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 5 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK6_Val _U_(0x40) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 6 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK7_Val _U_(0x80) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 7 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK8_Val _U_(0x100) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 8 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK9_Val _U_(0x200) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 9 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK10_Val _U_(0x400) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 10 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK11_Val _U_(0x800) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 11 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK9 (GCLK_SYNCBUSY_GENCTRL_GCLK9_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK10 (GCLK_SYNCBUSY_GENCTRL_GCLK10_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK11 (GCLK_SYNCBUSY_GENCTRL_GCLK11_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_MASK _U_(0x00003FFD) /**< \brief (GCLK_SYNCBUSY) MASK Register */
+
+/* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SRC:4; /*!< bit: 0.. 3 Source Select */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t GENEN:1; /*!< bit: 8 Generic Clock Generator Enable */
+ uint32_t IDC:1; /*!< bit: 9 Improve Duty Cycle */
+ uint32_t OOV:1; /*!< bit: 10 Output Off Value */
+ uint32_t OE:1; /*!< bit: 11 Output Enable */
+ uint32_t DIVSEL:1; /*!< bit: 12 Divide Selection */
+ uint32_t RUNSTDBY:1; /*!< bit: 13 Run in Standby */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t DIV:16; /*!< bit: 16..31 Division Factor */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GCLK_GENCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_GENCTRL_OFFSET 0x20 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
+#define GCLK_GENCTRL_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
+
+#define GCLK_GENCTRL_SRC_Pos 0 /**< \brief (GCLK_GENCTRL) Source Select */
+#define GCLK_GENCTRL_SRC_Msk (_U_(0xF) << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
+#define GCLK_GENCTRL_SRC_XOSC0_Val _U_(0x0) /**< \brief (GCLK_GENCTRL) XOSC0 oscillator output */
+#define GCLK_GENCTRL_SRC_XOSC1_Val _U_(0x1) /**< \brief (GCLK_GENCTRL) XOSC1 oscillator output */
+#define GCLK_GENCTRL_SRC_GCLKIN_Val _U_(0x2) /**< \brief (GCLK_GENCTRL) Generator input pad */
+#define GCLK_GENCTRL_SRC_GCLKGEN1_Val _U_(0x3) /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
+#define GCLK_GENCTRL_SRC_OSCULP32K_Val _U_(0x4) /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
+#define GCLK_GENCTRL_SRC_XOSC32K_Val _U_(0x5) /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
+#define GCLK_GENCTRL_SRC_DFLL_Val _U_(0x6) /**< \brief (GCLK_GENCTRL) DFLL output */
+#define GCLK_GENCTRL_SRC_DPLL0_Val _U_(0x7) /**< \brief (GCLK_GENCTRL) DPLL0 output */
+#define GCLK_GENCTRL_SRC_DPLL1_Val _U_(0x8) /**< \brief (GCLK_GENCTRL) DPLL1 output */
+#define GCLK_GENCTRL_SRC_XOSC0 (GCLK_GENCTRL_SRC_XOSC0_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_XOSC1 (GCLK_GENCTRL_SRC_XOSC1_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_DFLL (GCLK_GENCTRL_SRC_DFLL_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_DPLL0 (GCLK_GENCTRL_SRC_DPLL0_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_DPLL1 (GCLK_GENCTRL_SRC_DPLL1_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_GENEN_Pos 8 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
+#define GCLK_GENCTRL_GENEN (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos)
+#define GCLK_GENCTRL_IDC_Pos 9 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
+#define GCLK_GENCTRL_IDC (_U_(0x1) << GCLK_GENCTRL_IDC_Pos)
+#define GCLK_GENCTRL_OOV_Pos 10 /**< \brief (GCLK_GENCTRL) Output Off Value */
+#define GCLK_GENCTRL_OOV (_U_(0x1) << GCLK_GENCTRL_OOV_Pos)
+#define GCLK_GENCTRL_OE_Pos 11 /**< \brief (GCLK_GENCTRL) Output Enable */
+#define GCLK_GENCTRL_OE (_U_(0x1) << GCLK_GENCTRL_OE_Pos)
+#define GCLK_GENCTRL_DIVSEL_Pos 12 /**< \brief (GCLK_GENCTRL) Divide Selection */
+#define GCLK_GENCTRL_DIVSEL (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos)
+#define GCLK_GENCTRL_RUNSTDBY_Pos 13 /**< \brief (GCLK_GENCTRL) Run in Standby */
+#define GCLK_GENCTRL_RUNSTDBY (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)
+#define GCLK_GENCTRL_DIV_Pos 16 /**< \brief (GCLK_GENCTRL) Division Factor */
+#define GCLK_GENCTRL_DIV_Msk (_U_(0xFFFF) << GCLK_GENCTRL_DIV_Pos)
+#define GCLK_GENCTRL_DIV(value) (GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos))
+#define GCLK_GENCTRL_MASK _U_(0xFFFF3F0F) /**< \brief (GCLK_GENCTRL) MASK Register */
+
+/* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t GEN:4; /*!< bit: 0.. 3 Generic Clock Generator */
+ uint32_t :2; /*!< bit: 4.. 5 Reserved */
+ uint32_t CHEN:1; /*!< bit: 6 Channel Enable */
+ uint32_t WRTLOCK:1; /*!< bit: 7 Write Lock */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GCLK_PCHCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_PCHCTRL_OFFSET 0x80 /**< \brief (GCLK_PCHCTRL offset) Peripheral Clock Control */
+#define GCLK_PCHCTRL_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_PCHCTRL reset_value) Peripheral Clock Control */
+
+#define GCLK_PCHCTRL_GEN_Pos 0 /**< \brief (GCLK_PCHCTRL) Generic Clock Generator */
+#define GCLK_PCHCTRL_GEN_Msk (_U_(0xF) << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN(value) (GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos))
+#define GCLK_PCHCTRL_GEN_GCLK0_Val _U_(0x0) /**< \brief (GCLK_PCHCTRL) Generic clock generator 0 */
+#define GCLK_PCHCTRL_GEN_GCLK1_Val _U_(0x1) /**< \brief (GCLK_PCHCTRL) Generic clock generator 1 */
+#define GCLK_PCHCTRL_GEN_GCLK2_Val _U_(0x2) /**< \brief (GCLK_PCHCTRL) Generic clock generator 2 */
+#define GCLK_PCHCTRL_GEN_GCLK3_Val _U_(0x3) /**< \brief (GCLK_PCHCTRL) Generic clock generator 3 */
+#define GCLK_PCHCTRL_GEN_GCLK4_Val _U_(0x4) /**< \brief (GCLK_PCHCTRL) Generic clock generator 4 */
+#define GCLK_PCHCTRL_GEN_GCLK5_Val _U_(0x5) /**< \brief (GCLK_PCHCTRL) Generic clock generator 5 */
+#define GCLK_PCHCTRL_GEN_GCLK6_Val _U_(0x6) /**< \brief (GCLK_PCHCTRL) Generic clock generator 6 */
+#define GCLK_PCHCTRL_GEN_GCLK7_Val _U_(0x7) /**< \brief (GCLK_PCHCTRL) Generic clock generator 7 */
+#define GCLK_PCHCTRL_GEN_GCLK8_Val _U_(0x8) /**< \brief (GCLK_PCHCTRL) Generic clock generator 8 */
+#define GCLK_PCHCTRL_GEN_GCLK9_Val _U_(0x9) /**< \brief (GCLK_PCHCTRL) Generic clock generator 9 */
+#define GCLK_PCHCTRL_GEN_GCLK10_Val _U_(0xA) /**< \brief (GCLK_PCHCTRL) Generic clock generator 10 */
+#define GCLK_PCHCTRL_GEN_GCLK11_Val _U_(0xB) /**< \brief (GCLK_PCHCTRL) Generic clock generator 11 */
+#define GCLK_PCHCTRL_GEN_GCLK0 (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK1 (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK2 (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK3 (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK4 (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK5 (GCLK_PCHCTRL_GEN_GCLK5_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK6 (GCLK_PCHCTRL_GEN_GCLK6_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK7 (GCLK_PCHCTRL_GEN_GCLK7_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK8 (GCLK_PCHCTRL_GEN_GCLK8_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK9 (GCLK_PCHCTRL_GEN_GCLK9_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK10 (GCLK_PCHCTRL_GEN_GCLK10_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK11 (GCLK_PCHCTRL_GEN_GCLK11_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_CHEN_Pos 6 /**< \brief (GCLK_PCHCTRL) Channel Enable */
+#define GCLK_PCHCTRL_CHEN (_U_(0x1) << GCLK_PCHCTRL_CHEN_Pos)
+#define GCLK_PCHCTRL_WRTLOCK_Pos 7 /**< \brief (GCLK_PCHCTRL) Write Lock */
+#define GCLK_PCHCTRL_WRTLOCK (_U_(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos)
+#define GCLK_PCHCTRL_MASK _U_(0x000000CF) /**< \brief (GCLK_PCHCTRL) MASK Register */
+
+/** \brief GCLK hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO GCLK_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */
+ RoReg8 Reserved1[0x3];
+ __I GCLK_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Synchronization Busy */
+ RoReg8 Reserved2[0x18];
+ __IO GCLK_GENCTRL_Type GENCTRL[12]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Generator Control */
+ RoReg8 Reserved3[0x30];
+ __IO GCLK_PCHCTRL_Type PCHCTRL[48]; /**< \brief Offset: 0x80 (R/W 32) Peripheral Clock Control */
+} Gclk;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_GCLK_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/gmac.h b/sysmoOCTSIM/include/component/gmac.h
index 133719f..558cebc 100644
--- a/sysmoOCTSIM/include/component/gmac.h
+++ b/sysmoOCTSIM/include/component/gmac.h
@@ -1,2593 +1,2593 @@
-/**
- * \file
- *
- * \brief Component description for GMAC
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_GMAC_COMPONENT_
-#define _SAME54_GMAC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR GMAC */
-/* ========================================================================== */
-/** \addtogroup SAME54_GMAC Ethernet MAC */
-/*@{*/
-
-#define GMAC_U2005
-#define REV_GMAC 0x100
-
-/* -------- GMAC_NCR : (GMAC Offset: 0x000) (R/W 32) Network Control Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t LBL:1; /*!< bit: 1 Loop Back Local */
- uint32_t RXEN:1; /*!< bit: 2 Receive Enable */
- uint32_t TXEN:1; /*!< bit: 3 Transmit Enable */
- uint32_t MPE:1; /*!< bit: 4 Management Port Enable */
- uint32_t CLRSTAT:1; /*!< bit: 5 Clear Statistics Registers */
- uint32_t INCSTAT:1; /*!< bit: 6 Increment Statistics Registers */
- uint32_t WESTAT:1; /*!< bit: 7 Write Enable for Statistics Registers */
- uint32_t BP:1; /*!< bit: 8 Back pressure */
- uint32_t TSTART:1; /*!< bit: 9 Start Transmission */
- uint32_t THALT:1; /*!< bit: 10 Transmit Halt */
- uint32_t TXPF:1; /*!< bit: 11 Transmit Pause Frame */
- uint32_t TXZQPF:1; /*!< bit: 12 Transmit Zero Quantum Pause Frame */
- uint32_t :2; /*!< bit: 13..14 Reserved */
- uint32_t SRTSM:1; /*!< bit: 15 Store Receive Time Stamp to Memory */
- uint32_t ENPBPR:1; /*!< bit: 16 Enable PFC Priority-based Pause Reception */
- uint32_t TXPBPF:1; /*!< bit: 17 Transmit PFC Priority-based Pause Frame */
- uint32_t FNP:1; /*!< bit: 18 Flush Next Packet */
- uint32_t LPI:1; /*!< bit: 19 Low Power Idle Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_NCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_NCR_OFFSET 0x000 /**< \brief (GMAC_NCR offset) Network Control Register */
-#define GMAC_NCR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_NCR reset_value) Network Control Register */
-
-#define GMAC_NCR_LBL_Pos 1 /**< \brief (GMAC_NCR) Loop Back Local */
-#define GMAC_NCR_LBL (_U_(0x1) << GMAC_NCR_LBL_Pos)
-#define GMAC_NCR_RXEN_Pos 2 /**< \brief (GMAC_NCR) Receive Enable */
-#define GMAC_NCR_RXEN (_U_(0x1) << GMAC_NCR_RXEN_Pos)
-#define GMAC_NCR_TXEN_Pos 3 /**< \brief (GMAC_NCR) Transmit Enable */
-#define GMAC_NCR_TXEN (_U_(0x1) << GMAC_NCR_TXEN_Pos)
-#define GMAC_NCR_MPE_Pos 4 /**< \brief (GMAC_NCR) Management Port Enable */
-#define GMAC_NCR_MPE (_U_(0x1) << GMAC_NCR_MPE_Pos)
-#define GMAC_NCR_CLRSTAT_Pos 5 /**< \brief (GMAC_NCR) Clear Statistics Registers */
-#define GMAC_NCR_CLRSTAT (_U_(0x1) << GMAC_NCR_CLRSTAT_Pos)
-#define GMAC_NCR_INCSTAT_Pos 6 /**< \brief (GMAC_NCR) Increment Statistics Registers */
-#define GMAC_NCR_INCSTAT (_U_(0x1) << GMAC_NCR_INCSTAT_Pos)
-#define GMAC_NCR_WESTAT_Pos 7 /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */
-#define GMAC_NCR_WESTAT (_U_(0x1) << GMAC_NCR_WESTAT_Pos)
-#define GMAC_NCR_BP_Pos 8 /**< \brief (GMAC_NCR) Back pressure */
-#define GMAC_NCR_BP (_U_(0x1) << GMAC_NCR_BP_Pos)
-#define GMAC_NCR_TSTART_Pos 9 /**< \brief (GMAC_NCR) Start Transmission */
-#define GMAC_NCR_TSTART (_U_(0x1) << GMAC_NCR_TSTART_Pos)
-#define GMAC_NCR_THALT_Pos 10 /**< \brief (GMAC_NCR) Transmit Halt */
-#define GMAC_NCR_THALT (_U_(0x1) << GMAC_NCR_THALT_Pos)
-#define GMAC_NCR_TXPF_Pos 11 /**< \brief (GMAC_NCR) Transmit Pause Frame */
-#define GMAC_NCR_TXPF (_U_(0x1) << GMAC_NCR_TXPF_Pos)
-#define GMAC_NCR_TXZQPF_Pos 12 /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */
-#define GMAC_NCR_TXZQPF (_U_(0x1) << GMAC_NCR_TXZQPF_Pos)
-#define GMAC_NCR_SRTSM_Pos 15 /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */
-#define GMAC_NCR_SRTSM (_U_(0x1) << GMAC_NCR_SRTSM_Pos)
-#define GMAC_NCR_ENPBPR_Pos 16 /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */
-#define GMAC_NCR_ENPBPR (_U_(0x1) << GMAC_NCR_ENPBPR_Pos)
-#define GMAC_NCR_TXPBPF_Pos 17 /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */
-#define GMAC_NCR_TXPBPF (_U_(0x1) << GMAC_NCR_TXPBPF_Pos)
-#define GMAC_NCR_FNP_Pos 18 /**< \brief (GMAC_NCR) Flush Next Packet */
-#define GMAC_NCR_FNP (_U_(0x1) << GMAC_NCR_FNP_Pos)
-#define GMAC_NCR_LPI_Pos 19 /**< \brief (GMAC_NCR) Low Power Idle Enable */
-#define GMAC_NCR_LPI (_U_(0x1) << GMAC_NCR_LPI_Pos)
-#define GMAC_NCR_MASK _U_(0x000F9FFE) /**< \brief (GMAC_NCR) MASK Register */
-
-/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) (R/W 32) Network Configuration Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SPD:1; /*!< bit: 0 Speed */
- uint32_t FD:1; /*!< bit: 1 Full Duplex */
- uint32_t DNVLAN:1; /*!< bit: 2 Discard Non-VLAN FRAMES */
- uint32_t JFRAME:1; /*!< bit: 3 Jumbo Frame Size */
- uint32_t CAF:1; /*!< bit: 4 Copy All Frames */
- uint32_t NBC:1; /*!< bit: 5 No Broadcast */
- uint32_t MTIHEN:1; /*!< bit: 6 Multicast Hash Enable */
- uint32_t UNIHEN:1; /*!< bit: 7 Unicast Hash Enable */
- uint32_t MAXFS:1; /*!< bit: 8 1536 Maximum Frame Size */
- uint32_t :3; /*!< bit: 9..11 Reserved */
- uint32_t RTY:1; /*!< bit: 12 Retry Test */
- uint32_t PEN:1; /*!< bit: 13 Pause Enable */
- uint32_t RXBUFO:2; /*!< bit: 14..15 Receive Buffer Offset */
- uint32_t LFERD:1; /*!< bit: 16 Length Field Error Frame Discard */
- uint32_t RFCS:1; /*!< bit: 17 Remove FCS */
- uint32_t CLK:3; /*!< bit: 18..20 MDC CLock Division */
- uint32_t DBW:2; /*!< bit: 21..22 Data Bus Width */
- uint32_t DCPF:1; /*!< bit: 23 Disable Copy of Pause Frames */
- uint32_t RXCOEN:1; /*!< bit: 24 Receive Checksum Offload Enable */
- uint32_t EFRHD:1; /*!< bit: 25 Enable Frames Received in Half Duplex */
- uint32_t IRXFCS:1; /*!< bit: 26 Ignore RX FCS */
- uint32_t :1; /*!< bit: 27 Reserved */
- uint32_t IPGSEN:1; /*!< bit: 28 IP Stretch Enable */
- uint32_t RXBP:1; /*!< bit: 29 Receive Bad Preamble */
- uint32_t IRXER:1; /*!< bit: 30 Ignore IPG GRXER */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_NCFGR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_NCFGR_OFFSET 0x004 /**< \brief (GMAC_NCFGR offset) Network Configuration Register */
-#define GMAC_NCFGR_RESETVALUE _U_(0x00080000) /**< \brief (GMAC_NCFGR reset_value) Network Configuration Register */
-
-#define GMAC_NCFGR_SPD_Pos 0 /**< \brief (GMAC_NCFGR) Speed */
-#define GMAC_NCFGR_SPD (_U_(0x1) << GMAC_NCFGR_SPD_Pos)
-#define GMAC_NCFGR_FD_Pos 1 /**< \brief (GMAC_NCFGR) Full Duplex */
-#define GMAC_NCFGR_FD (_U_(0x1) << GMAC_NCFGR_FD_Pos)
-#define GMAC_NCFGR_DNVLAN_Pos 2 /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */
-#define GMAC_NCFGR_DNVLAN (_U_(0x1) << GMAC_NCFGR_DNVLAN_Pos)
-#define GMAC_NCFGR_JFRAME_Pos 3 /**< \brief (GMAC_NCFGR) Jumbo Frame Size */
-#define GMAC_NCFGR_JFRAME (_U_(0x1) << GMAC_NCFGR_JFRAME_Pos)
-#define GMAC_NCFGR_CAF_Pos 4 /**< \brief (GMAC_NCFGR) Copy All Frames */
-#define GMAC_NCFGR_CAF (_U_(0x1) << GMAC_NCFGR_CAF_Pos)
-#define GMAC_NCFGR_NBC_Pos 5 /**< \brief (GMAC_NCFGR) No Broadcast */
-#define GMAC_NCFGR_NBC (_U_(0x1) << GMAC_NCFGR_NBC_Pos)
-#define GMAC_NCFGR_MTIHEN_Pos 6 /**< \brief (GMAC_NCFGR) Multicast Hash Enable */
-#define GMAC_NCFGR_MTIHEN (_U_(0x1) << GMAC_NCFGR_MTIHEN_Pos)
-#define GMAC_NCFGR_UNIHEN_Pos 7 /**< \brief (GMAC_NCFGR) Unicast Hash Enable */
-#define GMAC_NCFGR_UNIHEN (_U_(0x1) << GMAC_NCFGR_UNIHEN_Pos)
-#define GMAC_NCFGR_MAXFS_Pos 8 /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */
-#define GMAC_NCFGR_MAXFS (_U_(0x1) << GMAC_NCFGR_MAXFS_Pos)
-#define GMAC_NCFGR_RTY_Pos 12 /**< \brief (GMAC_NCFGR) Retry Test */
-#define GMAC_NCFGR_RTY (_U_(0x1) << GMAC_NCFGR_RTY_Pos)
-#define GMAC_NCFGR_PEN_Pos 13 /**< \brief (GMAC_NCFGR) Pause Enable */
-#define GMAC_NCFGR_PEN (_U_(0x1) << GMAC_NCFGR_PEN_Pos)
-#define GMAC_NCFGR_RXBUFO_Pos 14 /**< \brief (GMAC_NCFGR) Receive Buffer Offset */
-#define GMAC_NCFGR_RXBUFO_Msk (_U_(0x3) << GMAC_NCFGR_RXBUFO_Pos)
-#define GMAC_NCFGR_RXBUFO(value) (GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))
-#define GMAC_NCFGR_LFERD_Pos 16 /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */
-#define GMAC_NCFGR_LFERD (_U_(0x1) << GMAC_NCFGR_LFERD_Pos)
-#define GMAC_NCFGR_RFCS_Pos 17 /**< \brief (GMAC_NCFGR) Remove FCS */
-#define GMAC_NCFGR_RFCS (_U_(0x1) << GMAC_NCFGR_RFCS_Pos)
-#define GMAC_NCFGR_CLK_Pos 18 /**< \brief (GMAC_NCFGR) MDC CLock Division */
-#define GMAC_NCFGR_CLK_Msk (_U_(0x7) << GMAC_NCFGR_CLK_Pos)
-#define GMAC_NCFGR_CLK(value) (GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos))
-#define GMAC_NCFGR_DBW_Pos 21 /**< \brief (GMAC_NCFGR) Data Bus Width */
-#define GMAC_NCFGR_DBW_Msk (_U_(0x3) << GMAC_NCFGR_DBW_Pos)
-#define GMAC_NCFGR_DBW(value) (GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos))
-#define GMAC_NCFGR_DCPF_Pos 23 /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */
-#define GMAC_NCFGR_DCPF (_U_(0x1) << GMAC_NCFGR_DCPF_Pos)
-#define GMAC_NCFGR_RXCOEN_Pos 24 /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */
-#define GMAC_NCFGR_RXCOEN (_U_(0x1) << GMAC_NCFGR_RXCOEN_Pos)
-#define GMAC_NCFGR_EFRHD_Pos 25 /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */
-#define GMAC_NCFGR_EFRHD (_U_(0x1) << GMAC_NCFGR_EFRHD_Pos)
-#define GMAC_NCFGR_IRXFCS_Pos 26 /**< \brief (GMAC_NCFGR) Ignore RX FCS */
-#define GMAC_NCFGR_IRXFCS (_U_(0x1) << GMAC_NCFGR_IRXFCS_Pos)
-#define GMAC_NCFGR_IPGSEN_Pos 28 /**< \brief (GMAC_NCFGR) IP Stretch Enable */
-#define GMAC_NCFGR_IPGSEN (_U_(0x1) << GMAC_NCFGR_IPGSEN_Pos)
-#define GMAC_NCFGR_RXBP_Pos 29 /**< \brief (GMAC_NCFGR) Receive Bad Preamble */
-#define GMAC_NCFGR_RXBP (_U_(0x1) << GMAC_NCFGR_RXBP_Pos)
-#define GMAC_NCFGR_IRXER_Pos 30 /**< \brief (GMAC_NCFGR) Ignore IPG GRXER */
-#define GMAC_NCFGR_IRXER (_U_(0x1) << GMAC_NCFGR_IRXER_Pos)
-#define GMAC_NCFGR_MASK _U_(0x77FFF1FF) /**< \brief (GMAC_NCFGR) MASK Register */
-
-/* -------- GMAC_NSR : (GMAC Offset: 0x008) (R/ 32) Network Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t MDIO:1; /*!< bit: 1 MDIO Input Status */
- uint32_t IDLE:1; /*!< bit: 2 PHY Management Logic Idle */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_NSR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_NSR_OFFSET 0x008 /**< \brief (GMAC_NSR offset) Network Status Register */
-#define GMAC_NSR_RESETVALUE _U_(0x00000004) /**< \brief (GMAC_NSR reset_value) Network Status Register */
-
-#define GMAC_NSR_MDIO_Pos 1 /**< \brief (GMAC_NSR) MDIO Input Status */
-#define GMAC_NSR_MDIO (_U_(0x1) << GMAC_NSR_MDIO_Pos)
-#define GMAC_NSR_IDLE_Pos 2 /**< \brief (GMAC_NSR) PHY Management Logic Idle */
-#define GMAC_NSR_IDLE (_U_(0x1) << GMAC_NSR_IDLE_Pos)
-#define GMAC_NSR_MASK _U_(0x00000006) /**< \brief (GMAC_NSR) MASK Register */
-
-/* -------- GMAC_UR : (GMAC Offset: 0x00C) (R/W 32) User Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t MII:1; /*!< bit: 0 MII Mode */
- uint32_t :31; /*!< bit: 1..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_UR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_UR_OFFSET 0x00C /**< \brief (GMAC_UR offset) User Register */
-#define GMAC_UR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_UR reset_value) User Register */
-
-#define GMAC_UR_MII_Pos 0 /**< \brief (GMAC_UR) MII Mode */
-#define GMAC_UR_MII (_U_(0x1) << GMAC_UR_MII_Pos)
-#define GMAC_UR_MASK _U_(0x00000001) /**< \brief (GMAC_UR) MASK Register */
-
-/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) (R/W 32) DMA Configuration Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t FBLDO:5; /*!< bit: 0.. 4 Fixed Burst Length for DMA Data Operations: */
- uint32_t :1; /*!< bit: 5 Reserved */
- uint32_t ESMA:1; /*!< bit: 6 Endian Swap Mode Enable for Management Descriptor Accesses */
- uint32_t ESPA:1; /*!< bit: 7 Endian Swap Mode Enable for Packet Data Accesses */
- uint32_t RXBMS:2; /*!< bit: 8.. 9 Receiver Packet Buffer Memory Size Select */
- uint32_t TXPBMS:1; /*!< bit: 10 Transmitter Packet Buffer Memory Size Select */
- uint32_t TXCOEN:1; /*!< bit: 11 Transmitter Checksum Generation Offload Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t DRBS:8; /*!< bit: 16..23 DMA Receive Buffer Size */
- uint32_t DDRP:1; /*!< bit: 24 DMA Discard Receive Packets */
- uint32_t :7; /*!< bit: 25..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_DCFGR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_DCFGR_OFFSET 0x010 /**< \brief (GMAC_DCFGR offset) DMA Configuration Register */
-#define GMAC_DCFGR_RESETVALUE _U_(0x00020704) /**< \brief (GMAC_DCFGR reset_value) DMA Configuration Register */
-
-#define GMAC_DCFGR_FBLDO_Pos 0 /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */
-#define GMAC_DCFGR_FBLDO_Msk (_U_(0x1F) << GMAC_DCFGR_FBLDO_Pos)
-#define GMAC_DCFGR_FBLDO(value) (GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos))
-#define GMAC_DCFGR_ESMA_Pos 6 /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */
-#define GMAC_DCFGR_ESMA (_U_(0x1) << GMAC_DCFGR_ESMA_Pos)
-#define GMAC_DCFGR_ESPA_Pos 7 /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */
-#define GMAC_DCFGR_ESPA (_U_(0x1) << GMAC_DCFGR_ESPA_Pos)
-#define GMAC_DCFGR_RXBMS_Pos 8 /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */
-#define GMAC_DCFGR_RXBMS_Msk (_U_(0x3) << GMAC_DCFGR_RXBMS_Pos)
-#define GMAC_DCFGR_RXBMS(value) (GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos))
-#define GMAC_DCFGR_TXPBMS_Pos 10 /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */
-#define GMAC_DCFGR_TXPBMS (_U_(0x1) << GMAC_DCFGR_TXPBMS_Pos)
-#define GMAC_DCFGR_TXCOEN_Pos 11 /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */
-#define GMAC_DCFGR_TXCOEN (_U_(0x1) << GMAC_DCFGR_TXCOEN_Pos)
-#define GMAC_DCFGR_DRBS_Pos 16 /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */
-#define GMAC_DCFGR_DRBS_Msk (_U_(0xFF) << GMAC_DCFGR_DRBS_Pos)
-#define GMAC_DCFGR_DRBS(value) (GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))
-#define GMAC_DCFGR_DDRP_Pos 24 /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */
-#define GMAC_DCFGR_DDRP (_U_(0x1) << GMAC_DCFGR_DDRP_Pos)
-#define GMAC_DCFGR_MASK _U_(0x01FF0FDF) /**< \brief (GMAC_DCFGR) MASK Register */
-
-/* -------- GMAC_TSR : (GMAC Offset: 0x014) (R/W 32) Transmit Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t UBR:1; /*!< bit: 0 Used Bit Read */
- uint32_t COL:1; /*!< bit: 1 Collision Occurred */
- uint32_t RLE:1; /*!< bit: 2 Retry Limit Exceeded */
- uint32_t TXGO:1; /*!< bit: 3 Transmit Go */
- uint32_t TFC:1; /*!< bit: 4 Transmit Frame Corruption Due to AHB Error */
- uint32_t TXCOMP:1; /*!< bit: 5 Transmit Complete */
- uint32_t UND:1; /*!< bit: 6 Transmit Underrun */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t HRESP:1; /*!< bit: 8 HRESP Not OK */
- uint32_t :23; /*!< bit: 9..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TSR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TSR_OFFSET 0x014 /**< \brief (GMAC_TSR offset) Transmit Status Register */
-#define GMAC_TSR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSR reset_value) Transmit Status Register */
-
-#define GMAC_TSR_UBR_Pos 0 /**< \brief (GMAC_TSR) Used Bit Read */
-#define GMAC_TSR_UBR (_U_(0x1) << GMAC_TSR_UBR_Pos)
-#define GMAC_TSR_COL_Pos 1 /**< \brief (GMAC_TSR) Collision Occurred */
-#define GMAC_TSR_COL (_U_(0x1) << GMAC_TSR_COL_Pos)
-#define GMAC_TSR_RLE_Pos 2 /**< \brief (GMAC_TSR) Retry Limit Exceeded */
-#define GMAC_TSR_RLE (_U_(0x1) << GMAC_TSR_RLE_Pos)
-#define GMAC_TSR_TXGO_Pos 3 /**< \brief (GMAC_TSR) Transmit Go */
-#define GMAC_TSR_TXGO (_U_(0x1) << GMAC_TSR_TXGO_Pos)
-#define GMAC_TSR_TFC_Pos 4 /**< \brief (GMAC_TSR) Transmit Frame Corruption Due to AHB Error */
-#define GMAC_TSR_TFC (_U_(0x1) << GMAC_TSR_TFC_Pos)
-#define GMAC_TSR_TXCOMP_Pos 5 /**< \brief (GMAC_TSR) Transmit Complete */
-#define GMAC_TSR_TXCOMP (_U_(0x1) << GMAC_TSR_TXCOMP_Pos)
-#define GMAC_TSR_UND_Pos 6 /**< \brief (GMAC_TSR) Transmit Underrun */
-#define GMAC_TSR_UND (_U_(0x1) << GMAC_TSR_UND_Pos)
-#define GMAC_TSR_HRESP_Pos 8 /**< \brief (GMAC_TSR) HRESP Not OK */
-#define GMAC_TSR_HRESP (_U_(0x1) << GMAC_TSR_HRESP_Pos)
-#define GMAC_TSR_MASK _U_(0x0000017F) /**< \brief (GMAC_TSR) MASK Register */
-
-/* -------- GMAC_RBQB : (GMAC Offset: 0x018) (R/W 32) Receive Buffer Queue Base Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t ADDR:30; /*!< bit: 2..31 Receive Buffer Queue Base Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_RBQB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_RBQB_OFFSET 0x018 /**< \brief (GMAC_RBQB offset) Receive Buffer Queue Base Address */
-#define GMAC_RBQB_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RBQB reset_value) Receive Buffer Queue Base Address */
-
-#define GMAC_RBQB_ADDR_Pos 2 /**< \brief (GMAC_RBQB) Receive Buffer Queue Base Address */
-#define GMAC_RBQB_ADDR_Msk (_U_(0x3FFFFFFF) << GMAC_RBQB_ADDR_Pos)
-#define GMAC_RBQB_ADDR(value) (GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))
-#define GMAC_RBQB_MASK _U_(0xFFFFFFFC) /**< \brief (GMAC_RBQB) MASK Register */
-
-/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) (R/W 32) Transmit Buffer Queue Base Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t ADDR:30; /*!< bit: 2..31 Transmit Buffer Queue Base Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TBQB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TBQB_OFFSET 0x01C /**< \brief (GMAC_TBQB offset) Transmit Buffer Queue Base Address */
-#define GMAC_TBQB_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBQB reset_value) Transmit Buffer Queue Base Address */
-
-#define GMAC_TBQB_ADDR_Pos 2 /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */
-#define GMAC_TBQB_ADDR_Msk (_U_(0x3FFFFFFF) << GMAC_TBQB_ADDR_Pos)
-#define GMAC_TBQB_ADDR(value) (GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))
-#define GMAC_TBQB_MASK _U_(0xFFFFFFFC) /**< \brief (GMAC_TBQB) MASK Register */
-
-/* -------- GMAC_RSR : (GMAC Offset: 0x020) (R/W 32) Receive Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t BNA:1; /*!< bit: 0 Buffer Not Available */
- uint32_t REC:1; /*!< bit: 1 Frame Received */
- uint32_t RXOVR:1; /*!< bit: 2 Receive Overrun */
- uint32_t HNO:1; /*!< bit: 3 HRESP Not OK */
- uint32_t :28; /*!< bit: 4..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_RSR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_RSR_OFFSET 0x020 /**< \brief (GMAC_RSR offset) Receive Status Register */
-#define GMAC_RSR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RSR reset_value) Receive Status Register */
-
-#define GMAC_RSR_BNA_Pos 0 /**< \brief (GMAC_RSR) Buffer Not Available */
-#define GMAC_RSR_BNA (_U_(0x1) << GMAC_RSR_BNA_Pos)
-#define GMAC_RSR_REC_Pos 1 /**< \brief (GMAC_RSR) Frame Received */
-#define GMAC_RSR_REC (_U_(0x1) << GMAC_RSR_REC_Pos)
-#define GMAC_RSR_RXOVR_Pos 2 /**< \brief (GMAC_RSR) Receive Overrun */
-#define GMAC_RSR_RXOVR (_U_(0x1) << GMAC_RSR_RXOVR_Pos)
-#define GMAC_RSR_HNO_Pos 3 /**< \brief (GMAC_RSR) HRESP Not OK */
-#define GMAC_RSR_HNO (_U_(0x1) << GMAC_RSR_HNO_Pos)
-#define GMAC_RSR_MASK _U_(0x0000000F) /**< \brief (GMAC_RSR) MASK Register */
-
-/* -------- GMAC_ISR : (GMAC Offset: 0x024) (R/W 32) Interrupt Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t MFS:1; /*!< bit: 0 Management Frame Sent */
- uint32_t RCOMP:1; /*!< bit: 1 Receive Complete */
- uint32_t RXUBR:1; /*!< bit: 2 RX Used Bit Read */
- uint32_t TXUBR:1; /*!< bit: 3 TX Used Bit Read */
- uint32_t TUR:1; /*!< bit: 4 Transmit Underrun */
- uint32_t RLEX:1; /*!< bit: 5 Retry Limit Exceeded */
- uint32_t TFC:1; /*!< bit: 6 Transmit Frame Corruption Due to AHB Error */
- uint32_t TCOMP:1; /*!< bit: 7 Transmit Complete */
- uint32_t :2; /*!< bit: 8.. 9 Reserved */
- uint32_t ROVR:1; /*!< bit: 10 Receive Overrun */
- uint32_t HRESP:1; /*!< bit: 11 HRESP Not OK */
- uint32_t PFNZ:1; /*!< bit: 12 Pause Frame with Non-zero Pause Quantum Received */
- uint32_t PTZ:1; /*!< bit: 13 Pause Time Zero */
- uint32_t PFTR:1; /*!< bit: 14 Pause Frame Transmitted */
- uint32_t :3; /*!< bit: 15..17 Reserved */
- uint32_t DRQFR:1; /*!< bit: 18 PTP Delay Request Frame Received */
- uint32_t SFR:1; /*!< bit: 19 PTP Sync Frame Received */
- uint32_t DRQFT:1; /*!< bit: 20 PTP Delay Request Frame Transmitted */
- uint32_t SFT:1; /*!< bit: 21 PTP Sync Frame Transmitted */
- uint32_t PDRQFR:1; /*!< bit: 22 PDelay Request Frame Received */
- uint32_t PDRSFR:1; /*!< bit: 23 PDelay Response Frame Received */
- uint32_t PDRQFT:1; /*!< bit: 24 PDelay Request Frame Transmitted */
- uint32_t PDRSFT:1; /*!< bit: 25 PDelay Response Frame Transmitted */
- uint32_t SRI:1; /*!< bit: 26 TSU Seconds Register Increment */
- uint32_t :1; /*!< bit: 27 Reserved */
- uint32_t WOL:1; /*!< bit: 28 Wake On LAN */
- uint32_t TSUCMP:1; /*!< bit: 29 Tsu timer comparison */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_ISR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_ISR_OFFSET 0x024 /**< \brief (GMAC_ISR offset) Interrupt Status Register */
-#define GMAC_ISR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_ISR reset_value) Interrupt Status Register */
-
-#define GMAC_ISR_MFS_Pos 0 /**< \brief (GMAC_ISR) Management Frame Sent */
-#define GMAC_ISR_MFS (_U_(0x1) << GMAC_ISR_MFS_Pos)
-#define GMAC_ISR_RCOMP_Pos 1 /**< \brief (GMAC_ISR) Receive Complete */
-#define GMAC_ISR_RCOMP (_U_(0x1) << GMAC_ISR_RCOMP_Pos)
-#define GMAC_ISR_RXUBR_Pos 2 /**< \brief (GMAC_ISR) RX Used Bit Read */
-#define GMAC_ISR_RXUBR (_U_(0x1) << GMAC_ISR_RXUBR_Pos)
-#define GMAC_ISR_TXUBR_Pos 3 /**< \brief (GMAC_ISR) TX Used Bit Read */
-#define GMAC_ISR_TXUBR (_U_(0x1) << GMAC_ISR_TXUBR_Pos)
-#define GMAC_ISR_TUR_Pos 4 /**< \brief (GMAC_ISR) Transmit Underrun */
-#define GMAC_ISR_TUR (_U_(0x1) << GMAC_ISR_TUR_Pos)
-#define GMAC_ISR_RLEX_Pos 5 /**< \brief (GMAC_ISR) Retry Limit Exceeded */
-#define GMAC_ISR_RLEX (_U_(0x1) << GMAC_ISR_RLEX_Pos)
-#define GMAC_ISR_TFC_Pos 6 /**< \brief (GMAC_ISR) Transmit Frame Corruption Due to AHB Error */
-#define GMAC_ISR_TFC (_U_(0x1) << GMAC_ISR_TFC_Pos)
-#define GMAC_ISR_TCOMP_Pos 7 /**< \brief (GMAC_ISR) Transmit Complete */
-#define GMAC_ISR_TCOMP (_U_(0x1) << GMAC_ISR_TCOMP_Pos)
-#define GMAC_ISR_ROVR_Pos 10 /**< \brief (GMAC_ISR) Receive Overrun */
-#define GMAC_ISR_ROVR (_U_(0x1) << GMAC_ISR_ROVR_Pos)
-#define GMAC_ISR_HRESP_Pos 11 /**< \brief (GMAC_ISR) HRESP Not OK */
-#define GMAC_ISR_HRESP (_U_(0x1) << GMAC_ISR_HRESP_Pos)
-#define GMAC_ISR_PFNZ_Pos 12 /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */
-#define GMAC_ISR_PFNZ (_U_(0x1) << GMAC_ISR_PFNZ_Pos)
-#define GMAC_ISR_PTZ_Pos 13 /**< \brief (GMAC_ISR) Pause Time Zero */
-#define GMAC_ISR_PTZ (_U_(0x1) << GMAC_ISR_PTZ_Pos)
-#define GMAC_ISR_PFTR_Pos 14 /**< \brief (GMAC_ISR) Pause Frame Transmitted */
-#define GMAC_ISR_PFTR (_U_(0x1) << GMAC_ISR_PFTR_Pos)
-#define GMAC_ISR_DRQFR_Pos 18 /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */
-#define GMAC_ISR_DRQFR (_U_(0x1) << GMAC_ISR_DRQFR_Pos)
-#define GMAC_ISR_SFR_Pos 19 /**< \brief (GMAC_ISR) PTP Sync Frame Received */
-#define GMAC_ISR_SFR (_U_(0x1) << GMAC_ISR_SFR_Pos)
-#define GMAC_ISR_DRQFT_Pos 20 /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */
-#define GMAC_ISR_DRQFT (_U_(0x1) << GMAC_ISR_DRQFT_Pos)
-#define GMAC_ISR_SFT_Pos 21 /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */
-#define GMAC_ISR_SFT (_U_(0x1) << GMAC_ISR_SFT_Pos)
-#define GMAC_ISR_PDRQFR_Pos 22 /**< \brief (GMAC_ISR) PDelay Request Frame Received */
-#define GMAC_ISR_PDRQFR (_U_(0x1) << GMAC_ISR_PDRQFR_Pos)
-#define GMAC_ISR_PDRSFR_Pos 23 /**< \brief (GMAC_ISR) PDelay Response Frame Received */
-#define GMAC_ISR_PDRSFR (_U_(0x1) << GMAC_ISR_PDRSFR_Pos)
-#define GMAC_ISR_PDRQFT_Pos 24 /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */
-#define GMAC_ISR_PDRQFT (_U_(0x1) << GMAC_ISR_PDRQFT_Pos)
-#define GMAC_ISR_PDRSFT_Pos 25 /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */
-#define GMAC_ISR_PDRSFT (_U_(0x1) << GMAC_ISR_PDRSFT_Pos)
-#define GMAC_ISR_SRI_Pos 26 /**< \brief (GMAC_ISR) TSU Seconds Register Increment */
-#define GMAC_ISR_SRI (_U_(0x1) << GMAC_ISR_SRI_Pos)
-#define GMAC_ISR_WOL_Pos 28 /**< \brief (GMAC_ISR) Wake On LAN */
-#define GMAC_ISR_WOL (_U_(0x1) << GMAC_ISR_WOL_Pos)
-#define GMAC_ISR_TSUCMP_Pos 29 /**< \brief (GMAC_ISR) Tsu timer comparison */
-#define GMAC_ISR_TSUCMP (_U_(0x1) << GMAC_ISR_TSUCMP_Pos)
-#define GMAC_ISR_MASK _U_(0x37FC7CFF) /**< \brief (GMAC_ISR) MASK Register */
-
-/* -------- GMAC_IER : (GMAC Offset: 0x028) ( /W 32) Interrupt Enable Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t MFS:1; /*!< bit: 0 Management Frame Sent */
- uint32_t RCOMP:1; /*!< bit: 1 Receive Complete */
- uint32_t RXUBR:1; /*!< bit: 2 RX Used Bit Read */
- uint32_t TXUBR:1; /*!< bit: 3 TX Used Bit Read */
- uint32_t TUR:1; /*!< bit: 4 Transmit Underrun */
- uint32_t RLEX:1; /*!< bit: 5 Retry Limit Exceeded or Late Collision */
- uint32_t TFC:1; /*!< bit: 6 Transmit Frame Corruption Due to AHB Error */
- uint32_t TCOMP:1; /*!< bit: 7 Transmit Complete */
- uint32_t :2; /*!< bit: 8.. 9 Reserved */
- uint32_t ROVR:1; /*!< bit: 10 Receive Overrun */
- uint32_t HRESP:1; /*!< bit: 11 HRESP Not OK */
- uint32_t PFNZ:1; /*!< bit: 12 Pause Frame with Non-zero Pause Quantum Received */
- uint32_t PTZ:1; /*!< bit: 13 Pause Time Zero */
- uint32_t PFTR:1; /*!< bit: 14 Pause Frame Transmitted */
- uint32_t EXINT:1; /*!< bit: 15 External Interrupt */
- uint32_t :2; /*!< bit: 16..17 Reserved */
- uint32_t DRQFR:1; /*!< bit: 18 PTP Delay Request Frame Received */
- uint32_t SFR:1; /*!< bit: 19 PTP Sync Frame Received */
- uint32_t DRQFT:1; /*!< bit: 20 PTP Delay Request Frame Transmitted */
- uint32_t SFT:1; /*!< bit: 21 PTP Sync Frame Transmitted */
- uint32_t PDRQFR:1; /*!< bit: 22 PDelay Request Frame Received */
- uint32_t PDRSFR:1; /*!< bit: 23 PDelay Response Frame Received */
- uint32_t PDRQFT:1; /*!< bit: 24 PDelay Request Frame Transmitted */
- uint32_t PDRSFT:1; /*!< bit: 25 PDelay Response Frame Transmitted */
- uint32_t SRI:1; /*!< bit: 26 TSU Seconds Register Increment */
- uint32_t :1; /*!< bit: 27 Reserved */
- uint32_t WOL:1; /*!< bit: 28 Wake On LAN */
- uint32_t TSUCMP:1; /*!< bit: 29 Tsu timer comparison */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_IER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_IER_OFFSET 0x028 /**< \brief (GMAC_IER offset) Interrupt Enable Register */
-
-#define GMAC_IER_MFS_Pos 0 /**< \brief (GMAC_IER) Management Frame Sent */
-#define GMAC_IER_MFS (_U_(0x1) << GMAC_IER_MFS_Pos)
-#define GMAC_IER_RCOMP_Pos 1 /**< \brief (GMAC_IER) Receive Complete */
-#define GMAC_IER_RCOMP (_U_(0x1) << GMAC_IER_RCOMP_Pos)
-#define GMAC_IER_RXUBR_Pos 2 /**< \brief (GMAC_IER) RX Used Bit Read */
-#define GMAC_IER_RXUBR (_U_(0x1) << GMAC_IER_RXUBR_Pos)
-#define GMAC_IER_TXUBR_Pos 3 /**< \brief (GMAC_IER) TX Used Bit Read */
-#define GMAC_IER_TXUBR (_U_(0x1) << GMAC_IER_TXUBR_Pos)
-#define GMAC_IER_TUR_Pos 4 /**< \brief (GMAC_IER) Transmit Underrun */
-#define GMAC_IER_TUR (_U_(0x1) << GMAC_IER_TUR_Pos)
-#define GMAC_IER_RLEX_Pos 5 /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */
-#define GMAC_IER_RLEX (_U_(0x1) << GMAC_IER_RLEX_Pos)
-#define GMAC_IER_TFC_Pos 6 /**< \brief (GMAC_IER) Transmit Frame Corruption Due to AHB Error */
-#define GMAC_IER_TFC (_U_(0x1) << GMAC_IER_TFC_Pos)
-#define GMAC_IER_TCOMP_Pos 7 /**< \brief (GMAC_IER) Transmit Complete */
-#define GMAC_IER_TCOMP (_U_(0x1) << GMAC_IER_TCOMP_Pos)
-#define GMAC_IER_ROVR_Pos 10 /**< \brief (GMAC_IER) Receive Overrun */
-#define GMAC_IER_ROVR (_U_(0x1) << GMAC_IER_ROVR_Pos)
-#define GMAC_IER_HRESP_Pos 11 /**< \brief (GMAC_IER) HRESP Not OK */
-#define GMAC_IER_HRESP (_U_(0x1) << GMAC_IER_HRESP_Pos)
-#define GMAC_IER_PFNZ_Pos 12 /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */
-#define GMAC_IER_PFNZ (_U_(0x1) << GMAC_IER_PFNZ_Pos)
-#define GMAC_IER_PTZ_Pos 13 /**< \brief (GMAC_IER) Pause Time Zero */
-#define GMAC_IER_PTZ (_U_(0x1) << GMAC_IER_PTZ_Pos)
-#define GMAC_IER_PFTR_Pos 14 /**< \brief (GMAC_IER) Pause Frame Transmitted */
-#define GMAC_IER_PFTR (_U_(0x1) << GMAC_IER_PFTR_Pos)
-#define GMAC_IER_EXINT_Pos 15 /**< \brief (GMAC_IER) External Interrupt */
-#define GMAC_IER_EXINT (_U_(0x1) << GMAC_IER_EXINT_Pos)
-#define GMAC_IER_DRQFR_Pos 18 /**< \brief (GMAC_IER) PTP Delay Request Frame Received */
-#define GMAC_IER_DRQFR (_U_(0x1) << GMAC_IER_DRQFR_Pos)
-#define GMAC_IER_SFR_Pos 19 /**< \brief (GMAC_IER) PTP Sync Frame Received */
-#define GMAC_IER_SFR (_U_(0x1) << GMAC_IER_SFR_Pos)
-#define GMAC_IER_DRQFT_Pos 20 /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */
-#define GMAC_IER_DRQFT (_U_(0x1) << GMAC_IER_DRQFT_Pos)
-#define GMAC_IER_SFT_Pos 21 /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */
-#define GMAC_IER_SFT (_U_(0x1) << GMAC_IER_SFT_Pos)
-#define GMAC_IER_PDRQFR_Pos 22 /**< \brief (GMAC_IER) PDelay Request Frame Received */
-#define GMAC_IER_PDRQFR (_U_(0x1) << GMAC_IER_PDRQFR_Pos)
-#define GMAC_IER_PDRSFR_Pos 23 /**< \brief (GMAC_IER) PDelay Response Frame Received */
-#define GMAC_IER_PDRSFR (_U_(0x1) << GMAC_IER_PDRSFR_Pos)
-#define GMAC_IER_PDRQFT_Pos 24 /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */
-#define GMAC_IER_PDRQFT (_U_(0x1) << GMAC_IER_PDRQFT_Pos)
-#define GMAC_IER_PDRSFT_Pos 25 /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */
-#define GMAC_IER_PDRSFT (_U_(0x1) << GMAC_IER_PDRSFT_Pos)
-#define GMAC_IER_SRI_Pos 26 /**< \brief (GMAC_IER) TSU Seconds Register Increment */
-#define GMAC_IER_SRI (_U_(0x1) << GMAC_IER_SRI_Pos)
-#define GMAC_IER_WOL_Pos 28 /**< \brief (GMAC_IER) Wake On LAN */
-#define GMAC_IER_WOL (_U_(0x1) << GMAC_IER_WOL_Pos)
-#define GMAC_IER_TSUCMP_Pos 29 /**< \brief (GMAC_IER) Tsu timer comparison */
-#define GMAC_IER_TSUCMP (_U_(0x1) << GMAC_IER_TSUCMP_Pos)
-#define GMAC_IER_MASK _U_(0x37FCFCFF) /**< \brief (GMAC_IER) MASK Register */
-
-/* -------- GMAC_IDR : (GMAC Offset: 0x02C) ( /W 32) Interrupt Disable Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t MFS:1; /*!< bit: 0 Management Frame Sent */
- uint32_t RCOMP:1; /*!< bit: 1 Receive Complete */
- uint32_t RXUBR:1; /*!< bit: 2 RX Used Bit Read */
- uint32_t TXUBR:1; /*!< bit: 3 TX Used Bit Read */
- uint32_t TUR:1; /*!< bit: 4 Transmit Underrun */
- uint32_t RLEX:1; /*!< bit: 5 Retry Limit Exceeded or Late Collision */
- uint32_t TFC:1; /*!< bit: 6 Transmit Frame Corruption Due to AHB Error */
- uint32_t TCOMP:1; /*!< bit: 7 Transmit Complete */
- uint32_t :2; /*!< bit: 8.. 9 Reserved */
- uint32_t ROVR:1; /*!< bit: 10 Receive Overrun */
- uint32_t HRESP:1; /*!< bit: 11 HRESP Not OK */
- uint32_t PFNZ:1; /*!< bit: 12 Pause Frame with Non-zero Pause Quantum Received */
- uint32_t PTZ:1; /*!< bit: 13 Pause Time Zero */
- uint32_t PFTR:1; /*!< bit: 14 Pause Frame Transmitted */
- uint32_t EXINT:1; /*!< bit: 15 External Interrupt */
- uint32_t :2; /*!< bit: 16..17 Reserved */
- uint32_t DRQFR:1; /*!< bit: 18 PTP Delay Request Frame Received */
- uint32_t SFR:1; /*!< bit: 19 PTP Sync Frame Received */
- uint32_t DRQFT:1; /*!< bit: 20 PTP Delay Request Frame Transmitted */
- uint32_t SFT:1; /*!< bit: 21 PTP Sync Frame Transmitted */
- uint32_t PDRQFR:1; /*!< bit: 22 PDelay Request Frame Received */
- uint32_t PDRSFR:1; /*!< bit: 23 PDelay Response Frame Received */
- uint32_t PDRQFT:1; /*!< bit: 24 PDelay Request Frame Transmitted */
- uint32_t PDRSFT:1; /*!< bit: 25 PDelay Response Frame Transmitted */
- uint32_t SRI:1; /*!< bit: 26 TSU Seconds Register Increment */
- uint32_t :1; /*!< bit: 27 Reserved */
- uint32_t WOL:1; /*!< bit: 28 Wake On LAN */
- uint32_t TSUCMP:1; /*!< bit: 29 Tsu timer comparison */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_IDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_IDR_OFFSET 0x02C /**< \brief (GMAC_IDR offset) Interrupt Disable Register */
-
-#define GMAC_IDR_MFS_Pos 0 /**< \brief (GMAC_IDR) Management Frame Sent */
-#define GMAC_IDR_MFS (_U_(0x1) << GMAC_IDR_MFS_Pos)
-#define GMAC_IDR_RCOMP_Pos 1 /**< \brief (GMAC_IDR) Receive Complete */
-#define GMAC_IDR_RCOMP (_U_(0x1) << GMAC_IDR_RCOMP_Pos)
-#define GMAC_IDR_RXUBR_Pos 2 /**< \brief (GMAC_IDR) RX Used Bit Read */
-#define GMAC_IDR_RXUBR (_U_(0x1) << GMAC_IDR_RXUBR_Pos)
-#define GMAC_IDR_TXUBR_Pos 3 /**< \brief (GMAC_IDR) TX Used Bit Read */
-#define GMAC_IDR_TXUBR (_U_(0x1) << GMAC_IDR_TXUBR_Pos)
-#define GMAC_IDR_TUR_Pos 4 /**< \brief (GMAC_IDR) Transmit Underrun */
-#define GMAC_IDR_TUR (_U_(0x1) << GMAC_IDR_TUR_Pos)
-#define GMAC_IDR_RLEX_Pos 5 /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */
-#define GMAC_IDR_RLEX (_U_(0x1) << GMAC_IDR_RLEX_Pos)
-#define GMAC_IDR_TFC_Pos 6 /**< \brief (GMAC_IDR) Transmit Frame Corruption Due to AHB Error */
-#define GMAC_IDR_TFC (_U_(0x1) << GMAC_IDR_TFC_Pos)
-#define GMAC_IDR_TCOMP_Pos 7 /**< \brief (GMAC_IDR) Transmit Complete */
-#define GMAC_IDR_TCOMP (_U_(0x1) << GMAC_IDR_TCOMP_Pos)
-#define GMAC_IDR_ROVR_Pos 10 /**< \brief (GMAC_IDR) Receive Overrun */
-#define GMAC_IDR_ROVR (_U_(0x1) << GMAC_IDR_ROVR_Pos)
-#define GMAC_IDR_HRESP_Pos 11 /**< \brief (GMAC_IDR) HRESP Not OK */
-#define GMAC_IDR_HRESP (_U_(0x1) << GMAC_IDR_HRESP_Pos)
-#define GMAC_IDR_PFNZ_Pos 12 /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */
-#define GMAC_IDR_PFNZ (_U_(0x1) << GMAC_IDR_PFNZ_Pos)
-#define GMAC_IDR_PTZ_Pos 13 /**< \brief (GMAC_IDR) Pause Time Zero */
-#define GMAC_IDR_PTZ (_U_(0x1) << GMAC_IDR_PTZ_Pos)
-#define GMAC_IDR_PFTR_Pos 14 /**< \brief (GMAC_IDR) Pause Frame Transmitted */
-#define GMAC_IDR_PFTR (_U_(0x1) << GMAC_IDR_PFTR_Pos)
-#define GMAC_IDR_EXINT_Pos 15 /**< \brief (GMAC_IDR) External Interrupt */
-#define GMAC_IDR_EXINT (_U_(0x1) << GMAC_IDR_EXINT_Pos)
-#define GMAC_IDR_DRQFR_Pos 18 /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */
-#define GMAC_IDR_DRQFR (_U_(0x1) << GMAC_IDR_DRQFR_Pos)
-#define GMAC_IDR_SFR_Pos 19 /**< \brief (GMAC_IDR) PTP Sync Frame Received */
-#define GMAC_IDR_SFR (_U_(0x1) << GMAC_IDR_SFR_Pos)
-#define GMAC_IDR_DRQFT_Pos 20 /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */
-#define GMAC_IDR_DRQFT (_U_(0x1) << GMAC_IDR_DRQFT_Pos)
-#define GMAC_IDR_SFT_Pos 21 /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */
-#define GMAC_IDR_SFT (_U_(0x1) << GMAC_IDR_SFT_Pos)
-#define GMAC_IDR_PDRQFR_Pos 22 /**< \brief (GMAC_IDR) PDelay Request Frame Received */
-#define GMAC_IDR_PDRQFR (_U_(0x1) << GMAC_IDR_PDRQFR_Pos)
-#define GMAC_IDR_PDRSFR_Pos 23 /**< \brief (GMAC_IDR) PDelay Response Frame Received */
-#define GMAC_IDR_PDRSFR (_U_(0x1) << GMAC_IDR_PDRSFR_Pos)
-#define GMAC_IDR_PDRQFT_Pos 24 /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */
-#define GMAC_IDR_PDRQFT (_U_(0x1) << GMAC_IDR_PDRQFT_Pos)
-#define GMAC_IDR_PDRSFT_Pos 25 /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */
-#define GMAC_IDR_PDRSFT (_U_(0x1) << GMAC_IDR_PDRSFT_Pos)
-#define GMAC_IDR_SRI_Pos 26 /**< \brief (GMAC_IDR) TSU Seconds Register Increment */
-#define GMAC_IDR_SRI (_U_(0x1) << GMAC_IDR_SRI_Pos)
-#define GMAC_IDR_WOL_Pos 28 /**< \brief (GMAC_IDR) Wake On LAN */
-#define GMAC_IDR_WOL (_U_(0x1) << GMAC_IDR_WOL_Pos)
-#define GMAC_IDR_TSUCMP_Pos 29 /**< \brief (GMAC_IDR) Tsu timer comparison */
-#define GMAC_IDR_TSUCMP (_U_(0x1) << GMAC_IDR_TSUCMP_Pos)
-#define GMAC_IDR_MASK _U_(0x37FCFCFF) /**< \brief (GMAC_IDR) MASK Register */
-
-/* -------- GMAC_IMR : (GMAC Offset: 0x030) (R/ 32) Interrupt Mask Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t MFS:1; /*!< bit: 0 Management Frame Sent */
- uint32_t RCOMP:1; /*!< bit: 1 Receive Complete */
- uint32_t RXUBR:1; /*!< bit: 2 RX Used Bit Read */
- uint32_t TXUBR:1; /*!< bit: 3 TX Used Bit Read */
- uint32_t TUR:1; /*!< bit: 4 Transmit Underrun */
- uint32_t RLEX:1; /*!< bit: 5 Retry Limit Exceeded */
- uint32_t TFC:1; /*!< bit: 6 Transmit Frame Corruption Due to AHB Error */
- uint32_t TCOMP:1; /*!< bit: 7 Transmit Complete */
- uint32_t :2; /*!< bit: 8.. 9 Reserved */
- uint32_t ROVR:1; /*!< bit: 10 Receive Overrun */
- uint32_t HRESP:1; /*!< bit: 11 HRESP Not OK */
- uint32_t PFNZ:1; /*!< bit: 12 Pause Frame with Non-zero Pause Quantum Received */
- uint32_t PTZ:1; /*!< bit: 13 Pause Time Zero */
- uint32_t PFTR:1; /*!< bit: 14 Pause Frame Transmitted */
- uint32_t EXINT:1; /*!< bit: 15 External Interrupt */
- uint32_t :2; /*!< bit: 16..17 Reserved */
- uint32_t DRQFR:1; /*!< bit: 18 PTP Delay Request Frame Received */
- uint32_t SFR:1; /*!< bit: 19 PTP Sync Frame Received */
- uint32_t DRQFT:1; /*!< bit: 20 PTP Delay Request Frame Transmitted */
- uint32_t SFT:1; /*!< bit: 21 PTP Sync Frame Transmitted */
- uint32_t PDRQFR:1; /*!< bit: 22 PDelay Request Frame Received */
- uint32_t PDRSFR:1; /*!< bit: 23 PDelay Response Frame Received */
- uint32_t PDRQFT:1; /*!< bit: 24 PDelay Request Frame Transmitted */
- uint32_t PDRSFT:1; /*!< bit: 25 PDelay Response Frame Transmitted */
- uint32_t SRI:1; /*!< bit: 26 TSU Seconds Register Increment */
- uint32_t :1; /*!< bit: 27 Reserved */
- uint32_t WOL:1; /*!< bit: 28 Wake On Lan */
- uint32_t TSUCMP:1; /*!< bit: 29 Tsu timer comparison */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_IMR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_IMR_OFFSET 0x030 /**< \brief (GMAC_IMR offset) Interrupt Mask Register */
-#define GMAC_IMR_RESETVALUE _U_(0x3FFFFFFF) /**< \brief (GMAC_IMR reset_value) Interrupt Mask Register */
-
-#define GMAC_IMR_MFS_Pos 0 /**< \brief (GMAC_IMR) Management Frame Sent */
-#define GMAC_IMR_MFS (_U_(0x1) << GMAC_IMR_MFS_Pos)
-#define GMAC_IMR_RCOMP_Pos 1 /**< \brief (GMAC_IMR) Receive Complete */
-#define GMAC_IMR_RCOMP (_U_(0x1) << GMAC_IMR_RCOMP_Pos)
-#define GMAC_IMR_RXUBR_Pos 2 /**< \brief (GMAC_IMR) RX Used Bit Read */
-#define GMAC_IMR_RXUBR (_U_(0x1) << GMAC_IMR_RXUBR_Pos)
-#define GMAC_IMR_TXUBR_Pos 3 /**< \brief (GMAC_IMR) TX Used Bit Read */
-#define GMAC_IMR_TXUBR (_U_(0x1) << GMAC_IMR_TXUBR_Pos)
-#define GMAC_IMR_TUR_Pos 4 /**< \brief (GMAC_IMR) Transmit Underrun */
-#define GMAC_IMR_TUR (_U_(0x1) << GMAC_IMR_TUR_Pos)
-#define GMAC_IMR_RLEX_Pos 5 /**< \brief (GMAC_IMR) Retry Limit Exceeded */
-#define GMAC_IMR_RLEX (_U_(0x1) << GMAC_IMR_RLEX_Pos)
-#define GMAC_IMR_TFC_Pos 6 /**< \brief (GMAC_IMR) Transmit Frame Corruption Due to AHB Error */
-#define GMAC_IMR_TFC (_U_(0x1) << GMAC_IMR_TFC_Pos)
-#define GMAC_IMR_TCOMP_Pos 7 /**< \brief (GMAC_IMR) Transmit Complete */
-#define GMAC_IMR_TCOMP (_U_(0x1) << GMAC_IMR_TCOMP_Pos)
-#define GMAC_IMR_ROVR_Pos 10 /**< \brief (GMAC_IMR) Receive Overrun */
-#define GMAC_IMR_ROVR (_U_(0x1) << GMAC_IMR_ROVR_Pos)
-#define GMAC_IMR_HRESP_Pos 11 /**< \brief (GMAC_IMR) HRESP Not OK */
-#define GMAC_IMR_HRESP (_U_(0x1) << GMAC_IMR_HRESP_Pos)
-#define GMAC_IMR_PFNZ_Pos 12 /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */
-#define GMAC_IMR_PFNZ (_U_(0x1) << GMAC_IMR_PFNZ_Pos)
-#define GMAC_IMR_PTZ_Pos 13 /**< \brief (GMAC_IMR) Pause Time Zero */
-#define GMAC_IMR_PTZ (_U_(0x1) << GMAC_IMR_PTZ_Pos)
-#define GMAC_IMR_PFTR_Pos 14 /**< \brief (GMAC_IMR) Pause Frame Transmitted */
-#define GMAC_IMR_PFTR (_U_(0x1) << GMAC_IMR_PFTR_Pos)
-#define GMAC_IMR_EXINT_Pos 15 /**< \brief (GMAC_IMR) External Interrupt */
-#define GMAC_IMR_EXINT (_U_(0x1) << GMAC_IMR_EXINT_Pos)
-#define GMAC_IMR_DRQFR_Pos 18 /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */
-#define GMAC_IMR_DRQFR (_U_(0x1) << GMAC_IMR_DRQFR_Pos)
-#define GMAC_IMR_SFR_Pos 19 /**< \brief (GMAC_IMR) PTP Sync Frame Received */
-#define GMAC_IMR_SFR (_U_(0x1) << GMAC_IMR_SFR_Pos)
-#define GMAC_IMR_DRQFT_Pos 20 /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */
-#define GMAC_IMR_DRQFT (_U_(0x1) << GMAC_IMR_DRQFT_Pos)
-#define GMAC_IMR_SFT_Pos 21 /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */
-#define GMAC_IMR_SFT (_U_(0x1) << GMAC_IMR_SFT_Pos)
-#define GMAC_IMR_PDRQFR_Pos 22 /**< \brief (GMAC_IMR) PDelay Request Frame Received */
-#define GMAC_IMR_PDRQFR (_U_(0x1) << GMAC_IMR_PDRQFR_Pos)
-#define GMAC_IMR_PDRSFR_Pos 23 /**< \brief (GMAC_IMR) PDelay Response Frame Received */
-#define GMAC_IMR_PDRSFR (_U_(0x1) << GMAC_IMR_PDRSFR_Pos)
-#define GMAC_IMR_PDRQFT_Pos 24 /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */
-#define GMAC_IMR_PDRQFT (_U_(0x1) << GMAC_IMR_PDRQFT_Pos)
-#define GMAC_IMR_PDRSFT_Pos 25 /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */
-#define GMAC_IMR_PDRSFT (_U_(0x1) << GMAC_IMR_PDRSFT_Pos)
-#define GMAC_IMR_SRI_Pos 26 /**< \brief (GMAC_IMR) TSU Seconds Register Increment */
-#define GMAC_IMR_SRI (_U_(0x1) << GMAC_IMR_SRI_Pos)
-#define GMAC_IMR_WOL_Pos 28 /**< \brief (GMAC_IMR) Wake On Lan */
-#define GMAC_IMR_WOL (_U_(0x1) << GMAC_IMR_WOL_Pos)
-#define GMAC_IMR_TSUCMP_Pos 29 /**< \brief (GMAC_IMR) Tsu timer comparison */
-#define GMAC_IMR_TSUCMP (_U_(0x1) << GMAC_IMR_TSUCMP_Pos)
-#define GMAC_IMR_MASK _U_(0x37FCFCFF) /**< \brief (GMAC_IMR) MASK Register */
-
-/* -------- GMAC_MAN : (GMAC Offset: 0x034) (R/W 32) PHY Maintenance Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DATA:16; /*!< bit: 0..15 PHY Data */
- uint32_t WTN:2; /*!< bit: 16..17 Write Ten */
- uint32_t REGA:5; /*!< bit: 18..22 Register Address */
- uint32_t PHYA:5; /*!< bit: 23..27 PHY Address */
- uint32_t OP:2; /*!< bit: 28..29 Operation */
- uint32_t CLTTO:1; /*!< bit: 30 Clause 22 Operation */
- uint32_t WZO:1; /*!< bit: 31 Write ZERO */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_MAN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_MAN_OFFSET 0x034 /**< \brief (GMAC_MAN offset) PHY Maintenance Register */
-#define GMAC_MAN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_MAN reset_value) PHY Maintenance Register */
-
-#define GMAC_MAN_DATA_Pos 0 /**< \brief (GMAC_MAN) PHY Data */
-#define GMAC_MAN_DATA_Msk (_U_(0xFFFF) << GMAC_MAN_DATA_Pos)
-#define GMAC_MAN_DATA(value) (GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))
-#define GMAC_MAN_WTN_Pos 16 /**< \brief (GMAC_MAN) Write Ten */
-#define GMAC_MAN_WTN_Msk (_U_(0x3) << GMAC_MAN_WTN_Pos)
-#define GMAC_MAN_WTN(value) (GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))
-#define GMAC_MAN_REGA_Pos 18 /**< \brief (GMAC_MAN) Register Address */
-#define GMAC_MAN_REGA_Msk (_U_(0x1F) << GMAC_MAN_REGA_Pos)
-#define GMAC_MAN_REGA(value) (GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))
-#define GMAC_MAN_PHYA_Pos 23 /**< \brief (GMAC_MAN) PHY Address */
-#define GMAC_MAN_PHYA_Msk (_U_(0x1F) << GMAC_MAN_PHYA_Pos)
-#define GMAC_MAN_PHYA(value) (GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))
-#define GMAC_MAN_OP_Pos 28 /**< \brief (GMAC_MAN) Operation */
-#define GMAC_MAN_OP_Msk (_U_(0x3) << GMAC_MAN_OP_Pos)
-#define GMAC_MAN_OP(value) (GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))
-#define GMAC_MAN_CLTTO_Pos 30 /**< \brief (GMAC_MAN) Clause 22 Operation */
-#define GMAC_MAN_CLTTO (_U_(0x1) << GMAC_MAN_CLTTO_Pos)
-#define GMAC_MAN_WZO_Pos 31 /**< \brief (GMAC_MAN) Write ZERO */
-#define GMAC_MAN_WZO (_U_(0x1) << GMAC_MAN_WZO_Pos)
-#define GMAC_MAN_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_MAN) MASK Register */
-
-/* -------- GMAC_RPQ : (GMAC Offset: 0x038) (R/ 32) Received Pause Quantum Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RPQ:16; /*!< bit: 0..15 Received Pause Quantum */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_RPQ_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_RPQ_OFFSET 0x038 /**< \brief (GMAC_RPQ offset) Received Pause Quantum Register */
-#define GMAC_RPQ_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RPQ reset_value) Received Pause Quantum Register */
-
-#define GMAC_RPQ_RPQ_Pos 0 /**< \brief (GMAC_RPQ) Received Pause Quantum */
-#define GMAC_RPQ_RPQ_Msk (_U_(0xFFFF) << GMAC_RPQ_RPQ_Pos)
-#define GMAC_RPQ_RPQ(value) (GMAC_RPQ_RPQ_Msk & ((value) << GMAC_RPQ_RPQ_Pos))
-#define GMAC_RPQ_MASK _U_(0x0000FFFF) /**< \brief (GMAC_RPQ) MASK Register */
-
-/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) (R/W 32) Transmit Pause Quantum Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TPQ:16; /*!< bit: 0..15 Transmit Pause Quantum */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TPQ_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TPQ_OFFSET 0x03C /**< \brief (GMAC_TPQ offset) Transmit Pause Quantum Register */
-#define GMAC_TPQ_RESETVALUE _U_(0x0000FFFF) /**< \brief (GMAC_TPQ reset_value) Transmit Pause Quantum Register */
-
-#define GMAC_TPQ_TPQ_Pos 0 /**< \brief (GMAC_TPQ) Transmit Pause Quantum */
-#define GMAC_TPQ_TPQ_Msk (_U_(0xFFFF) << GMAC_TPQ_TPQ_Pos)
-#define GMAC_TPQ_TPQ(value) (GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))
-#define GMAC_TPQ_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TPQ) MASK Register */
-
-/* -------- GMAC_TPSF : (GMAC Offset: 0x040) (R/W 32) TX partial store and forward Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TPB1ADR:10; /*!< bit: 0.. 9 TX packet buffer address */
- uint32_t :21; /*!< bit: 10..30 Reserved */
- uint32_t ENTXP:1; /*!< bit: 31 Enable TX partial store and forward operation */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TPSF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TPSF_OFFSET 0x040 /**< \brief (GMAC_TPSF offset) TX partial store and forward Register */
-#define GMAC_TPSF_RESETVALUE _U_(0x000003FF) /**< \brief (GMAC_TPSF reset_value) TX partial store and forward Register */
-
-#define GMAC_TPSF_TPB1ADR_Pos 0 /**< \brief (GMAC_TPSF) TX packet buffer address */
-#define GMAC_TPSF_TPB1ADR_Msk (_U_(0x3FF) << GMAC_TPSF_TPB1ADR_Pos)
-#define GMAC_TPSF_TPB1ADR(value) (GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos))
-#define GMAC_TPSF_ENTXP_Pos 31 /**< \brief (GMAC_TPSF) Enable TX partial store and forward operation */
-#define GMAC_TPSF_ENTXP (_U_(0x1) << GMAC_TPSF_ENTXP_Pos)
-#define GMAC_TPSF_MASK _U_(0x800003FF) /**< \brief (GMAC_TPSF) MASK Register */
-
-/* -------- GMAC_RPSF : (GMAC Offset: 0x044) (R/W 32) RX partial store and forward Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RPB1ADR:10; /*!< bit: 0.. 9 RX packet buffer address */
- uint32_t :21; /*!< bit: 10..30 Reserved */
- uint32_t ENRXP:1; /*!< bit: 31 Enable RX partial store and forward operation */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_RPSF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_RPSF_OFFSET 0x044 /**< \brief (GMAC_RPSF offset) RX partial store and forward Register */
-#define GMAC_RPSF_RESETVALUE _U_(0x000003FF) /**< \brief (GMAC_RPSF reset_value) RX partial store and forward Register */
-
-#define GMAC_RPSF_RPB1ADR_Pos 0 /**< \brief (GMAC_RPSF) RX packet buffer address */
-#define GMAC_RPSF_RPB1ADR_Msk (_U_(0x3FF) << GMAC_RPSF_RPB1ADR_Pos)
-#define GMAC_RPSF_RPB1ADR(value) (GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos))
-#define GMAC_RPSF_ENRXP_Pos 31 /**< \brief (GMAC_RPSF) Enable RX partial store and forward operation */
-#define GMAC_RPSF_ENRXP (_U_(0x1) << GMAC_RPSF_ENRXP_Pos)
-#define GMAC_RPSF_MASK _U_(0x800003FF) /**< \brief (GMAC_RPSF) MASK Register */
-
-/* -------- GMAC_RJFML : (GMAC Offset: 0x048) (R/W 32) RX Jumbo Frame Max Length Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t FML:14; /*!< bit: 0..13 Frame Max Length */
- uint32_t :18; /*!< bit: 14..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_RJFML_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_RJFML_OFFSET 0x048 /**< \brief (GMAC_RJFML offset) RX Jumbo Frame Max Length Register */
-#define GMAC_RJFML_RESETVALUE _U_(0x00003FFF) /**< \brief (GMAC_RJFML reset_value) RX Jumbo Frame Max Length Register */
-
-#define GMAC_RJFML_FML_Pos 0 /**< \brief (GMAC_RJFML) Frame Max Length */
-#define GMAC_RJFML_FML_Msk (_U_(0x3FFF) << GMAC_RJFML_FML_Pos)
-#define GMAC_RJFML_FML(value) (GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos))
-#define GMAC_RJFML_MASK _U_(0x00003FFF) /**< \brief (GMAC_RJFML) MASK Register */
-
-/* -------- GMAC_HRB : (GMAC Offset: 0x080) (R/W 32) Hash Register Bottom [31:0] -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ADDR:32; /*!< bit: 0..31 Hash Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_HRB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_HRB_OFFSET 0x080 /**< \brief (GMAC_HRB offset) Hash Register Bottom [31:0] */
-#define GMAC_HRB_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_HRB reset_value) Hash Register Bottom [31:0] */
-
-#define GMAC_HRB_ADDR_Pos 0 /**< \brief (GMAC_HRB) Hash Address */
-#define GMAC_HRB_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_HRB_ADDR_Pos)
-#define GMAC_HRB_ADDR(value) (GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))
-#define GMAC_HRB_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_HRB) MASK Register */
-
-/* -------- GMAC_HRT : (GMAC Offset: 0x084) (R/W 32) Hash Register Top [63:32] -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ADDR:32; /*!< bit: 0..31 Hash Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_HRT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_HRT_OFFSET 0x084 /**< \brief (GMAC_HRT offset) Hash Register Top [63:32] */
-#define GMAC_HRT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_HRT reset_value) Hash Register Top [63:32] */
-
-#define GMAC_HRT_ADDR_Pos 0 /**< \brief (GMAC_HRT) Hash Address */
-#define GMAC_HRT_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_HRT_ADDR_Pos)
-#define GMAC_HRT_ADDR(value) (GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))
-#define GMAC_HRT_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_HRT) MASK Register */
-
-/* -------- GMAC_SAB : (GMAC Offset: 0x088) (R/W 32) SA Specific Address Bottom [31:0] Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ADDR:32; /*!< bit: 0..31 Specific Address 1 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_SAB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_SAB_OFFSET 0x088 /**< \brief (GMAC_SAB offset) Specific Address Bottom [31:0] Register */
-#define GMAC_SAB_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SAB reset_value) Specific Address Bottom [31:0] Register */
-
-#define GMAC_SAB_ADDR_Pos 0 /**< \brief (GMAC_SAB) Specific Address 1 */
-#define GMAC_SAB_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_SAB_ADDR_Pos)
-#define GMAC_SAB_ADDR(value) (GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos))
-#define GMAC_SAB_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_SAB) MASK Register */
-
-/* -------- GMAC_SAT : (GMAC Offset: 0x08C) (R/W 32) SA Specific Address Top [47:32] Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ADDR:16; /*!< bit: 0..15 Specific Address 1 */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_SAT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_SAT_OFFSET 0x08C /**< \brief (GMAC_SAT offset) Specific Address Top [47:32] Register */
-#define GMAC_SAT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SAT reset_value) Specific Address Top [47:32] Register */
-
-#define GMAC_SAT_ADDR_Pos 0 /**< \brief (GMAC_SAT) Specific Address 1 */
-#define GMAC_SAT_ADDR_Msk (_U_(0xFFFF) << GMAC_SAT_ADDR_Pos)
-#define GMAC_SAT_ADDR(value) (GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos))
-#define GMAC_SAT_MASK _U_(0x0000FFFF) /**< \brief (GMAC_SAT) MASK Register */
-
-/* -------- GMAC_TIDM : (GMAC Offset: 0x0A8) (R/W 32) Type ID Match Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TID:16; /*!< bit: 0..15 Type ID Match 1 */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TIDM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TIDM_OFFSET 0x0A8 /**< \brief (GMAC_TIDM offset) Type ID Match Register */
-#define GMAC_TIDM_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TIDM reset_value) Type ID Match Register */
-
-#define GMAC_TIDM_TID_Pos 0 /**< \brief (GMAC_TIDM) Type ID Match 1 */
-#define GMAC_TIDM_TID_Msk (_U_(0xFFFF) << GMAC_TIDM_TID_Pos)
-#define GMAC_TIDM_TID(value) (GMAC_TIDM_TID_Msk & ((value) << GMAC_TIDM_TID_Pos))
-#define GMAC_TIDM_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TIDM) MASK Register */
-
-/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) (R/W 32) Wake on LAN -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t IP:16; /*!< bit: 0..15 IP address */
- uint32_t MAG:1; /*!< bit: 16 Event enable */
- uint32_t ARP:1; /*!< bit: 17 LAN ARP req */
- uint32_t SA1:1; /*!< bit: 18 WOL specific address reg 1 */
- uint32_t MTI:1; /*!< bit: 19 WOL LAN multicast */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_WOL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_WOL_OFFSET 0x0B8 /**< \brief (GMAC_WOL offset) Wake on LAN */
-#define GMAC_WOL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_WOL reset_value) Wake on LAN */
-
-#define GMAC_WOL_IP_Pos 0 /**< \brief (GMAC_WOL) IP address */
-#define GMAC_WOL_IP_Msk (_U_(0xFFFF) << GMAC_WOL_IP_Pos)
-#define GMAC_WOL_IP(value) (GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos))
-#define GMAC_WOL_MAG_Pos 16 /**< \brief (GMAC_WOL) Event enable */
-#define GMAC_WOL_MAG (_U_(0x1) << GMAC_WOL_MAG_Pos)
-#define GMAC_WOL_ARP_Pos 17 /**< \brief (GMAC_WOL) LAN ARP req */
-#define GMAC_WOL_ARP (_U_(0x1) << GMAC_WOL_ARP_Pos)
-#define GMAC_WOL_SA1_Pos 18 /**< \brief (GMAC_WOL) WOL specific address reg 1 */
-#define GMAC_WOL_SA1 (_U_(0x1) << GMAC_WOL_SA1_Pos)
-#define GMAC_WOL_MTI_Pos 19 /**< \brief (GMAC_WOL) WOL LAN multicast */
-#define GMAC_WOL_MTI (_U_(0x1) << GMAC_WOL_MTI_Pos)
-#define GMAC_WOL_MASK _U_(0x000FFFFF) /**< \brief (GMAC_WOL) MASK Register */
-
-/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) (R/W 32) IPG Stretch Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t FL:16; /*!< bit: 0..15 Frame Length */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_IPGS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_IPGS_OFFSET 0x0BC /**< \brief (GMAC_IPGS offset) IPG Stretch Register */
-#define GMAC_IPGS_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_IPGS reset_value) IPG Stretch Register */
-
-#define GMAC_IPGS_FL_Pos 0 /**< \brief (GMAC_IPGS) Frame Length */
-#define GMAC_IPGS_FL_Msk (_U_(0xFFFF) << GMAC_IPGS_FL_Pos)
-#define GMAC_IPGS_FL(value) (GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))
-#define GMAC_IPGS_MASK _U_(0x0000FFFF) /**< \brief (GMAC_IPGS) MASK Register */
-
-/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) (R/W 32) Stacked VLAN Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t VLAN_TYPE:16; /*!< bit: 0..15 User Defined VLAN_TYPE Field */
- uint32_t :15; /*!< bit: 16..30 Reserved */
- uint32_t ESVLAN:1; /*!< bit: 31 Enable Stacked VLAN Processing Mode */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_SVLAN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_SVLAN_OFFSET 0x0C0 /**< \brief (GMAC_SVLAN offset) Stacked VLAN Register */
-#define GMAC_SVLAN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SVLAN reset_value) Stacked VLAN Register */
-
-#define GMAC_SVLAN_VLAN_TYPE_Pos 0 /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */
-#define GMAC_SVLAN_VLAN_TYPE_Msk (_U_(0xFFFF) << GMAC_SVLAN_VLAN_TYPE_Pos)
-#define GMAC_SVLAN_VLAN_TYPE(value) (GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))
-#define GMAC_SVLAN_ESVLAN_Pos 31 /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */
-#define GMAC_SVLAN_ESVLAN (_U_(0x1) << GMAC_SVLAN_ESVLAN_Pos)
-#define GMAC_SVLAN_MASK _U_(0x8000FFFF) /**< \brief (GMAC_SVLAN) MASK Register */
-
-/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) (R/W 32) Transmit PFC Pause Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t PEV:8; /*!< bit: 0.. 7 Priority Enable Vector */
- uint32_t PQ:8; /*!< bit: 8..15 Pause Quantum */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TPFCP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TPFCP_OFFSET 0x0C4 /**< \brief (GMAC_TPFCP offset) Transmit PFC Pause Register */
-#define GMAC_TPFCP_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TPFCP reset_value) Transmit PFC Pause Register */
-
-#define GMAC_TPFCP_PEV_Pos 0 /**< \brief (GMAC_TPFCP) Priority Enable Vector */
-#define GMAC_TPFCP_PEV_Msk (_U_(0xFF) << GMAC_TPFCP_PEV_Pos)
-#define GMAC_TPFCP_PEV(value) (GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))
-#define GMAC_TPFCP_PQ_Pos 8 /**< \brief (GMAC_TPFCP) Pause Quantum */
-#define GMAC_TPFCP_PQ_Msk (_U_(0xFF) << GMAC_TPFCP_PQ_Pos)
-#define GMAC_TPFCP_PQ(value) (GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))
-#define GMAC_TPFCP_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TPFCP) MASK Register */
-
-/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) (R/W 32) Specific Address 1 Mask Bottom [31:0] Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ADDR:32; /*!< bit: 0..31 Specific Address 1 Mask */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_SAMB1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_SAMB1_OFFSET 0x0C8 /**< \brief (GMAC_SAMB1 offset) Specific Address 1 Mask Bottom [31:0] Register */
-#define GMAC_SAMB1_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SAMB1 reset_value) Specific Address 1 Mask Bottom [31:0] Register */
-
-#define GMAC_SAMB1_ADDR_Pos 0 /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */
-#define GMAC_SAMB1_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_SAMB1_ADDR_Pos)
-#define GMAC_SAMB1_ADDR(value) (GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))
-#define GMAC_SAMB1_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_SAMB1) MASK Register */
-
-/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) (R/W 32) Specific Address 1 Mask Top [47:32] Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ADDR:16; /*!< bit: 0..15 Specific Address 1 Mask */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_SAMT1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_SAMT1_OFFSET 0x0CC /**< \brief (GMAC_SAMT1 offset) Specific Address 1 Mask Top [47:32] Register */
-#define GMAC_SAMT1_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SAMT1 reset_value) Specific Address 1 Mask Top [47:32] Register */
-
-#define GMAC_SAMT1_ADDR_Pos 0 /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */
-#define GMAC_SAMT1_ADDR_Msk (_U_(0xFFFF) << GMAC_SAMT1_ADDR_Pos)
-#define GMAC_SAMT1_ADDR(value) (GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))
-#define GMAC_SAMT1_MASK _U_(0x0000FFFF) /**< \brief (GMAC_SAMT1) MASK Register */
-
-/* -------- GMAC_NSC : (GMAC Offset: 0x0DC) (R/W 32) Tsu timer comparison nanoseconds Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t NANOSEC:21; /*!< bit: 0..20 1588 Timer Nanosecond comparison value */
- uint32_t :11; /*!< bit: 21..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_NSC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_NSC_OFFSET 0x0DC /**< \brief (GMAC_NSC offset) Tsu timer comparison nanoseconds Register */
-#define GMAC_NSC_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_NSC reset_value) Tsu timer comparison nanoseconds Register */
-
-#define GMAC_NSC_NANOSEC_Pos 0 /**< \brief (GMAC_NSC) 1588 Timer Nanosecond comparison value */
-#define GMAC_NSC_NANOSEC_Msk (_U_(0x1FFFFF) << GMAC_NSC_NANOSEC_Pos)
-#define GMAC_NSC_NANOSEC(value) (GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos))
-#define GMAC_NSC_MASK _U_(0x001FFFFF) /**< \brief (GMAC_NSC) MASK Register */
-
-/* -------- GMAC_SCL : (GMAC Offset: 0x0E0) (R/W 32) Tsu timer second comparison Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SEC:32; /*!< bit: 0..31 1588 Timer Second comparison value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_SCL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_SCL_OFFSET 0x0E0 /**< \brief (GMAC_SCL offset) Tsu timer second comparison Register */
-#define GMAC_SCL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SCL reset_value) Tsu timer second comparison Register */
-
-#define GMAC_SCL_SEC_Pos 0 /**< \brief (GMAC_SCL) 1588 Timer Second comparison value */
-#define GMAC_SCL_SEC_Msk (_U_(0xFFFFFFFF) << GMAC_SCL_SEC_Pos)
-#define GMAC_SCL_SEC(value) (GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos))
-#define GMAC_SCL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_SCL) MASK Register */
-
-/* -------- GMAC_SCH : (GMAC Offset: 0x0E4) (R/W 32) Tsu timer second comparison Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SEC:16; /*!< bit: 0..15 1588 Timer Second comparison value */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_SCH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_SCH_OFFSET 0x0E4 /**< \brief (GMAC_SCH offset) Tsu timer second comparison Register */
-#define GMAC_SCH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SCH reset_value) Tsu timer second comparison Register */
-
-#define GMAC_SCH_SEC_Pos 0 /**< \brief (GMAC_SCH) 1588 Timer Second comparison value */
-#define GMAC_SCH_SEC_Msk (_U_(0xFFFF) << GMAC_SCH_SEC_Pos)
-#define GMAC_SCH_SEC(value) (GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos))
-#define GMAC_SCH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_SCH) MASK Register */
-
-/* -------- GMAC_EFTSH : (GMAC Offset: 0x0E8) (R/ 32) PTP Event Frame Transmitted Seconds High Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RUD:16; /*!< bit: 0..15 Register Update */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_EFTSH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_EFTSH_OFFSET 0x0E8 /**< \brief (GMAC_EFTSH offset) PTP Event Frame Transmitted Seconds High Register */
-#define GMAC_EFTSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFTSH reset_value) PTP Event Frame Transmitted Seconds High Register */
-
-#define GMAC_EFTSH_RUD_Pos 0 /**< \brief (GMAC_EFTSH) Register Update */
-#define GMAC_EFTSH_RUD_Msk (_U_(0xFFFF) << GMAC_EFTSH_RUD_Pos)
-#define GMAC_EFTSH_RUD(value) (GMAC_EFTSH_RUD_Msk & ((value) << GMAC_EFTSH_RUD_Pos))
-#define GMAC_EFTSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_EFTSH) MASK Register */
-
-/* -------- GMAC_EFRSH : (GMAC Offset: 0x0EC) (R/ 32) PTP Event Frame Received Seconds High Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RUD:16; /*!< bit: 0..15 Register Update */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_EFRSH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_EFRSH_OFFSET 0x0EC /**< \brief (GMAC_EFRSH offset) PTP Event Frame Received Seconds High Register */
-#define GMAC_EFRSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFRSH reset_value) PTP Event Frame Received Seconds High Register */
-
-#define GMAC_EFRSH_RUD_Pos 0 /**< \brief (GMAC_EFRSH) Register Update */
-#define GMAC_EFRSH_RUD_Msk (_U_(0xFFFF) << GMAC_EFRSH_RUD_Pos)
-#define GMAC_EFRSH_RUD(value) (GMAC_EFRSH_RUD_Msk & ((value) << GMAC_EFRSH_RUD_Pos))
-#define GMAC_EFRSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_EFRSH) MASK Register */
-
-/* -------- GMAC_PEFTSH : (GMAC Offset: 0x0F0) (R/ 32) PTP Peer Event Frame Transmitted Seconds High Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RUD:16; /*!< bit: 0..15 Register Update */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_PEFTSH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_PEFTSH_OFFSET 0x0F0 /**< \brief (GMAC_PEFTSH offset) PTP Peer Event Frame Transmitted Seconds High Register */
-#define GMAC_PEFTSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFTSH reset_value) PTP Peer Event Frame Transmitted Seconds High Register */
-
-#define GMAC_PEFTSH_RUD_Pos 0 /**< \brief (GMAC_PEFTSH) Register Update */
-#define GMAC_PEFTSH_RUD_Msk (_U_(0xFFFF) << GMAC_PEFTSH_RUD_Pos)
-#define GMAC_PEFTSH_RUD(value) (GMAC_PEFTSH_RUD_Msk & ((value) << GMAC_PEFTSH_RUD_Pos))
-#define GMAC_PEFTSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_PEFTSH) MASK Register */
-
-/* -------- GMAC_PEFRSH : (GMAC Offset: 0x0F4) (R/ 32) PTP Peer Event Frame Received Seconds High Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RUD:16; /*!< bit: 0..15 Register Update */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_PEFRSH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_PEFRSH_OFFSET 0x0F4 /**< \brief (GMAC_PEFRSH offset) PTP Peer Event Frame Received Seconds High Register */
-#define GMAC_PEFRSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFRSH reset_value) PTP Peer Event Frame Received Seconds High Register */
-
-#define GMAC_PEFRSH_RUD_Pos 0 /**< \brief (GMAC_PEFRSH) Register Update */
-#define GMAC_PEFRSH_RUD_Msk (_U_(0xFFFF) << GMAC_PEFRSH_RUD_Pos)
-#define GMAC_PEFRSH_RUD(value) (GMAC_PEFRSH_RUD_Msk & ((value) << GMAC_PEFRSH_RUD_Pos))
-#define GMAC_PEFRSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_PEFRSH) MASK Register */
-
-/* -------- GMAC_OTLO : (GMAC Offset: 0x100) (R/ 32) Octets Transmitted [31:0] Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TXO:32; /*!< bit: 0..31 Transmitted Octets */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_OTLO_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_OTLO_OFFSET 0x100 /**< \brief (GMAC_OTLO offset) Octets Transmitted [31:0] Register */
-#define GMAC_OTLO_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_OTLO reset_value) Octets Transmitted [31:0] Register */
-
-#define GMAC_OTLO_TXO_Pos 0 /**< \brief (GMAC_OTLO) Transmitted Octets */
-#define GMAC_OTLO_TXO_Msk (_U_(0xFFFFFFFF) << GMAC_OTLO_TXO_Pos)
-#define GMAC_OTLO_TXO(value) (GMAC_OTLO_TXO_Msk & ((value) << GMAC_OTLO_TXO_Pos))
-#define GMAC_OTLO_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_OTLO) MASK Register */
-
-/* -------- GMAC_OTHI : (GMAC Offset: 0x104) (R/ 32) Octets Transmitted [47:32] Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TXO:16; /*!< bit: 0..15 Transmitted Octets */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_OTHI_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_OTHI_OFFSET 0x104 /**< \brief (GMAC_OTHI offset) Octets Transmitted [47:32] Register */
-#define GMAC_OTHI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_OTHI reset_value) Octets Transmitted [47:32] Register */
-
-#define GMAC_OTHI_TXO_Pos 0 /**< \brief (GMAC_OTHI) Transmitted Octets */
-#define GMAC_OTHI_TXO_Msk (_U_(0xFFFF) << GMAC_OTHI_TXO_Pos)
-#define GMAC_OTHI_TXO(value) (GMAC_OTHI_TXO_Msk & ((value) << GMAC_OTHI_TXO_Pos))
-#define GMAC_OTHI_MASK _U_(0x0000FFFF) /**< \brief (GMAC_OTHI) MASK Register */
-
-/* -------- GMAC_FT : (GMAC Offset: 0x108) (R/ 32) Frames Transmitted Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t FTX:32; /*!< bit: 0..31 Frames Transmitted without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_FT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_FT_OFFSET 0x108 /**< \brief (GMAC_FT offset) Frames Transmitted Register */
-#define GMAC_FT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_FT reset_value) Frames Transmitted Register */
-
-#define GMAC_FT_FTX_Pos 0 /**< \brief (GMAC_FT) Frames Transmitted without Error */
-#define GMAC_FT_FTX_Msk (_U_(0xFFFFFFFF) << GMAC_FT_FTX_Pos)
-#define GMAC_FT_FTX(value) (GMAC_FT_FTX_Msk & ((value) << GMAC_FT_FTX_Pos))
-#define GMAC_FT_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_FT) MASK Register */
-
-/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) (R/ 32) Broadcast Frames Transmitted Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t BFTX:32; /*!< bit: 0..31 Broadcast Frames Transmitted without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_BCFT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_BCFT_OFFSET 0x10C /**< \brief (GMAC_BCFT offset) Broadcast Frames Transmitted Register */
-#define GMAC_BCFT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_BCFT reset_value) Broadcast Frames Transmitted Register */
-
-#define GMAC_BCFT_BFTX_Pos 0 /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */
-#define GMAC_BCFT_BFTX_Msk (_U_(0xFFFFFFFF) << GMAC_BCFT_BFTX_Pos)
-#define GMAC_BCFT_BFTX(value) (GMAC_BCFT_BFTX_Msk & ((value) << GMAC_BCFT_BFTX_Pos))
-#define GMAC_BCFT_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_BCFT) MASK Register */
-
-/* -------- GMAC_MFT : (GMAC Offset: 0x110) (R/ 32) Multicast Frames Transmitted Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t MFTX:32; /*!< bit: 0..31 Multicast Frames Transmitted without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_MFT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_MFT_OFFSET 0x110 /**< \brief (GMAC_MFT offset) Multicast Frames Transmitted Register */
-#define GMAC_MFT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_MFT reset_value) Multicast Frames Transmitted Register */
-
-#define GMAC_MFT_MFTX_Pos 0 /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */
-#define GMAC_MFT_MFTX_Msk (_U_(0xFFFFFFFF) << GMAC_MFT_MFTX_Pos)
-#define GMAC_MFT_MFTX(value) (GMAC_MFT_MFTX_Msk & ((value) << GMAC_MFT_MFTX_Pos))
-#define GMAC_MFT_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_MFT) MASK Register */
-
-/* -------- GMAC_PFT : (GMAC Offset: 0x114) (R/ 32) Pause Frames Transmitted Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t PFTX:16; /*!< bit: 0..15 Pause Frames Transmitted Register */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_PFT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_PFT_OFFSET 0x114 /**< \brief (GMAC_PFT offset) Pause Frames Transmitted Register */
-#define GMAC_PFT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PFT reset_value) Pause Frames Transmitted Register */
-
-#define GMAC_PFT_PFTX_Pos 0 /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */
-#define GMAC_PFT_PFTX_Msk (_U_(0xFFFF) << GMAC_PFT_PFTX_Pos)
-#define GMAC_PFT_PFTX(value) (GMAC_PFT_PFTX_Msk & ((value) << GMAC_PFT_PFTX_Pos))
-#define GMAC_PFT_MASK _U_(0x0000FFFF) /**< \brief (GMAC_PFT) MASK Register */
-
-/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) (R/ 32) 64 Byte Frames Transmitted Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t NFTX:32; /*!< bit: 0..31 64 Byte Frames Transmitted without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_BFT64_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_BFT64_OFFSET 0x118 /**< \brief (GMAC_BFT64 offset) 64 Byte Frames Transmitted Register */
-#define GMAC_BFT64_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_BFT64 reset_value) 64 Byte Frames Transmitted Register */
-
-#define GMAC_BFT64_NFTX_Pos 0 /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */
-#define GMAC_BFT64_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_BFT64_NFTX_Pos)
-#define GMAC_BFT64_NFTX(value) (GMAC_BFT64_NFTX_Msk & ((value) << GMAC_BFT64_NFTX_Pos))
-#define GMAC_BFT64_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_BFT64) MASK Register */
-
-/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) (R/ 32) 65 to 127 Byte Frames Transmitted Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t NFTX:32; /*!< bit: 0..31 65 to 127 Byte Frames Transmitted without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TBFT127_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TBFT127_OFFSET 0x11C /**< \brief (GMAC_TBFT127 offset) 65 to 127 Byte Frames Transmitted Register */
-#define GMAC_TBFT127_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT127 reset_value) 65 to 127 Byte Frames Transmitted Register */
-
-#define GMAC_TBFT127_NFTX_Pos 0 /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */
-#define GMAC_TBFT127_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT127_NFTX_Pos)
-#define GMAC_TBFT127_NFTX(value) (GMAC_TBFT127_NFTX_Msk & ((value) << GMAC_TBFT127_NFTX_Pos))
-#define GMAC_TBFT127_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT127) MASK Register */
-
-/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) (R/ 32) 128 to 255 Byte Frames Transmitted Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t NFTX:32; /*!< bit: 0..31 128 to 255 Byte Frames Transmitted without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TBFT255_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TBFT255_OFFSET 0x120 /**< \brief (GMAC_TBFT255 offset) 128 to 255 Byte Frames Transmitted Register */
-#define GMAC_TBFT255_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT255 reset_value) 128 to 255 Byte Frames Transmitted Register */
-
-#define GMAC_TBFT255_NFTX_Pos 0 /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */
-#define GMAC_TBFT255_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT255_NFTX_Pos)
-#define GMAC_TBFT255_NFTX(value) (GMAC_TBFT255_NFTX_Msk & ((value) << GMAC_TBFT255_NFTX_Pos))
-#define GMAC_TBFT255_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT255) MASK Register */
-
-/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) (R/ 32) 256 to 511 Byte Frames Transmitted Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t NFTX:32; /*!< bit: 0..31 256 to 511 Byte Frames Transmitted without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TBFT511_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TBFT511_OFFSET 0x124 /**< \brief (GMAC_TBFT511 offset) 256 to 511 Byte Frames Transmitted Register */
-#define GMAC_TBFT511_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT511 reset_value) 256 to 511 Byte Frames Transmitted Register */
-
-#define GMAC_TBFT511_NFTX_Pos 0 /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */
-#define GMAC_TBFT511_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT511_NFTX_Pos)
-#define GMAC_TBFT511_NFTX(value) (GMAC_TBFT511_NFTX_Msk & ((value) << GMAC_TBFT511_NFTX_Pos))
-#define GMAC_TBFT511_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT511) MASK Register */
-
-/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) (R/ 32) 512 to 1023 Byte Frames Transmitted Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t NFTX:32; /*!< bit: 0..31 512 to 1023 Byte Frames Transmitted without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TBFT1023_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TBFT1023_OFFSET 0x128 /**< \brief (GMAC_TBFT1023 offset) 512 to 1023 Byte Frames Transmitted Register */
-#define GMAC_TBFT1023_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT1023 reset_value) 512 to 1023 Byte Frames Transmitted Register */
-
-#define GMAC_TBFT1023_NFTX_Pos 0 /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */
-#define GMAC_TBFT1023_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT1023_NFTX_Pos)
-#define GMAC_TBFT1023_NFTX(value) (GMAC_TBFT1023_NFTX_Msk & ((value) << GMAC_TBFT1023_NFTX_Pos))
-#define GMAC_TBFT1023_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT1023) MASK Register */
-
-/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) (R/ 32) 1024 to 1518 Byte Frames Transmitted Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t NFTX:32; /*!< bit: 0..31 1024 to 1518 Byte Frames Transmitted without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TBFT1518_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TBFT1518_OFFSET 0x12C /**< \brief (GMAC_TBFT1518 offset) 1024 to 1518 Byte Frames Transmitted Register */
-#define GMAC_TBFT1518_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT1518 reset_value) 1024 to 1518 Byte Frames Transmitted Register */
-
-#define GMAC_TBFT1518_NFTX_Pos 0 /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */
-#define GMAC_TBFT1518_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT1518_NFTX_Pos)
-#define GMAC_TBFT1518_NFTX(value) (GMAC_TBFT1518_NFTX_Msk & ((value) << GMAC_TBFT1518_NFTX_Pos))
-#define GMAC_TBFT1518_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT1518) MASK Register */
-
-/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) (R/ 32) Greater Than 1518 Byte Frames Transmitted Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t NFTX:32; /*!< bit: 0..31 Greater than 1518 Byte Frames Transmitted without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_GTBFT1518_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_GTBFT1518_OFFSET 0x130 /**< \brief (GMAC_GTBFT1518 offset) Greater Than 1518 Byte Frames Transmitted Register */
-#define GMAC_GTBFT1518_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_GTBFT1518 reset_value) Greater Than 1518 Byte Frames Transmitted Register */
-
-#define GMAC_GTBFT1518_NFTX_Pos 0 /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */
-#define GMAC_GTBFT1518_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_GTBFT1518_NFTX_Pos)
-#define GMAC_GTBFT1518_NFTX(value) (GMAC_GTBFT1518_NFTX_Msk & ((value) << GMAC_GTBFT1518_NFTX_Pos))
-#define GMAC_GTBFT1518_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_GTBFT1518) MASK Register */
-
-/* -------- GMAC_TUR : (GMAC Offset: 0x134) (R/ 32) Transmit Underruns Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TXUNR:10; /*!< bit: 0.. 9 Transmit Underruns */
- uint32_t :22; /*!< bit: 10..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TUR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TUR_OFFSET 0x134 /**< \brief (GMAC_TUR offset) Transmit Underruns Register */
-#define GMAC_TUR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TUR reset_value) Transmit Underruns Register */
-
-#define GMAC_TUR_TXUNR_Pos 0 /**< \brief (GMAC_TUR) Transmit Underruns */
-#define GMAC_TUR_TXUNR_Msk (_U_(0x3FF) << GMAC_TUR_TXUNR_Pos)
-#define GMAC_TUR_TXUNR(value) (GMAC_TUR_TXUNR_Msk & ((value) << GMAC_TUR_TXUNR_Pos))
-#define GMAC_TUR_MASK _U_(0x000003FF) /**< \brief (GMAC_TUR) MASK Register */
-
-/* -------- GMAC_SCF : (GMAC Offset: 0x138) (R/ 32) Single Collision Frames Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SCOL:18; /*!< bit: 0..17 Single Collision */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_SCF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_SCF_OFFSET 0x138 /**< \brief (GMAC_SCF offset) Single Collision Frames Register */
-#define GMAC_SCF_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SCF reset_value) Single Collision Frames Register */
-
-#define GMAC_SCF_SCOL_Pos 0 /**< \brief (GMAC_SCF) Single Collision */
-#define GMAC_SCF_SCOL_Msk (_U_(0x3FFFF) << GMAC_SCF_SCOL_Pos)
-#define GMAC_SCF_SCOL(value) (GMAC_SCF_SCOL_Msk & ((value) << GMAC_SCF_SCOL_Pos))
-#define GMAC_SCF_MASK _U_(0x0003FFFF) /**< \brief (GMAC_SCF) MASK Register */
-
-/* -------- GMAC_MCF : (GMAC Offset: 0x13C) (R/ 32) Multiple Collision Frames Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t MCOL:18; /*!< bit: 0..17 Multiple Collision */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_MCF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_MCF_OFFSET 0x13C /**< \brief (GMAC_MCF offset) Multiple Collision Frames Register */
-#define GMAC_MCF_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_MCF reset_value) Multiple Collision Frames Register */
-
-#define GMAC_MCF_MCOL_Pos 0 /**< \brief (GMAC_MCF) Multiple Collision */
-#define GMAC_MCF_MCOL_Msk (_U_(0x3FFFF) << GMAC_MCF_MCOL_Pos)
-#define GMAC_MCF_MCOL(value) (GMAC_MCF_MCOL_Msk & ((value) << GMAC_MCF_MCOL_Pos))
-#define GMAC_MCF_MASK _U_(0x0003FFFF) /**< \brief (GMAC_MCF) MASK Register */
-
-/* -------- GMAC_EC : (GMAC Offset: 0x140) (R/ 32) Excessive Collisions Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t XCOL:10; /*!< bit: 0.. 9 Excessive Collisions */
- uint32_t :22; /*!< bit: 10..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_EC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_EC_OFFSET 0x140 /**< \brief (GMAC_EC offset) Excessive Collisions Register */
-#define GMAC_EC_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EC reset_value) Excessive Collisions Register */
-
-#define GMAC_EC_XCOL_Pos 0 /**< \brief (GMAC_EC) Excessive Collisions */
-#define GMAC_EC_XCOL_Msk (_U_(0x3FF) << GMAC_EC_XCOL_Pos)
-#define GMAC_EC_XCOL(value) (GMAC_EC_XCOL_Msk & ((value) << GMAC_EC_XCOL_Pos))
-#define GMAC_EC_MASK _U_(0x000003FF) /**< \brief (GMAC_EC) MASK Register */
-
-/* -------- GMAC_LC : (GMAC Offset: 0x144) (R/ 32) Late Collisions Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t LCOL:10; /*!< bit: 0.. 9 Late Collisions */
- uint32_t :22; /*!< bit: 10..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_LC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_LC_OFFSET 0x144 /**< \brief (GMAC_LC offset) Late Collisions Register */
-#define GMAC_LC_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_LC reset_value) Late Collisions Register */
-
-#define GMAC_LC_LCOL_Pos 0 /**< \brief (GMAC_LC) Late Collisions */
-#define GMAC_LC_LCOL_Msk (_U_(0x3FF) << GMAC_LC_LCOL_Pos)
-#define GMAC_LC_LCOL(value) (GMAC_LC_LCOL_Msk & ((value) << GMAC_LC_LCOL_Pos))
-#define GMAC_LC_MASK _U_(0x000003FF) /**< \brief (GMAC_LC) MASK Register */
-
-/* -------- GMAC_DTF : (GMAC Offset: 0x148) (R/ 32) Deferred Transmission Frames Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DEFT:18; /*!< bit: 0..17 Deferred Transmission */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_DTF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_DTF_OFFSET 0x148 /**< \brief (GMAC_DTF offset) Deferred Transmission Frames Register */
-#define GMAC_DTF_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_DTF reset_value) Deferred Transmission Frames Register */
-
-#define GMAC_DTF_DEFT_Pos 0 /**< \brief (GMAC_DTF) Deferred Transmission */
-#define GMAC_DTF_DEFT_Msk (_U_(0x3FFFF) << GMAC_DTF_DEFT_Pos)
-#define GMAC_DTF_DEFT(value) (GMAC_DTF_DEFT_Msk & ((value) << GMAC_DTF_DEFT_Pos))
-#define GMAC_DTF_MASK _U_(0x0003FFFF) /**< \brief (GMAC_DTF) MASK Register */
-
-/* -------- GMAC_CSE : (GMAC Offset: 0x14C) (R/ 32) Carrier Sense Errors Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CSR:10; /*!< bit: 0.. 9 Carrier Sense Error */
- uint32_t :22; /*!< bit: 10..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_CSE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_CSE_OFFSET 0x14C /**< \brief (GMAC_CSE offset) Carrier Sense Errors Register */
-#define GMAC_CSE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_CSE reset_value) Carrier Sense Errors Register */
-
-#define GMAC_CSE_CSR_Pos 0 /**< \brief (GMAC_CSE) Carrier Sense Error */
-#define GMAC_CSE_CSR_Msk (_U_(0x3FF) << GMAC_CSE_CSR_Pos)
-#define GMAC_CSE_CSR(value) (GMAC_CSE_CSR_Msk & ((value) << GMAC_CSE_CSR_Pos))
-#define GMAC_CSE_MASK _U_(0x000003FF) /**< \brief (GMAC_CSE) MASK Register */
-
-/* -------- GMAC_ORLO : (GMAC Offset: 0x150) (R/ 32) Octets Received [31:0] Received -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RXO:32; /*!< bit: 0..31 Received Octets */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_ORLO_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_ORLO_OFFSET 0x150 /**< \brief (GMAC_ORLO offset) Octets Received [31:0] Received */
-#define GMAC_ORLO_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_ORLO reset_value) Octets Received [31:0] Received */
-
-#define GMAC_ORLO_RXO_Pos 0 /**< \brief (GMAC_ORLO) Received Octets */
-#define GMAC_ORLO_RXO_Msk (_U_(0xFFFFFFFF) << GMAC_ORLO_RXO_Pos)
-#define GMAC_ORLO_RXO(value) (GMAC_ORLO_RXO_Msk & ((value) << GMAC_ORLO_RXO_Pos))
-#define GMAC_ORLO_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_ORLO) MASK Register */
-
-/* -------- GMAC_ORHI : (GMAC Offset: 0x154) (R/ 32) Octets Received [47:32] Received -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RXO:16; /*!< bit: 0..15 Received Octets */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_ORHI_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_ORHI_OFFSET 0x154 /**< \brief (GMAC_ORHI offset) Octets Received [47:32] Received */
-#define GMAC_ORHI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_ORHI reset_value) Octets Received [47:32] Received */
-
-#define GMAC_ORHI_RXO_Pos 0 /**< \brief (GMAC_ORHI) Received Octets */
-#define GMAC_ORHI_RXO_Msk (_U_(0xFFFF) << GMAC_ORHI_RXO_Pos)
-#define GMAC_ORHI_RXO(value) (GMAC_ORHI_RXO_Msk & ((value) << GMAC_ORHI_RXO_Pos))
-#define GMAC_ORHI_MASK _U_(0x0000FFFF) /**< \brief (GMAC_ORHI) MASK Register */
-
-/* -------- GMAC_FR : (GMAC Offset: 0x158) (R/ 32) Frames Received Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t FRX:32; /*!< bit: 0..31 Frames Received without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_FR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_FR_OFFSET 0x158 /**< \brief (GMAC_FR offset) Frames Received Register */
-#define GMAC_FR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_FR reset_value) Frames Received Register */
-
-#define GMAC_FR_FRX_Pos 0 /**< \brief (GMAC_FR) Frames Received without Error */
-#define GMAC_FR_FRX_Msk (_U_(0xFFFFFFFF) << GMAC_FR_FRX_Pos)
-#define GMAC_FR_FRX(value) (GMAC_FR_FRX_Msk & ((value) << GMAC_FR_FRX_Pos))
-#define GMAC_FR_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_FR) MASK Register */
-
-/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) (R/ 32) Broadcast Frames Received Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t BFRX:32; /*!< bit: 0..31 Broadcast Frames Received without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_BCFR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_BCFR_OFFSET 0x15C /**< \brief (GMAC_BCFR offset) Broadcast Frames Received Register */
-#define GMAC_BCFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_BCFR reset_value) Broadcast Frames Received Register */
-
-#define GMAC_BCFR_BFRX_Pos 0 /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */
-#define GMAC_BCFR_BFRX_Msk (_U_(0xFFFFFFFF) << GMAC_BCFR_BFRX_Pos)
-#define GMAC_BCFR_BFRX(value) (GMAC_BCFR_BFRX_Msk & ((value) << GMAC_BCFR_BFRX_Pos))
-#define GMAC_BCFR_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_BCFR) MASK Register */
-
-/* -------- GMAC_MFR : (GMAC Offset: 0x160) (R/ 32) Multicast Frames Received Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t MFRX:32; /*!< bit: 0..31 Multicast Frames Received without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_MFR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_MFR_OFFSET 0x160 /**< \brief (GMAC_MFR offset) Multicast Frames Received Register */
-#define GMAC_MFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_MFR reset_value) Multicast Frames Received Register */
-
-#define GMAC_MFR_MFRX_Pos 0 /**< \brief (GMAC_MFR) Multicast Frames Received without Error */
-#define GMAC_MFR_MFRX_Msk (_U_(0xFFFFFFFF) << GMAC_MFR_MFRX_Pos)
-#define GMAC_MFR_MFRX(value) (GMAC_MFR_MFRX_Msk & ((value) << GMAC_MFR_MFRX_Pos))
-#define GMAC_MFR_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_MFR) MASK Register */
-
-/* -------- GMAC_PFR : (GMAC Offset: 0x164) (R/ 32) Pause Frames Received Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t PFRX:16; /*!< bit: 0..15 Pause Frames Received Register */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_PFR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_PFR_OFFSET 0x164 /**< \brief (GMAC_PFR offset) Pause Frames Received Register */
-#define GMAC_PFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PFR reset_value) Pause Frames Received Register */
-
-#define GMAC_PFR_PFRX_Pos 0 /**< \brief (GMAC_PFR) Pause Frames Received Register */
-#define GMAC_PFR_PFRX_Msk (_U_(0xFFFF) << GMAC_PFR_PFRX_Pos)
-#define GMAC_PFR_PFRX(value) (GMAC_PFR_PFRX_Msk & ((value) << GMAC_PFR_PFRX_Pos))
-#define GMAC_PFR_MASK _U_(0x0000FFFF) /**< \brief (GMAC_PFR) MASK Register */
-
-/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) (R/ 32) 64 Byte Frames Received Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t NFRX:32; /*!< bit: 0..31 64 Byte Frames Received without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_BFR64_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_BFR64_OFFSET 0x168 /**< \brief (GMAC_BFR64 offset) 64 Byte Frames Received Register */
-#define GMAC_BFR64_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_BFR64 reset_value) 64 Byte Frames Received Register */
-
-#define GMAC_BFR64_NFRX_Pos 0 /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */
-#define GMAC_BFR64_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_BFR64_NFRX_Pos)
-#define GMAC_BFR64_NFRX(value) (GMAC_BFR64_NFRX_Msk & ((value) << GMAC_BFR64_NFRX_Pos))
-#define GMAC_BFR64_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_BFR64) MASK Register */
-
-/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) (R/ 32) 65 to 127 Byte Frames Received Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t NFRX:32; /*!< bit: 0..31 65 to 127 Byte Frames Received without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TBFR127_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TBFR127_OFFSET 0x16C /**< \brief (GMAC_TBFR127 offset) 65 to 127 Byte Frames Received Register */
-#define GMAC_TBFR127_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR127 reset_value) 65 to 127 Byte Frames Received Register */
-
-#define GMAC_TBFR127_NFRX_Pos 0 /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */
-#define GMAC_TBFR127_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR127_NFRX_Pos)
-#define GMAC_TBFR127_NFRX(value) (GMAC_TBFR127_NFRX_Msk & ((value) << GMAC_TBFR127_NFRX_Pos))
-#define GMAC_TBFR127_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR127) MASK Register */
-
-/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) (R/ 32) 128 to 255 Byte Frames Received Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t NFRX:32; /*!< bit: 0..31 128 to 255 Byte Frames Received without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TBFR255_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TBFR255_OFFSET 0x170 /**< \brief (GMAC_TBFR255 offset) 128 to 255 Byte Frames Received Register */
-#define GMAC_TBFR255_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR255 reset_value) 128 to 255 Byte Frames Received Register */
-
-#define GMAC_TBFR255_NFRX_Pos 0 /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */
-#define GMAC_TBFR255_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR255_NFRX_Pos)
-#define GMAC_TBFR255_NFRX(value) (GMAC_TBFR255_NFRX_Msk & ((value) << GMAC_TBFR255_NFRX_Pos))
-#define GMAC_TBFR255_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR255) MASK Register */
-
-/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) (R/ 32) 256 to 511Byte Frames Received Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t NFRX:32; /*!< bit: 0..31 256 to 511 Byte Frames Received without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TBFR511_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TBFR511_OFFSET 0x174 /**< \brief (GMAC_TBFR511 offset) 256 to 511Byte Frames Received Register */
-#define GMAC_TBFR511_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR511 reset_value) 256 to 511Byte Frames Received Register */
-
-#define GMAC_TBFR511_NFRX_Pos 0 /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */
-#define GMAC_TBFR511_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR511_NFRX_Pos)
-#define GMAC_TBFR511_NFRX(value) (GMAC_TBFR511_NFRX_Msk & ((value) << GMAC_TBFR511_NFRX_Pos))
-#define GMAC_TBFR511_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR511) MASK Register */
-
-/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) (R/ 32) 512 to 1023 Byte Frames Received Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t NFRX:32; /*!< bit: 0..31 512 to 1023 Byte Frames Received without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TBFR1023_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TBFR1023_OFFSET 0x178 /**< \brief (GMAC_TBFR1023 offset) 512 to 1023 Byte Frames Received Register */
-#define GMAC_TBFR1023_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR1023 reset_value) 512 to 1023 Byte Frames Received Register */
-
-#define GMAC_TBFR1023_NFRX_Pos 0 /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */
-#define GMAC_TBFR1023_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR1023_NFRX_Pos)
-#define GMAC_TBFR1023_NFRX(value) (GMAC_TBFR1023_NFRX_Msk & ((value) << GMAC_TBFR1023_NFRX_Pos))
-#define GMAC_TBFR1023_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR1023) MASK Register */
-
-/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) (R/ 32) 1024 to 1518 Byte Frames Received Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t NFRX:32; /*!< bit: 0..31 1024 to 1518 Byte Frames Received without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TBFR1518_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TBFR1518_OFFSET 0x17C /**< \brief (GMAC_TBFR1518 offset) 1024 to 1518 Byte Frames Received Register */
-#define GMAC_TBFR1518_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR1518 reset_value) 1024 to 1518 Byte Frames Received Register */
-
-#define GMAC_TBFR1518_NFRX_Pos 0 /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */
-#define GMAC_TBFR1518_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR1518_NFRX_Pos)
-#define GMAC_TBFR1518_NFRX(value) (GMAC_TBFR1518_NFRX_Msk & ((value) << GMAC_TBFR1518_NFRX_Pos))
-#define GMAC_TBFR1518_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR1518) MASK Register */
-
-/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) (R/ 32) 1519 to Maximum Byte Frames Received Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t NFRX:32; /*!< bit: 0..31 1519 to Maximum Byte Frames Received without Error */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TMXBFR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TMXBFR_OFFSET 0x180 /**< \brief (GMAC_TMXBFR offset) 1519 to Maximum Byte Frames Received Register */
-#define GMAC_TMXBFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TMXBFR reset_value) 1519 to Maximum Byte Frames Received Register */
-
-#define GMAC_TMXBFR_NFRX_Pos 0 /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */
-#define GMAC_TMXBFR_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TMXBFR_NFRX_Pos)
-#define GMAC_TMXBFR_NFRX(value) (GMAC_TMXBFR_NFRX_Msk & ((value) << GMAC_TMXBFR_NFRX_Pos))
-#define GMAC_TMXBFR_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TMXBFR) MASK Register */
-
-/* -------- GMAC_UFR : (GMAC Offset: 0x184) (R/ 32) Undersize Frames Received Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t UFRX:10; /*!< bit: 0.. 9 Undersize Frames Received */
- uint32_t :22; /*!< bit: 10..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_UFR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_UFR_OFFSET 0x184 /**< \brief (GMAC_UFR offset) Undersize Frames Received Register */
-#define GMAC_UFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_UFR reset_value) Undersize Frames Received Register */
-
-#define GMAC_UFR_UFRX_Pos 0 /**< \brief (GMAC_UFR) Undersize Frames Received */
-#define GMAC_UFR_UFRX_Msk (_U_(0x3FF) << GMAC_UFR_UFRX_Pos)
-#define GMAC_UFR_UFRX(value) (GMAC_UFR_UFRX_Msk & ((value) << GMAC_UFR_UFRX_Pos))
-#define GMAC_UFR_MASK _U_(0x000003FF) /**< \brief (GMAC_UFR) MASK Register */
-
-/* -------- GMAC_OFR : (GMAC Offset: 0x188) (R/ 32) Oversize Frames Received Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t OFRX:10; /*!< bit: 0.. 9 Oversized Frames Received */
- uint32_t :22; /*!< bit: 10..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_OFR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_OFR_OFFSET 0x188 /**< \brief (GMAC_OFR offset) Oversize Frames Received Register */
-#define GMAC_OFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_OFR reset_value) Oversize Frames Received Register */
-
-#define GMAC_OFR_OFRX_Pos 0 /**< \brief (GMAC_OFR) Oversized Frames Received */
-#define GMAC_OFR_OFRX_Msk (_U_(0x3FF) << GMAC_OFR_OFRX_Pos)
-#define GMAC_OFR_OFRX(value) (GMAC_OFR_OFRX_Msk & ((value) << GMAC_OFR_OFRX_Pos))
-#define GMAC_OFR_MASK _U_(0x000003FF) /**< \brief (GMAC_OFR) MASK Register */
-
-/* -------- GMAC_JR : (GMAC Offset: 0x18C) (R/ 32) Jabbers Received Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t JRX:10; /*!< bit: 0.. 9 Jabbers Received */
- uint32_t :22; /*!< bit: 10..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_JR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_JR_OFFSET 0x18C /**< \brief (GMAC_JR offset) Jabbers Received Register */
-#define GMAC_JR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_JR reset_value) Jabbers Received Register */
-
-#define GMAC_JR_JRX_Pos 0 /**< \brief (GMAC_JR) Jabbers Received */
-#define GMAC_JR_JRX_Msk (_U_(0x3FF) << GMAC_JR_JRX_Pos)
-#define GMAC_JR_JRX(value) (GMAC_JR_JRX_Msk & ((value) << GMAC_JR_JRX_Pos))
-#define GMAC_JR_MASK _U_(0x000003FF) /**< \brief (GMAC_JR) MASK Register */
-
-/* -------- GMAC_FCSE : (GMAC Offset: 0x190) (R/ 32) Frame Check Sequence Errors Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t FCKR:10; /*!< bit: 0.. 9 Frame Check Sequence Errors */
- uint32_t :22; /*!< bit: 10..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_FCSE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_FCSE_OFFSET 0x190 /**< \brief (GMAC_FCSE offset) Frame Check Sequence Errors Register */
-#define GMAC_FCSE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_FCSE reset_value) Frame Check Sequence Errors Register */
-
-#define GMAC_FCSE_FCKR_Pos 0 /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */
-#define GMAC_FCSE_FCKR_Msk (_U_(0x3FF) << GMAC_FCSE_FCKR_Pos)
-#define GMAC_FCSE_FCKR(value) (GMAC_FCSE_FCKR_Msk & ((value) << GMAC_FCSE_FCKR_Pos))
-#define GMAC_FCSE_MASK _U_(0x000003FF) /**< \brief (GMAC_FCSE) MASK Register */
-
-/* -------- GMAC_LFFE : (GMAC Offset: 0x194) (R/ 32) Length Field Frame Errors Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t LFER:10; /*!< bit: 0.. 9 Length Field Frame Errors */
- uint32_t :22; /*!< bit: 10..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_LFFE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_LFFE_OFFSET 0x194 /**< \brief (GMAC_LFFE offset) Length Field Frame Errors Register */
-#define GMAC_LFFE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_LFFE reset_value) Length Field Frame Errors Register */
-
-#define GMAC_LFFE_LFER_Pos 0 /**< \brief (GMAC_LFFE) Length Field Frame Errors */
-#define GMAC_LFFE_LFER_Msk (_U_(0x3FF) << GMAC_LFFE_LFER_Pos)
-#define GMAC_LFFE_LFER(value) (GMAC_LFFE_LFER_Msk & ((value) << GMAC_LFFE_LFER_Pos))
-#define GMAC_LFFE_MASK _U_(0x000003FF) /**< \brief (GMAC_LFFE) MASK Register */
-
-/* -------- GMAC_RSE : (GMAC Offset: 0x198) (R/ 32) Receive Symbol Errors Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RXSE:10; /*!< bit: 0.. 9 Receive Symbol Errors */
- uint32_t :22; /*!< bit: 10..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_RSE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_RSE_OFFSET 0x198 /**< \brief (GMAC_RSE offset) Receive Symbol Errors Register */
-#define GMAC_RSE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RSE reset_value) Receive Symbol Errors Register */
-
-#define GMAC_RSE_RXSE_Pos 0 /**< \brief (GMAC_RSE) Receive Symbol Errors */
-#define GMAC_RSE_RXSE_Msk (_U_(0x3FF) << GMAC_RSE_RXSE_Pos)
-#define GMAC_RSE_RXSE(value) (GMAC_RSE_RXSE_Msk & ((value) << GMAC_RSE_RXSE_Pos))
-#define GMAC_RSE_MASK _U_(0x000003FF) /**< \brief (GMAC_RSE) MASK Register */
-
-/* -------- GMAC_AE : (GMAC Offset: 0x19C) (R/ 32) Alignment Errors Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t AER:10; /*!< bit: 0.. 9 Alignment Errors */
- uint32_t :22; /*!< bit: 10..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_AE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_AE_OFFSET 0x19C /**< \brief (GMAC_AE offset) Alignment Errors Register */
-#define GMAC_AE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_AE reset_value) Alignment Errors Register */
-
-#define GMAC_AE_AER_Pos 0 /**< \brief (GMAC_AE) Alignment Errors */
-#define GMAC_AE_AER_Msk (_U_(0x3FF) << GMAC_AE_AER_Pos)
-#define GMAC_AE_AER(value) (GMAC_AE_AER_Msk & ((value) << GMAC_AE_AER_Pos))
-#define GMAC_AE_MASK _U_(0x000003FF) /**< \brief (GMAC_AE) MASK Register */
-
-/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) (R/ 32) Receive Resource Errors Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RXRER:18; /*!< bit: 0..17 Receive Resource Errors */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_RRE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_RRE_OFFSET 0x1A0 /**< \brief (GMAC_RRE offset) Receive Resource Errors Register */
-#define GMAC_RRE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RRE reset_value) Receive Resource Errors Register */
-
-#define GMAC_RRE_RXRER_Pos 0 /**< \brief (GMAC_RRE) Receive Resource Errors */
-#define GMAC_RRE_RXRER_Msk (_U_(0x3FFFF) << GMAC_RRE_RXRER_Pos)
-#define GMAC_RRE_RXRER(value) (GMAC_RRE_RXRER_Msk & ((value) << GMAC_RRE_RXRER_Pos))
-#define GMAC_RRE_MASK _U_(0x0003FFFF) /**< \brief (GMAC_RRE) MASK Register */
-
-/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) (R/ 32) Receive Overrun Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RXOVR:10; /*!< bit: 0.. 9 Receive Overruns */
- uint32_t :22; /*!< bit: 10..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_ROE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_ROE_OFFSET 0x1A4 /**< \brief (GMAC_ROE offset) Receive Overrun Register */
-#define GMAC_ROE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_ROE reset_value) Receive Overrun Register */
-
-#define GMAC_ROE_RXOVR_Pos 0 /**< \brief (GMAC_ROE) Receive Overruns */
-#define GMAC_ROE_RXOVR_Msk (_U_(0x3FF) << GMAC_ROE_RXOVR_Pos)
-#define GMAC_ROE_RXOVR(value) (GMAC_ROE_RXOVR_Msk & ((value) << GMAC_ROE_RXOVR_Pos))
-#define GMAC_ROE_MASK _U_(0x000003FF) /**< \brief (GMAC_ROE) MASK Register */
-
-/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) (R/ 32) IP Header Checksum Errors Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t HCKER:8; /*!< bit: 0.. 7 IP Header Checksum Errors */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_IHCE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_IHCE_OFFSET 0x1A8 /**< \brief (GMAC_IHCE offset) IP Header Checksum Errors Register */
-#define GMAC_IHCE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_IHCE reset_value) IP Header Checksum Errors Register */
-
-#define GMAC_IHCE_HCKER_Pos 0 /**< \brief (GMAC_IHCE) IP Header Checksum Errors */
-#define GMAC_IHCE_HCKER_Msk (_U_(0xFF) << GMAC_IHCE_HCKER_Pos)
-#define GMAC_IHCE_HCKER(value) (GMAC_IHCE_HCKER_Msk & ((value) << GMAC_IHCE_HCKER_Pos))
-#define GMAC_IHCE_MASK _U_(0x000000FF) /**< \brief (GMAC_IHCE) MASK Register */
-
-/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) (R/ 32) TCP Checksum Errors Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TCKER:8; /*!< bit: 0.. 7 TCP Checksum Errors */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TCE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TCE_OFFSET 0x1AC /**< \brief (GMAC_TCE offset) TCP Checksum Errors Register */
-#define GMAC_TCE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TCE reset_value) TCP Checksum Errors Register */
-
-#define GMAC_TCE_TCKER_Pos 0 /**< \brief (GMAC_TCE) TCP Checksum Errors */
-#define GMAC_TCE_TCKER_Msk (_U_(0xFF) << GMAC_TCE_TCKER_Pos)
-#define GMAC_TCE_TCKER(value) (GMAC_TCE_TCKER_Msk & ((value) << GMAC_TCE_TCKER_Pos))
-#define GMAC_TCE_MASK _U_(0x000000FF) /**< \brief (GMAC_TCE) MASK Register */
-
-/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) (R/ 32) UDP Checksum Errors Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t UCKER:8; /*!< bit: 0.. 7 UDP Checksum Errors */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_UCE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_UCE_OFFSET 0x1B0 /**< \brief (GMAC_UCE offset) UDP Checksum Errors Register */
-#define GMAC_UCE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_UCE reset_value) UDP Checksum Errors Register */
-
-#define GMAC_UCE_UCKER_Pos 0 /**< \brief (GMAC_UCE) UDP Checksum Errors */
-#define GMAC_UCE_UCKER_Msk (_U_(0xFF) << GMAC_UCE_UCKER_Pos)
-#define GMAC_UCE_UCKER(value) (GMAC_UCE_UCKER_Msk & ((value) << GMAC_UCE_UCKER_Pos))
-#define GMAC_UCE_MASK _U_(0x000000FF) /**< \brief (GMAC_UCE) MASK Register */
-
-/* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) (R/W 32) 1588 Timer Increment [15:0] Sub-Nanoseconds Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t LSBTIR:16; /*!< bit: 0..15 Lower Significant Bits of Timer Increment */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TISUBN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TISUBN_OFFSET 0x1BC /**< \brief (GMAC_TISUBN offset) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
-#define GMAC_TISUBN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TISUBN reset_value) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
-
-#define GMAC_TISUBN_LSBTIR_Pos 0 /**< \brief (GMAC_TISUBN) Lower Significant Bits of Timer Increment */
-#define GMAC_TISUBN_LSBTIR_Msk (_U_(0xFFFF) << GMAC_TISUBN_LSBTIR_Pos)
-#define GMAC_TISUBN_LSBTIR(value) (GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos))
-#define GMAC_TISUBN_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TISUBN) MASK Register */
-
-/* -------- GMAC_TSH : (GMAC Offset: 0x1C0) (R/W 32) 1588 Timer Seconds High [15:0] Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TCS:16; /*!< bit: 0..15 Timer Count in Seconds */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TSH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TSH_OFFSET 0x1C0 /**< \brief (GMAC_TSH offset) 1588 Timer Seconds High [15:0] Register */
-#define GMAC_TSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSH reset_value) 1588 Timer Seconds High [15:0] Register */
-
-#define GMAC_TSH_TCS_Pos 0 /**< \brief (GMAC_TSH) Timer Count in Seconds */
-#define GMAC_TSH_TCS_Msk (_U_(0xFFFF) << GMAC_TSH_TCS_Pos)
-#define GMAC_TSH_TCS(value) (GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos))
-#define GMAC_TSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TSH) MASK Register */
-
-/* -------- GMAC_TSSSL : (GMAC Offset: 0x1C8) (R/W 32) 1588 Timer Sync Strobe Seconds [31:0] Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t VTS:32; /*!< bit: 0..31 Value of Timer Seconds Register Capture */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TSSSL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TSSSL_OFFSET 0x1C8 /**< \brief (GMAC_TSSSL offset) 1588 Timer Sync Strobe Seconds [31:0] Register */
-#define GMAC_TSSSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSSSL reset_value) 1588 Timer Sync Strobe Seconds [31:0] Register */
-
-#define GMAC_TSSSL_VTS_Pos 0 /**< \brief (GMAC_TSSSL) Value of Timer Seconds Register Capture */
-#define GMAC_TSSSL_VTS_Msk (_U_(0xFFFFFFFF) << GMAC_TSSSL_VTS_Pos)
-#define GMAC_TSSSL_VTS(value) (GMAC_TSSSL_VTS_Msk & ((value) << GMAC_TSSSL_VTS_Pos))
-#define GMAC_TSSSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TSSSL) MASK Register */
-
-/* -------- GMAC_TSSN : (GMAC Offset: 0x1CC) (R/W 32) 1588 Timer Sync Strobe Nanoseconds Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t VTN:30; /*!< bit: 0..29 Value Timer Nanoseconds Register Capture */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TSSN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TSSN_OFFSET 0x1CC /**< \brief (GMAC_TSSN offset) 1588 Timer Sync Strobe Nanoseconds Register */
-#define GMAC_TSSN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSSN reset_value) 1588 Timer Sync Strobe Nanoseconds Register */
-
-#define GMAC_TSSN_VTN_Pos 0 /**< \brief (GMAC_TSSN) Value Timer Nanoseconds Register Capture */
-#define GMAC_TSSN_VTN_Msk (_U_(0x3FFFFFFF) << GMAC_TSSN_VTN_Pos)
-#define GMAC_TSSN_VTN(value) (GMAC_TSSN_VTN_Msk & ((value) << GMAC_TSSN_VTN_Pos))
-#define GMAC_TSSN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_TSSN) MASK Register */
-
-/* -------- GMAC_TSL : (GMAC Offset: 0x1D0) (R/W 32) 1588 Timer Seconds [31:0] Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TCS:32; /*!< bit: 0..31 Timer Count in Seconds */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TSL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TSL_OFFSET 0x1D0 /**< \brief (GMAC_TSL offset) 1588 Timer Seconds [31:0] Register */
-#define GMAC_TSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSL reset_value) 1588 Timer Seconds [31:0] Register */
-
-#define GMAC_TSL_TCS_Pos 0 /**< \brief (GMAC_TSL) Timer Count in Seconds */
-#define GMAC_TSL_TCS_Msk (_U_(0xFFFFFFFF) << GMAC_TSL_TCS_Pos)
-#define GMAC_TSL_TCS(value) (GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos))
-#define GMAC_TSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TSL) MASK Register */
-
-/* -------- GMAC_TN : (GMAC Offset: 0x1D4) (R/W 32) 1588 Timer Nanoseconds Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TNS:30; /*!< bit: 0..29 Timer Count in Nanoseconds */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TN_OFFSET 0x1D4 /**< \brief (GMAC_TN offset) 1588 Timer Nanoseconds Register */
-#define GMAC_TN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TN reset_value) 1588 Timer Nanoseconds Register */
-
-#define GMAC_TN_TNS_Pos 0 /**< \brief (GMAC_TN) Timer Count in Nanoseconds */
-#define GMAC_TN_TNS_Msk (_U_(0x3FFFFFFF) << GMAC_TN_TNS_Pos)
-#define GMAC_TN_TNS(value) (GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))
-#define GMAC_TN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_TN) MASK Register */
-
-/* -------- GMAC_TA : (GMAC Offset: 0x1D8) ( /W 32) 1588 Timer Adjust Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ITDT:30; /*!< bit: 0..29 Increment/Decrement */
- uint32_t :1; /*!< bit: 30 Reserved */
- uint32_t ADJ:1; /*!< bit: 31 Adjust 1588 Timer */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TA_OFFSET 0x1D8 /**< \brief (GMAC_TA offset) 1588 Timer Adjust Register */
-#define GMAC_TA_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TA reset_value) 1588 Timer Adjust Register */
-
-#define GMAC_TA_ITDT_Pos 0 /**< \brief (GMAC_TA) Increment/Decrement */
-#define GMAC_TA_ITDT_Msk (_U_(0x3FFFFFFF) << GMAC_TA_ITDT_Pos)
-#define GMAC_TA_ITDT(value) (GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))
-#define GMAC_TA_ADJ_Pos 31 /**< \brief (GMAC_TA) Adjust 1588 Timer */
-#define GMAC_TA_ADJ (_U_(0x1) << GMAC_TA_ADJ_Pos)
-#define GMAC_TA_MASK _U_(0xBFFFFFFF) /**< \brief (GMAC_TA) MASK Register */
-
-/* -------- GMAC_TI : (GMAC Offset: 0x1DC) (R/W 32) 1588 Timer Increment Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CNS:8; /*!< bit: 0.. 7 Count Nanoseconds */
- uint32_t ACNS:8; /*!< bit: 8..15 Alternative Count Nanoseconds */
- uint32_t NIT:8; /*!< bit: 16..23 Number of Increments */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TI_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TI_OFFSET 0x1DC /**< \brief (GMAC_TI offset) 1588 Timer Increment Register */
-#define GMAC_TI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TI reset_value) 1588 Timer Increment Register */
-
-#define GMAC_TI_CNS_Pos 0 /**< \brief (GMAC_TI) Count Nanoseconds */
-#define GMAC_TI_CNS_Msk (_U_(0xFF) << GMAC_TI_CNS_Pos)
-#define GMAC_TI_CNS(value) (GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))
-#define GMAC_TI_ACNS_Pos 8 /**< \brief (GMAC_TI) Alternative Count Nanoseconds */
-#define GMAC_TI_ACNS_Msk (_U_(0xFF) << GMAC_TI_ACNS_Pos)
-#define GMAC_TI_ACNS(value) (GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))
-#define GMAC_TI_NIT_Pos 16 /**< \brief (GMAC_TI) Number of Increments */
-#define GMAC_TI_NIT_Msk (_U_(0xFF) << GMAC_TI_NIT_Pos)
-#define GMAC_TI_NIT(value) (GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))
-#define GMAC_TI_MASK _U_(0x00FFFFFF) /**< \brief (GMAC_TI) MASK Register */
-
-/* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) (R/ 32) PTP Event Frame Transmitted Seconds Low Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RUD:32; /*!< bit: 0..31 Register Update */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_EFTSL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_EFTSL_OFFSET 0x1E0 /**< \brief (GMAC_EFTSL offset) PTP Event Frame Transmitted Seconds Low Register */
-#define GMAC_EFTSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFTSL reset_value) PTP Event Frame Transmitted Seconds Low Register */
-
-#define GMAC_EFTSL_RUD_Pos 0 /**< \brief (GMAC_EFTSL) Register Update */
-#define GMAC_EFTSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_EFTSL_RUD_Pos)
-#define GMAC_EFTSL_RUD(value) (GMAC_EFTSL_RUD_Msk & ((value) << GMAC_EFTSL_RUD_Pos))
-#define GMAC_EFTSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_EFTSL) MASK Register */
-
-/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) (R/ 32) PTP Event Frame Transmitted Nanoseconds -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RUD:30; /*!< bit: 0..29 Register Update */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_EFTN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_EFTN_OFFSET 0x1E4 /**< \brief (GMAC_EFTN offset) PTP Event Frame Transmitted Nanoseconds */
-#define GMAC_EFTN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFTN reset_value) PTP Event Frame Transmitted Nanoseconds */
-
-#define GMAC_EFTN_RUD_Pos 0 /**< \brief (GMAC_EFTN) Register Update */
-#define GMAC_EFTN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_EFTN_RUD_Pos)
-#define GMAC_EFTN_RUD(value) (GMAC_EFTN_RUD_Msk & ((value) << GMAC_EFTN_RUD_Pos))
-#define GMAC_EFTN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_EFTN) MASK Register */
-
-/* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) (R/ 32) PTP Event Frame Received Seconds Low Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RUD:32; /*!< bit: 0..31 Register Update */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_EFRSL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_EFRSL_OFFSET 0x1E8 /**< \brief (GMAC_EFRSL offset) PTP Event Frame Received Seconds Low Register */
-#define GMAC_EFRSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFRSL reset_value) PTP Event Frame Received Seconds Low Register */
-
-#define GMAC_EFRSL_RUD_Pos 0 /**< \brief (GMAC_EFRSL) Register Update */
-#define GMAC_EFRSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_EFRSL_RUD_Pos)
-#define GMAC_EFRSL_RUD(value) (GMAC_EFRSL_RUD_Msk & ((value) << GMAC_EFRSL_RUD_Pos))
-#define GMAC_EFRSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_EFRSL) MASK Register */
-
-/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) (R/ 32) PTP Event Frame Received Nanoseconds -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RUD:30; /*!< bit: 0..29 Register Update */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_EFRN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_EFRN_OFFSET 0x1EC /**< \brief (GMAC_EFRN offset) PTP Event Frame Received Nanoseconds */
-#define GMAC_EFRN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFRN reset_value) PTP Event Frame Received Nanoseconds */
-
-#define GMAC_EFRN_RUD_Pos 0 /**< \brief (GMAC_EFRN) Register Update */
-#define GMAC_EFRN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_EFRN_RUD_Pos)
-#define GMAC_EFRN_RUD(value) (GMAC_EFRN_RUD_Msk & ((value) << GMAC_EFRN_RUD_Pos))
-#define GMAC_EFRN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_EFRN) MASK Register */
-
-/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) (R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RUD:32; /*!< bit: 0..31 Register Update */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_PEFTSL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_PEFTSL_OFFSET 0x1F0 /**< \brief (GMAC_PEFTSL offset) PTP Peer Event Frame Transmitted Seconds Low Register */
-#define GMAC_PEFTSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFTSL reset_value) PTP Peer Event Frame Transmitted Seconds Low Register */
-
-#define GMAC_PEFTSL_RUD_Pos 0 /**< \brief (GMAC_PEFTSL) Register Update */
-#define GMAC_PEFTSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_PEFTSL_RUD_Pos)
-#define GMAC_PEFTSL_RUD(value) (GMAC_PEFTSL_RUD_Msk & ((value) << GMAC_PEFTSL_RUD_Pos))
-#define GMAC_PEFTSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_PEFTSL) MASK Register */
-
-/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) (R/ 32) PTP Peer Event Frame Transmitted Nanoseconds -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RUD:30; /*!< bit: 0..29 Register Update */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_PEFTN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_PEFTN_OFFSET 0x1F4 /**< \brief (GMAC_PEFTN offset) PTP Peer Event Frame Transmitted Nanoseconds */
-#define GMAC_PEFTN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFTN reset_value) PTP Peer Event Frame Transmitted Nanoseconds */
-
-#define GMAC_PEFTN_RUD_Pos 0 /**< \brief (GMAC_PEFTN) Register Update */
-#define GMAC_PEFTN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_PEFTN_RUD_Pos)
-#define GMAC_PEFTN_RUD(value) (GMAC_PEFTN_RUD_Msk & ((value) << GMAC_PEFTN_RUD_Pos))
-#define GMAC_PEFTN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_PEFTN) MASK Register */
-
-/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) (R/ 32) PTP Peer Event Frame Received Seconds Low Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RUD:32; /*!< bit: 0..31 Register Update */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_PEFRSL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_PEFRSL_OFFSET 0x1F8 /**< \brief (GMAC_PEFRSL offset) PTP Peer Event Frame Received Seconds Low Register */
-#define GMAC_PEFRSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFRSL reset_value) PTP Peer Event Frame Received Seconds Low Register */
-
-#define GMAC_PEFRSL_RUD_Pos 0 /**< \brief (GMAC_PEFRSL) Register Update */
-#define GMAC_PEFRSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_PEFRSL_RUD_Pos)
-#define GMAC_PEFRSL_RUD(value) (GMAC_PEFRSL_RUD_Msk & ((value) << GMAC_PEFRSL_RUD_Pos))
-#define GMAC_PEFRSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_PEFRSL) MASK Register */
-
-/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) (R/ 32) PTP Peer Event Frame Received Nanoseconds -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RUD:30; /*!< bit: 0..29 Register Update */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_PEFRN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_PEFRN_OFFSET 0x1FC /**< \brief (GMAC_PEFRN offset) PTP Peer Event Frame Received Nanoseconds */
-#define GMAC_PEFRN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFRN reset_value) PTP Peer Event Frame Received Nanoseconds */
-
-#define GMAC_PEFRN_RUD_Pos 0 /**< \brief (GMAC_PEFRN) Register Update */
-#define GMAC_PEFRN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_PEFRN_RUD_Pos)
-#define GMAC_PEFRN_RUD(value) (GMAC_PEFRN_RUD_Msk & ((value) << GMAC_PEFRN_RUD_Pos))
-#define GMAC_PEFRN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_PEFRN) MASK Register */
-
-/* -------- GMAC_RLPITR : (GMAC Offset: 0x270) (R/ 32) Receive LPI transition Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RLPITR:16; /*!< bit: 0..15 Count number of times transition from rx normal idle to low power idle */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_RLPITR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_RLPITR_OFFSET 0x270 /**< \brief (GMAC_RLPITR offset) Receive LPI transition Register */
-#define GMAC_RLPITR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RLPITR reset_value) Receive LPI transition Register */
-
-#define GMAC_RLPITR_RLPITR_Pos 0 /**< \brief (GMAC_RLPITR) Count number of times transition from rx normal idle to low power idle */
-#define GMAC_RLPITR_RLPITR_Msk (_U_(0xFFFF) << GMAC_RLPITR_RLPITR_Pos)
-#define GMAC_RLPITR_RLPITR(value) (GMAC_RLPITR_RLPITR_Msk & ((value) << GMAC_RLPITR_RLPITR_Pos))
-#define GMAC_RLPITR_MASK _U_(0x0000FFFF) /**< \brief (GMAC_RLPITR) MASK Register */
-
-/* -------- GMAC_RLPITI : (GMAC Offset: 0x274) (R/ 32) Receive LPI Time Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RLPITI:24; /*!< bit: 0..23 Increment once over 16 ahb clock when LPI indication bit 20 is set in rx mode */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_RLPITI_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_RLPITI_OFFSET 0x274 /**< \brief (GMAC_RLPITI offset) Receive LPI Time Register */
-#define GMAC_RLPITI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RLPITI reset_value) Receive LPI Time Register */
-
-#define GMAC_RLPITI_RLPITI_Pos 0 /**< \brief (GMAC_RLPITI) Increment once over 16 ahb clock when LPI indication bit 20 is set in rx mode */
-#define GMAC_RLPITI_RLPITI_Msk (_U_(0xFFFFFF) << GMAC_RLPITI_RLPITI_Pos)
-#define GMAC_RLPITI_RLPITI(value) (GMAC_RLPITI_RLPITI_Msk & ((value) << GMAC_RLPITI_RLPITI_Pos))
-#define GMAC_RLPITI_MASK _U_(0x00FFFFFF) /**< \brief (GMAC_RLPITI) MASK Register */
-
-/* -------- GMAC_TLPITR : (GMAC Offset: 0x278) (R/ 32) Receive LPI transition Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TLPITR:16; /*!< bit: 0..15 Count number of times enable LPI tx bit 20 goes from low to high */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TLPITR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TLPITR_OFFSET 0x278 /**< \brief (GMAC_TLPITR offset) Receive LPI transition Register */
-#define GMAC_TLPITR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TLPITR reset_value) Receive LPI transition Register */
-
-#define GMAC_TLPITR_TLPITR_Pos 0 /**< \brief (GMAC_TLPITR) Count number of times enable LPI tx bit 20 goes from low to high */
-#define GMAC_TLPITR_TLPITR_Msk (_U_(0xFFFF) << GMAC_TLPITR_TLPITR_Pos)
-#define GMAC_TLPITR_TLPITR(value) (GMAC_TLPITR_TLPITR_Msk & ((value) << GMAC_TLPITR_TLPITR_Pos))
-#define GMAC_TLPITR_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TLPITR) MASK Register */
-
-/* -------- GMAC_TLPITI : (GMAC Offset: 0x27C) (R/ 32) Receive LPI Time Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TLPITI:24; /*!< bit: 0..23 Increment once over 16 ahb clock when LPI indication bit 20 is set in tx mode */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} GMAC_TLPITI_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GMAC_TLPITI_OFFSET 0x27C /**< \brief (GMAC_TLPITI offset) Receive LPI Time Register */
-#define GMAC_TLPITI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TLPITI reset_value) Receive LPI Time Register */
-
-#define GMAC_TLPITI_TLPITI_Pos 0 /**< \brief (GMAC_TLPITI) Increment once over 16 ahb clock when LPI indication bit 20 is set in tx mode */
-#define GMAC_TLPITI_TLPITI_Msk (_U_(0xFFFFFF) << GMAC_TLPITI_TLPITI_Pos)
-#define GMAC_TLPITI_TLPITI(value) (GMAC_TLPITI_TLPITI_Msk & ((value) << GMAC_TLPITI_TLPITI_Pos))
-#define GMAC_TLPITI_MASK _U_(0x00FFFFFF) /**< \brief (GMAC_TLPITI) MASK Register */
-
-/** \brief GmacSa hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO GMAC_SAB_Type SAB; /**< \brief Offset: 0x000 (R/W 32) Specific Address Bottom [31:0] Register */
- __IO GMAC_SAT_Type SAT; /**< \brief Offset: 0x004 (R/W 32) Specific Address Top [47:32] Register */
-} GmacSa;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief GMAC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO GMAC_NCR_Type NCR; /**< \brief Offset: 0x000 (R/W 32) Network Control Register */
- __IO GMAC_NCFGR_Type NCFGR; /**< \brief Offset: 0x004 (R/W 32) Network Configuration Register */
- __I GMAC_NSR_Type NSR; /**< \brief Offset: 0x008 (R/ 32) Network Status Register */
- __IO GMAC_UR_Type UR; /**< \brief Offset: 0x00C (R/W 32) User Register */
- __IO GMAC_DCFGR_Type DCFGR; /**< \brief Offset: 0x010 (R/W 32) DMA Configuration Register */
- __IO GMAC_TSR_Type TSR; /**< \brief Offset: 0x014 (R/W 32) Transmit Status Register */
- __IO GMAC_RBQB_Type RBQB; /**< \brief Offset: 0x018 (R/W 32) Receive Buffer Queue Base Address */
- __IO GMAC_TBQB_Type TBQB; /**< \brief Offset: 0x01C (R/W 32) Transmit Buffer Queue Base Address */
- __IO GMAC_RSR_Type RSR; /**< \brief Offset: 0x020 (R/W 32) Receive Status Register */
- __IO GMAC_ISR_Type ISR; /**< \brief Offset: 0x024 (R/W 32) Interrupt Status Register */
- __O GMAC_IER_Type IER; /**< \brief Offset: 0x028 ( /W 32) Interrupt Enable Register */
- __O GMAC_IDR_Type IDR; /**< \brief Offset: 0x02C ( /W 32) Interrupt Disable Register */
- __I GMAC_IMR_Type IMR; /**< \brief Offset: 0x030 (R/ 32) Interrupt Mask Register */
- __IO GMAC_MAN_Type MAN; /**< \brief Offset: 0x034 (R/W 32) PHY Maintenance Register */
- __I GMAC_RPQ_Type RPQ; /**< \brief Offset: 0x038 (R/ 32) Received Pause Quantum Register */
- __IO GMAC_TPQ_Type TPQ; /**< \brief Offset: 0x03C (R/W 32) Transmit Pause Quantum Register */
- __IO GMAC_TPSF_Type TPSF; /**< \brief Offset: 0x040 (R/W 32) TX partial store and forward Register */
- __IO GMAC_RPSF_Type RPSF; /**< \brief Offset: 0x044 (R/W 32) RX partial store and forward Register */
- __IO GMAC_RJFML_Type RJFML; /**< \brief Offset: 0x048 (R/W 32) RX Jumbo Frame Max Length Register */
- RoReg8 Reserved1[0x34];
- __IO GMAC_HRB_Type HRB; /**< \brief Offset: 0x080 (R/W 32) Hash Register Bottom [31:0] */
- __IO GMAC_HRT_Type HRT; /**< \brief Offset: 0x084 (R/W 32) Hash Register Top [63:32] */
- GmacSa Sa[4]; /**< \brief Offset: 0x088 GmacSa groups */
- __IO GMAC_TIDM_Type TIDM[4]; /**< \brief Offset: 0x0A8 (R/W 32) Type ID Match Register */
- __IO GMAC_WOL_Type WOL; /**< \brief Offset: 0x0B8 (R/W 32) Wake on LAN */
- __IO GMAC_IPGS_Type IPGS; /**< \brief Offset: 0x0BC (R/W 32) IPG Stretch Register */
- __IO GMAC_SVLAN_Type SVLAN; /**< \brief Offset: 0x0C0 (R/W 32) Stacked VLAN Register */
- __IO GMAC_TPFCP_Type TPFCP; /**< \brief Offset: 0x0C4 (R/W 32) Transmit PFC Pause Register */
- __IO GMAC_SAMB1_Type SAMB1; /**< \brief Offset: 0x0C8 (R/W 32) Specific Address 1 Mask Bottom [31:0] Register */
- __IO GMAC_SAMT1_Type SAMT1; /**< \brief Offset: 0x0CC (R/W 32) Specific Address 1 Mask Top [47:32] Register */
- RoReg8 Reserved2[0xC];
- __IO GMAC_NSC_Type NSC; /**< \brief Offset: 0x0DC (R/W 32) Tsu timer comparison nanoseconds Register */
- __IO GMAC_SCL_Type SCL; /**< \brief Offset: 0x0E0 (R/W 32) Tsu timer second comparison Register */
- __IO GMAC_SCH_Type SCH; /**< \brief Offset: 0x0E4 (R/W 32) Tsu timer second comparison Register */
- __I GMAC_EFTSH_Type EFTSH; /**< \brief Offset: 0x0E8 (R/ 32) PTP Event Frame Transmitted Seconds High Register */
- __I GMAC_EFRSH_Type EFRSH; /**< \brief Offset: 0x0EC (R/ 32) PTP Event Frame Received Seconds High Register */
- __I GMAC_PEFTSH_Type PEFTSH; /**< \brief Offset: 0x0F0 (R/ 32) PTP Peer Event Frame Transmitted Seconds High Register */
- __I GMAC_PEFRSH_Type PEFRSH; /**< \brief Offset: 0x0F4 (R/ 32) PTP Peer Event Frame Received Seconds High Register */
- RoReg8 Reserved3[0x8];
- __I GMAC_OTLO_Type OTLO; /**< \brief Offset: 0x100 (R/ 32) Octets Transmitted [31:0] Register */
- __I GMAC_OTHI_Type OTHI; /**< \brief Offset: 0x104 (R/ 32) Octets Transmitted [47:32] Register */
- __I GMAC_FT_Type FT; /**< \brief Offset: 0x108 (R/ 32) Frames Transmitted Register */
- __I GMAC_BCFT_Type BCFT; /**< \brief Offset: 0x10C (R/ 32) Broadcast Frames Transmitted Register */
- __I GMAC_MFT_Type MFT; /**< \brief Offset: 0x110 (R/ 32) Multicast Frames Transmitted Register */
- __I GMAC_PFT_Type PFT; /**< \brief Offset: 0x114 (R/ 32) Pause Frames Transmitted Register */
- __I GMAC_BFT64_Type BFT64; /**< \brief Offset: 0x118 (R/ 32) 64 Byte Frames Transmitted Register */
- __I GMAC_TBFT127_Type TBFT127; /**< \brief Offset: 0x11C (R/ 32) 65 to 127 Byte Frames Transmitted Register */
- __I GMAC_TBFT255_Type TBFT255; /**< \brief Offset: 0x120 (R/ 32) 128 to 255 Byte Frames Transmitted Register */
- __I GMAC_TBFT511_Type TBFT511; /**< \brief Offset: 0x124 (R/ 32) 256 to 511 Byte Frames Transmitted Register */
- __I GMAC_TBFT1023_Type TBFT1023; /**< \brief Offset: 0x128 (R/ 32) 512 to 1023 Byte Frames Transmitted Register */
- __I GMAC_TBFT1518_Type TBFT1518; /**< \brief Offset: 0x12C (R/ 32) 1024 to 1518 Byte Frames Transmitted Register */
- __I GMAC_GTBFT1518_Type GTBFT1518; /**< \brief Offset: 0x130 (R/ 32) Greater Than 1518 Byte Frames Transmitted Register */
- __I GMAC_TUR_Type TUR; /**< \brief Offset: 0x134 (R/ 32) Transmit Underruns Register */
- __I GMAC_SCF_Type SCF; /**< \brief Offset: 0x138 (R/ 32) Single Collision Frames Register */
- __I GMAC_MCF_Type MCF; /**< \brief Offset: 0x13C (R/ 32) Multiple Collision Frames Register */
- __I GMAC_EC_Type EC; /**< \brief Offset: 0x140 (R/ 32) Excessive Collisions Register */
- __I GMAC_LC_Type LC; /**< \brief Offset: 0x144 (R/ 32) Late Collisions Register */
- __I GMAC_DTF_Type DTF; /**< \brief Offset: 0x148 (R/ 32) Deferred Transmission Frames Register */
- __I GMAC_CSE_Type CSE; /**< \brief Offset: 0x14C (R/ 32) Carrier Sense Errors Register */
- __I GMAC_ORLO_Type ORLO; /**< \brief Offset: 0x150 (R/ 32) Octets Received [31:0] Received */
- __I GMAC_ORHI_Type ORHI; /**< \brief Offset: 0x154 (R/ 32) Octets Received [47:32] Received */
- __I GMAC_FR_Type FR; /**< \brief Offset: 0x158 (R/ 32) Frames Received Register */
- __I GMAC_BCFR_Type BCFR; /**< \brief Offset: 0x15C (R/ 32) Broadcast Frames Received Register */
- __I GMAC_MFR_Type MFR; /**< \brief Offset: 0x160 (R/ 32) Multicast Frames Received Register */
- __I GMAC_PFR_Type PFR; /**< \brief Offset: 0x164 (R/ 32) Pause Frames Received Register */
- __I GMAC_BFR64_Type BFR64; /**< \brief Offset: 0x168 (R/ 32) 64 Byte Frames Received Register */
- __I GMAC_TBFR127_Type TBFR127; /**< \brief Offset: 0x16C (R/ 32) 65 to 127 Byte Frames Received Register */
- __I GMAC_TBFR255_Type TBFR255; /**< \brief Offset: 0x170 (R/ 32) 128 to 255 Byte Frames Received Register */
- __I GMAC_TBFR511_Type TBFR511; /**< \brief Offset: 0x174 (R/ 32) 256 to 511Byte Frames Received Register */
- __I GMAC_TBFR1023_Type TBFR1023; /**< \brief Offset: 0x178 (R/ 32) 512 to 1023 Byte Frames Received Register */
- __I GMAC_TBFR1518_Type TBFR1518; /**< \brief Offset: 0x17C (R/ 32) 1024 to 1518 Byte Frames Received Register */
- __I GMAC_TMXBFR_Type TMXBFR; /**< \brief Offset: 0x180 (R/ 32) 1519 to Maximum Byte Frames Received Register */
- __I GMAC_UFR_Type UFR; /**< \brief Offset: 0x184 (R/ 32) Undersize Frames Received Register */
- __I GMAC_OFR_Type OFR; /**< \brief Offset: 0x188 (R/ 32) Oversize Frames Received Register */
- __I GMAC_JR_Type JR; /**< \brief Offset: 0x18C (R/ 32) Jabbers Received Register */
- __I GMAC_FCSE_Type FCSE; /**< \brief Offset: 0x190 (R/ 32) Frame Check Sequence Errors Register */
- __I GMAC_LFFE_Type LFFE; /**< \brief Offset: 0x194 (R/ 32) Length Field Frame Errors Register */
- __I GMAC_RSE_Type RSE; /**< \brief Offset: 0x198 (R/ 32) Receive Symbol Errors Register */
- __I GMAC_AE_Type AE; /**< \brief Offset: 0x19C (R/ 32) Alignment Errors Register */
- __I GMAC_RRE_Type RRE; /**< \brief Offset: 0x1A0 (R/ 32) Receive Resource Errors Register */
- __I GMAC_ROE_Type ROE; /**< \brief Offset: 0x1A4 (R/ 32) Receive Overrun Register */
- __I GMAC_IHCE_Type IHCE; /**< \brief Offset: 0x1A8 (R/ 32) IP Header Checksum Errors Register */
- __I GMAC_TCE_Type TCE; /**< \brief Offset: 0x1AC (R/ 32) TCP Checksum Errors Register */
- __I GMAC_UCE_Type UCE; /**< \brief Offset: 0x1B0 (R/ 32) UDP Checksum Errors Register */
- RoReg8 Reserved4[0x8];
- __IO GMAC_TISUBN_Type TISUBN; /**< \brief Offset: 0x1BC (R/W 32) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
- __IO GMAC_TSH_Type TSH; /**< \brief Offset: 0x1C0 (R/W 32) 1588 Timer Seconds High [15:0] Register */
- RoReg8 Reserved5[0x4];
- __IO GMAC_TSSSL_Type TSSSL; /**< \brief Offset: 0x1C8 (R/W 32) 1588 Timer Sync Strobe Seconds [31:0] Register */
- __IO GMAC_TSSN_Type TSSN; /**< \brief Offset: 0x1CC (R/W 32) 1588 Timer Sync Strobe Nanoseconds Register */
- __IO GMAC_TSL_Type TSL; /**< \brief Offset: 0x1D0 (R/W 32) 1588 Timer Seconds [31:0] Register */
- __IO GMAC_TN_Type TN; /**< \brief Offset: 0x1D4 (R/W 32) 1588 Timer Nanoseconds Register */
- __O GMAC_TA_Type TA; /**< \brief Offset: 0x1D8 ( /W 32) 1588 Timer Adjust Register */
- __IO GMAC_TI_Type TI; /**< \brief Offset: 0x1DC (R/W 32) 1588 Timer Increment Register */
- __I GMAC_EFTSL_Type EFTSL; /**< \brief Offset: 0x1E0 (R/ 32) PTP Event Frame Transmitted Seconds Low Register */
- __I GMAC_EFTN_Type EFTN; /**< \brief Offset: 0x1E4 (R/ 32) PTP Event Frame Transmitted Nanoseconds */
- __I GMAC_EFRSL_Type EFRSL; /**< \brief Offset: 0x1E8 (R/ 32) PTP Event Frame Received Seconds Low Register */
- __I GMAC_EFRN_Type EFRN; /**< \brief Offset: 0x1EC (R/ 32) PTP Event Frame Received Nanoseconds */
- __I GMAC_PEFTSL_Type PEFTSL; /**< \brief Offset: 0x1F0 (R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register */
- __I GMAC_PEFTN_Type PEFTN; /**< \brief Offset: 0x1F4 (R/ 32) PTP Peer Event Frame Transmitted Nanoseconds */
- __I GMAC_PEFRSL_Type PEFRSL; /**< \brief Offset: 0x1F8 (R/ 32) PTP Peer Event Frame Received Seconds Low Register */
- __I GMAC_PEFRN_Type PEFRN; /**< \brief Offset: 0x1FC (R/ 32) PTP Peer Event Frame Received Nanoseconds */
- RoReg8 Reserved6[0x70];
- __I GMAC_RLPITR_Type RLPITR; /**< \brief Offset: 0x270 (R/ 32) Receive LPI transition Register */
- __I GMAC_RLPITI_Type RLPITI; /**< \brief Offset: 0x274 (R/ 32) Receive LPI Time Register */
- __I GMAC_TLPITR_Type TLPITR; /**< \brief Offset: 0x278 (R/ 32) Receive LPI transition Register */
- __I GMAC_TLPITI_Type TLPITI; /**< \brief Offset: 0x27C (R/ 32) Receive LPI Time Register */
-} Gmac;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_GMAC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for GMAC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_GMAC_COMPONENT_
+#define _SAME54_GMAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR GMAC */
+/* ========================================================================== */
+/** \addtogroup SAME54_GMAC Ethernet MAC */
+/*@{*/
+
+#define GMAC_U2005
+#define REV_GMAC 0x100
+
+/* -------- GMAC_NCR : (GMAC Offset: 0x000) (R/W 32) Network Control Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t LBL:1; /*!< bit: 1 Loop Back Local */
+ uint32_t RXEN:1; /*!< bit: 2 Receive Enable */
+ uint32_t TXEN:1; /*!< bit: 3 Transmit Enable */
+ uint32_t MPE:1; /*!< bit: 4 Management Port Enable */
+ uint32_t CLRSTAT:1; /*!< bit: 5 Clear Statistics Registers */
+ uint32_t INCSTAT:1; /*!< bit: 6 Increment Statistics Registers */
+ uint32_t WESTAT:1; /*!< bit: 7 Write Enable for Statistics Registers */
+ uint32_t BP:1; /*!< bit: 8 Back pressure */
+ uint32_t TSTART:1; /*!< bit: 9 Start Transmission */
+ uint32_t THALT:1; /*!< bit: 10 Transmit Halt */
+ uint32_t TXPF:1; /*!< bit: 11 Transmit Pause Frame */
+ uint32_t TXZQPF:1; /*!< bit: 12 Transmit Zero Quantum Pause Frame */
+ uint32_t :2; /*!< bit: 13..14 Reserved */
+ uint32_t SRTSM:1; /*!< bit: 15 Store Receive Time Stamp to Memory */
+ uint32_t ENPBPR:1; /*!< bit: 16 Enable PFC Priority-based Pause Reception */
+ uint32_t TXPBPF:1; /*!< bit: 17 Transmit PFC Priority-based Pause Frame */
+ uint32_t FNP:1; /*!< bit: 18 Flush Next Packet */
+ uint32_t LPI:1; /*!< bit: 19 Low Power Idle Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_NCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_NCR_OFFSET 0x000 /**< \brief (GMAC_NCR offset) Network Control Register */
+#define GMAC_NCR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_NCR reset_value) Network Control Register */
+
+#define GMAC_NCR_LBL_Pos 1 /**< \brief (GMAC_NCR) Loop Back Local */
+#define GMAC_NCR_LBL (_U_(0x1) << GMAC_NCR_LBL_Pos)
+#define GMAC_NCR_RXEN_Pos 2 /**< \brief (GMAC_NCR) Receive Enable */
+#define GMAC_NCR_RXEN (_U_(0x1) << GMAC_NCR_RXEN_Pos)
+#define GMAC_NCR_TXEN_Pos 3 /**< \brief (GMAC_NCR) Transmit Enable */
+#define GMAC_NCR_TXEN (_U_(0x1) << GMAC_NCR_TXEN_Pos)
+#define GMAC_NCR_MPE_Pos 4 /**< \brief (GMAC_NCR) Management Port Enable */
+#define GMAC_NCR_MPE (_U_(0x1) << GMAC_NCR_MPE_Pos)
+#define GMAC_NCR_CLRSTAT_Pos 5 /**< \brief (GMAC_NCR) Clear Statistics Registers */
+#define GMAC_NCR_CLRSTAT (_U_(0x1) << GMAC_NCR_CLRSTAT_Pos)
+#define GMAC_NCR_INCSTAT_Pos 6 /**< \brief (GMAC_NCR) Increment Statistics Registers */
+#define GMAC_NCR_INCSTAT (_U_(0x1) << GMAC_NCR_INCSTAT_Pos)
+#define GMAC_NCR_WESTAT_Pos 7 /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */
+#define GMAC_NCR_WESTAT (_U_(0x1) << GMAC_NCR_WESTAT_Pos)
+#define GMAC_NCR_BP_Pos 8 /**< \brief (GMAC_NCR) Back pressure */
+#define GMAC_NCR_BP (_U_(0x1) << GMAC_NCR_BP_Pos)
+#define GMAC_NCR_TSTART_Pos 9 /**< \brief (GMAC_NCR) Start Transmission */
+#define GMAC_NCR_TSTART (_U_(0x1) << GMAC_NCR_TSTART_Pos)
+#define GMAC_NCR_THALT_Pos 10 /**< \brief (GMAC_NCR) Transmit Halt */
+#define GMAC_NCR_THALT (_U_(0x1) << GMAC_NCR_THALT_Pos)
+#define GMAC_NCR_TXPF_Pos 11 /**< \brief (GMAC_NCR) Transmit Pause Frame */
+#define GMAC_NCR_TXPF (_U_(0x1) << GMAC_NCR_TXPF_Pos)
+#define GMAC_NCR_TXZQPF_Pos 12 /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */
+#define GMAC_NCR_TXZQPF (_U_(0x1) << GMAC_NCR_TXZQPF_Pos)
+#define GMAC_NCR_SRTSM_Pos 15 /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */
+#define GMAC_NCR_SRTSM (_U_(0x1) << GMAC_NCR_SRTSM_Pos)
+#define GMAC_NCR_ENPBPR_Pos 16 /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */
+#define GMAC_NCR_ENPBPR (_U_(0x1) << GMAC_NCR_ENPBPR_Pos)
+#define GMAC_NCR_TXPBPF_Pos 17 /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */
+#define GMAC_NCR_TXPBPF (_U_(0x1) << GMAC_NCR_TXPBPF_Pos)
+#define GMAC_NCR_FNP_Pos 18 /**< \brief (GMAC_NCR) Flush Next Packet */
+#define GMAC_NCR_FNP (_U_(0x1) << GMAC_NCR_FNP_Pos)
+#define GMAC_NCR_LPI_Pos 19 /**< \brief (GMAC_NCR) Low Power Idle Enable */
+#define GMAC_NCR_LPI (_U_(0x1) << GMAC_NCR_LPI_Pos)
+#define GMAC_NCR_MASK _U_(0x000F9FFE) /**< \brief (GMAC_NCR) MASK Register */
+
+/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) (R/W 32) Network Configuration Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SPD:1; /*!< bit: 0 Speed */
+ uint32_t FD:1; /*!< bit: 1 Full Duplex */
+ uint32_t DNVLAN:1; /*!< bit: 2 Discard Non-VLAN FRAMES */
+ uint32_t JFRAME:1; /*!< bit: 3 Jumbo Frame Size */
+ uint32_t CAF:1; /*!< bit: 4 Copy All Frames */
+ uint32_t NBC:1; /*!< bit: 5 No Broadcast */
+ uint32_t MTIHEN:1; /*!< bit: 6 Multicast Hash Enable */
+ uint32_t UNIHEN:1; /*!< bit: 7 Unicast Hash Enable */
+ uint32_t MAXFS:1; /*!< bit: 8 1536 Maximum Frame Size */
+ uint32_t :3; /*!< bit: 9..11 Reserved */
+ uint32_t RTY:1; /*!< bit: 12 Retry Test */
+ uint32_t PEN:1; /*!< bit: 13 Pause Enable */
+ uint32_t RXBUFO:2; /*!< bit: 14..15 Receive Buffer Offset */
+ uint32_t LFERD:1; /*!< bit: 16 Length Field Error Frame Discard */
+ uint32_t RFCS:1; /*!< bit: 17 Remove FCS */
+ uint32_t CLK:3; /*!< bit: 18..20 MDC CLock Division */
+ uint32_t DBW:2; /*!< bit: 21..22 Data Bus Width */
+ uint32_t DCPF:1; /*!< bit: 23 Disable Copy of Pause Frames */
+ uint32_t RXCOEN:1; /*!< bit: 24 Receive Checksum Offload Enable */
+ uint32_t EFRHD:1; /*!< bit: 25 Enable Frames Received in Half Duplex */
+ uint32_t IRXFCS:1; /*!< bit: 26 Ignore RX FCS */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t IPGSEN:1; /*!< bit: 28 IP Stretch Enable */
+ uint32_t RXBP:1; /*!< bit: 29 Receive Bad Preamble */
+ uint32_t IRXER:1; /*!< bit: 30 Ignore IPG GRXER */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_NCFGR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_NCFGR_OFFSET 0x004 /**< \brief (GMAC_NCFGR offset) Network Configuration Register */
+#define GMAC_NCFGR_RESETVALUE _U_(0x00080000) /**< \brief (GMAC_NCFGR reset_value) Network Configuration Register */
+
+#define GMAC_NCFGR_SPD_Pos 0 /**< \brief (GMAC_NCFGR) Speed */
+#define GMAC_NCFGR_SPD (_U_(0x1) << GMAC_NCFGR_SPD_Pos)
+#define GMAC_NCFGR_FD_Pos 1 /**< \brief (GMAC_NCFGR) Full Duplex */
+#define GMAC_NCFGR_FD (_U_(0x1) << GMAC_NCFGR_FD_Pos)
+#define GMAC_NCFGR_DNVLAN_Pos 2 /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */
+#define GMAC_NCFGR_DNVLAN (_U_(0x1) << GMAC_NCFGR_DNVLAN_Pos)
+#define GMAC_NCFGR_JFRAME_Pos 3 /**< \brief (GMAC_NCFGR) Jumbo Frame Size */
+#define GMAC_NCFGR_JFRAME (_U_(0x1) << GMAC_NCFGR_JFRAME_Pos)
+#define GMAC_NCFGR_CAF_Pos 4 /**< \brief (GMAC_NCFGR) Copy All Frames */
+#define GMAC_NCFGR_CAF (_U_(0x1) << GMAC_NCFGR_CAF_Pos)
+#define GMAC_NCFGR_NBC_Pos 5 /**< \brief (GMAC_NCFGR) No Broadcast */
+#define GMAC_NCFGR_NBC (_U_(0x1) << GMAC_NCFGR_NBC_Pos)
+#define GMAC_NCFGR_MTIHEN_Pos 6 /**< \brief (GMAC_NCFGR) Multicast Hash Enable */
+#define GMAC_NCFGR_MTIHEN (_U_(0x1) << GMAC_NCFGR_MTIHEN_Pos)
+#define GMAC_NCFGR_UNIHEN_Pos 7 /**< \brief (GMAC_NCFGR) Unicast Hash Enable */
+#define GMAC_NCFGR_UNIHEN (_U_(0x1) << GMAC_NCFGR_UNIHEN_Pos)
+#define GMAC_NCFGR_MAXFS_Pos 8 /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */
+#define GMAC_NCFGR_MAXFS (_U_(0x1) << GMAC_NCFGR_MAXFS_Pos)
+#define GMAC_NCFGR_RTY_Pos 12 /**< \brief (GMAC_NCFGR) Retry Test */
+#define GMAC_NCFGR_RTY (_U_(0x1) << GMAC_NCFGR_RTY_Pos)
+#define GMAC_NCFGR_PEN_Pos 13 /**< \brief (GMAC_NCFGR) Pause Enable */
+#define GMAC_NCFGR_PEN (_U_(0x1) << GMAC_NCFGR_PEN_Pos)
+#define GMAC_NCFGR_RXBUFO_Pos 14 /**< \brief (GMAC_NCFGR) Receive Buffer Offset */
+#define GMAC_NCFGR_RXBUFO_Msk (_U_(0x3) << GMAC_NCFGR_RXBUFO_Pos)
+#define GMAC_NCFGR_RXBUFO(value) (GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))
+#define GMAC_NCFGR_LFERD_Pos 16 /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */
+#define GMAC_NCFGR_LFERD (_U_(0x1) << GMAC_NCFGR_LFERD_Pos)
+#define GMAC_NCFGR_RFCS_Pos 17 /**< \brief (GMAC_NCFGR) Remove FCS */
+#define GMAC_NCFGR_RFCS (_U_(0x1) << GMAC_NCFGR_RFCS_Pos)
+#define GMAC_NCFGR_CLK_Pos 18 /**< \brief (GMAC_NCFGR) MDC CLock Division */
+#define GMAC_NCFGR_CLK_Msk (_U_(0x7) << GMAC_NCFGR_CLK_Pos)
+#define GMAC_NCFGR_CLK(value) (GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos))
+#define GMAC_NCFGR_DBW_Pos 21 /**< \brief (GMAC_NCFGR) Data Bus Width */
+#define GMAC_NCFGR_DBW_Msk (_U_(0x3) << GMAC_NCFGR_DBW_Pos)
+#define GMAC_NCFGR_DBW(value) (GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos))
+#define GMAC_NCFGR_DCPF_Pos 23 /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */
+#define GMAC_NCFGR_DCPF (_U_(0x1) << GMAC_NCFGR_DCPF_Pos)
+#define GMAC_NCFGR_RXCOEN_Pos 24 /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */
+#define GMAC_NCFGR_RXCOEN (_U_(0x1) << GMAC_NCFGR_RXCOEN_Pos)
+#define GMAC_NCFGR_EFRHD_Pos 25 /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */
+#define GMAC_NCFGR_EFRHD (_U_(0x1) << GMAC_NCFGR_EFRHD_Pos)
+#define GMAC_NCFGR_IRXFCS_Pos 26 /**< \brief (GMAC_NCFGR) Ignore RX FCS */
+#define GMAC_NCFGR_IRXFCS (_U_(0x1) << GMAC_NCFGR_IRXFCS_Pos)
+#define GMAC_NCFGR_IPGSEN_Pos 28 /**< \brief (GMAC_NCFGR) IP Stretch Enable */
+#define GMAC_NCFGR_IPGSEN (_U_(0x1) << GMAC_NCFGR_IPGSEN_Pos)
+#define GMAC_NCFGR_RXBP_Pos 29 /**< \brief (GMAC_NCFGR) Receive Bad Preamble */
+#define GMAC_NCFGR_RXBP (_U_(0x1) << GMAC_NCFGR_RXBP_Pos)
+#define GMAC_NCFGR_IRXER_Pos 30 /**< \brief (GMAC_NCFGR) Ignore IPG GRXER */
+#define GMAC_NCFGR_IRXER (_U_(0x1) << GMAC_NCFGR_IRXER_Pos)
+#define GMAC_NCFGR_MASK _U_(0x77FFF1FF) /**< \brief (GMAC_NCFGR) MASK Register */
+
+/* -------- GMAC_NSR : (GMAC Offset: 0x008) (R/ 32) Network Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t MDIO:1; /*!< bit: 1 MDIO Input Status */
+ uint32_t IDLE:1; /*!< bit: 2 PHY Management Logic Idle */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_NSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_NSR_OFFSET 0x008 /**< \brief (GMAC_NSR offset) Network Status Register */
+#define GMAC_NSR_RESETVALUE _U_(0x00000004) /**< \brief (GMAC_NSR reset_value) Network Status Register */
+
+#define GMAC_NSR_MDIO_Pos 1 /**< \brief (GMAC_NSR) MDIO Input Status */
+#define GMAC_NSR_MDIO (_U_(0x1) << GMAC_NSR_MDIO_Pos)
+#define GMAC_NSR_IDLE_Pos 2 /**< \brief (GMAC_NSR) PHY Management Logic Idle */
+#define GMAC_NSR_IDLE (_U_(0x1) << GMAC_NSR_IDLE_Pos)
+#define GMAC_NSR_MASK _U_(0x00000006) /**< \brief (GMAC_NSR) MASK Register */
+
+/* -------- GMAC_UR : (GMAC Offset: 0x00C) (R/W 32) User Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MII:1; /*!< bit: 0 MII Mode */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_UR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_UR_OFFSET 0x00C /**< \brief (GMAC_UR offset) User Register */
+#define GMAC_UR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_UR reset_value) User Register */
+
+#define GMAC_UR_MII_Pos 0 /**< \brief (GMAC_UR) MII Mode */
+#define GMAC_UR_MII (_U_(0x1) << GMAC_UR_MII_Pos)
+#define GMAC_UR_MASK _U_(0x00000001) /**< \brief (GMAC_UR) MASK Register */
+
+/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) (R/W 32) DMA Configuration Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FBLDO:5; /*!< bit: 0.. 4 Fixed Burst Length for DMA Data Operations: */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t ESMA:1; /*!< bit: 6 Endian Swap Mode Enable for Management Descriptor Accesses */
+ uint32_t ESPA:1; /*!< bit: 7 Endian Swap Mode Enable for Packet Data Accesses */
+ uint32_t RXBMS:2; /*!< bit: 8.. 9 Receiver Packet Buffer Memory Size Select */
+ uint32_t TXPBMS:1; /*!< bit: 10 Transmitter Packet Buffer Memory Size Select */
+ uint32_t TXCOEN:1; /*!< bit: 11 Transmitter Checksum Generation Offload Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t DRBS:8; /*!< bit: 16..23 DMA Receive Buffer Size */
+ uint32_t DDRP:1; /*!< bit: 24 DMA Discard Receive Packets */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_DCFGR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_DCFGR_OFFSET 0x010 /**< \brief (GMAC_DCFGR offset) DMA Configuration Register */
+#define GMAC_DCFGR_RESETVALUE _U_(0x00020704) /**< \brief (GMAC_DCFGR reset_value) DMA Configuration Register */
+
+#define GMAC_DCFGR_FBLDO_Pos 0 /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */
+#define GMAC_DCFGR_FBLDO_Msk (_U_(0x1F) << GMAC_DCFGR_FBLDO_Pos)
+#define GMAC_DCFGR_FBLDO(value) (GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos))
+#define GMAC_DCFGR_ESMA_Pos 6 /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */
+#define GMAC_DCFGR_ESMA (_U_(0x1) << GMAC_DCFGR_ESMA_Pos)
+#define GMAC_DCFGR_ESPA_Pos 7 /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */
+#define GMAC_DCFGR_ESPA (_U_(0x1) << GMAC_DCFGR_ESPA_Pos)
+#define GMAC_DCFGR_RXBMS_Pos 8 /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */
+#define GMAC_DCFGR_RXBMS_Msk (_U_(0x3) << GMAC_DCFGR_RXBMS_Pos)
+#define GMAC_DCFGR_RXBMS(value) (GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos))
+#define GMAC_DCFGR_TXPBMS_Pos 10 /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */
+#define GMAC_DCFGR_TXPBMS (_U_(0x1) << GMAC_DCFGR_TXPBMS_Pos)
+#define GMAC_DCFGR_TXCOEN_Pos 11 /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */
+#define GMAC_DCFGR_TXCOEN (_U_(0x1) << GMAC_DCFGR_TXCOEN_Pos)
+#define GMAC_DCFGR_DRBS_Pos 16 /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */
+#define GMAC_DCFGR_DRBS_Msk (_U_(0xFF) << GMAC_DCFGR_DRBS_Pos)
+#define GMAC_DCFGR_DRBS(value) (GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))
+#define GMAC_DCFGR_DDRP_Pos 24 /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */
+#define GMAC_DCFGR_DDRP (_U_(0x1) << GMAC_DCFGR_DDRP_Pos)
+#define GMAC_DCFGR_MASK _U_(0x01FF0FDF) /**< \brief (GMAC_DCFGR) MASK Register */
+
+/* -------- GMAC_TSR : (GMAC Offset: 0x014) (R/W 32) Transmit Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t UBR:1; /*!< bit: 0 Used Bit Read */
+ uint32_t COL:1; /*!< bit: 1 Collision Occurred */
+ uint32_t RLE:1; /*!< bit: 2 Retry Limit Exceeded */
+ uint32_t TXGO:1; /*!< bit: 3 Transmit Go */
+ uint32_t TFC:1; /*!< bit: 4 Transmit Frame Corruption Due to AHB Error */
+ uint32_t TXCOMP:1; /*!< bit: 5 Transmit Complete */
+ uint32_t UND:1; /*!< bit: 6 Transmit Underrun */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t HRESP:1; /*!< bit: 8 HRESP Not OK */
+ uint32_t :23; /*!< bit: 9..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TSR_OFFSET 0x014 /**< \brief (GMAC_TSR offset) Transmit Status Register */
+#define GMAC_TSR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSR reset_value) Transmit Status Register */
+
+#define GMAC_TSR_UBR_Pos 0 /**< \brief (GMAC_TSR) Used Bit Read */
+#define GMAC_TSR_UBR (_U_(0x1) << GMAC_TSR_UBR_Pos)
+#define GMAC_TSR_COL_Pos 1 /**< \brief (GMAC_TSR) Collision Occurred */
+#define GMAC_TSR_COL (_U_(0x1) << GMAC_TSR_COL_Pos)
+#define GMAC_TSR_RLE_Pos 2 /**< \brief (GMAC_TSR) Retry Limit Exceeded */
+#define GMAC_TSR_RLE (_U_(0x1) << GMAC_TSR_RLE_Pos)
+#define GMAC_TSR_TXGO_Pos 3 /**< \brief (GMAC_TSR) Transmit Go */
+#define GMAC_TSR_TXGO (_U_(0x1) << GMAC_TSR_TXGO_Pos)
+#define GMAC_TSR_TFC_Pos 4 /**< \brief (GMAC_TSR) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_TSR_TFC (_U_(0x1) << GMAC_TSR_TFC_Pos)
+#define GMAC_TSR_TXCOMP_Pos 5 /**< \brief (GMAC_TSR) Transmit Complete */
+#define GMAC_TSR_TXCOMP (_U_(0x1) << GMAC_TSR_TXCOMP_Pos)
+#define GMAC_TSR_UND_Pos 6 /**< \brief (GMAC_TSR) Transmit Underrun */
+#define GMAC_TSR_UND (_U_(0x1) << GMAC_TSR_UND_Pos)
+#define GMAC_TSR_HRESP_Pos 8 /**< \brief (GMAC_TSR) HRESP Not OK */
+#define GMAC_TSR_HRESP (_U_(0x1) << GMAC_TSR_HRESP_Pos)
+#define GMAC_TSR_MASK _U_(0x0000017F) /**< \brief (GMAC_TSR) MASK Register */
+
+/* -------- GMAC_RBQB : (GMAC Offset: 0x018) (R/W 32) Receive Buffer Queue Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t ADDR:30; /*!< bit: 2..31 Receive Buffer Queue Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_RBQB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RBQB_OFFSET 0x018 /**< \brief (GMAC_RBQB offset) Receive Buffer Queue Base Address */
+#define GMAC_RBQB_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RBQB reset_value) Receive Buffer Queue Base Address */
+
+#define GMAC_RBQB_ADDR_Pos 2 /**< \brief (GMAC_RBQB) Receive Buffer Queue Base Address */
+#define GMAC_RBQB_ADDR_Msk (_U_(0x3FFFFFFF) << GMAC_RBQB_ADDR_Pos)
+#define GMAC_RBQB_ADDR(value) (GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))
+#define GMAC_RBQB_MASK _U_(0xFFFFFFFC) /**< \brief (GMAC_RBQB) MASK Register */
+
+/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) (R/W 32) Transmit Buffer Queue Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t ADDR:30; /*!< bit: 2..31 Transmit Buffer Queue Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBQB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBQB_OFFSET 0x01C /**< \brief (GMAC_TBQB offset) Transmit Buffer Queue Base Address */
+#define GMAC_TBQB_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBQB reset_value) Transmit Buffer Queue Base Address */
+
+#define GMAC_TBQB_ADDR_Pos 2 /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */
+#define GMAC_TBQB_ADDR_Msk (_U_(0x3FFFFFFF) << GMAC_TBQB_ADDR_Pos)
+#define GMAC_TBQB_ADDR(value) (GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))
+#define GMAC_TBQB_MASK _U_(0xFFFFFFFC) /**< \brief (GMAC_TBQB) MASK Register */
+
+/* -------- GMAC_RSR : (GMAC Offset: 0x020) (R/W 32) Receive Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BNA:1; /*!< bit: 0 Buffer Not Available */
+ uint32_t REC:1; /*!< bit: 1 Frame Received */
+ uint32_t RXOVR:1; /*!< bit: 2 Receive Overrun */
+ uint32_t HNO:1; /*!< bit: 3 HRESP Not OK */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_RSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RSR_OFFSET 0x020 /**< \brief (GMAC_RSR offset) Receive Status Register */
+#define GMAC_RSR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RSR reset_value) Receive Status Register */
+
+#define GMAC_RSR_BNA_Pos 0 /**< \brief (GMAC_RSR) Buffer Not Available */
+#define GMAC_RSR_BNA (_U_(0x1) << GMAC_RSR_BNA_Pos)
+#define GMAC_RSR_REC_Pos 1 /**< \brief (GMAC_RSR) Frame Received */
+#define GMAC_RSR_REC (_U_(0x1) << GMAC_RSR_REC_Pos)
+#define GMAC_RSR_RXOVR_Pos 2 /**< \brief (GMAC_RSR) Receive Overrun */
+#define GMAC_RSR_RXOVR (_U_(0x1) << GMAC_RSR_RXOVR_Pos)
+#define GMAC_RSR_HNO_Pos 3 /**< \brief (GMAC_RSR) HRESP Not OK */
+#define GMAC_RSR_HNO (_U_(0x1) << GMAC_RSR_HNO_Pos)
+#define GMAC_RSR_MASK _U_(0x0000000F) /**< \brief (GMAC_RSR) MASK Register */
+
+/* -------- GMAC_ISR : (GMAC Offset: 0x024) (R/W 32) Interrupt Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MFS:1; /*!< bit: 0 Management Frame Sent */
+ uint32_t RCOMP:1; /*!< bit: 1 Receive Complete */
+ uint32_t RXUBR:1; /*!< bit: 2 RX Used Bit Read */
+ uint32_t TXUBR:1; /*!< bit: 3 TX Used Bit Read */
+ uint32_t TUR:1; /*!< bit: 4 Transmit Underrun */
+ uint32_t RLEX:1; /*!< bit: 5 Retry Limit Exceeded */
+ uint32_t TFC:1; /*!< bit: 6 Transmit Frame Corruption Due to AHB Error */
+ uint32_t TCOMP:1; /*!< bit: 7 Transmit Complete */
+ uint32_t :2; /*!< bit: 8.. 9 Reserved */
+ uint32_t ROVR:1; /*!< bit: 10 Receive Overrun */
+ uint32_t HRESP:1; /*!< bit: 11 HRESP Not OK */
+ uint32_t PFNZ:1; /*!< bit: 12 Pause Frame with Non-zero Pause Quantum Received */
+ uint32_t PTZ:1; /*!< bit: 13 Pause Time Zero */
+ uint32_t PFTR:1; /*!< bit: 14 Pause Frame Transmitted */
+ uint32_t :3; /*!< bit: 15..17 Reserved */
+ uint32_t DRQFR:1; /*!< bit: 18 PTP Delay Request Frame Received */
+ uint32_t SFR:1; /*!< bit: 19 PTP Sync Frame Received */
+ uint32_t DRQFT:1; /*!< bit: 20 PTP Delay Request Frame Transmitted */
+ uint32_t SFT:1; /*!< bit: 21 PTP Sync Frame Transmitted */
+ uint32_t PDRQFR:1; /*!< bit: 22 PDelay Request Frame Received */
+ uint32_t PDRSFR:1; /*!< bit: 23 PDelay Response Frame Received */
+ uint32_t PDRQFT:1; /*!< bit: 24 PDelay Request Frame Transmitted */
+ uint32_t PDRSFT:1; /*!< bit: 25 PDelay Response Frame Transmitted */
+ uint32_t SRI:1; /*!< bit: 26 TSU Seconds Register Increment */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t WOL:1; /*!< bit: 28 Wake On LAN */
+ uint32_t TSUCMP:1; /*!< bit: 29 Tsu timer comparison */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_ISR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_ISR_OFFSET 0x024 /**< \brief (GMAC_ISR offset) Interrupt Status Register */
+#define GMAC_ISR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_ISR reset_value) Interrupt Status Register */
+
+#define GMAC_ISR_MFS_Pos 0 /**< \brief (GMAC_ISR) Management Frame Sent */
+#define GMAC_ISR_MFS (_U_(0x1) << GMAC_ISR_MFS_Pos)
+#define GMAC_ISR_RCOMP_Pos 1 /**< \brief (GMAC_ISR) Receive Complete */
+#define GMAC_ISR_RCOMP (_U_(0x1) << GMAC_ISR_RCOMP_Pos)
+#define GMAC_ISR_RXUBR_Pos 2 /**< \brief (GMAC_ISR) RX Used Bit Read */
+#define GMAC_ISR_RXUBR (_U_(0x1) << GMAC_ISR_RXUBR_Pos)
+#define GMAC_ISR_TXUBR_Pos 3 /**< \brief (GMAC_ISR) TX Used Bit Read */
+#define GMAC_ISR_TXUBR (_U_(0x1) << GMAC_ISR_TXUBR_Pos)
+#define GMAC_ISR_TUR_Pos 4 /**< \brief (GMAC_ISR) Transmit Underrun */
+#define GMAC_ISR_TUR (_U_(0x1) << GMAC_ISR_TUR_Pos)
+#define GMAC_ISR_RLEX_Pos 5 /**< \brief (GMAC_ISR) Retry Limit Exceeded */
+#define GMAC_ISR_RLEX (_U_(0x1) << GMAC_ISR_RLEX_Pos)
+#define GMAC_ISR_TFC_Pos 6 /**< \brief (GMAC_ISR) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_ISR_TFC (_U_(0x1) << GMAC_ISR_TFC_Pos)
+#define GMAC_ISR_TCOMP_Pos 7 /**< \brief (GMAC_ISR) Transmit Complete */
+#define GMAC_ISR_TCOMP (_U_(0x1) << GMAC_ISR_TCOMP_Pos)
+#define GMAC_ISR_ROVR_Pos 10 /**< \brief (GMAC_ISR) Receive Overrun */
+#define GMAC_ISR_ROVR (_U_(0x1) << GMAC_ISR_ROVR_Pos)
+#define GMAC_ISR_HRESP_Pos 11 /**< \brief (GMAC_ISR) HRESP Not OK */
+#define GMAC_ISR_HRESP (_U_(0x1) << GMAC_ISR_HRESP_Pos)
+#define GMAC_ISR_PFNZ_Pos 12 /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */
+#define GMAC_ISR_PFNZ (_U_(0x1) << GMAC_ISR_PFNZ_Pos)
+#define GMAC_ISR_PTZ_Pos 13 /**< \brief (GMAC_ISR) Pause Time Zero */
+#define GMAC_ISR_PTZ (_U_(0x1) << GMAC_ISR_PTZ_Pos)
+#define GMAC_ISR_PFTR_Pos 14 /**< \brief (GMAC_ISR) Pause Frame Transmitted */
+#define GMAC_ISR_PFTR (_U_(0x1) << GMAC_ISR_PFTR_Pos)
+#define GMAC_ISR_DRQFR_Pos 18 /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */
+#define GMAC_ISR_DRQFR (_U_(0x1) << GMAC_ISR_DRQFR_Pos)
+#define GMAC_ISR_SFR_Pos 19 /**< \brief (GMAC_ISR) PTP Sync Frame Received */
+#define GMAC_ISR_SFR (_U_(0x1) << GMAC_ISR_SFR_Pos)
+#define GMAC_ISR_DRQFT_Pos 20 /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */
+#define GMAC_ISR_DRQFT (_U_(0x1) << GMAC_ISR_DRQFT_Pos)
+#define GMAC_ISR_SFT_Pos 21 /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */
+#define GMAC_ISR_SFT (_U_(0x1) << GMAC_ISR_SFT_Pos)
+#define GMAC_ISR_PDRQFR_Pos 22 /**< \brief (GMAC_ISR) PDelay Request Frame Received */
+#define GMAC_ISR_PDRQFR (_U_(0x1) << GMAC_ISR_PDRQFR_Pos)
+#define GMAC_ISR_PDRSFR_Pos 23 /**< \brief (GMAC_ISR) PDelay Response Frame Received */
+#define GMAC_ISR_PDRSFR (_U_(0x1) << GMAC_ISR_PDRSFR_Pos)
+#define GMAC_ISR_PDRQFT_Pos 24 /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */
+#define GMAC_ISR_PDRQFT (_U_(0x1) << GMAC_ISR_PDRQFT_Pos)
+#define GMAC_ISR_PDRSFT_Pos 25 /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */
+#define GMAC_ISR_PDRSFT (_U_(0x1) << GMAC_ISR_PDRSFT_Pos)
+#define GMAC_ISR_SRI_Pos 26 /**< \brief (GMAC_ISR) TSU Seconds Register Increment */
+#define GMAC_ISR_SRI (_U_(0x1) << GMAC_ISR_SRI_Pos)
+#define GMAC_ISR_WOL_Pos 28 /**< \brief (GMAC_ISR) Wake On LAN */
+#define GMAC_ISR_WOL (_U_(0x1) << GMAC_ISR_WOL_Pos)
+#define GMAC_ISR_TSUCMP_Pos 29 /**< \brief (GMAC_ISR) Tsu timer comparison */
+#define GMAC_ISR_TSUCMP (_U_(0x1) << GMAC_ISR_TSUCMP_Pos)
+#define GMAC_ISR_MASK _U_(0x37FC7CFF) /**< \brief (GMAC_ISR) MASK Register */
+
+/* -------- GMAC_IER : (GMAC Offset: 0x028) ( /W 32) Interrupt Enable Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MFS:1; /*!< bit: 0 Management Frame Sent */
+ uint32_t RCOMP:1; /*!< bit: 1 Receive Complete */
+ uint32_t RXUBR:1; /*!< bit: 2 RX Used Bit Read */
+ uint32_t TXUBR:1; /*!< bit: 3 TX Used Bit Read */
+ uint32_t TUR:1; /*!< bit: 4 Transmit Underrun */
+ uint32_t RLEX:1; /*!< bit: 5 Retry Limit Exceeded or Late Collision */
+ uint32_t TFC:1; /*!< bit: 6 Transmit Frame Corruption Due to AHB Error */
+ uint32_t TCOMP:1; /*!< bit: 7 Transmit Complete */
+ uint32_t :2; /*!< bit: 8.. 9 Reserved */
+ uint32_t ROVR:1; /*!< bit: 10 Receive Overrun */
+ uint32_t HRESP:1; /*!< bit: 11 HRESP Not OK */
+ uint32_t PFNZ:1; /*!< bit: 12 Pause Frame with Non-zero Pause Quantum Received */
+ uint32_t PTZ:1; /*!< bit: 13 Pause Time Zero */
+ uint32_t PFTR:1; /*!< bit: 14 Pause Frame Transmitted */
+ uint32_t EXINT:1; /*!< bit: 15 External Interrupt */
+ uint32_t :2; /*!< bit: 16..17 Reserved */
+ uint32_t DRQFR:1; /*!< bit: 18 PTP Delay Request Frame Received */
+ uint32_t SFR:1; /*!< bit: 19 PTP Sync Frame Received */
+ uint32_t DRQFT:1; /*!< bit: 20 PTP Delay Request Frame Transmitted */
+ uint32_t SFT:1; /*!< bit: 21 PTP Sync Frame Transmitted */
+ uint32_t PDRQFR:1; /*!< bit: 22 PDelay Request Frame Received */
+ uint32_t PDRSFR:1; /*!< bit: 23 PDelay Response Frame Received */
+ uint32_t PDRQFT:1; /*!< bit: 24 PDelay Request Frame Transmitted */
+ uint32_t PDRSFT:1; /*!< bit: 25 PDelay Response Frame Transmitted */
+ uint32_t SRI:1; /*!< bit: 26 TSU Seconds Register Increment */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t WOL:1; /*!< bit: 28 Wake On LAN */
+ uint32_t TSUCMP:1; /*!< bit: 29 Tsu timer comparison */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_IER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_IER_OFFSET 0x028 /**< \brief (GMAC_IER offset) Interrupt Enable Register */
+
+#define GMAC_IER_MFS_Pos 0 /**< \brief (GMAC_IER) Management Frame Sent */
+#define GMAC_IER_MFS (_U_(0x1) << GMAC_IER_MFS_Pos)
+#define GMAC_IER_RCOMP_Pos 1 /**< \brief (GMAC_IER) Receive Complete */
+#define GMAC_IER_RCOMP (_U_(0x1) << GMAC_IER_RCOMP_Pos)
+#define GMAC_IER_RXUBR_Pos 2 /**< \brief (GMAC_IER) RX Used Bit Read */
+#define GMAC_IER_RXUBR (_U_(0x1) << GMAC_IER_RXUBR_Pos)
+#define GMAC_IER_TXUBR_Pos 3 /**< \brief (GMAC_IER) TX Used Bit Read */
+#define GMAC_IER_TXUBR (_U_(0x1) << GMAC_IER_TXUBR_Pos)
+#define GMAC_IER_TUR_Pos 4 /**< \brief (GMAC_IER) Transmit Underrun */
+#define GMAC_IER_TUR (_U_(0x1) << GMAC_IER_TUR_Pos)
+#define GMAC_IER_RLEX_Pos 5 /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */
+#define GMAC_IER_RLEX (_U_(0x1) << GMAC_IER_RLEX_Pos)
+#define GMAC_IER_TFC_Pos 6 /**< \brief (GMAC_IER) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_IER_TFC (_U_(0x1) << GMAC_IER_TFC_Pos)
+#define GMAC_IER_TCOMP_Pos 7 /**< \brief (GMAC_IER) Transmit Complete */
+#define GMAC_IER_TCOMP (_U_(0x1) << GMAC_IER_TCOMP_Pos)
+#define GMAC_IER_ROVR_Pos 10 /**< \brief (GMAC_IER) Receive Overrun */
+#define GMAC_IER_ROVR (_U_(0x1) << GMAC_IER_ROVR_Pos)
+#define GMAC_IER_HRESP_Pos 11 /**< \brief (GMAC_IER) HRESP Not OK */
+#define GMAC_IER_HRESP (_U_(0x1) << GMAC_IER_HRESP_Pos)
+#define GMAC_IER_PFNZ_Pos 12 /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */
+#define GMAC_IER_PFNZ (_U_(0x1) << GMAC_IER_PFNZ_Pos)
+#define GMAC_IER_PTZ_Pos 13 /**< \brief (GMAC_IER) Pause Time Zero */
+#define GMAC_IER_PTZ (_U_(0x1) << GMAC_IER_PTZ_Pos)
+#define GMAC_IER_PFTR_Pos 14 /**< \brief (GMAC_IER) Pause Frame Transmitted */
+#define GMAC_IER_PFTR (_U_(0x1) << GMAC_IER_PFTR_Pos)
+#define GMAC_IER_EXINT_Pos 15 /**< \brief (GMAC_IER) External Interrupt */
+#define GMAC_IER_EXINT (_U_(0x1) << GMAC_IER_EXINT_Pos)
+#define GMAC_IER_DRQFR_Pos 18 /**< \brief (GMAC_IER) PTP Delay Request Frame Received */
+#define GMAC_IER_DRQFR (_U_(0x1) << GMAC_IER_DRQFR_Pos)
+#define GMAC_IER_SFR_Pos 19 /**< \brief (GMAC_IER) PTP Sync Frame Received */
+#define GMAC_IER_SFR (_U_(0x1) << GMAC_IER_SFR_Pos)
+#define GMAC_IER_DRQFT_Pos 20 /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */
+#define GMAC_IER_DRQFT (_U_(0x1) << GMAC_IER_DRQFT_Pos)
+#define GMAC_IER_SFT_Pos 21 /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */
+#define GMAC_IER_SFT (_U_(0x1) << GMAC_IER_SFT_Pos)
+#define GMAC_IER_PDRQFR_Pos 22 /**< \brief (GMAC_IER) PDelay Request Frame Received */
+#define GMAC_IER_PDRQFR (_U_(0x1) << GMAC_IER_PDRQFR_Pos)
+#define GMAC_IER_PDRSFR_Pos 23 /**< \brief (GMAC_IER) PDelay Response Frame Received */
+#define GMAC_IER_PDRSFR (_U_(0x1) << GMAC_IER_PDRSFR_Pos)
+#define GMAC_IER_PDRQFT_Pos 24 /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */
+#define GMAC_IER_PDRQFT (_U_(0x1) << GMAC_IER_PDRQFT_Pos)
+#define GMAC_IER_PDRSFT_Pos 25 /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */
+#define GMAC_IER_PDRSFT (_U_(0x1) << GMAC_IER_PDRSFT_Pos)
+#define GMAC_IER_SRI_Pos 26 /**< \brief (GMAC_IER) TSU Seconds Register Increment */
+#define GMAC_IER_SRI (_U_(0x1) << GMAC_IER_SRI_Pos)
+#define GMAC_IER_WOL_Pos 28 /**< \brief (GMAC_IER) Wake On LAN */
+#define GMAC_IER_WOL (_U_(0x1) << GMAC_IER_WOL_Pos)
+#define GMAC_IER_TSUCMP_Pos 29 /**< \brief (GMAC_IER) Tsu timer comparison */
+#define GMAC_IER_TSUCMP (_U_(0x1) << GMAC_IER_TSUCMP_Pos)
+#define GMAC_IER_MASK _U_(0x37FCFCFF) /**< \brief (GMAC_IER) MASK Register */
+
+/* -------- GMAC_IDR : (GMAC Offset: 0x02C) ( /W 32) Interrupt Disable Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MFS:1; /*!< bit: 0 Management Frame Sent */
+ uint32_t RCOMP:1; /*!< bit: 1 Receive Complete */
+ uint32_t RXUBR:1; /*!< bit: 2 RX Used Bit Read */
+ uint32_t TXUBR:1; /*!< bit: 3 TX Used Bit Read */
+ uint32_t TUR:1; /*!< bit: 4 Transmit Underrun */
+ uint32_t RLEX:1; /*!< bit: 5 Retry Limit Exceeded or Late Collision */
+ uint32_t TFC:1; /*!< bit: 6 Transmit Frame Corruption Due to AHB Error */
+ uint32_t TCOMP:1; /*!< bit: 7 Transmit Complete */
+ uint32_t :2; /*!< bit: 8.. 9 Reserved */
+ uint32_t ROVR:1; /*!< bit: 10 Receive Overrun */
+ uint32_t HRESP:1; /*!< bit: 11 HRESP Not OK */
+ uint32_t PFNZ:1; /*!< bit: 12 Pause Frame with Non-zero Pause Quantum Received */
+ uint32_t PTZ:1; /*!< bit: 13 Pause Time Zero */
+ uint32_t PFTR:1; /*!< bit: 14 Pause Frame Transmitted */
+ uint32_t EXINT:1; /*!< bit: 15 External Interrupt */
+ uint32_t :2; /*!< bit: 16..17 Reserved */
+ uint32_t DRQFR:1; /*!< bit: 18 PTP Delay Request Frame Received */
+ uint32_t SFR:1; /*!< bit: 19 PTP Sync Frame Received */
+ uint32_t DRQFT:1; /*!< bit: 20 PTP Delay Request Frame Transmitted */
+ uint32_t SFT:1; /*!< bit: 21 PTP Sync Frame Transmitted */
+ uint32_t PDRQFR:1; /*!< bit: 22 PDelay Request Frame Received */
+ uint32_t PDRSFR:1; /*!< bit: 23 PDelay Response Frame Received */
+ uint32_t PDRQFT:1; /*!< bit: 24 PDelay Request Frame Transmitted */
+ uint32_t PDRSFT:1; /*!< bit: 25 PDelay Response Frame Transmitted */
+ uint32_t SRI:1; /*!< bit: 26 TSU Seconds Register Increment */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t WOL:1; /*!< bit: 28 Wake On LAN */
+ uint32_t TSUCMP:1; /*!< bit: 29 Tsu timer comparison */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_IDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_IDR_OFFSET 0x02C /**< \brief (GMAC_IDR offset) Interrupt Disable Register */
+
+#define GMAC_IDR_MFS_Pos 0 /**< \brief (GMAC_IDR) Management Frame Sent */
+#define GMAC_IDR_MFS (_U_(0x1) << GMAC_IDR_MFS_Pos)
+#define GMAC_IDR_RCOMP_Pos 1 /**< \brief (GMAC_IDR) Receive Complete */
+#define GMAC_IDR_RCOMP (_U_(0x1) << GMAC_IDR_RCOMP_Pos)
+#define GMAC_IDR_RXUBR_Pos 2 /**< \brief (GMAC_IDR) RX Used Bit Read */
+#define GMAC_IDR_RXUBR (_U_(0x1) << GMAC_IDR_RXUBR_Pos)
+#define GMAC_IDR_TXUBR_Pos 3 /**< \brief (GMAC_IDR) TX Used Bit Read */
+#define GMAC_IDR_TXUBR (_U_(0x1) << GMAC_IDR_TXUBR_Pos)
+#define GMAC_IDR_TUR_Pos 4 /**< \brief (GMAC_IDR) Transmit Underrun */
+#define GMAC_IDR_TUR (_U_(0x1) << GMAC_IDR_TUR_Pos)
+#define GMAC_IDR_RLEX_Pos 5 /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */
+#define GMAC_IDR_RLEX (_U_(0x1) << GMAC_IDR_RLEX_Pos)
+#define GMAC_IDR_TFC_Pos 6 /**< \brief (GMAC_IDR) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_IDR_TFC (_U_(0x1) << GMAC_IDR_TFC_Pos)
+#define GMAC_IDR_TCOMP_Pos 7 /**< \brief (GMAC_IDR) Transmit Complete */
+#define GMAC_IDR_TCOMP (_U_(0x1) << GMAC_IDR_TCOMP_Pos)
+#define GMAC_IDR_ROVR_Pos 10 /**< \brief (GMAC_IDR) Receive Overrun */
+#define GMAC_IDR_ROVR (_U_(0x1) << GMAC_IDR_ROVR_Pos)
+#define GMAC_IDR_HRESP_Pos 11 /**< \brief (GMAC_IDR) HRESP Not OK */
+#define GMAC_IDR_HRESP (_U_(0x1) << GMAC_IDR_HRESP_Pos)
+#define GMAC_IDR_PFNZ_Pos 12 /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */
+#define GMAC_IDR_PFNZ (_U_(0x1) << GMAC_IDR_PFNZ_Pos)
+#define GMAC_IDR_PTZ_Pos 13 /**< \brief (GMAC_IDR) Pause Time Zero */
+#define GMAC_IDR_PTZ (_U_(0x1) << GMAC_IDR_PTZ_Pos)
+#define GMAC_IDR_PFTR_Pos 14 /**< \brief (GMAC_IDR) Pause Frame Transmitted */
+#define GMAC_IDR_PFTR (_U_(0x1) << GMAC_IDR_PFTR_Pos)
+#define GMAC_IDR_EXINT_Pos 15 /**< \brief (GMAC_IDR) External Interrupt */
+#define GMAC_IDR_EXINT (_U_(0x1) << GMAC_IDR_EXINT_Pos)
+#define GMAC_IDR_DRQFR_Pos 18 /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */
+#define GMAC_IDR_DRQFR (_U_(0x1) << GMAC_IDR_DRQFR_Pos)
+#define GMAC_IDR_SFR_Pos 19 /**< \brief (GMAC_IDR) PTP Sync Frame Received */
+#define GMAC_IDR_SFR (_U_(0x1) << GMAC_IDR_SFR_Pos)
+#define GMAC_IDR_DRQFT_Pos 20 /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */
+#define GMAC_IDR_DRQFT (_U_(0x1) << GMAC_IDR_DRQFT_Pos)
+#define GMAC_IDR_SFT_Pos 21 /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */
+#define GMAC_IDR_SFT (_U_(0x1) << GMAC_IDR_SFT_Pos)
+#define GMAC_IDR_PDRQFR_Pos 22 /**< \brief (GMAC_IDR) PDelay Request Frame Received */
+#define GMAC_IDR_PDRQFR (_U_(0x1) << GMAC_IDR_PDRQFR_Pos)
+#define GMAC_IDR_PDRSFR_Pos 23 /**< \brief (GMAC_IDR) PDelay Response Frame Received */
+#define GMAC_IDR_PDRSFR (_U_(0x1) << GMAC_IDR_PDRSFR_Pos)
+#define GMAC_IDR_PDRQFT_Pos 24 /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */
+#define GMAC_IDR_PDRQFT (_U_(0x1) << GMAC_IDR_PDRQFT_Pos)
+#define GMAC_IDR_PDRSFT_Pos 25 /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */
+#define GMAC_IDR_PDRSFT (_U_(0x1) << GMAC_IDR_PDRSFT_Pos)
+#define GMAC_IDR_SRI_Pos 26 /**< \brief (GMAC_IDR) TSU Seconds Register Increment */
+#define GMAC_IDR_SRI (_U_(0x1) << GMAC_IDR_SRI_Pos)
+#define GMAC_IDR_WOL_Pos 28 /**< \brief (GMAC_IDR) Wake On LAN */
+#define GMAC_IDR_WOL (_U_(0x1) << GMAC_IDR_WOL_Pos)
+#define GMAC_IDR_TSUCMP_Pos 29 /**< \brief (GMAC_IDR) Tsu timer comparison */
+#define GMAC_IDR_TSUCMP (_U_(0x1) << GMAC_IDR_TSUCMP_Pos)
+#define GMAC_IDR_MASK _U_(0x37FCFCFF) /**< \brief (GMAC_IDR) MASK Register */
+
+/* -------- GMAC_IMR : (GMAC Offset: 0x030) (R/ 32) Interrupt Mask Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MFS:1; /*!< bit: 0 Management Frame Sent */
+ uint32_t RCOMP:1; /*!< bit: 1 Receive Complete */
+ uint32_t RXUBR:1; /*!< bit: 2 RX Used Bit Read */
+ uint32_t TXUBR:1; /*!< bit: 3 TX Used Bit Read */
+ uint32_t TUR:1; /*!< bit: 4 Transmit Underrun */
+ uint32_t RLEX:1; /*!< bit: 5 Retry Limit Exceeded */
+ uint32_t TFC:1; /*!< bit: 6 Transmit Frame Corruption Due to AHB Error */
+ uint32_t TCOMP:1; /*!< bit: 7 Transmit Complete */
+ uint32_t :2; /*!< bit: 8.. 9 Reserved */
+ uint32_t ROVR:1; /*!< bit: 10 Receive Overrun */
+ uint32_t HRESP:1; /*!< bit: 11 HRESP Not OK */
+ uint32_t PFNZ:1; /*!< bit: 12 Pause Frame with Non-zero Pause Quantum Received */
+ uint32_t PTZ:1; /*!< bit: 13 Pause Time Zero */
+ uint32_t PFTR:1; /*!< bit: 14 Pause Frame Transmitted */
+ uint32_t EXINT:1; /*!< bit: 15 External Interrupt */
+ uint32_t :2; /*!< bit: 16..17 Reserved */
+ uint32_t DRQFR:1; /*!< bit: 18 PTP Delay Request Frame Received */
+ uint32_t SFR:1; /*!< bit: 19 PTP Sync Frame Received */
+ uint32_t DRQFT:1; /*!< bit: 20 PTP Delay Request Frame Transmitted */
+ uint32_t SFT:1; /*!< bit: 21 PTP Sync Frame Transmitted */
+ uint32_t PDRQFR:1; /*!< bit: 22 PDelay Request Frame Received */
+ uint32_t PDRSFR:1; /*!< bit: 23 PDelay Response Frame Received */
+ uint32_t PDRQFT:1; /*!< bit: 24 PDelay Request Frame Transmitted */
+ uint32_t PDRSFT:1; /*!< bit: 25 PDelay Response Frame Transmitted */
+ uint32_t SRI:1; /*!< bit: 26 TSU Seconds Register Increment */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t WOL:1; /*!< bit: 28 Wake On Lan */
+ uint32_t TSUCMP:1; /*!< bit: 29 Tsu timer comparison */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_IMR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_IMR_OFFSET 0x030 /**< \brief (GMAC_IMR offset) Interrupt Mask Register */
+#define GMAC_IMR_RESETVALUE _U_(0x3FFFFFFF) /**< \brief (GMAC_IMR reset_value) Interrupt Mask Register */
+
+#define GMAC_IMR_MFS_Pos 0 /**< \brief (GMAC_IMR) Management Frame Sent */
+#define GMAC_IMR_MFS (_U_(0x1) << GMAC_IMR_MFS_Pos)
+#define GMAC_IMR_RCOMP_Pos 1 /**< \brief (GMAC_IMR) Receive Complete */
+#define GMAC_IMR_RCOMP (_U_(0x1) << GMAC_IMR_RCOMP_Pos)
+#define GMAC_IMR_RXUBR_Pos 2 /**< \brief (GMAC_IMR) RX Used Bit Read */
+#define GMAC_IMR_RXUBR (_U_(0x1) << GMAC_IMR_RXUBR_Pos)
+#define GMAC_IMR_TXUBR_Pos 3 /**< \brief (GMAC_IMR) TX Used Bit Read */
+#define GMAC_IMR_TXUBR (_U_(0x1) << GMAC_IMR_TXUBR_Pos)
+#define GMAC_IMR_TUR_Pos 4 /**< \brief (GMAC_IMR) Transmit Underrun */
+#define GMAC_IMR_TUR (_U_(0x1) << GMAC_IMR_TUR_Pos)
+#define GMAC_IMR_RLEX_Pos 5 /**< \brief (GMAC_IMR) Retry Limit Exceeded */
+#define GMAC_IMR_RLEX (_U_(0x1) << GMAC_IMR_RLEX_Pos)
+#define GMAC_IMR_TFC_Pos 6 /**< \brief (GMAC_IMR) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_IMR_TFC (_U_(0x1) << GMAC_IMR_TFC_Pos)
+#define GMAC_IMR_TCOMP_Pos 7 /**< \brief (GMAC_IMR) Transmit Complete */
+#define GMAC_IMR_TCOMP (_U_(0x1) << GMAC_IMR_TCOMP_Pos)
+#define GMAC_IMR_ROVR_Pos 10 /**< \brief (GMAC_IMR) Receive Overrun */
+#define GMAC_IMR_ROVR (_U_(0x1) << GMAC_IMR_ROVR_Pos)
+#define GMAC_IMR_HRESP_Pos 11 /**< \brief (GMAC_IMR) HRESP Not OK */
+#define GMAC_IMR_HRESP (_U_(0x1) << GMAC_IMR_HRESP_Pos)
+#define GMAC_IMR_PFNZ_Pos 12 /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */
+#define GMAC_IMR_PFNZ (_U_(0x1) << GMAC_IMR_PFNZ_Pos)
+#define GMAC_IMR_PTZ_Pos 13 /**< \brief (GMAC_IMR) Pause Time Zero */
+#define GMAC_IMR_PTZ (_U_(0x1) << GMAC_IMR_PTZ_Pos)
+#define GMAC_IMR_PFTR_Pos 14 /**< \brief (GMAC_IMR) Pause Frame Transmitted */
+#define GMAC_IMR_PFTR (_U_(0x1) << GMAC_IMR_PFTR_Pos)
+#define GMAC_IMR_EXINT_Pos 15 /**< \brief (GMAC_IMR) External Interrupt */
+#define GMAC_IMR_EXINT (_U_(0x1) << GMAC_IMR_EXINT_Pos)
+#define GMAC_IMR_DRQFR_Pos 18 /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */
+#define GMAC_IMR_DRQFR (_U_(0x1) << GMAC_IMR_DRQFR_Pos)
+#define GMAC_IMR_SFR_Pos 19 /**< \brief (GMAC_IMR) PTP Sync Frame Received */
+#define GMAC_IMR_SFR (_U_(0x1) << GMAC_IMR_SFR_Pos)
+#define GMAC_IMR_DRQFT_Pos 20 /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */
+#define GMAC_IMR_DRQFT (_U_(0x1) << GMAC_IMR_DRQFT_Pos)
+#define GMAC_IMR_SFT_Pos 21 /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */
+#define GMAC_IMR_SFT (_U_(0x1) << GMAC_IMR_SFT_Pos)
+#define GMAC_IMR_PDRQFR_Pos 22 /**< \brief (GMAC_IMR) PDelay Request Frame Received */
+#define GMAC_IMR_PDRQFR (_U_(0x1) << GMAC_IMR_PDRQFR_Pos)
+#define GMAC_IMR_PDRSFR_Pos 23 /**< \brief (GMAC_IMR) PDelay Response Frame Received */
+#define GMAC_IMR_PDRSFR (_U_(0x1) << GMAC_IMR_PDRSFR_Pos)
+#define GMAC_IMR_PDRQFT_Pos 24 /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */
+#define GMAC_IMR_PDRQFT (_U_(0x1) << GMAC_IMR_PDRQFT_Pos)
+#define GMAC_IMR_PDRSFT_Pos 25 /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */
+#define GMAC_IMR_PDRSFT (_U_(0x1) << GMAC_IMR_PDRSFT_Pos)
+#define GMAC_IMR_SRI_Pos 26 /**< \brief (GMAC_IMR) TSU Seconds Register Increment */
+#define GMAC_IMR_SRI (_U_(0x1) << GMAC_IMR_SRI_Pos)
+#define GMAC_IMR_WOL_Pos 28 /**< \brief (GMAC_IMR) Wake On Lan */
+#define GMAC_IMR_WOL (_U_(0x1) << GMAC_IMR_WOL_Pos)
+#define GMAC_IMR_TSUCMP_Pos 29 /**< \brief (GMAC_IMR) Tsu timer comparison */
+#define GMAC_IMR_TSUCMP (_U_(0x1) << GMAC_IMR_TSUCMP_Pos)
+#define GMAC_IMR_MASK _U_(0x37FCFCFF) /**< \brief (GMAC_IMR) MASK Register */
+
+/* -------- GMAC_MAN : (GMAC Offset: 0x034) (R/W 32) PHY Maintenance Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:16; /*!< bit: 0..15 PHY Data */
+ uint32_t WTN:2; /*!< bit: 16..17 Write Ten */
+ uint32_t REGA:5; /*!< bit: 18..22 Register Address */
+ uint32_t PHYA:5; /*!< bit: 23..27 PHY Address */
+ uint32_t OP:2; /*!< bit: 28..29 Operation */
+ uint32_t CLTTO:1; /*!< bit: 30 Clause 22 Operation */
+ uint32_t WZO:1; /*!< bit: 31 Write ZERO */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_MAN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_MAN_OFFSET 0x034 /**< \brief (GMAC_MAN offset) PHY Maintenance Register */
+#define GMAC_MAN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_MAN reset_value) PHY Maintenance Register */
+
+#define GMAC_MAN_DATA_Pos 0 /**< \brief (GMAC_MAN) PHY Data */
+#define GMAC_MAN_DATA_Msk (_U_(0xFFFF) << GMAC_MAN_DATA_Pos)
+#define GMAC_MAN_DATA(value) (GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))
+#define GMAC_MAN_WTN_Pos 16 /**< \brief (GMAC_MAN) Write Ten */
+#define GMAC_MAN_WTN_Msk (_U_(0x3) << GMAC_MAN_WTN_Pos)
+#define GMAC_MAN_WTN(value) (GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))
+#define GMAC_MAN_REGA_Pos 18 /**< \brief (GMAC_MAN) Register Address */
+#define GMAC_MAN_REGA_Msk (_U_(0x1F) << GMAC_MAN_REGA_Pos)
+#define GMAC_MAN_REGA(value) (GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))
+#define GMAC_MAN_PHYA_Pos 23 /**< \brief (GMAC_MAN) PHY Address */
+#define GMAC_MAN_PHYA_Msk (_U_(0x1F) << GMAC_MAN_PHYA_Pos)
+#define GMAC_MAN_PHYA(value) (GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))
+#define GMAC_MAN_OP_Pos 28 /**< \brief (GMAC_MAN) Operation */
+#define GMAC_MAN_OP_Msk (_U_(0x3) << GMAC_MAN_OP_Pos)
+#define GMAC_MAN_OP(value) (GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))
+#define GMAC_MAN_CLTTO_Pos 30 /**< \brief (GMAC_MAN) Clause 22 Operation */
+#define GMAC_MAN_CLTTO (_U_(0x1) << GMAC_MAN_CLTTO_Pos)
+#define GMAC_MAN_WZO_Pos 31 /**< \brief (GMAC_MAN) Write ZERO */
+#define GMAC_MAN_WZO (_U_(0x1) << GMAC_MAN_WZO_Pos)
+#define GMAC_MAN_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_MAN) MASK Register */
+
+/* -------- GMAC_RPQ : (GMAC Offset: 0x038) (R/ 32) Received Pause Quantum Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RPQ:16; /*!< bit: 0..15 Received Pause Quantum */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_RPQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RPQ_OFFSET 0x038 /**< \brief (GMAC_RPQ offset) Received Pause Quantum Register */
+#define GMAC_RPQ_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RPQ reset_value) Received Pause Quantum Register */
+
+#define GMAC_RPQ_RPQ_Pos 0 /**< \brief (GMAC_RPQ) Received Pause Quantum */
+#define GMAC_RPQ_RPQ_Msk (_U_(0xFFFF) << GMAC_RPQ_RPQ_Pos)
+#define GMAC_RPQ_RPQ(value) (GMAC_RPQ_RPQ_Msk & ((value) << GMAC_RPQ_RPQ_Pos))
+#define GMAC_RPQ_MASK _U_(0x0000FFFF) /**< \brief (GMAC_RPQ) MASK Register */
+
+/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) (R/W 32) Transmit Pause Quantum Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TPQ:16; /*!< bit: 0..15 Transmit Pause Quantum */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TPQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TPQ_OFFSET 0x03C /**< \brief (GMAC_TPQ offset) Transmit Pause Quantum Register */
+#define GMAC_TPQ_RESETVALUE _U_(0x0000FFFF) /**< \brief (GMAC_TPQ reset_value) Transmit Pause Quantum Register */
+
+#define GMAC_TPQ_TPQ_Pos 0 /**< \brief (GMAC_TPQ) Transmit Pause Quantum */
+#define GMAC_TPQ_TPQ_Msk (_U_(0xFFFF) << GMAC_TPQ_TPQ_Pos)
+#define GMAC_TPQ_TPQ(value) (GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))
+#define GMAC_TPQ_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TPQ) MASK Register */
+
+/* -------- GMAC_TPSF : (GMAC Offset: 0x040) (R/W 32) TX partial store and forward Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TPB1ADR:10; /*!< bit: 0.. 9 TX packet buffer address */
+ uint32_t :21; /*!< bit: 10..30 Reserved */
+ uint32_t ENTXP:1; /*!< bit: 31 Enable TX partial store and forward operation */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TPSF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TPSF_OFFSET 0x040 /**< \brief (GMAC_TPSF offset) TX partial store and forward Register */
+#define GMAC_TPSF_RESETVALUE _U_(0x000003FF) /**< \brief (GMAC_TPSF reset_value) TX partial store and forward Register */
+
+#define GMAC_TPSF_TPB1ADR_Pos 0 /**< \brief (GMAC_TPSF) TX packet buffer address */
+#define GMAC_TPSF_TPB1ADR_Msk (_U_(0x3FF) << GMAC_TPSF_TPB1ADR_Pos)
+#define GMAC_TPSF_TPB1ADR(value) (GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos))
+#define GMAC_TPSF_ENTXP_Pos 31 /**< \brief (GMAC_TPSF) Enable TX partial store and forward operation */
+#define GMAC_TPSF_ENTXP (_U_(0x1) << GMAC_TPSF_ENTXP_Pos)
+#define GMAC_TPSF_MASK _U_(0x800003FF) /**< \brief (GMAC_TPSF) MASK Register */
+
+/* -------- GMAC_RPSF : (GMAC Offset: 0x044) (R/W 32) RX partial store and forward Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RPB1ADR:10; /*!< bit: 0.. 9 RX packet buffer address */
+ uint32_t :21; /*!< bit: 10..30 Reserved */
+ uint32_t ENRXP:1; /*!< bit: 31 Enable RX partial store and forward operation */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_RPSF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RPSF_OFFSET 0x044 /**< \brief (GMAC_RPSF offset) RX partial store and forward Register */
+#define GMAC_RPSF_RESETVALUE _U_(0x000003FF) /**< \brief (GMAC_RPSF reset_value) RX partial store and forward Register */
+
+#define GMAC_RPSF_RPB1ADR_Pos 0 /**< \brief (GMAC_RPSF) RX packet buffer address */
+#define GMAC_RPSF_RPB1ADR_Msk (_U_(0x3FF) << GMAC_RPSF_RPB1ADR_Pos)
+#define GMAC_RPSF_RPB1ADR(value) (GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos))
+#define GMAC_RPSF_ENRXP_Pos 31 /**< \brief (GMAC_RPSF) Enable RX partial store and forward operation */
+#define GMAC_RPSF_ENRXP (_U_(0x1) << GMAC_RPSF_ENRXP_Pos)
+#define GMAC_RPSF_MASK _U_(0x800003FF) /**< \brief (GMAC_RPSF) MASK Register */
+
+/* -------- GMAC_RJFML : (GMAC Offset: 0x048) (R/W 32) RX Jumbo Frame Max Length Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FML:14; /*!< bit: 0..13 Frame Max Length */
+ uint32_t :18; /*!< bit: 14..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_RJFML_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RJFML_OFFSET 0x048 /**< \brief (GMAC_RJFML offset) RX Jumbo Frame Max Length Register */
+#define GMAC_RJFML_RESETVALUE _U_(0x00003FFF) /**< \brief (GMAC_RJFML reset_value) RX Jumbo Frame Max Length Register */
+
+#define GMAC_RJFML_FML_Pos 0 /**< \brief (GMAC_RJFML) Frame Max Length */
+#define GMAC_RJFML_FML_Msk (_U_(0x3FFF) << GMAC_RJFML_FML_Pos)
+#define GMAC_RJFML_FML(value) (GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos))
+#define GMAC_RJFML_MASK _U_(0x00003FFF) /**< \brief (GMAC_RJFML) MASK Register */
+
+/* -------- GMAC_HRB : (GMAC Offset: 0x080) (R/W 32) Hash Register Bottom [31:0] -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Hash Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_HRB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_HRB_OFFSET 0x080 /**< \brief (GMAC_HRB offset) Hash Register Bottom [31:0] */
+#define GMAC_HRB_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_HRB reset_value) Hash Register Bottom [31:0] */
+
+#define GMAC_HRB_ADDR_Pos 0 /**< \brief (GMAC_HRB) Hash Address */
+#define GMAC_HRB_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_HRB_ADDR_Pos)
+#define GMAC_HRB_ADDR(value) (GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))
+#define GMAC_HRB_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_HRB) MASK Register */
+
+/* -------- GMAC_HRT : (GMAC Offset: 0x084) (R/W 32) Hash Register Top [63:32] -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Hash Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_HRT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_HRT_OFFSET 0x084 /**< \brief (GMAC_HRT offset) Hash Register Top [63:32] */
+#define GMAC_HRT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_HRT reset_value) Hash Register Top [63:32] */
+
+#define GMAC_HRT_ADDR_Pos 0 /**< \brief (GMAC_HRT) Hash Address */
+#define GMAC_HRT_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_HRT_ADDR_Pos)
+#define GMAC_HRT_ADDR(value) (GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))
+#define GMAC_HRT_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_HRT) MASK Register */
+
+/* -------- GMAC_SAB : (GMAC Offset: 0x088) (R/W 32) SA Specific Address Bottom [31:0] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Specific Address 1 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_SAB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SAB_OFFSET 0x088 /**< \brief (GMAC_SAB offset) Specific Address Bottom [31:0] Register */
+#define GMAC_SAB_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SAB reset_value) Specific Address Bottom [31:0] Register */
+
+#define GMAC_SAB_ADDR_Pos 0 /**< \brief (GMAC_SAB) Specific Address 1 */
+#define GMAC_SAB_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_SAB_ADDR_Pos)
+#define GMAC_SAB_ADDR(value) (GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos))
+#define GMAC_SAB_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_SAB) MASK Register */
+
+/* -------- GMAC_SAT : (GMAC Offset: 0x08C) (R/W 32) SA Specific Address Top [47:32] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:16; /*!< bit: 0..15 Specific Address 1 */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_SAT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SAT_OFFSET 0x08C /**< \brief (GMAC_SAT offset) Specific Address Top [47:32] Register */
+#define GMAC_SAT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SAT reset_value) Specific Address Top [47:32] Register */
+
+#define GMAC_SAT_ADDR_Pos 0 /**< \brief (GMAC_SAT) Specific Address 1 */
+#define GMAC_SAT_ADDR_Msk (_U_(0xFFFF) << GMAC_SAT_ADDR_Pos)
+#define GMAC_SAT_ADDR(value) (GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos))
+#define GMAC_SAT_MASK _U_(0x0000FFFF) /**< \brief (GMAC_SAT) MASK Register */
+
+/* -------- GMAC_TIDM : (GMAC Offset: 0x0A8) (R/W 32) Type ID Match Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TID:16; /*!< bit: 0..15 Type ID Match 1 */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TIDM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TIDM_OFFSET 0x0A8 /**< \brief (GMAC_TIDM offset) Type ID Match Register */
+#define GMAC_TIDM_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TIDM reset_value) Type ID Match Register */
+
+#define GMAC_TIDM_TID_Pos 0 /**< \brief (GMAC_TIDM) Type ID Match 1 */
+#define GMAC_TIDM_TID_Msk (_U_(0xFFFF) << GMAC_TIDM_TID_Pos)
+#define GMAC_TIDM_TID(value) (GMAC_TIDM_TID_Msk & ((value) << GMAC_TIDM_TID_Pos))
+#define GMAC_TIDM_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TIDM) MASK Register */
+
+/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) (R/W 32) Wake on LAN -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t IP:16; /*!< bit: 0..15 IP address */
+ uint32_t MAG:1; /*!< bit: 16 Event enable */
+ uint32_t ARP:1; /*!< bit: 17 LAN ARP req */
+ uint32_t SA1:1; /*!< bit: 18 WOL specific address reg 1 */
+ uint32_t MTI:1; /*!< bit: 19 WOL LAN multicast */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_WOL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_WOL_OFFSET 0x0B8 /**< \brief (GMAC_WOL offset) Wake on LAN */
+#define GMAC_WOL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_WOL reset_value) Wake on LAN */
+
+#define GMAC_WOL_IP_Pos 0 /**< \brief (GMAC_WOL) IP address */
+#define GMAC_WOL_IP_Msk (_U_(0xFFFF) << GMAC_WOL_IP_Pos)
+#define GMAC_WOL_IP(value) (GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos))
+#define GMAC_WOL_MAG_Pos 16 /**< \brief (GMAC_WOL) Event enable */
+#define GMAC_WOL_MAG (_U_(0x1) << GMAC_WOL_MAG_Pos)
+#define GMAC_WOL_ARP_Pos 17 /**< \brief (GMAC_WOL) LAN ARP req */
+#define GMAC_WOL_ARP (_U_(0x1) << GMAC_WOL_ARP_Pos)
+#define GMAC_WOL_SA1_Pos 18 /**< \brief (GMAC_WOL) WOL specific address reg 1 */
+#define GMAC_WOL_SA1 (_U_(0x1) << GMAC_WOL_SA1_Pos)
+#define GMAC_WOL_MTI_Pos 19 /**< \brief (GMAC_WOL) WOL LAN multicast */
+#define GMAC_WOL_MTI (_U_(0x1) << GMAC_WOL_MTI_Pos)
+#define GMAC_WOL_MASK _U_(0x000FFFFF) /**< \brief (GMAC_WOL) MASK Register */
+
+/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) (R/W 32) IPG Stretch Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FL:16; /*!< bit: 0..15 Frame Length */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_IPGS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_IPGS_OFFSET 0x0BC /**< \brief (GMAC_IPGS offset) IPG Stretch Register */
+#define GMAC_IPGS_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_IPGS reset_value) IPG Stretch Register */
+
+#define GMAC_IPGS_FL_Pos 0 /**< \brief (GMAC_IPGS) Frame Length */
+#define GMAC_IPGS_FL_Msk (_U_(0xFFFF) << GMAC_IPGS_FL_Pos)
+#define GMAC_IPGS_FL(value) (GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))
+#define GMAC_IPGS_MASK _U_(0x0000FFFF) /**< \brief (GMAC_IPGS) MASK Register */
+
+/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) (R/W 32) Stacked VLAN Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t VLAN_TYPE:16; /*!< bit: 0..15 User Defined VLAN_TYPE Field */
+ uint32_t :15; /*!< bit: 16..30 Reserved */
+ uint32_t ESVLAN:1; /*!< bit: 31 Enable Stacked VLAN Processing Mode */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_SVLAN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SVLAN_OFFSET 0x0C0 /**< \brief (GMAC_SVLAN offset) Stacked VLAN Register */
+#define GMAC_SVLAN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SVLAN reset_value) Stacked VLAN Register */
+
+#define GMAC_SVLAN_VLAN_TYPE_Pos 0 /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */
+#define GMAC_SVLAN_VLAN_TYPE_Msk (_U_(0xFFFF) << GMAC_SVLAN_VLAN_TYPE_Pos)
+#define GMAC_SVLAN_VLAN_TYPE(value) (GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))
+#define GMAC_SVLAN_ESVLAN_Pos 31 /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */
+#define GMAC_SVLAN_ESVLAN (_U_(0x1) << GMAC_SVLAN_ESVLAN_Pos)
+#define GMAC_SVLAN_MASK _U_(0x8000FFFF) /**< \brief (GMAC_SVLAN) MASK Register */
+
+/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) (R/W 32) Transmit PFC Pause Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PEV:8; /*!< bit: 0.. 7 Priority Enable Vector */
+ uint32_t PQ:8; /*!< bit: 8..15 Pause Quantum */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TPFCP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TPFCP_OFFSET 0x0C4 /**< \brief (GMAC_TPFCP offset) Transmit PFC Pause Register */
+#define GMAC_TPFCP_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TPFCP reset_value) Transmit PFC Pause Register */
+
+#define GMAC_TPFCP_PEV_Pos 0 /**< \brief (GMAC_TPFCP) Priority Enable Vector */
+#define GMAC_TPFCP_PEV_Msk (_U_(0xFF) << GMAC_TPFCP_PEV_Pos)
+#define GMAC_TPFCP_PEV(value) (GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))
+#define GMAC_TPFCP_PQ_Pos 8 /**< \brief (GMAC_TPFCP) Pause Quantum */
+#define GMAC_TPFCP_PQ_Msk (_U_(0xFF) << GMAC_TPFCP_PQ_Pos)
+#define GMAC_TPFCP_PQ(value) (GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))
+#define GMAC_TPFCP_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TPFCP) MASK Register */
+
+/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) (R/W 32) Specific Address 1 Mask Bottom [31:0] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Specific Address 1 Mask */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_SAMB1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SAMB1_OFFSET 0x0C8 /**< \brief (GMAC_SAMB1 offset) Specific Address 1 Mask Bottom [31:0] Register */
+#define GMAC_SAMB1_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SAMB1 reset_value) Specific Address 1 Mask Bottom [31:0] Register */
+
+#define GMAC_SAMB1_ADDR_Pos 0 /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */
+#define GMAC_SAMB1_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_SAMB1_ADDR_Pos)
+#define GMAC_SAMB1_ADDR(value) (GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))
+#define GMAC_SAMB1_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_SAMB1) MASK Register */
+
+/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) (R/W 32) Specific Address 1 Mask Top [47:32] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:16; /*!< bit: 0..15 Specific Address 1 Mask */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_SAMT1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SAMT1_OFFSET 0x0CC /**< \brief (GMAC_SAMT1 offset) Specific Address 1 Mask Top [47:32] Register */
+#define GMAC_SAMT1_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SAMT1 reset_value) Specific Address 1 Mask Top [47:32] Register */
+
+#define GMAC_SAMT1_ADDR_Pos 0 /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */
+#define GMAC_SAMT1_ADDR_Msk (_U_(0xFFFF) << GMAC_SAMT1_ADDR_Pos)
+#define GMAC_SAMT1_ADDR(value) (GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))
+#define GMAC_SAMT1_MASK _U_(0x0000FFFF) /**< \brief (GMAC_SAMT1) MASK Register */
+
+/* -------- GMAC_NSC : (GMAC Offset: 0x0DC) (R/W 32) Tsu timer comparison nanoseconds Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NANOSEC:21; /*!< bit: 0..20 1588 Timer Nanosecond comparison value */
+ uint32_t :11; /*!< bit: 21..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_NSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_NSC_OFFSET 0x0DC /**< \brief (GMAC_NSC offset) Tsu timer comparison nanoseconds Register */
+#define GMAC_NSC_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_NSC reset_value) Tsu timer comparison nanoseconds Register */
+
+#define GMAC_NSC_NANOSEC_Pos 0 /**< \brief (GMAC_NSC) 1588 Timer Nanosecond comparison value */
+#define GMAC_NSC_NANOSEC_Msk (_U_(0x1FFFFF) << GMAC_NSC_NANOSEC_Pos)
+#define GMAC_NSC_NANOSEC(value) (GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos))
+#define GMAC_NSC_MASK _U_(0x001FFFFF) /**< \brief (GMAC_NSC) MASK Register */
+
+/* -------- GMAC_SCL : (GMAC Offset: 0x0E0) (R/W 32) Tsu timer second comparison Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SEC:32; /*!< bit: 0..31 1588 Timer Second comparison value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_SCL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SCL_OFFSET 0x0E0 /**< \brief (GMAC_SCL offset) Tsu timer second comparison Register */
+#define GMAC_SCL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SCL reset_value) Tsu timer second comparison Register */
+
+#define GMAC_SCL_SEC_Pos 0 /**< \brief (GMAC_SCL) 1588 Timer Second comparison value */
+#define GMAC_SCL_SEC_Msk (_U_(0xFFFFFFFF) << GMAC_SCL_SEC_Pos)
+#define GMAC_SCL_SEC(value) (GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos))
+#define GMAC_SCL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_SCL) MASK Register */
+
+/* -------- GMAC_SCH : (GMAC Offset: 0x0E4) (R/W 32) Tsu timer second comparison Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SEC:16; /*!< bit: 0..15 1588 Timer Second comparison value */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_SCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SCH_OFFSET 0x0E4 /**< \brief (GMAC_SCH offset) Tsu timer second comparison Register */
+#define GMAC_SCH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SCH reset_value) Tsu timer second comparison Register */
+
+#define GMAC_SCH_SEC_Pos 0 /**< \brief (GMAC_SCH) 1588 Timer Second comparison value */
+#define GMAC_SCH_SEC_Msk (_U_(0xFFFF) << GMAC_SCH_SEC_Pos)
+#define GMAC_SCH_SEC(value) (GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos))
+#define GMAC_SCH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_SCH) MASK Register */
+
+/* -------- GMAC_EFTSH : (GMAC Offset: 0x0E8) (R/ 32) PTP Event Frame Transmitted Seconds High Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:16; /*!< bit: 0..15 Register Update */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_EFTSH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EFTSH_OFFSET 0x0E8 /**< \brief (GMAC_EFTSH offset) PTP Event Frame Transmitted Seconds High Register */
+#define GMAC_EFTSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFTSH reset_value) PTP Event Frame Transmitted Seconds High Register */
+
+#define GMAC_EFTSH_RUD_Pos 0 /**< \brief (GMAC_EFTSH) Register Update */
+#define GMAC_EFTSH_RUD_Msk (_U_(0xFFFF) << GMAC_EFTSH_RUD_Pos)
+#define GMAC_EFTSH_RUD(value) (GMAC_EFTSH_RUD_Msk & ((value) << GMAC_EFTSH_RUD_Pos))
+#define GMAC_EFTSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_EFTSH) MASK Register */
+
+/* -------- GMAC_EFRSH : (GMAC Offset: 0x0EC) (R/ 32) PTP Event Frame Received Seconds High Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:16; /*!< bit: 0..15 Register Update */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_EFRSH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EFRSH_OFFSET 0x0EC /**< \brief (GMAC_EFRSH offset) PTP Event Frame Received Seconds High Register */
+#define GMAC_EFRSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFRSH reset_value) PTP Event Frame Received Seconds High Register */
+
+#define GMAC_EFRSH_RUD_Pos 0 /**< \brief (GMAC_EFRSH) Register Update */
+#define GMAC_EFRSH_RUD_Msk (_U_(0xFFFF) << GMAC_EFRSH_RUD_Pos)
+#define GMAC_EFRSH_RUD(value) (GMAC_EFRSH_RUD_Msk & ((value) << GMAC_EFRSH_RUD_Pos))
+#define GMAC_EFRSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_EFRSH) MASK Register */
+
+/* -------- GMAC_PEFTSH : (GMAC Offset: 0x0F0) (R/ 32) PTP Peer Event Frame Transmitted Seconds High Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:16; /*!< bit: 0..15 Register Update */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_PEFTSH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PEFTSH_OFFSET 0x0F0 /**< \brief (GMAC_PEFTSH offset) PTP Peer Event Frame Transmitted Seconds High Register */
+#define GMAC_PEFTSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFTSH reset_value) PTP Peer Event Frame Transmitted Seconds High Register */
+
+#define GMAC_PEFTSH_RUD_Pos 0 /**< \brief (GMAC_PEFTSH) Register Update */
+#define GMAC_PEFTSH_RUD_Msk (_U_(0xFFFF) << GMAC_PEFTSH_RUD_Pos)
+#define GMAC_PEFTSH_RUD(value) (GMAC_PEFTSH_RUD_Msk & ((value) << GMAC_PEFTSH_RUD_Pos))
+#define GMAC_PEFTSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_PEFTSH) MASK Register */
+
+/* -------- GMAC_PEFRSH : (GMAC Offset: 0x0F4) (R/ 32) PTP Peer Event Frame Received Seconds High Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:16; /*!< bit: 0..15 Register Update */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_PEFRSH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PEFRSH_OFFSET 0x0F4 /**< \brief (GMAC_PEFRSH offset) PTP Peer Event Frame Received Seconds High Register */
+#define GMAC_PEFRSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFRSH reset_value) PTP Peer Event Frame Received Seconds High Register */
+
+#define GMAC_PEFRSH_RUD_Pos 0 /**< \brief (GMAC_PEFRSH) Register Update */
+#define GMAC_PEFRSH_RUD_Msk (_U_(0xFFFF) << GMAC_PEFRSH_RUD_Pos)
+#define GMAC_PEFRSH_RUD(value) (GMAC_PEFRSH_RUD_Msk & ((value) << GMAC_PEFRSH_RUD_Pos))
+#define GMAC_PEFRSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_PEFRSH) MASK Register */
+
+/* -------- GMAC_OTLO : (GMAC Offset: 0x100) (R/ 32) Octets Transmitted [31:0] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TXO:32; /*!< bit: 0..31 Transmitted Octets */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_OTLO_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_OTLO_OFFSET 0x100 /**< \brief (GMAC_OTLO offset) Octets Transmitted [31:0] Register */
+#define GMAC_OTLO_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_OTLO reset_value) Octets Transmitted [31:0] Register */
+
+#define GMAC_OTLO_TXO_Pos 0 /**< \brief (GMAC_OTLO) Transmitted Octets */
+#define GMAC_OTLO_TXO_Msk (_U_(0xFFFFFFFF) << GMAC_OTLO_TXO_Pos)
+#define GMAC_OTLO_TXO(value) (GMAC_OTLO_TXO_Msk & ((value) << GMAC_OTLO_TXO_Pos))
+#define GMAC_OTLO_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_OTLO) MASK Register */
+
+/* -------- GMAC_OTHI : (GMAC Offset: 0x104) (R/ 32) Octets Transmitted [47:32] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TXO:16; /*!< bit: 0..15 Transmitted Octets */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_OTHI_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_OTHI_OFFSET 0x104 /**< \brief (GMAC_OTHI offset) Octets Transmitted [47:32] Register */
+#define GMAC_OTHI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_OTHI reset_value) Octets Transmitted [47:32] Register */
+
+#define GMAC_OTHI_TXO_Pos 0 /**< \brief (GMAC_OTHI) Transmitted Octets */
+#define GMAC_OTHI_TXO_Msk (_U_(0xFFFF) << GMAC_OTHI_TXO_Pos)
+#define GMAC_OTHI_TXO(value) (GMAC_OTHI_TXO_Msk & ((value) << GMAC_OTHI_TXO_Pos))
+#define GMAC_OTHI_MASK _U_(0x0000FFFF) /**< \brief (GMAC_OTHI) MASK Register */
+
+/* -------- GMAC_FT : (GMAC Offset: 0x108) (R/ 32) Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FTX:32; /*!< bit: 0..31 Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_FT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_FT_OFFSET 0x108 /**< \brief (GMAC_FT offset) Frames Transmitted Register */
+#define GMAC_FT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_FT reset_value) Frames Transmitted Register */
+
+#define GMAC_FT_FTX_Pos 0 /**< \brief (GMAC_FT) Frames Transmitted without Error */
+#define GMAC_FT_FTX_Msk (_U_(0xFFFFFFFF) << GMAC_FT_FTX_Pos)
+#define GMAC_FT_FTX(value) (GMAC_FT_FTX_Msk & ((value) << GMAC_FT_FTX_Pos))
+#define GMAC_FT_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_FT) MASK Register */
+
+/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) (R/ 32) Broadcast Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BFTX:32; /*!< bit: 0..31 Broadcast Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_BCFT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_BCFT_OFFSET 0x10C /**< \brief (GMAC_BCFT offset) Broadcast Frames Transmitted Register */
+#define GMAC_BCFT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_BCFT reset_value) Broadcast Frames Transmitted Register */
+
+#define GMAC_BCFT_BFTX_Pos 0 /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */
+#define GMAC_BCFT_BFTX_Msk (_U_(0xFFFFFFFF) << GMAC_BCFT_BFTX_Pos)
+#define GMAC_BCFT_BFTX(value) (GMAC_BCFT_BFTX_Msk & ((value) << GMAC_BCFT_BFTX_Pos))
+#define GMAC_BCFT_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_BCFT) MASK Register */
+
+/* -------- GMAC_MFT : (GMAC Offset: 0x110) (R/ 32) Multicast Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MFTX:32; /*!< bit: 0..31 Multicast Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_MFT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_MFT_OFFSET 0x110 /**< \brief (GMAC_MFT offset) Multicast Frames Transmitted Register */
+#define GMAC_MFT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_MFT reset_value) Multicast Frames Transmitted Register */
+
+#define GMAC_MFT_MFTX_Pos 0 /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */
+#define GMAC_MFT_MFTX_Msk (_U_(0xFFFFFFFF) << GMAC_MFT_MFTX_Pos)
+#define GMAC_MFT_MFTX(value) (GMAC_MFT_MFTX_Msk & ((value) << GMAC_MFT_MFTX_Pos))
+#define GMAC_MFT_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_MFT) MASK Register */
+
+/* -------- GMAC_PFT : (GMAC Offset: 0x114) (R/ 32) Pause Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PFTX:16; /*!< bit: 0..15 Pause Frames Transmitted Register */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_PFT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PFT_OFFSET 0x114 /**< \brief (GMAC_PFT offset) Pause Frames Transmitted Register */
+#define GMAC_PFT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PFT reset_value) Pause Frames Transmitted Register */
+
+#define GMAC_PFT_PFTX_Pos 0 /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */
+#define GMAC_PFT_PFTX_Msk (_U_(0xFFFF) << GMAC_PFT_PFTX_Pos)
+#define GMAC_PFT_PFTX(value) (GMAC_PFT_PFTX_Msk & ((value) << GMAC_PFT_PFTX_Pos))
+#define GMAC_PFT_MASK _U_(0x0000FFFF) /**< \brief (GMAC_PFT) MASK Register */
+
+/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) (R/ 32) 64 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFTX:32; /*!< bit: 0..31 64 Byte Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_BFT64_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_BFT64_OFFSET 0x118 /**< \brief (GMAC_BFT64 offset) 64 Byte Frames Transmitted Register */
+#define GMAC_BFT64_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_BFT64 reset_value) 64 Byte Frames Transmitted Register */
+
+#define GMAC_BFT64_NFTX_Pos 0 /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */
+#define GMAC_BFT64_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_BFT64_NFTX_Pos)
+#define GMAC_BFT64_NFTX(value) (GMAC_BFT64_NFTX_Msk & ((value) << GMAC_BFT64_NFTX_Pos))
+#define GMAC_BFT64_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_BFT64) MASK Register */
+
+/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) (R/ 32) 65 to 127 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFTX:32; /*!< bit: 0..31 65 to 127 Byte Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFT127_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFT127_OFFSET 0x11C /**< \brief (GMAC_TBFT127 offset) 65 to 127 Byte Frames Transmitted Register */
+#define GMAC_TBFT127_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT127 reset_value) 65 to 127 Byte Frames Transmitted Register */
+
+#define GMAC_TBFT127_NFTX_Pos 0 /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */
+#define GMAC_TBFT127_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT127_NFTX_Pos)
+#define GMAC_TBFT127_NFTX(value) (GMAC_TBFT127_NFTX_Msk & ((value) << GMAC_TBFT127_NFTX_Pos))
+#define GMAC_TBFT127_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT127) MASK Register */
+
+/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) (R/ 32) 128 to 255 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFTX:32; /*!< bit: 0..31 128 to 255 Byte Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFT255_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFT255_OFFSET 0x120 /**< \brief (GMAC_TBFT255 offset) 128 to 255 Byte Frames Transmitted Register */
+#define GMAC_TBFT255_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT255 reset_value) 128 to 255 Byte Frames Transmitted Register */
+
+#define GMAC_TBFT255_NFTX_Pos 0 /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */
+#define GMAC_TBFT255_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT255_NFTX_Pos)
+#define GMAC_TBFT255_NFTX(value) (GMAC_TBFT255_NFTX_Msk & ((value) << GMAC_TBFT255_NFTX_Pos))
+#define GMAC_TBFT255_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT255) MASK Register */
+
+/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) (R/ 32) 256 to 511 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFTX:32; /*!< bit: 0..31 256 to 511 Byte Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFT511_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFT511_OFFSET 0x124 /**< \brief (GMAC_TBFT511 offset) 256 to 511 Byte Frames Transmitted Register */
+#define GMAC_TBFT511_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT511 reset_value) 256 to 511 Byte Frames Transmitted Register */
+
+#define GMAC_TBFT511_NFTX_Pos 0 /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */
+#define GMAC_TBFT511_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT511_NFTX_Pos)
+#define GMAC_TBFT511_NFTX(value) (GMAC_TBFT511_NFTX_Msk & ((value) << GMAC_TBFT511_NFTX_Pos))
+#define GMAC_TBFT511_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT511) MASK Register */
+
+/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) (R/ 32) 512 to 1023 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFTX:32; /*!< bit: 0..31 512 to 1023 Byte Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFT1023_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFT1023_OFFSET 0x128 /**< \brief (GMAC_TBFT1023 offset) 512 to 1023 Byte Frames Transmitted Register */
+#define GMAC_TBFT1023_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT1023 reset_value) 512 to 1023 Byte Frames Transmitted Register */
+
+#define GMAC_TBFT1023_NFTX_Pos 0 /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */
+#define GMAC_TBFT1023_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT1023_NFTX_Pos)
+#define GMAC_TBFT1023_NFTX(value) (GMAC_TBFT1023_NFTX_Msk & ((value) << GMAC_TBFT1023_NFTX_Pos))
+#define GMAC_TBFT1023_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT1023) MASK Register */
+
+/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) (R/ 32) 1024 to 1518 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFTX:32; /*!< bit: 0..31 1024 to 1518 Byte Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFT1518_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFT1518_OFFSET 0x12C /**< \brief (GMAC_TBFT1518 offset) 1024 to 1518 Byte Frames Transmitted Register */
+#define GMAC_TBFT1518_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT1518 reset_value) 1024 to 1518 Byte Frames Transmitted Register */
+
+#define GMAC_TBFT1518_NFTX_Pos 0 /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */
+#define GMAC_TBFT1518_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT1518_NFTX_Pos)
+#define GMAC_TBFT1518_NFTX(value) (GMAC_TBFT1518_NFTX_Msk & ((value) << GMAC_TBFT1518_NFTX_Pos))
+#define GMAC_TBFT1518_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT1518) MASK Register */
+
+/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) (R/ 32) Greater Than 1518 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFTX:32; /*!< bit: 0..31 Greater than 1518 Byte Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_GTBFT1518_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_GTBFT1518_OFFSET 0x130 /**< \brief (GMAC_GTBFT1518 offset) Greater Than 1518 Byte Frames Transmitted Register */
+#define GMAC_GTBFT1518_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_GTBFT1518 reset_value) Greater Than 1518 Byte Frames Transmitted Register */
+
+#define GMAC_GTBFT1518_NFTX_Pos 0 /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */
+#define GMAC_GTBFT1518_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_GTBFT1518_NFTX_Pos)
+#define GMAC_GTBFT1518_NFTX(value) (GMAC_GTBFT1518_NFTX_Msk & ((value) << GMAC_GTBFT1518_NFTX_Pos))
+#define GMAC_GTBFT1518_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_GTBFT1518) MASK Register */
+
+/* -------- GMAC_TUR : (GMAC Offset: 0x134) (R/ 32) Transmit Underruns Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TXUNR:10; /*!< bit: 0.. 9 Transmit Underruns */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TUR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TUR_OFFSET 0x134 /**< \brief (GMAC_TUR offset) Transmit Underruns Register */
+#define GMAC_TUR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TUR reset_value) Transmit Underruns Register */
+
+#define GMAC_TUR_TXUNR_Pos 0 /**< \brief (GMAC_TUR) Transmit Underruns */
+#define GMAC_TUR_TXUNR_Msk (_U_(0x3FF) << GMAC_TUR_TXUNR_Pos)
+#define GMAC_TUR_TXUNR(value) (GMAC_TUR_TXUNR_Msk & ((value) << GMAC_TUR_TXUNR_Pos))
+#define GMAC_TUR_MASK _U_(0x000003FF) /**< \brief (GMAC_TUR) MASK Register */
+
+/* -------- GMAC_SCF : (GMAC Offset: 0x138) (R/ 32) Single Collision Frames Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SCOL:18; /*!< bit: 0..17 Single Collision */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_SCF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SCF_OFFSET 0x138 /**< \brief (GMAC_SCF offset) Single Collision Frames Register */
+#define GMAC_SCF_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SCF reset_value) Single Collision Frames Register */
+
+#define GMAC_SCF_SCOL_Pos 0 /**< \brief (GMAC_SCF) Single Collision */
+#define GMAC_SCF_SCOL_Msk (_U_(0x3FFFF) << GMAC_SCF_SCOL_Pos)
+#define GMAC_SCF_SCOL(value) (GMAC_SCF_SCOL_Msk & ((value) << GMAC_SCF_SCOL_Pos))
+#define GMAC_SCF_MASK _U_(0x0003FFFF) /**< \brief (GMAC_SCF) MASK Register */
+
+/* -------- GMAC_MCF : (GMAC Offset: 0x13C) (R/ 32) Multiple Collision Frames Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MCOL:18; /*!< bit: 0..17 Multiple Collision */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_MCF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_MCF_OFFSET 0x13C /**< \brief (GMAC_MCF offset) Multiple Collision Frames Register */
+#define GMAC_MCF_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_MCF reset_value) Multiple Collision Frames Register */
+
+#define GMAC_MCF_MCOL_Pos 0 /**< \brief (GMAC_MCF) Multiple Collision */
+#define GMAC_MCF_MCOL_Msk (_U_(0x3FFFF) << GMAC_MCF_MCOL_Pos)
+#define GMAC_MCF_MCOL(value) (GMAC_MCF_MCOL_Msk & ((value) << GMAC_MCF_MCOL_Pos))
+#define GMAC_MCF_MASK _U_(0x0003FFFF) /**< \brief (GMAC_MCF) MASK Register */
+
+/* -------- GMAC_EC : (GMAC Offset: 0x140) (R/ 32) Excessive Collisions Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XCOL:10; /*!< bit: 0.. 9 Excessive Collisions */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_EC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EC_OFFSET 0x140 /**< \brief (GMAC_EC offset) Excessive Collisions Register */
+#define GMAC_EC_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EC reset_value) Excessive Collisions Register */
+
+#define GMAC_EC_XCOL_Pos 0 /**< \brief (GMAC_EC) Excessive Collisions */
+#define GMAC_EC_XCOL_Msk (_U_(0x3FF) << GMAC_EC_XCOL_Pos)
+#define GMAC_EC_XCOL(value) (GMAC_EC_XCOL_Msk & ((value) << GMAC_EC_XCOL_Pos))
+#define GMAC_EC_MASK _U_(0x000003FF) /**< \brief (GMAC_EC) MASK Register */
+
+/* -------- GMAC_LC : (GMAC Offset: 0x144) (R/ 32) Late Collisions Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LCOL:10; /*!< bit: 0.. 9 Late Collisions */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_LC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_LC_OFFSET 0x144 /**< \brief (GMAC_LC offset) Late Collisions Register */
+#define GMAC_LC_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_LC reset_value) Late Collisions Register */
+
+#define GMAC_LC_LCOL_Pos 0 /**< \brief (GMAC_LC) Late Collisions */
+#define GMAC_LC_LCOL_Msk (_U_(0x3FF) << GMAC_LC_LCOL_Pos)
+#define GMAC_LC_LCOL(value) (GMAC_LC_LCOL_Msk & ((value) << GMAC_LC_LCOL_Pos))
+#define GMAC_LC_MASK _U_(0x000003FF) /**< \brief (GMAC_LC) MASK Register */
+
+/* -------- GMAC_DTF : (GMAC Offset: 0x148) (R/ 32) Deferred Transmission Frames Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DEFT:18; /*!< bit: 0..17 Deferred Transmission */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_DTF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_DTF_OFFSET 0x148 /**< \brief (GMAC_DTF offset) Deferred Transmission Frames Register */
+#define GMAC_DTF_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_DTF reset_value) Deferred Transmission Frames Register */
+
+#define GMAC_DTF_DEFT_Pos 0 /**< \brief (GMAC_DTF) Deferred Transmission */
+#define GMAC_DTF_DEFT_Msk (_U_(0x3FFFF) << GMAC_DTF_DEFT_Pos)
+#define GMAC_DTF_DEFT(value) (GMAC_DTF_DEFT_Msk & ((value) << GMAC_DTF_DEFT_Pos))
+#define GMAC_DTF_MASK _U_(0x0003FFFF) /**< \brief (GMAC_DTF) MASK Register */
+
+/* -------- GMAC_CSE : (GMAC Offset: 0x14C) (R/ 32) Carrier Sense Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CSR:10; /*!< bit: 0.. 9 Carrier Sense Error */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_CSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_CSE_OFFSET 0x14C /**< \brief (GMAC_CSE offset) Carrier Sense Errors Register */
+#define GMAC_CSE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_CSE reset_value) Carrier Sense Errors Register */
+
+#define GMAC_CSE_CSR_Pos 0 /**< \brief (GMAC_CSE) Carrier Sense Error */
+#define GMAC_CSE_CSR_Msk (_U_(0x3FF) << GMAC_CSE_CSR_Pos)
+#define GMAC_CSE_CSR(value) (GMAC_CSE_CSR_Msk & ((value) << GMAC_CSE_CSR_Pos))
+#define GMAC_CSE_MASK _U_(0x000003FF) /**< \brief (GMAC_CSE) MASK Register */
+
+/* -------- GMAC_ORLO : (GMAC Offset: 0x150) (R/ 32) Octets Received [31:0] Received -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXO:32; /*!< bit: 0..31 Received Octets */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_ORLO_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_ORLO_OFFSET 0x150 /**< \brief (GMAC_ORLO offset) Octets Received [31:0] Received */
+#define GMAC_ORLO_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_ORLO reset_value) Octets Received [31:0] Received */
+
+#define GMAC_ORLO_RXO_Pos 0 /**< \brief (GMAC_ORLO) Received Octets */
+#define GMAC_ORLO_RXO_Msk (_U_(0xFFFFFFFF) << GMAC_ORLO_RXO_Pos)
+#define GMAC_ORLO_RXO(value) (GMAC_ORLO_RXO_Msk & ((value) << GMAC_ORLO_RXO_Pos))
+#define GMAC_ORLO_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_ORLO) MASK Register */
+
+/* -------- GMAC_ORHI : (GMAC Offset: 0x154) (R/ 32) Octets Received [47:32] Received -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXO:16; /*!< bit: 0..15 Received Octets */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_ORHI_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_ORHI_OFFSET 0x154 /**< \brief (GMAC_ORHI offset) Octets Received [47:32] Received */
+#define GMAC_ORHI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_ORHI reset_value) Octets Received [47:32] Received */
+
+#define GMAC_ORHI_RXO_Pos 0 /**< \brief (GMAC_ORHI) Received Octets */
+#define GMAC_ORHI_RXO_Msk (_U_(0xFFFF) << GMAC_ORHI_RXO_Pos)
+#define GMAC_ORHI_RXO(value) (GMAC_ORHI_RXO_Msk & ((value) << GMAC_ORHI_RXO_Pos))
+#define GMAC_ORHI_MASK _U_(0x0000FFFF) /**< \brief (GMAC_ORHI) MASK Register */
+
+/* -------- GMAC_FR : (GMAC Offset: 0x158) (R/ 32) Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FRX:32; /*!< bit: 0..31 Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_FR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_FR_OFFSET 0x158 /**< \brief (GMAC_FR offset) Frames Received Register */
+#define GMAC_FR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_FR reset_value) Frames Received Register */
+
+#define GMAC_FR_FRX_Pos 0 /**< \brief (GMAC_FR) Frames Received without Error */
+#define GMAC_FR_FRX_Msk (_U_(0xFFFFFFFF) << GMAC_FR_FRX_Pos)
+#define GMAC_FR_FRX(value) (GMAC_FR_FRX_Msk & ((value) << GMAC_FR_FRX_Pos))
+#define GMAC_FR_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_FR) MASK Register */
+
+/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) (R/ 32) Broadcast Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BFRX:32; /*!< bit: 0..31 Broadcast Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_BCFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_BCFR_OFFSET 0x15C /**< \brief (GMAC_BCFR offset) Broadcast Frames Received Register */
+#define GMAC_BCFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_BCFR reset_value) Broadcast Frames Received Register */
+
+#define GMAC_BCFR_BFRX_Pos 0 /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */
+#define GMAC_BCFR_BFRX_Msk (_U_(0xFFFFFFFF) << GMAC_BCFR_BFRX_Pos)
+#define GMAC_BCFR_BFRX(value) (GMAC_BCFR_BFRX_Msk & ((value) << GMAC_BCFR_BFRX_Pos))
+#define GMAC_BCFR_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_BCFR) MASK Register */
+
+/* -------- GMAC_MFR : (GMAC Offset: 0x160) (R/ 32) Multicast Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MFRX:32; /*!< bit: 0..31 Multicast Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_MFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_MFR_OFFSET 0x160 /**< \brief (GMAC_MFR offset) Multicast Frames Received Register */
+#define GMAC_MFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_MFR reset_value) Multicast Frames Received Register */
+
+#define GMAC_MFR_MFRX_Pos 0 /**< \brief (GMAC_MFR) Multicast Frames Received without Error */
+#define GMAC_MFR_MFRX_Msk (_U_(0xFFFFFFFF) << GMAC_MFR_MFRX_Pos)
+#define GMAC_MFR_MFRX(value) (GMAC_MFR_MFRX_Msk & ((value) << GMAC_MFR_MFRX_Pos))
+#define GMAC_MFR_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_MFR) MASK Register */
+
+/* -------- GMAC_PFR : (GMAC Offset: 0x164) (R/ 32) Pause Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PFRX:16; /*!< bit: 0..15 Pause Frames Received Register */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_PFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PFR_OFFSET 0x164 /**< \brief (GMAC_PFR offset) Pause Frames Received Register */
+#define GMAC_PFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PFR reset_value) Pause Frames Received Register */
+
+#define GMAC_PFR_PFRX_Pos 0 /**< \brief (GMAC_PFR) Pause Frames Received Register */
+#define GMAC_PFR_PFRX_Msk (_U_(0xFFFF) << GMAC_PFR_PFRX_Pos)
+#define GMAC_PFR_PFRX(value) (GMAC_PFR_PFRX_Msk & ((value) << GMAC_PFR_PFRX_Pos))
+#define GMAC_PFR_MASK _U_(0x0000FFFF) /**< \brief (GMAC_PFR) MASK Register */
+
+/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) (R/ 32) 64 Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFRX:32; /*!< bit: 0..31 64 Byte Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_BFR64_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_BFR64_OFFSET 0x168 /**< \brief (GMAC_BFR64 offset) 64 Byte Frames Received Register */
+#define GMAC_BFR64_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_BFR64 reset_value) 64 Byte Frames Received Register */
+
+#define GMAC_BFR64_NFRX_Pos 0 /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */
+#define GMAC_BFR64_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_BFR64_NFRX_Pos)
+#define GMAC_BFR64_NFRX(value) (GMAC_BFR64_NFRX_Msk & ((value) << GMAC_BFR64_NFRX_Pos))
+#define GMAC_BFR64_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_BFR64) MASK Register */
+
+/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) (R/ 32) 65 to 127 Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFRX:32; /*!< bit: 0..31 65 to 127 Byte Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFR127_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFR127_OFFSET 0x16C /**< \brief (GMAC_TBFR127 offset) 65 to 127 Byte Frames Received Register */
+#define GMAC_TBFR127_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR127 reset_value) 65 to 127 Byte Frames Received Register */
+
+#define GMAC_TBFR127_NFRX_Pos 0 /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */
+#define GMAC_TBFR127_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR127_NFRX_Pos)
+#define GMAC_TBFR127_NFRX(value) (GMAC_TBFR127_NFRX_Msk & ((value) << GMAC_TBFR127_NFRX_Pos))
+#define GMAC_TBFR127_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR127) MASK Register */
+
+/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) (R/ 32) 128 to 255 Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFRX:32; /*!< bit: 0..31 128 to 255 Byte Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFR255_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFR255_OFFSET 0x170 /**< \brief (GMAC_TBFR255 offset) 128 to 255 Byte Frames Received Register */
+#define GMAC_TBFR255_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR255 reset_value) 128 to 255 Byte Frames Received Register */
+
+#define GMAC_TBFR255_NFRX_Pos 0 /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */
+#define GMAC_TBFR255_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR255_NFRX_Pos)
+#define GMAC_TBFR255_NFRX(value) (GMAC_TBFR255_NFRX_Msk & ((value) << GMAC_TBFR255_NFRX_Pos))
+#define GMAC_TBFR255_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR255) MASK Register */
+
+/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) (R/ 32) 256 to 511Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFRX:32; /*!< bit: 0..31 256 to 511 Byte Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFR511_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFR511_OFFSET 0x174 /**< \brief (GMAC_TBFR511 offset) 256 to 511Byte Frames Received Register */
+#define GMAC_TBFR511_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR511 reset_value) 256 to 511Byte Frames Received Register */
+
+#define GMAC_TBFR511_NFRX_Pos 0 /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */
+#define GMAC_TBFR511_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR511_NFRX_Pos)
+#define GMAC_TBFR511_NFRX(value) (GMAC_TBFR511_NFRX_Msk & ((value) << GMAC_TBFR511_NFRX_Pos))
+#define GMAC_TBFR511_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR511) MASK Register */
+
+/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) (R/ 32) 512 to 1023 Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFRX:32; /*!< bit: 0..31 512 to 1023 Byte Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFR1023_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFR1023_OFFSET 0x178 /**< \brief (GMAC_TBFR1023 offset) 512 to 1023 Byte Frames Received Register */
+#define GMAC_TBFR1023_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR1023 reset_value) 512 to 1023 Byte Frames Received Register */
+
+#define GMAC_TBFR1023_NFRX_Pos 0 /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */
+#define GMAC_TBFR1023_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR1023_NFRX_Pos)
+#define GMAC_TBFR1023_NFRX(value) (GMAC_TBFR1023_NFRX_Msk & ((value) << GMAC_TBFR1023_NFRX_Pos))
+#define GMAC_TBFR1023_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR1023) MASK Register */
+
+/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) (R/ 32) 1024 to 1518 Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFRX:32; /*!< bit: 0..31 1024 to 1518 Byte Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFR1518_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFR1518_OFFSET 0x17C /**< \brief (GMAC_TBFR1518 offset) 1024 to 1518 Byte Frames Received Register */
+#define GMAC_TBFR1518_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR1518 reset_value) 1024 to 1518 Byte Frames Received Register */
+
+#define GMAC_TBFR1518_NFRX_Pos 0 /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */
+#define GMAC_TBFR1518_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR1518_NFRX_Pos)
+#define GMAC_TBFR1518_NFRX(value) (GMAC_TBFR1518_NFRX_Msk & ((value) << GMAC_TBFR1518_NFRX_Pos))
+#define GMAC_TBFR1518_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR1518) MASK Register */
+
+/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) (R/ 32) 1519 to Maximum Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFRX:32; /*!< bit: 0..31 1519 to Maximum Byte Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TMXBFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TMXBFR_OFFSET 0x180 /**< \brief (GMAC_TMXBFR offset) 1519 to Maximum Byte Frames Received Register */
+#define GMAC_TMXBFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TMXBFR reset_value) 1519 to Maximum Byte Frames Received Register */
+
+#define GMAC_TMXBFR_NFRX_Pos 0 /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */
+#define GMAC_TMXBFR_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TMXBFR_NFRX_Pos)
+#define GMAC_TMXBFR_NFRX(value) (GMAC_TMXBFR_NFRX_Msk & ((value) << GMAC_TMXBFR_NFRX_Pos))
+#define GMAC_TMXBFR_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TMXBFR) MASK Register */
+
+/* -------- GMAC_UFR : (GMAC Offset: 0x184) (R/ 32) Undersize Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t UFRX:10; /*!< bit: 0.. 9 Undersize Frames Received */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_UFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_UFR_OFFSET 0x184 /**< \brief (GMAC_UFR offset) Undersize Frames Received Register */
+#define GMAC_UFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_UFR reset_value) Undersize Frames Received Register */
+
+#define GMAC_UFR_UFRX_Pos 0 /**< \brief (GMAC_UFR) Undersize Frames Received */
+#define GMAC_UFR_UFRX_Msk (_U_(0x3FF) << GMAC_UFR_UFRX_Pos)
+#define GMAC_UFR_UFRX(value) (GMAC_UFR_UFRX_Msk & ((value) << GMAC_UFR_UFRX_Pos))
+#define GMAC_UFR_MASK _U_(0x000003FF) /**< \brief (GMAC_UFR) MASK Register */
+
+/* -------- GMAC_OFR : (GMAC Offset: 0x188) (R/ 32) Oversize Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OFRX:10; /*!< bit: 0.. 9 Oversized Frames Received */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_OFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_OFR_OFFSET 0x188 /**< \brief (GMAC_OFR offset) Oversize Frames Received Register */
+#define GMAC_OFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_OFR reset_value) Oversize Frames Received Register */
+
+#define GMAC_OFR_OFRX_Pos 0 /**< \brief (GMAC_OFR) Oversized Frames Received */
+#define GMAC_OFR_OFRX_Msk (_U_(0x3FF) << GMAC_OFR_OFRX_Pos)
+#define GMAC_OFR_OFRX(value) (GMAC_OFR_OFRX_Msk & ((value) << GMAC_OFR_OFRX_Pos))
+#define GMAC_OFR_MASK _U_(0x000003FF) /**< \brief (GMAC_OFR) MASK Register */
+
+/* -------- GMAC_JR : (GMAC Offset: 0x18C) (R/ 32) Jabbers Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t JRX:10; /*!< bit: 0.. 9 Jabbers Received */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_JR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_JR_OFFSET 0x18C /**< \brief (GMAC_JR offset) Jabbers Received Register */
+#define GMAC_JR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_JR reset_value) Jabbers Received Register */
+
+#define GMAC_JR_JRX_Pos 0 /**< \brief (GMAC_JR) Jabbers Received */
+#define GMAC_JR_JRX_Msk (_U_(0x3FF) << GMAC_JR_JRX_Pos)
+#define GMAC_JR_JRX(value) (GMAC_JR_JRX_Msk & ((value) << GMAC_JR_JRX_Pos))
+#define GMAC_JR_MASK _U_(0x000003FF) /**< \brief (GMAC_JR) MASK Register */
+
+/* -------- GMAC_FCSE : (GMAC Offset: 0x190) (R/ 32) Frame Check Sequence Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FCKR:10; /*!< bit: 0.. 9 Frame Check Sequence Errors */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_FCSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_FCSE_OFFSET 0x190 /**< \brief (GMAC_FCSE offset) Frame Check Sequence Errors Register */
+#define GMAC_FCSE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_FCSE reset_value) Frame Check Sequence Errors Register */
+
+#define GMAC_FCSE_FCKR_Pos 0 /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */
+#define GMAC_FCSE_FCKR_Msk (_U_(0x3FF) << GMAC_FCSE_FCKR_Pos)
+#define GMAC_FCSE_FCKR(value) (GMAC_FCSE_FCKR_Msk & ((value) << GMAC_FCSE_FCKR_Pos))
+#define GMAC_FCSE_MASK _U_(0x000003FF) /**< \brief (GMAC_FCSE) MASK Register */
+
+/* -------- GMAC_LFFE : (GMAC Offset: 0x194) (R/ 32) Length Field Frame Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LFER:10; /*!< bit: 0.. 9 Length Field Frame Errors */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_LFFE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_LFFE_OFFSET 0x194 /**< \brief (GMAC_LFFE offset) Length Field Frame Errors Register */
+#define GMAC_LFFE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_LFFE reset_value) Length Field Frame Errors Register */
+
+#define GMAC_LFFE_LFER_Pos 0 /**< \brief (GMAC_LFFE) Length Field Frame Errors */
+#define GMAC_LFFE_LFER_Msk (_U_(0x3FF) << GMAC_LFFE_LFER_Pos)
+#define GMAC_LFFE_LFER(value) (GMAC_LFFE_LFER_Msk & ((value) << GMAC_LFFE_LFER_Pos))
+#define GMAC_LFFE_MASK _U_(0x000003FF) /**< \brief (GMAC_LFFE) MASK Register */
+
+/* -------- GMAC_RSE : (GMAC Offset: 0x198) (R/ 32) Receive Symbol Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXSE:10; /*!< bit: 0.. 9 Receive Symbol Errors */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_RSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RSE_OFFSET 0x198 /**< \brief (GMAC_RSE offset) Receive Symbol Errors Register */
+#define GMAC_RSE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RSE reset_value) Receive Symbol Errors Register */
+
+#define GMAC_RSE_RXSE_Pos 0 /**< \brief (GMAC_RSE) Receive Symbol Errors */
+#define GMAC_RSE_RXSE_Msk (_U_(0x3FF) << GMAC_RSE_RXSE_Pos)
+#define GMAC_RSE_RXSE(value) (GMAC_RSE_RXSE_Msk & ((value) << GMAC_RSE_RXSE_Pos))
+#define GMAC_RSE_MASK _U_(0x000003FF) /**< \brief (GMAC_RSE) MASK Register */
+
+/* -------- GMAC_AE : (GMAC Offset: 0x19C) (R/ 32) Alignment Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t AER:10; /*!< bit: 0.. 9 Alignment Errors */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_AE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_AE_OFFSET 0x19C /**< \brief (GMAC_AE offset) Alignment Errors Register */
+#define GMAC_AE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_AE reset_value) Alignment Errors Register */
+
+#define GMAC_AE_AER_Pos 0 /**< \brief (GMAC_AE) Alignment Errors */
+#define GMAC_AE_AER_Msk (_U_(0x3FF) << GMAC_AE_AER_Pos)
+#define GMAC_AE_AER(value) (GMAC_AE_AER_Msk & ((value) << GMAC_AE_AER_Pos))
+#define GMAC_AE_MASK _U_(0x000003FF) /**< \brief (GMAC_AE) MASK Register */
+
+/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) (R/ 32) Receive Resource Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXRER:18; /*!< bit: 0..17 Receive Resource Errors */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_RRE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RRE_OFFSET 0x1A0 /**< \brief (GMAC_RRE offset) Receive Resource Errors Register */
+#define GMAC_RRE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RRE reset_value) Receive Resource Errors Register */
+
+#define GMAC_RRE_RXRER_Pos 0 /**< \brief (GMAC_RRE) Receive Resource Errors */
+#define GMAC_RRE_RXRER_Msk (_U_(0x3FFFF) << GMAC_RRE_RXRER_Pos)
+#define GMAC_RRE_RXRER(value) (GMAC_RRE_RXRER_Msk & ((value) << GMAC_RRE_RXRER_Pos))
+#define GMAC_RRE_MASK _U_(0x0003FFFF) /**< \brief (GMAC_RRE) MASK Register */
+
+/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) (R/ 32) Receive Overrun Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXOVR:10; /*!< bit: 0.. 9 Receive Overruns */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_ROE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_ROE_OFFSET 0x1A4 /**< \brief (GMAC_ROE offset) Receive Overrun Register */
+#define GMAC_ROE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_ROE reset_value) Receive Overrun Register */
+
+#define GMAC_ROE_RXOVR_Pos 0 /**< \brief (GMAC_ROE) Receive Overruns */
+#define GMAC_ROE_RXOVR_Msk (_U_(0x3FF) << GMAC_ROE_RXOVR_Pos)
+#define GMAC_ROE_RXOVR(value) (GMAC_ROE_RXOVR_Msk & ((value) << GMAC_ROE_RXOVR_Pos))
+#define GMAC_ROE_MASK _U_(0x000003FF) /**< \brief (GMAC_ROE) MASK Register */
+
+/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) (R/ 32) IP Header Checksum Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t HCKER:8; /*!< bit: 0.. 7 IP Header Checksum Errors */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_IHCE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_IHCE_OFFSET 0x1A8 /**< \brief (GMAC_IHCE offset) IP Header Checksum Errors Register */
+#define GMAC_IHCE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_IHCE reset_value) IP Header Checksum Errors Register */
+
+#define GMAC_IHCE_HCKER_Pos 0 /**< \brief (GMAC_IHCE) IP Header Checksum Errors */
+#define GMAC_IHCE_HCKER_Msk (_U_(0xFF) << GMAC_IHCE_HCKER_Pos)
+#define GMAC_IHCE_HCKER(value) (GMAC_IHCE_HCKER_Msk & ((value) << GMAC_IHCE_HCKER_Pos))
+#define GMAC_IHCE_MASK _U_(0x000000FF) /**< \brief (GMAC_IHCE) MASK Register */
+
+/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) (R/ 32) TCP Checksum Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TCKER:8; /*!< bit: 0.. 7 TCP Checksum Errors */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TCE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TCE_OFFSET 0x1AC /**< \brief (GMAC_TCE offset) TCP Checksum Errors Register */
+#define GMAC_TCE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TCE reset_value) TCP Checksum Errors Register */
+
+#define GMAC_TCE_TCKER_Pos 0 /**< \brief (GMAC_TCE) TCP Checksum Errors */
+#define GMAC_TCE_TCKER_Msk (_U_(0xFF) << GMAC_TCE_TCKER_Pos)
+#define GMAC_TCE_TCKER(value) (GMAC_TCE_TCKER_Msk & ((value) << GMAC_TCE_TCKER_Pos))
+#define GMAC_TCE_MASK _U_(0x000000FF) /**< \brief (GMAC_TCE) MASK Register */
+
+/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) (R/ 32) UDP Checksum Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t UCKER:8; /*!< bit: 0.. 7 UDP Checksum Errors */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_UCE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_UCE_OFFSET 0x1B0 /**< \brief (GMAC_UCE offset) UDP Checksum Errors Register */
+#define GMAC_UCE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_UCE reset_value) UDP Checksum Errors Register */
+
+#define GMAC_UCE_UCKER_Pos 0 /**< \brief (GMAC_UCE) UDP Checksum Errors */
+#define GMAC_UCE_UCKER_Msk (_U_(0xFF) << GMAC_UCE_UCKER_Pos)
+#define GMAC_UCE_UCKER(value) (GMAC_UCE_UCKER_Msk & ((value) << GMAC_UCE_UCKER_Pos))
+#define GMAC_UCE_MASK _U_(0x000000FF) /**< \brief (GMAC_UCE) MASK Register */
+
+/* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) (R/W 32) 1588 Timer Increment [15:0] Sub-Nanoseconds Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LSBTIR:16; /*!< bit: 0..15 Lower Significant Bits of Timer Increment */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TISUBN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TISUBN_OFFSET 0x1BC /**< \brief (GMAC_TISUBN offset) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
+#define GMAC_TISUBN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TISUBN reset_value) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
+
+#define GMAC_TISUBN_LSBTIR_Pos 0 /**< \brief (GMAC_TISUBN) Lower Significant Bits of Timer Increment */
+#define GMAC_TISUBN_LSBTIR_Msk (_U_(0xFFFF) << GMAC_TISUBN_LSBTIR_Pos)
+#define GMAC_TISUBN_LSBTIR(value) (GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos))
+#define GMAC_TISUBN_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TISUBN) MASK Register */
+
+/* -------- GMAC_TSH : (GMAC Offset: 0x1C0) (R/W 32) 1588 Timer Seconds High [15:0] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TCS:16; /*!< bit: 0..15 Timer Count in Seconds */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TSH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TSH_OFFSET 0x1C0 /**< \brief (GMAC_TSH offset) 1588 Timer Seconds High [15:0] Register */
+#define GMAC_TSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSH reset_value) 1588 Timer Seconds High [15:0] Register */
+
+#define GMAC_TSH_TCS_Pos 0 /**< \brief (GMAC_TSH) Timer Count in Seconds */
+#define GMAC_TSH_TCS_Msk (_U_(0xFFFF) << GMAC_TSH_TCS_Pos)
+#define GMAC_TSH_TCS(value) (GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos))
+#define GMAC_TSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TSH) MASK Register */
+
+/* -------- GMAC_TSSSL : (GMAC Offset: 0x1C8) (R/W 32) 1588 Timer Sync Strobe Seconds [31:0] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t VTS:32; /*!< bit: 0..31 Value of Timer Seconds Register Capture */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TSSSL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TSSSL_OFFSET 0x1C8 /**< \brief (GMAC_TSSSL offset) 1588 Timer Sync Strobe Seconds [31:0] Register */
+#define GMAC_TSSSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSSSL reset_value) 1588 Timer Sync Strobe Seconds [31:0] Register */
+
+#define GMAC_TSSSL_VTS_Pos 0 /**< \brief (GMAC_TSSSL) Value of Timer Seconds Register Capture */
+#define GMAC_TSSSL_VTS_Msk (_U_(0xFFFFFFFF) << GMAC_TSSSL_VTS_Pos)
+#define GMAC_TSSSL_VTS(value) (GMAC_TSSSL_VTS_Msk & ((value) << GMAC_TSSSL_VTS_Pos))
+#define GMAC_TSSSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TSSSL) MASK Register */
+
+/* -------- GMAC_TSSN : (GMAC Offset: 0x1CC) (R/W 32) 1588 Timer Sync Strobe Nanoseconds Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t VTN:30; /*!< bit: 0..29 Value Timer Nanoseconds Register Capture */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TSSN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TSSN_OFFSET 0x1CC /**< \brief (GMAC_TSSN offset) 1588 Timer Sync Strobe Nanoseconds Register */
+#define GMAC_TSSN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSSN reset_value) 1588 Timer Sync Strobe Nanoseconds Register */
+
+#define GMAC_TSSN_VTN_Pos 0 /**< \brief (GMAC_TSSN) Value Timer Nanoseconds Register Capture */
+#define GMAC_TSSN_VTN_Msk (_U_(0x3FFFFFFF) << GMAC_TSSN_VTN_Pos)
+#define GMAC_TSSN_VTN(value) (GMAC_TSSN_VTN_Msk & ((value) << GMAC_TSSN_VTN_Pos))
+#define GMAC_TSSN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_TSSN) MASK Register */
+
+/* -------- GMAC_TSL : (GMAC Offset: 0x1D0) (R/W 32) 1588 Timer Seconds [31:0] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TCS:32; /*!< bit: 0..31 Timer Count in Seconds */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TSL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TSL_OFFSET 0x1D0 /**< \brief (GMAC_TSL offset) 1588 Timer Seconds [31:0] Register */
+#define GMAC_TSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSL reset_value) 1588 Timer Seconds [31:0] Register */
+
+#define GMAC_TSL_TCS_Pos 0 /**< \brief (GMAC_TSL) Timer Count in Seconds */
+#define GMAC_TSL_TCS_Msk (_U_(0xFFFFFFFF) << GMAC_TSL_TCS_Pos)
+#define GMAC_TSL_TCS(value) (GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos))
+#define GMAC_TSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TSL) MASK Register */
+
+/* -------- GMAC_TN : (GMAC Offset: 0x1D4) (R/W 32) 1588 Timer Nanoseconds Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TNS:30; /*!< bit: 0..29 Timer Count in Nanoseconds */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TN_OFFSET 0x1D4 /**< \brief (GMAC_TN offset) 1588 Timer Nanoseconds Register */
+#define GMAC_TN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TN reset_value) 1588 Timer Nanoseconds Register */
+
+#define GMAC_TN_TNS_Pos 0 /**< \brief (GMAC_TN) Timer Count in Nanoseconds */
+#define GMAC_TN_TNS_Msk (_U_(0x3FFFFFFF) << GMAC_TN_TNS_Pos)
+#define GMAC_TN_TNS(value) (GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))
+#define GMAC_TN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_TN) MASK Register */
+
+/* -------- GMAC_TA : (GMAC Offset: 0x1D8) ( /W 32) 1588 Timer Adjust Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ITDT:30; /*!< bit: 0..29 Increment/Decrement */
+ uint32_t :1; /*!< bit: 30 Reserved */
+ uint32_t ADJ:1; /*!< bit: 31 Adjust 1588 Timer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TA_OFFSET 0x1D8 /**< \brief (GMAC_TA offset) 1588 Timer Adjust Register */
+#define GMAC_TA_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TA reset_value) 1588 Timer Adjust Register */
+
+#define GMAC_TA_ITDT_Pos 0 /**< \brief (GMAC_TA) Increment/Decrement */
+#define GMAC_TA_ITDT_Msk (_U_(0x3FFFFFFF) << GMAC_TA_ITDT_Pos)
+#define GMAC_TA_ITDT(value) (GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))
+#define GMAC_TA_ADJ_Pos 31 /**< \brief (GMAC_TA) Adjust 1588 Timer */
+#define GMAC_TA_ADJ (_U_(0x1) << GMAC_TA_ADJ_Pos)
+#define GMAC_TA_MASK _U_(0xBFFFFFFF) /**< \brief (GMAC_TA) MASK Register */
+
+/* -------- GMAC_TI : (GMAC Offset: 0x1DC) (R/W 32) 1588 Timer Increment Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CNS:8; /*!< bit: 0.. 7 Count Nanoseconds */
+ uint32_t ACNS:8; /*!< bit: 8..15 Alternative Count Nanoseconds */
+ uint32_t NIT:8; /*!< bit: 16..23 Number of Increments */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TI_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TI_OFFSET 0x1DC /**< \brief (GMAC_TI offset) 1588 Timer Increment Register */
+#define GMAC_TI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TI reset_value) 1588 Timer Increment Register */
+
+#define GMAC_TI_CNS_Pos 0 /**< \brief (GMAC_TI) Count Nanoseconds */
+#define GMAC_TI_CNS_Msk (_U_(0xFF) << GMAC_TI_CNS_Pos)
+#define GMAC_TI_CNS(value) (GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))
+#define GMAC_TI_ACNS_Pos 8 /**< \brief (GMAC_TI) Alternative Count Nanoseconds */
+#define GMAC_TI_ACNS_Msk (_U_(0xFF) << GMAC_TI_ACNS_Pos)
+#define GMAC_TI_ACNS(value) (GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))
+#define GMAC_TI_NIT_Pos 16 /**< \brief (GMAC_TI) Number of Increments */
+#define GMAC_TI_NIT_Msk (_U_(0xFF) << GMAC_TI_NIT_Pos)
+#define GMAC_TI_NIT(value) (GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))
+#define GMAC_TI_MASK _U_(0x00FFFFFF) /**< \brief (GMAC_TI) MASK Register */
+
+/* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) (R/ 32) PTP Event Frame Transmitted Seconds Low Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:32; /*!< bit: 0..31 Register Update */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_EFTSL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EFTSL_OFFSET 0x1E0 /**< \brief (GMAC_EFTSL offset) PTP Event Frame Transmitted Seconds Low Register */
+#define GMAC_EFTSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFTSL reset_value) PTP Event Frame Transmitted Seconds Low Register */
+
+#define GMAC_EFTSL_RUD_Pos 0 /**< \brief (GMAC_EFTSL) Register Update */
+#define GMAC_EFTSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_EFTSL_RUD_Pos)
+#define GMAC_EFTSL_RUD(value) (GMAC_EFTSL_RUD_Msk & ((value) << GMAC_EFTSL_RUD_Pos))
+#define GMAC_EFTSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_EFTSL) MASK Register */
+
+/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) (R/ 32) PTP Event Frame Transmitted Nanoseconds -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:30; /*!< bit: 0..29 Register Update */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_EFTN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EFTN_OFFSET 0x1E4 /**< \brief (GMAC_EFTN offset) PTP Event Frame Transmitted Nanoseconds */
+#define GMAC_EFTN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFTN reset_value) PTP Event Frame Transmitted Nanoseconds */
+
+#define GMAC_EFTN_RUD_Pos 0 /**< \brief (GMAC_EFTN) Register Update */
+#define GMAC_EFTN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_EFTN_RUD_Pos)
+#define GMAC_EFTN_RUD(value) (GMAC_EFTN_RUD_Msk & ((value) << GMAC_EFTN_RUD_Pos))
+#define GMAC_EFTN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_EFTN) MASK Register */
+
+/* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) (R/ 32) PTP Event Frame Received Seconds Low Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:32; /*!< bit: 0..31 Register Update */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_EFRSL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EFRSL_OFFSET 0x1E8 /**< \brief (GMAC_EFRSL offset) PTP Event Frame Received Seconds Low Register */
+#define GMAC_EFRSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFRSL reset_value) PTP Event Frame Received Seconds Low Register */
+
+#define GMAC_EFRSL_RUD_Pos 0 /**< \brief (GMAC_EFRSL) Register Update */
+#define GMAC_EFRSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_EFRSL_RUD_Pos)
+#define GMAC_EFRSL_RUD(value) (GMAC_EFRSL_RUD_Msk & ((value) << GMAC_EFRSL_RUD_Pos))
+#define GMAC_EFRSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_EFRSL) MASK Register */
+
+/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) (R/ 32) PTP Event Frame Received Nanoseconds -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:30; /*!< bit: 0..29 Register Update */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_EFRN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EFRN_OFFSET 0x1EC /**< \brief (GMAC_EFRN offset) PTP Event Frame Received Nanoseconds */
+#define GMAC_EFRN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFRN reset_value) PTP Event Frame Received Nanoseconds */
+
+#define GMAC_EFRN_RUD_Pos 0 /**< \brief (GMAC_EFRN) Register Update */
+#define GMAC_EFRN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_EFRN_RUD_Pos)
+#define GMAC_EFRN_RUD(value) (GMAC_EFRN_RUD_Msk & ((value) << GMAC_EFRN_RUD_Pos))
+#define GMAC_EFRN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_EFRN) MASK Register */
+
+/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) (R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:32; /*!< bit: 0..31 Register Update */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_PEFTSL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PEFTSL_OFFSET 0x1F0 /**< \brief (GMAC_PEFTSL offset) PTP Peer Event Frame Transmitted Seconds Low Register */
+#define GMAC_PEFTSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFTSL reset_value) PTP Peer Event Frame Transmitted Seconds Low Register */
+
+#define GMAC_PEFTSL_RUD_Pos 0 /**< \brief (GMAC_PEFTSL) Register Update */
+#define GMAC_PEFTSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_PEFTSL_RUD_Pos)
+#define GMAC_PEFTSL_RUD(value) (GMAC_PEFTSL_RUD_Msk & ((value) << GMAC_PEFTSL_RUD_Pos))
+#define GMAC_PEFTSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_PEFTSL) MASK Register */
+
+/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) (R/ 32) PTP Peer Event Frame Transmitted Nanoseconds -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:30; /*!< bit: 0..29 Register Update */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_PEFTN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PEFTN_OFFSET 0x1F4 /**< \brief (GMAC_PEFTN offset) PTP Peer Event Frame Transmitted Nanoseconds */
+#define GMAC_PEFTN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFTN reset_value) PTP Peer Event Frame Transmitted Nanoseconds */
+
+#define GMAC_PEFTN_RUD_Pos 0 /**< \brief (GMAC_PEFTN) Register Update */
+#define GMAC_PEFTN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_PEFTN_RUD_Pos)
+#define GMAC_PEFTN_RUD(value) (GMAC_PEFTN_RUD_Msk & ((value) << GMAC_PEFTN_RUD_Pos))
+#define GMAC_PEFTN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_PEFTN) MASK Register */
+
+/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) (R/ 32) PTP Peer Event Frame Received Seconds Low Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:32; /*!< bit: 0..31 Register Update */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_PEFRSL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PEFRSL_OFFSET 0x1F8 /**< \brief (GMAC_PEFRSL offset) PTP Peer Event Frame Received Seconds Low Register */
+#define GMAC_PEFRSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFRSL reset_value) PTP Peer Event Frame Received Seconds Low Register */
+
+#define GMAC_PEFRSL_RUD_Pos 0 /**< \brief (GMAC_PEFRSL) Register Update */
+#define GMAC_PEFRSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_PEFRSL_RUD_Pos)
+#define GMAC_PEFRSL_RUD(value) (GMAC_PEFRSL_RUD_Msk & ((value) << GMAC_PEFRSL_RUD_Pos))
+#define GMAC_PEFRSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_PEFRSL) MASK Register */
+
+/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) (R/ 32) PTP Peer Event Frame Received Nanoseconds -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:30; /*!< bit: 0..29 Register Update */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_PEFRN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PEFRN_OFFSET 0x1FC /**< \brief (GMAC_PEFRN offset) PTP Peer Event Frame Received Nanoseconds */
+#define GMAC_PEFRN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFRN reset_value) PTP Peer Event Frame Received Nanoseconds */
+
+#define GMAC_PEFRN_RUD_Pos 0 /**< \brief (GMAC_PEFRN) Register Update */
+#define GMAC_PEFRN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_PEFRN_RUD_Pos)
+#define GMAC_PEFRN_RUD(value) (GMAC_PEFRN_RUD_Msk & ((value) << GMAC_PEFRN_RUD_Pos))
+#define GMAC_PEFRN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_PEFRN) MASK Register */
+
+/* -------- GMAC_RLPITR : (GMAC Offset: 0x270) (R/ 32) Receive LPI transition Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RLPITR:16; /*!< bit: 0..15 Count number of times transition from rx normal idle to low power idle */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_RLPITR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RLPITR_OFFSET 0x270 /**< \brief (GMAC_RLPITR offset) Receive LPI transition Register */
+#define GMAC_RLPITR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RLPITR reset_value) Receive LPI transition Register */
+
+#define GMAC_RLPITR_RLPITR_Pos 0 /**< \brief (GMAC_RLPITR) Count number of times transition from rx normal idle to low power idle */
+#define GMAC_RLPITR_RLPITR_Msk (_U_(0xFFFF) << GMAC_RLPITR_RLPITR_Pos)
+#define GMAC_RLPITR_RLPITR(value) (GMAC_RLPITR_RLPITR_Msk & ((value) << GMAC_RLPITR_RLPITR_Pos))
+#define GMAC_RLPITR_MASK _U_(0x0000FFFF) /**< \brief (GMAC_RLPITR) MASK Register */
+
+/* -------- GMAC_RLPITI : (GMAC Offset: 0x274) (R/ 32) Receive LPI Time Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RLPITI:24; /*!< bit: 0..23 Increment once over 16 ahb clock when LPI indication bit 20 is set in rx mode */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_RLPITI_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RLPITI_OFFSET 0x274 /**< \brief (GMAC_RLPITI offset) Receive LPI Time Register */
+#define GMAC_RLPITI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RLPITI reset_value) Receive LPI Time Register */
+
+#define GMAC_RLPITI_RLPITI_Pos 0 /**< \brief (GMAC_RLPITI) Increment once over 16 ahb clock when LPI indication bit 20 is set in rx mode */
+#define GMAC_RLPITI_RLPITI_Msk (_U_(0xFFFFFF) << GMAC_RLPITI_RLPITI_Pos)
+#define GMAC_RLPITI_RLPITI(value) (GMAC_RLPITI_RLPITI_Msk & ((value) << GMAC_RLPITI_RLPITI_Pos))
+#define GMAC_RLPITI_MASK _U_(0x00FFFFFF) /**< \brief (GMAC_RLPITI) MASK Register */
+
+/* -------- GMAC_TLPITR : (GMAC Offset: 0x278) (R/ 32) Receive LPI transition Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TLPITR:16; /*!< bit: 0..15 Count number of times enable LPI tx bit 20 goes from low to high */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TLPITR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TLPITR_OFFSET 0x278 /**< \brief (GMAC_TLPITR offset) Receive LPI transition Register */
+#define GMAC_TLPITR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TLPITR reset_value) Receive LPI transition Register */
+
+#define GMAC_TLPITR_TLPITR_Pos 0 /**< \brief (GMAC_TLPITR) Count number of times enable LPI tx bit 20 goes from low to high */
+#define GMAC_TLPITR_TLPITR_Msk (_U_(0xFFFF) << GMAC_TLPITR_TLPITR_Pos)
+#define GMAC_TLPITR_TLPITR(value) (GMAC_TLPITR_TLPITR_Msk & ((value) << GMAC_TLPITR_TLPITR_Pos))
+#define GMAC_TLPITR_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TLPITR) MASK Register */
+
+/* -------- GMAC_TLPITI : (GMAC Offset: 0x27C) (R/ 32) Receive LPI Time Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TLPITI:24; /*!< bit: 0..23 Increment once over 16 ahb clock when LPI indication bit 20 is set in tx mode */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TLPITI_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TLPITI_OFFSET 0x27C /**< \brief (GMAC_TLPITI offset) Receive LPI Time Register */
+#define GMAC_TLPITI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TLPITI reset_value) Receive LPI Time Register */
+
+#define GMAC_TLPITI_TLPITI_Pos 0 /**< \brief (GMAC_TLPITI) Increment once over 16 ahb clock when LPI indication bit 20 is set in tx mode */
+#define GMAC_TLPITI_TLPITI_Msk (_U_(0xFFFFFF) << GMAC_TLPITI_TLPITI_Pos)
+#define GMAC_TLPITI_TLPITI(value) (GMAC_TLPITI_TLPITI_Msk & ((value) << GMAC_TLPITI_TLPITI_Pos))
+#define GMAC_TLPITI_MASK _U_(0x00FFFFFF) /**< \brief (GMAC_TLPITI) MASK Register */
+
+/** \brief GmacSa hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO GMAC_SAB_Type SAB; /**< \brief Offset: 0x000 (R/W 32) Specific Address Bottom [31:0] Register */
+ __IO GMAC_SAT_Type SAT; /**< \brief Offset: 0x004 (R/W 32) Specific Address Top [47:32] Register */
+} GmacSa;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief GMAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO GMAC_NCR_Type NCR; /**< \brief Offset: 0x000 (R/W 32) Network Control Register */
+ __IO GMAC_NCFGR_Type NCFGR; /**< \brief Offset: 0x004 (R/W 32) Network Configuration Register */
+ __I GMAC_NSR_Type NSR; /**< \brief Offset: 0x008 (R/ 32) Network Status Register */
+ __IO GMAC_UR_Type UR; /**< \brief Offset: 0x00C (R/W 32) User Register */
+ __IO GMAC_DCFGR_Type DCFGR; /**< \brief Offset: 0x010 (R/W 32) DMA Configuration Register */
+ __IO GMAC_TSR_Type TSR; /**< \brief Offset: 0x014 (R/W 32) Transmit Status Register */
+ __IO GMAC_RBQB_Type RBQB; /**< \brief Offset: 0x018 (R/W 32) Receive Buffer Queue Base Address */
+ __IO GMAC_TBQB_Type TBQB; /**< \brief Offset: 0x01C (R/W 32) Transmit Buffer Queue Base Address */
+ __IO GMAC_RSR_Type RSR; /**< \brief Offset: 0x020 (R/W 32) Receive Status Register */
+ __IO GMAC_ISR_Type ISR; /**< \brief Offset: 0x024 (R/W 32) Interrupt Status Register */
+ __O GMAC_IER_Type IER; /**< \brief Offset: 0x028 ( /W 32) Interrupt Enable Register */
+ __O GMAC_IDR_Type IDR; /**< \brief Offset: 0x02C ( /W 32) Interrupt Disable Register */
+ __I GMAC_IMR_Type IMR; /**< \brief Offset: 0x030 (R/ 32) Interrupt Mask Register */
+ __IO GMAC_MAN_Type MAN; /**< \brief Offset: 0x034 (R/W 32) PHY Maintenance Register */
+ __I GMAC_RPQ_Type RPQ; /**< \brief Offset: 0x038 (R/ 32) Received Pause Quantum Register */
+ __IO GMAC_TPQ_Type TPQ; /**< \brief Offset: 0x03C (R/W 32) Transmit Pause Quantum Register */
+ __IO GMAC_TPSF_Type TPSF; /**< \brief Offset: 0x040 (R/W 32) TX partial store and forward Register */
+ __IO GMAC_RPSF_Type RPSF; /**< \brief Offset: 0x044 (R/W 32) RX partial store and forward Register */
+ __IO GMAC_RJFML_Type RJFML; /**< \brief Offset: 0x048 (R/W 32) RX Jumbo Frame Max Length Register */
+ RoReg8 Reserved1[0x34];
+ __IO GMAC_HRB_Type HRB; /**< \brief Offset: 0x080 (R/W 32) Hash Register Bottom [31:0] */
+ __IO GMAC_HRT_Type HRT; /**< \brief Offset: 0x084 (R/W 32) Hash Register Top [63:32] */
+ GmacSa Sa[4]; /**< \brief Offset: 0x088 GmacSa groups */
+ __IO GMAC_TIDM_Type TIDM[4]; /**< \brief Offset: 0x0A8 (R/W 32) Type ID Match Register */
+ __IO GMAC_WOL_Type WOL; /**< \brief Offset: 0x0B8 (R/W 32) Wake on LAN */
+ __IO GMAC_IPGS_Type IPGS; /**< \brief Offset: 0x0BC (R/W 32) IPG Stretch Register */
+ __IO GMAC_SVLAN_Type SVLAN; /**< \brief Offset: 0x0C0 (R/W 32) Stacked VLAN Register */
+ __IO GMAC_TPFCP_Type TPFCP; /**< \brief Offset: 0x0C4 (R/W 32) Transmit PFC Pause Register */
+ __IO GMAC_SAMB1_Type SAMB1; /**< \brief Offset: 0x0C8 (R/W 32) Specific Address 1 Mask Bottom [31:0] Register */
+ __IO GMAC_SAMT1_Type SAMT1; /**< \brief Offset: 0x0CC (R/W 32) Specific Address 1 Mask Top [47:32] Register */
+ RoReg8 Reserved2[0xC];
+ __IO GMAC_NSC_Type NSC; /**< \brief Offset: 0x0DC (R/W 32) Tsu timer comparison nanoseconds Register */
+ __IO GMAC_SCL_Type SCL; /**< \brief Offset: 0x0E0 (R/W 32) Tsu timer second comparison Register */
+ __IO GMAC_SCH_Type SCH; /**< \brief Offset: 0x0E4 (R/W 32) Tsu timer second comparison Register */
+ __I GMAC_EFTSH_Type EFTSH; /**< \brief Offset: 0x0E8 (R/ 32) PTP Event Frame Transmitted Seconds High Register */
+ __I GMAC_EFRSH_Type EFRSH; /**< \brief Offset: 0x0EC (R/ 32) PTP Event Frame Received Seconds High Register */
+ __I GMAC_PEFTSH_Type PEFTSH; /**< \brief Offset: 0x0F0 (R/ 32) PTP Peer Event Frame Transmitted Seconds High Register */
+ __I GMAC_PEFRSH_Type PEFRSH; /**< \brief Offset: 0x0F4 (R/ 32) PTP Peer Event Frame Received Seconds High Register */
+ RoReg8 Reserved3[0x8];
+ __I GMAC_OTLO_Type OTLO; /**< \brief Offset: 0x100 (R/ 32) Octets Transmitted [31:0] Register */
+ __I GMAC_OTHI_Type OTHI; /**< \brief Offset: 0x104 (R/ 32) Octets Transmitted [47:32] Register */
+ __I GMAC_FT_Type FT; /**< \brief Offset: 0x108 (R/ 32) Frames Transmitted Register */
+ __I GMAC_BCFT_Type BCFT; /**< \brief Offset: 0x10C (R/ 32) Broadcast Frames Transmitted Register */
+ __I GMAC_MFT_Type MFT; /**< \brief Offset: 0x110 (R/ 32) Multicast Frames Transmitted Register */
+ __I GMAC_PFT_Type PFT; /**< \brief Offset: 0x114 (R/ 32) Pause Frames Transmitted Register */
+ __I GMAC_BFT64_Type BFT64; /**< \brief Offset: 0x118 (R/ 32) 64 Byte Frames Transmitted Register */
+ __I GMAC_TBFT127_Type TBFT127; /**< \brief Offset: 0x11C (R/ 32) 65 to 127 Byte Frames Transmitted Register */
+ __I GMAC_TBFT255_Type TBFT255; /**< \brief Offset: 0x120 (R/ 32) 128 to 255 Byte Frames Transmitted Register */
+ __I GMAC_TBFT511_Type TBFT511; /**< \brief Offset: 0x124 (R/ 32) 256 to 511 Byte Frames Transmitted Register */
+ __I GMAC_TBFT1023_Type TBFT1023; /**< \brief Offset: 0x128 (R/ 32) 512 to 1023 Byte Frames Transmitted Register */
+ __I GMAC_TBFT1518_Type TBFT1518; /**< \brief Offset: 0x12C (R/ 32) 1024 to 1518 Byte Frames Transmitted Register */
+ __I GMAC_GTBFT1518_Type GTBFT1518; /**< \brief Offset: 0x130 (R/ 32) Greater Than 1518 Byte Frames Transmitted Register */
+ __I GMAC_TUR_Type TUR; /**< \brief Offset: 0x134 (R/ 32) Transmit Underruns Register */
+ __I GMAC_SCF_Type SCF; /**< \brief Offset: 0x138 (R/ 32) Single Collision Frames Register */
+ __I GMAC_MCF_Type MCF; /**< \brief Offset: 0x13C (R/ 32) Multiple Collision Frames Register */
+ __I GMAC_EC_Type EC; /**< \brief Offset: 0x140 (R/ 32) Excessive Collisions Register */
+ __I GMAC_LC_Type LC; /**< \brief Offset: 0x144 (R/ 32) Late Collisions Register */
+ __I GMAC_DTF_Type DTF; /**< \brief Offset: 0x148 (R/ 32) Deferred Transmission Frames Register */
+ __I GMAC_CSE_Type CSE; /**< \brief Offset: 0x14C (R/ 32) Carrier Sense Errors Register */
+ __I GMAC_ORLO_Type ORLO; /**< \brief Offset: 0x150 (R/ 32) Octets Received [31:0] Received */
+ __I GMAC_ORHI_Type ORHI; /**< \brief Offset: 0x154 (R/ 32) Octets Received [47:32] Received */
+ __I GMAC_FR_Type FR; /**< \brief Offset: 0x158 (R/ 32) Frames Received Register */
+ __I GMAC_BCFR_Type BCFR; /**< \brief Offset: 0x15C (R/ 32) Broadcast Frames Received Register */
+ __I GMAC_MFR_Type MFR; /**< \brief Offset: 0x160 (R/ 32) Multicast Frames Received Register */
+ __I GMAC_PFR_Type PFR; /**< \brief Offset: 0x164 (R/ 32) Pause Frames Received Register */
+ __I GMAC_BFR64_Type BFR64; /**< \brief Offset: 0x168 (R/ 32) 64 Byte Frames Received Register */
+ __I GMAC_TBFR127_Type TBFR127; /**< \brief Offset: 0x16C (R/ 32) 65 to 127 Byte Frames Received Register */
+ __I GMAC_TBFR255_Type TBFR255; /**< \brief Offset: 0x170 (R/ 32) 128 to 255 Byte Frames Received Register */
+ __I GMAC_TBFR511_Type TBFR511; /**< \brief Offset: 0x174 (R/ 32) 256 to 511Byte Frames Received Register */
+ __I GMAC_TBFR1023_Type TBFR1023; /**< \brief Offset: 0x178 (R/ 32) 512 to 1023 Byte Frames Received Register */
+ __I GMAC_TBFR1518_Type TBFR1518; /**< \brief Offset: 0x17C (R/ 32) 1024 to 1518 Byte Frames Received Register */
+ __I GMAC_TMXBFR_Type TMXBFR; /**< \brief Offset: 0x180 (R/ 32) 1519 to Maximum Byte Frames Received Register */
+ __I GMAC_UFR_Type UFR; /**< \brief Offset: 0x184 (R/ 32) Undersize Frames Received Register */
+ __I GMAC_OFR_Type OFR; /**< \brief Offset: 0x188 (R/ 32) Oversize Frames Received Register */
+ __I GMAC_JR_Type JR; /**< \brief Offset: 0x18C (R/ 32) Jabbers Received Register */
+ __I GMAC_FCSE_Type FCSE; /**< \brief Offset: 0x190 (R/ 32) Frame Check Sequence Errors Register */
+ __I GMAC_LFFE_Type LFFE; /**< \brief Offset: 0x194 (R/ 32) Length Field Frame Errors Register */
+ __I GMAC_RSE_Type RSE; /**< \brief Offset: 0x198 (R/ 32) Receive Symbol Errors Register */
+ __I GMAC_AE_Type AE; /**< \brief Offset: 0x19C (R/ 32) Alignment Errors Register */
+ __I GMAC_RRE_Type RRE; /**< \brief Offset: 0x1A0 (R/ 32) Receive Resource Errors Register */
+ __I GMAC_ROE_Type ROE; /**< \brief Offset: 0x1A4 (R/ 32) Receive Overrun Register */
+ __I GMAC_IHCE_Type IHCE; /**< \brief Offset: 0x1A8 (R/ 32) IP Header Checksum Errors Register */
+ __I GMAC_TCE_Type TCE; /**< \brief Offset: 0x1AC (R/ 32) TCP Checksum Errors Register */
+ __I GMAC_UCE_Type UCE; /**< \brief Offset: 0x1B0 (R/ 32) UDP Checksum Errors Register */
+ RoReg8 Reserved4[0x8];
+ __IO GMAC_TISUBN_Type TISUBN; /**< \brief Offset: 0x1BC (R/W 32) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
+ __IO GMAC_TSH_Type TSH; /**< \brief Offset: 0x1C0 (R/W 32) 1588 Timer Seconds High [15:0] Register */
+ RoReg8 Reserved5[0x4];
+ __IO GMAC_TSSSL_Type TSSSL; /**< \brief Offset: 0x1C8 (R/W 32) 1588 Timer Sync Strobe Seconds [31:0] Register */
+ __IO GMAC_TSSN_Type TSSN; /**< \brief Offset: 0x1CC (R/W 32) 1588 Timer Sync Strobe Nanoseconds Register */
+ __IO GMAC_TSL_Type TSL; /**< \brief Offset: 0x1D0 (R/W 32) 1588 Timer Seconds [31:0] Register */
+ __IO GMAC_TN_Type TN; /**< \brief Offset: 0x1D4 (R/W 32) 1588 Timer Nanoseconds Register */
+ __O GMAC_TA_Type TA; /**< \brief Offset: 0x1D8 ( /W 32) 1588 Timer Adjust Register */
+ __IO GMAC_TI_Type TI; /**< \brief Offset: 0x1DC (R/W 32) 1588 Timer Increment Register */
+ __I GMAC_EFTSL_Type EFTSL; /**< \brief Offset: 0x1E0 (R/ 32) PTP Event Frame Transmitted Seconds Low Register */
+ __I GMAC_EFTN_Type EFTN; /**< \brief Offset: 0x1E4 (R/ 32) PTP Event Frame Transmitted Nanoseconds */
+ __I GMAC_EFRSL_Type EFRSL; /**< \brief Offset: 0x1E8 (R/ 32) PTP Event Frame Received Seconds Low Register */
+ __I GMAC_EFRN_Type EFRN; /**< \brief Offset: 0x1EC (R/ 32) PTP Event Frame Received Nanoseconds */
+ __I GMAC_PEFTSL_Type PEFTSL; /**< \brief Offset: 0x1F0 (R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register */
+ __I GMAC_PEFTN_Type PEFTN; /**< \brief Offset: 0x1F4 (R/ 32) PTP Peer Event Frame Transmitted Nanoseconds */
+ __I GMAC_PEFRSL_Type PEFRSL; /**< \brief Offset: 0x1F8 (R/ 32) PTP Peer Event Frame Received Seconds Low Register */
+ __I GMAC_PEFRN_Type PEFRN; /**< \brief Offset: 0x1FC (R/ 32) PTP Peer Event Frame Received Nanoseconds */
+ RoReg8 Reserved6[0x70];
+ __I GMAC_RLPITR_Type RLPITR; /**< \brief Offset: 0x270 (R/ 32) Receive LPI transition Register */
+ __I GMAC_RLPITI_Type RLPITI; /**< \brief Offset: 0x274 (R/ 32) Receive LPI Time Register */
+ __I GMAC_TLPITR_Type TLPITR; /**< \brief Offset: 0x278 (R/ 32) Receive LPI transition Register */
+ __I GMAC_TLPITI_Type TLPITI; /**< \brief Offset: 0x27C (R/ 32) Receive LPI Time Register */
+} Gmac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_GMAC_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/hmatrixb.h b/sysmoOCTSIM/include/component/hmatrixb.h
index a0c99b9..72b47ff 100644
--- a/sysmoOCTSIM/include/component/hmatrixb.h
+++ b/sysmoOCTSIM/include/component/hmatrixb.h
@@ -1,84 +1,84 @@
-/**
- * \file
- *
- * \brief Component description for HMATRIXB
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_HMATRIXB_COMPONENT_
-#define _SAME54_HMATRIXB_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR HMATRIXB */
-/* ========================================================================== */
-/** \addtogroup SAME54_HMATRIXB HSB Matrix */
-/*@{*/
-
-#define HMATRIXB_I7638
-#define REV_HMATRIXB 0x214
-
-/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint32_t reg; /*!< Type used for register access */
-} HMATRIXB_PRAS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define HMATRIXB_PRAS_OFFSET 0x080 /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
-#define HMATRIXB_PRAS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
-
-#define HMATRIXB_PRAS_MASK _U_(0x00000000) /**< \brief (HMATRIXB_PRAS) MASK Register */
-
-/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint32_t reg; /*!< Type used for register access */
-} HMATRIXB_PRBS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define HMATRIXB_PRBS_OFFSET 0x084 /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
-#define HMATRIXB_PRBS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
-
-#define HMATRIXB_PRBS_MASK _U_(0x00000000) /**< \brief (HMATRIXB_PRBS) MASK Register */
-
-/** \brief HmatrixbPrs hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
- __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
-} HmatrixbPrs;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief HMATRIXB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- RoReg8 Reserved1[0x80];
- HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
-} Hmatrixb;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_HMATRIXB_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for HMATRIXB
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_HMATRIXB_COMPONENT_
+#define _SAME54_HMATRIXB_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR HMATRIXB */
+/* ========================================================================== */
+/** \addtogroup SAME54_HMATRIXB HSB Matrix */
+/*@{*/
+
+#define HMATRIXB_I7638
+#define REV_HMATRIXB 0x214
+
+/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} HMATRIXB_PRAS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_PRAS_OFFSET 0x080 /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
+#define HMATRIXB_PRAS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
+
+#define HMATRIXB_PRAS_MASK _U_(0x00000000) /**< \brief (HMATRIXB_PRAS) MASK Register */
+
+/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} HMATRIXB_PRBS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_PRBS_OFFSET 0x084 /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
+#define HMATRIXB_PRBS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
+
+#define HMATRIXB_PRBS_MASK _U_(0x00000000) /**< \brief (HMATRIXB_PRBS) MASK Register */
+
+/** \brief HmatrixbPrs hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
+ __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
+} HmatrixbPrs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief HMATRIXB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ RoReg8 Reserved1[0x80];
+ HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
+} Hmatrixb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_HMATRIXB_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/i2s.h b/sysmoOCTSIM/include/component/i2s.h
index b418d54..49a50af 100644
--- a/sysmoOCTSIM/include/component/i2s.h
+++ b/sysmoOCTSIM/include/component/i2s.h
@@ -1,747 +1,747 @@
-/**
- * \file
- *
- * \brief Component description for I2S
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_I2S_COMPONENT_
-#define _SAME54_I2S_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR I2S */
-/* ========================================================================== */
-/** \addtogroup SAME54_I2S Inter-IC Sound Interface */
-/*@{*/
-
-#define I2S_U2224
-#define REV_I2S 0x200
-
-/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
- uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
- uint8_t TXEN:1; /*!< bit: 4 Tx Serializer Enable */
- uint8_t RXEN:1; /*!< bit: 5 Rx Serializer Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :2; /*!< bit: 0.. 1 Reserved */
- uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} I2S_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_CTRLA_OFFSET 0x00 /**< \brief (I2S_CTRLA offset) Control A */
-#define I2S_CTRLA_RESETVALUE _U_(0x00) /**< \brief (I2S_CTRLA reset_value) Control A */
-
-#define I2S_CTRLA_SWRST_Pos 0 /**< \brief (I2S_CTRLA) Software Reset */
-#define I2S_CTRLA_SWRST (_U_(0x1) << I2S_CTRLA_SWRST_Pos)
-#define I2S_CTRLA_ENABLE_Pos 1 /**< \brief (I2S_CTRLA) Enable */
-#define I2S_CTRLA_ENABLE (_U_(0x1) << I2S_CTRLA_ENABLE_Pos)
-#define I2S_CTRLA_CKEN0_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
-#define I2S_CTRLA_CKEN0 (_U_(1) << I2S_CTRLA_CKEN0_Pos)
-#define I2S_CTRLA_CKEN1_Pos 3 /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
-#define I2S_CTRLA_CKEN1 (_U_(1) << I2S_CTRLA_CKEN1_Pos)
-#define I2S_CTRLA_CKEN_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit x Enable */
-#define I2S_CTRLA_CKEN_Msk (_U_(0x3) << I2S_CTRLA_CKEN_Pos)
-#define I2S_CTRLA_CKEN(value) (I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos))
-#define I2S_CTRLA_TXEN_Pos 4 /**< \brief (I2S_CTRLA) Tx Serializer Enable */
-#define I2S_CTRLA_TXEN (_U_(0x1) << I2S_CTRLA_TXEN_Pos)
-#define I2S_CTRLA_RXEN_Pos 5 /**< \brief (I2S_CTRLA) Rx Serializer Enable */
-#define I2S_CTRLA_RXEN (_U_(0x1) << I2S_CTRLA_RXEN_Pos)
-#define I2S_CTRLA_MASK _U_(0x3F) /**< \brief (I2S_CTRLA) MASK Register */
-
-/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
- uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
- uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
- uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
- uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
- uint32_t FSINV:1; /*!< bit: 9 Frame Sync Invert */
- uint32_t FSOUTINV:1; /*!< bit: 10 Frame Sync Output Invert */
- uint32_t SCKSEL:1; /*!< bit: 11 Serial Clock Select */
- uint32_t SCKOUTINV:1; /*!< bit: 12 Serial Clock Output Invert */
- uint32_t MCKSEL:1; /*!< bit: 13 Master Clock Select */
- uint32_t MCKEN:1; /*!< bit: 14 Master Clock Enable */
- uint32_t MCKOUTINV:1; /*!< bit: 15 Master Clock Output Invert */
- uint32_t MCKDIV:6; /*!< bit: 16..21 Master Clock Division Factor */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t MCKOUTDIV:6; /*!< bit: 24..29 Master Clock Output Division Factor */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} I2S_CLKCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_CLKCTRL_OFFSET 0x04 /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
-#define I2S_CLKCTRL_RESETVALUE _U_(0x00000000) /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
-
-#define I2S_CLKCTRL_SLOTSIZE_Pos 0 /**< \brief (I2S_CLKCTRL) Slot Size */
-#define I2S_CLKCTRL_SLOTSIZE_Msk (_U_(0x3) << I2S_CLKCTRL_SLOTSIZE_Pos)
-#define I2S_CLKCTRL_SLOTSIZE(value) (I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))
-#define I2S_CLKCTRL_SLOTSIZE_8_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
-#define I2S_CLKCTRL_SLOTSIZE_16_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
-#define I2S_CLKCTRL_SLOTSIZE_24_Val _U_(0x2) /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
-#define I2S_CLKCTRL_SLOTSIZE_32_Val _U_(0x3) /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
-#define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
-#define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
-#define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
-#define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
-#define I2S_CLKCTRL_NBSLOTS_Pos 2 /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
-#define I2S_CLKCTRL_NBSLOTS_Msk (_U_(0x7) << I2S_CLKCTRL_NBSLOTS_Pos)
-#define I2S_CLKCTRL_NBSLOTS(value) (I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))
-#define I2S_CLKCTRL_FSWIDTH_Pos 5 /**< \brief (I2S_CLKCTRL) Frame Sync Width */
-#define I2S_CLKCTRL_FSWIDTH_Msk (_U_(0x3) << I2S_CLKCTRL_FSWIDTH_Pos)
-#define I2S_CLKCTRL_FSWIDTH(value) (I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))
-#define I2S_CLKCTRL_FSWIDTH_SLOT_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
-#define I2S_CLKCTRL_FSWIDTH_HALF_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
-#define I2S_CLKCTRL_FSWIDTH_BIT_Val _U_(0x2) /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
-#define I2S_CLKCTRL_FSWIDTH_BURST_Val _U_(0x3) /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
-#define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
-#define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos)
-#define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
-#define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
-#define I2S_CLKCTRL_BITDELAY_Pos 7 /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
-#define I2S_CLKCTRL_BITDELAY (_U_(0x1) << I2S_CLKCTRL_BITDELAY_Pos)
-#define I2S_CLKCTRL_BITDELAY_LJ_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
-#define I2S_CLKCTRL_BITDELAY_I2S_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
-#define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos)
-#define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos)
-#define I2S_CLKCTRL_FSSEL_Pos 8 /**< \brief (I2S_CLKCTRL) Frame Sync Select */
-#define I2S_CLKCTRL_FSSEL (_U_(0x1) << I2S_CLKCTRL_FSSEL_Pos)
-#define I2S_CLKCTRL_FSSEL_SCKDIV_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
-#define I2S_CLKCTRL_FSSEL_FSPIN_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
-#define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos)
-#define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos)
-#define I2S_CLKCTRL_FSINV_Pos 9 /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
-#define I2S_CLKCTRL_FSINV (_U_(0x1) << I2S_CLKCTRL_FSINV_Pos)
-#define I2S_CLKCTRL_FSOUTINV_Pos 10 /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
-#define I2S_CLKCTRL_FSOUTINV (_U_(0x1) << I2S_CLKCTRL_FSOUTINV_Pos)
-#define I2S_CLKCTRL_SCKSEL_Pos 11 /**< \brief (I2S_CLKCTRL) Serial Clock Select */
-#define I2S_CLKCTRL_SCKSEL (_U_(0x1) << I2S_CLKCTRL_SCKSEL_Pos)
-#define I2S_CLKCTRL_SCKSEL_MCKDIV_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
-#define I2S_CLKCTRL_SCKSEL_SCKPIN_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
-#define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
-#define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
-#define I2S_CLKCTRL_SCKOUTINV_Pos 12 /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
-#define I2S_CLKCTRL_SCKOUTINV (_U_(0x1) << I2S_CLKCTRL_SCKOUTINV_Pos)
-#define I2S_CLKCTRL_MCKSEL_Pos 13 /**< \brief (I2S_CLKCTRL) Master Clock Select */
-#define I2S_CLKCTRL_MCKSEL (_U_(0x1) << I2S_CLKCTRL_MCKSEL_Pos)
-#define I2S_CLKCTRL_MCKSEL_GCLK_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
-#define I2S_CLKCTRL_MCKSEL_MCKPIN_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
-#define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos)
-#define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
-#define I2S_CLKCTRL_MCKEN_Pos 14 /**< \brief (I2S_CLKCTRL) Master Clock Enable */
-#define I2S_CLKCTRL_MCKEN (_U_(0x1) << I2S_CLKCTRL_MCKEN_Pos)
-#define I2S_CLKCTRL_MCKOUTINV_Pos 15 /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
-#define I2S_CLKCTRL_MCKOUTINV (_U_(0x1) << I2S_CLKCTRL_MCKOUTINV_Pos)
-#define I2S_CLKCTRL_MCKDIV_Pos 16 /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
-#define I2S_CLKCTRL_MCKDIV_Msk (_U_(0x3F) << I2S_CLKCTRL_MCKDIV_Pos)
-#define I2S_CLKCTRL_MCKDIV(value) (I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))
-#define I2S_CLKCTRL_MCKOUTDIV_Pos 24 /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
-#define I2S_CLKCTRL_MCKOUTDIV_Msk (_U_(0x3F) << I2S_CLKCTRL_MCKOUTDIV_Pos)
-#define I2S_CLKCTRL_MCKOUTDIV(value) (I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))
-#define I2S_CLKCTRL_MASK _U_(0x3F3FFFFF) /**< \brief (I2S_CLKCTRL) MASK Register */
-
-/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
- uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
- uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
- uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
- uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} I2S_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_INTENCLR_OFFSET 0x0C /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
-#define I2S_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define I2S_INTENCLR_RXRDY0_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
-#define I2S_INTENCLR_RXRDY0 (_U_(1) << I2S_INTENCLR_RXRDY0_Pos)
-#define I2S_INTENCLR_RXRDY1_Pos 1 /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
-#define I2S_INTENCLR_RXRDY1 (_U_(1) << I2S_INTENCLR_RXRDY1_Pos)
-#define I2S_INTENCLR_RXRDY_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
-#define I2S_INTENCLR_RXRDY_Msk (_U_(0x3) << I2S_INTENCLR_RXRDY_Pos)
-#define I2S_INTENCLR_RXRDY(value) (I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos))
-#define I2S_INTENCLR_RXOR0_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
-#define I2S_INTENCLR_RXOR0 (_U_(1) << I2S_INTENCLR_RXOR0_Pos)
-#define I2S_INTENCLR_RXOR1_Pos 5 /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
-#define I2S_INTENCLR_RXOR1 (_U_(1) << I2S_INTENCLR_RXOR1_Pos)
-#define I2S_INTENCLR_RXOR_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
-#define I2S_INTENCLR_RXOR_Msk (_U_(0x3) << I2S_INTENCLR_RXOR_Pos)
-#define I2S_INTENCLR_RXOR(value) (I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos))
-#define I2S_INTENCLR_TXRDY0_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
-#define I2S_INTENCLR_TXRDY0 (_U_(1) << I2S_INTENCLR_TXRDY0_Pos)
-#define I2S_INTENCLR_TXRDY1_Pos 9 /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
-#define I2S_INTENCLR_TXRDY1 (_U_(1) << I2S_INTENCLR_TXRDY1_Pos)
-#define I2S_INTENCLR_TXRDY_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
-#define I2S_INTENCLR_TXRDY_Msk (_U_(0x3) << I2S_INTENCLR_TXRDY_Pos)
-#define I2S_INTENCLR_TXRDY(value) (I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos))
-#define I2S_INTENCLR_TXUR0_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
-#define I2S_INTENCLR_TXUR0 (_U_(1) << I2S_INTENCLR_TXUR0_Pos)
-#define I2S_INTENCLR_TXUR1_Pos 13 /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
-#define I2S_INTENCLR_TXUR1 (_U_(1) << I2S_INTENCLR_TXUR1_Pos)
-#define I2S_INTENCLR_TXUR_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
-#define I2S_INTENCLR_TXUR_Msk (_U_(0x3) << I2S_INTENCLR_TXUR_Pos)
-#define I2S_INTENCLR_TXUR(value) (I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos))
-#define I2S_INTENCLR_MASK _U_(0x3333) /**< \brief (I2S_INTENCLR) MASK Register */
-
-/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
- uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
- uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
- uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
- uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} I2S_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_INTENSET_OFFSET 0x10 /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
-#define I2S_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
-
-#define I2S_INTENSET_RXRDY0_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
-#define I2S_INTENSET_RXRDY0 (_U_(1) << I2S_INTENSET_RXRDY0_Pos)
-#define I2S_INTENSET_RXRDY1_Pos 1 /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
-#define I2S_INTENSET_RXRDY1 (_U_(1) << I2S_INTENSET_RXRDY1_Pos)
-#define I2S_INTENSET_RXRDY_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
-#define I2S_INTENSET_RXRDY_Msk (_U_(0x3) << I2S_INTENSET_RXRDY_Pos)
-#define I2S_INTENSET_RXRDY(value) (I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos))
-#define I2S_INTENSET_RXOR0_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
-#define I2S_INTENSET_RXOR0 (_U_(1) << I2S_INTENSET_RXOR0_Pos)
-#define I2S_INTENSET_RXOR1_Pos 5 /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
-#define I2S_INTENSET_RXOR1 (_U_(1) << I2S_INTENSET_RXOR1_Pos)
-#define I2S_INTENSET_RXOR_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
-#define I2S_INTENSET_RXOR_Msk (_U_(0x3) << I2S_INTENSET_RXOR_Pos)
-#define I2S_INTENSET_RXOR(value) (I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos))
-#define I2S_INTENSET_TXRDY0_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
-#define I2S_INTENSET_TXRDY0 (_U_(1) << I2S_INTENSET_TXRDY0_Pos)
-#define I2S_INTENSET_TXRDY1_Pos 9 /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
-#define I2S_INTENSET_TXRDY1 (_U_(1) << I2S_INTENSET_TXRDY1_Pos)
-#define I2S_INTENSET_TXRDY_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
-#define I2S_INTENSET_TXRDY_Msk (_U_(0x3) << I2S_INTENSET_TXRDY_Pos)
-#define I2S_INTENSET_TXRDY(value) (I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos))
-#define I2S_INTENSET_TXUR0_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
-#define I2S_INTENSET_TXUR0 (_U_(1) << I2S_INTENSET_TXUR0_Pos)
-#define I2S_INTENSET_TXUR1_Pos 13 /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
-#define I2S_INTENSET_TXUR1 (_U_(1) << I2S_INTENSET_TXUR1_Pos)
-#define I2S_INTENSET_TXUR_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
-#define I2S_INTENSET_TXUR_Msk (_U_(0x3) << I2S_INTENSET_TXUR_Pos)
-#define I2S_INTENSET_TXUR(value) (I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos))
-#define I2S_INTENSET_MASK _U_(0x3333) /**< \brief (I2S_INTENSET) MASK Register */
-
-/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
- __I uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
- __I uint16_t :2; /*!< bit: 2.. 3 Reserved */
- __I uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
- __I uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
- __I uint16_t :2; /*!< bit: 6.. 7 Reserved */
- __I uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
- __I uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
- __I uint16_t :2; /*!< bit: 10..11 Reserved */
- __I uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
- __I uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
- __I uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
- __I uint16_t :2; /*!< bit: 2.. 3 Reserved */
- __I uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
- __I uint16_t :2; /*!< bit: 6.. 7 Reserved */
- __I uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
- __I uint16_t :2; /*!< bit: 10..11 Reserved */
- __I uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
- __I uint16_t :2; /*!< bit: 14..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} I2S_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_INTFLAG_OFFSET 0x14 /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
-#define I2S_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define I2S_INTFLAG_RXRDY0_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready 0 */
-#define I2S_INTFLAG_RXRDY0 (_U_(1) << I2S_INTFLAG_RXRDY0_Pos)
-#define I2S_INTFLAG_RXRDY1_Pos 1 /**< \brief (I2S_INTFLAG) Receive Ready 1 */
-#define I2S_INTFLAG_RXRDY1 (_U_(1) << I2S_INTFLAG_RXRDY1_Pos)
-#define I2S_INTFLAG_RXRDY_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready x */
-#define I2S_INTFLAG_RXRDY_Msk (_U_(0x3) << I2S_INTFLAG_RXRDY_Pos)
-#define I2S_INTFLAG_RXRDY(value) (I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos))
-#define I2S_INTFLAG_RXOR0_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
-#define I2S_INTFLAG_RXOR0 (_U_(1) << I2S_INTFLAG_RXOR0_Pos)
-#define I2S_INTFLAG_RXOR1_Pos 5 /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
-#define I2S_INTFLAG_RXOR1 (_U_(1) << I2S_INTFLAG_RXOR1_Pos)
-#define I2S_INTFLAG_RXOR_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun x */
-#define I2S_INTFLAG_RXOR_Msk (_U_(0x3) << I2S_INTFLAG_RXOR_Pos)
-#define I2S_INTFLAG_RXOR(value) (I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos))
-#define I2S_INTFLAG_TXRDY0_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
-#define I2S_INTFLAG_TXRDY0 (_U_(1) << I2S_INTFLAG_TXRDY0_Pos)
-#define I2S_INTFLAG_TXRDY1_Pos 9 /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
-#define I2S_INTFLAG_TXRDY1 (_U_(1) << I2S_INTFLAG_TXRDY1_Pos)
-#define I2S_INTFLAG_TXRDY_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready x */
-#define I2S_INTFLAG_TXRDY_Msk (_U_(0x3) << I2S_INTFLAG_TXRDY_Pos)
-#define I2S_INTFLAG_TXRDY(value) (I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos))
-#define I2S_INTFLAG_TXUR0_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
-#define I2S_INTFLAG_TXUR0 (_U_(1) << I2S_INTFLAG_TXUR0_Pos)
-#define I2S_INTFLAG_TXUR1_Pos 13 /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
-#define I2S_INTFLAG_TXUR1 (_U_(1) << I2S_INTFLAG_TXUR1_Pos)
-#define I2S_INTFLAG_TXUR_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun x */
-#define I2S_INTFLAG_TXUR_Msk (_U_(0x3) << I2S_INTFLAG_TXUR_Pos)
-#define I2S_INTFLAG_TXUR(value) (I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos))
-#define I2S_INTFLAG_MASK _U_(0x3333) /**< \brief (I2S_INTFLAG) MASK Register */
-
-/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
- uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
- uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
- uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
- uint16_t TXEN:1; /*!< bit: 4 Tx Serializer Enable Synchronization Status */
- uint16_t RXEN:1; /*!< bit: 5 Rx Serializer Enable Synchronization Status */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t TXDATA:1; /*!< bit: 8 Tx Data Synchronization Status */
- uint16_t RXDATA:1; /*!< bit: 9 Rx Data Synchronization Status */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
- uint16_t :12; /*!< bit: 4..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} I2S_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_SYNCBUSY_OFFSET 0x18 /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
-#define I2S_SYNCBUSY_RESETVALUE _U_(0x0000) /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
-
-#define I2S_SYNCBUSY_SWRST_Pos 0 /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
-#define I2S_SYNCBUSY_SWRST (_U_(0x1) << I2S_SYNCBUSY_SWRST_Pos)
-#define I2S_SYNCBUSY_ENABLE_Pos 1 /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
-#define I2S_SYNCBUSY_ENABLE (_U_(0x1) << I2S_SYNCBUSY_ENABLE_Pos)
-#define I2S_SYNCBUSY_CKEN0_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
-#define I2S_SYNCBUSY_CKEN0 (_U_(1) << I2S_SYNCBUSY_CKEN0_Pos)
-#define I2S_SYNCBUSY_CKEN1_Pos 3 /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
-#define I2S_SYNCBUSY_CKEN1 (_U_(1) << I2S_SYNCBUSY_CKEN1_Pos)
-#define I2S_SYNCBUSY_CKEN_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
-#define I2S_SYNCBUSY_CKEN_Msk (_U_(0x3) << I2S_SYNCBUSY_CKEN_Pos)
-#define I2S_SYNCBUSY_CKEN(value) (I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos))
-#define I2S_SYNCBUSY_TXEN_Pos 4 /**< \brief (I2S_SYNCBUSY) Tx Serializer Enable Synchronization Status */
-#define I2S_SYNCBUSY_TXEN (_U_(0x1) << I2S_SYNCBUSY_TXEN_Pos)
-#define I2S_SYNCBUSY_RXEN_Pos 5 /**< \brief (I2S_SYNCBUSY) Rx Serializer Enable Synchronization Status */
-#define I2S_SYNCBUSY_RXEN (_U_(0x1) << I2S_SYNCBUSY_RXEN_Pos)
-#define I2S_SYNCBUSY_TXDATA_Pos 8 /**< \brief (I2S_SYNCBUSY) Tx Data Synchronization Status */
-#define I2S_SYNCBUSY_TXDATA (_U_(0x1) << I2S_SYNCBUSY_TXDATA_Pos)
-#define I2S_SYNCBUSY_RXDATA_Pos 9 /**< \brief (I2S_SYNCBUSY) Rx Data Synchronization Status */
-#define I2S_SYNCBUSY_RXDATA (_U_(0x1) << I2S_SYNCBUSY_RXDATA_Pos)
-#define I2S_SYNCBUSY_MASK _U_(0x033F) /**< \brief (I2S_SYNCBUSY) MASK Register */
-
-/* -------- I2S_TXCTRL : (I2S Offset: 0x20) (R/W 32) Tx Serializer Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
- uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
- uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
- uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
- uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
- uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
- uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
- uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
- uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
- uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
- uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
- uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
- uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
- uint32_t MONO:1; /*!< bit: 24 Mono Mode */
- uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
- uint32_t :6; /*!< bit: 26..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} I2S_TXCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_TXCTRL_OFFSET 0x20 /**< \brief (I2S_TXCTRL offset) Tx Serializer Control */
-#define I2S_TXCTRL_RESETVALUE _U_(0x00000000) /**< \brief (I2S_TXCTRL reset_value) Tx Serializer Control */
-
-#define I2S_TXCTRL_TXDEFAULT_Pos 2 /**< \brief (I2S_TXCTRL) Line Default Line when Slot Disabled */
-#define I2S_TXCTRL_TXDEFAULT_Msk (_U_(0x3) << I2S_TXCTRL_TXDEFAULT_Pos)
-#define I2S_TXCTRL_TXDEFAULT(value) (I2S_TXCTRL_TXDEFAULT_Msk & ((value) << I2S_TXCTRL_TXDEFAULT_Pos))
-#define I2S_TXCTRL_TXDEFAULT_ZERO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Output Default Value is 0 */
-#define I2S_TXCTRL_TXDEFAULT_ONE_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Output Default Value is 1 */
-#define I2S_TXCTRL_TXDEFAULT_HIZ_Val _U_(0x3) /**< \brief (I2S_TXCTRL) Output Default Value is high impedance */
-#define I2S_TXCTRL_TXDEFAULT_ZERO (I2S_TXCTRL_TXDEFAULT_ZERO_Val << I2S_TXCTRL_TXDEFAULT_Pos)
-#define I2S_TXCTRL_TXDEFAULT_ONE (I2S_TXCTRL_TXDEFAULT_ONE_Val << I2S_TXCTRL_TXDEFAULT_Pos)
-#define I2S_TXCTRL_TXDEFAULT_HIZ (I2S_TXCTRL_TXDEFAULT_HIZ_Val << I2S_TXCTRL_TXDEFAULT_Pos)
-#define I2S_TXCTRL_TXSAME_Pos 4 /**< \brief (I2S_TXCTRL) Transmit Data when Underrun */
-#define I2S_TXCTRL_TXSAME (_U_(0x1) << I2S_TXCTRL_TXSAME_Pos)
-#define I2S_TXCTRL_TXSAME_ZERO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Zero data transmitted in case of underrun */
-#define I2S_TXCTRL_TXSAME_SAME_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Last data transmitted in case of underrun */
-#define I2S_TXCTRL_TXSAME_ZERO (I2S_TXCTRL_TXSAME_ZERO_Val << I2S_TXCTRL_TXSAME_Pos)
-#define I2S_TXCTRL_TXSAME_SAME (I2S_TXCTRL_TXSAME_SAME_Val << I2S_TXCTRL_TXSAME_Pos)
-#define I2S_TXCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_TXCTRL) Data Slot Formatting Adjust */
-#define I2S_TXCTRL_SLOTADJ (_U_(0x1) << I2S_TXCTRL_SLOTADJ_Pos)
-#define I2S_TXCTRL_SLOTADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Data is right adjusted in slot */
-#define I2S_TXCTRL_SLOTADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Data is left adjusted in slot */
-#define I2S_TXCTRL_SLOTADJ_RIGHT (I2S_TXCTRL_SLOTADJ_RIGHT_Val << I2S_TXCTRL_SLOTADJ_Pos)
-#define I2S_TXCTRL_SLOTADJ_LEFT (I2S_TXCTRL_SLOTADJ_LEFT_Val << I2S_TXCTRL_SLOTADJ_Pos)
-#define I2S_TXCTRL_DATASIZE_Pos 8 /**< \brief (I2S_TXCTRL) Data Word Size */
-#define I2S_TXCTRL_DATASIZE_Msk (_U_(0x7) << I2S_TXCTRL_DATASIZE_Pos)
-#define I2S_TXCTRL_DATASIZE(value) (I2S_TXCTRL_DATASIZE_Msk & ((value) << I2S_TXCTRL_DATASIZE_Pos))
-#define I2S_TXCTRL_DATASIZE_32_Val _U_(0x0) /**< \brief (I2S_TXCTRL) 32 bits */
-#define I2S_TXCTRL_DATASIZE_24_Val _U_(0x1) /**< \brief (I2S_TXCTRL) 24 bits */
-#define I2S_TXCTRL_DATASIZE_20_Val _U_(0x2) /**< \brief (I2S_TXCTRL) 20 bits */
-#define I2S_TXCTRL_DATASIZE_18_Val _U_(0x3) /**< \brief (I2S_TXCTRL) 18 bits */
-#define I2S_TXCTRL_DATASIZE_16_Val _U_(0x4) /**< \brief (I2S_TXCTRL) 16 bits */
-#define I2S_TXCTRL_DATASIZE_16C_Val _U_(0x5) /**< \brief (I2S_TXCTRL) 16 bits compact stereo */
-#define I2S_TXCTRL_DATASIZE_8_Val _U_(0x6) /**< \brief (I2S_TXCTRL) 8 bits */
-#define I2S_TXCTRL_DATASIZE_8C_Val _U_(0x7) /**< \brief (I2S_TXCTRL) 8 bits compact stereo */
-#define I2S_TXCTRL_DATASIZE_32 (I2S_TXCTRL_DATASIZE_32_Val << I2S_TXCTRL_DATASIZE_Pos)
-#define I2S_TXCTRL_DATASIZE_24 (I2S_TXCTRL_DATASIZE_24_Val << I2S_TXCTRL_DATASIZE_Pos)
-#define I2S_TXCTRL_DATASIZE_20 (I2S_TXCTRL_DATASIZE_20_Val << I2S_TXCTRL_DATASIZE_Pos)
-#define I2S_TXCTRL_DATASIZE_18 (I2S_TXCTRL_DATASIZE_18_Val << I2S_TXCTRL_DATASIZE_Pos)
-#define I2S_TXCTRL_DATASIZE_16 (I2S_TXCTRL_DATASIZE_16_Val << I2S_TXCTRL_DATASIZE_Pos)
-#define I2S_TXCTRL_DATASIZE_16C (I2S_TXCTRL_DATASIZE_16C_Val << I2S_TXCTRL_DATASIZE_Pos)
-#define I2S_TXCTRL_DATASIZE_8 (I2S_TXCTRL_DATASIZE_8_Val << I2S_TXCTRL_DATASIZE_Pos)
-#define I2S_TXCTRL_DATASIZE_8C (I2S_TXCTRL_DATASIZE_8C_Val << I2S_TXCTRL_DATASIZE_Pos)
-#define I2S_TXCTRL_WORDADJ_Pos 12 /**< \brief (I2S_TXCTRL) Data Word Formatting Adjust */
-#define I2S_TXCTRL_WORDADJ (_U_(0x1) << I2S_TXCTRL_WORDADJ_Pos)
-#define I2S_TXCTRL_WORDADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Data is right adjusted in word */
-#define I2S_TXCTRL_WORDADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Data is left adjusted in word */
-#define I2S_TXCTRL_WORDADJ_RIGHT (I2S_TXCTRL_WORDADJ_RIGHT_Val << I2S_TXCTRL_WORDADJ_Pos)
-#define I2S_TXCTRL_WORDADJ_LEFT (I2S_TXCTRL_WORDADJ_LEFT_Val << I2S_TXCTRL_WORDADJ_Pos)
-#define I2S_TXCTRL_EXTEND_Pos 13 /**< \brief (I2S_TXCTRL) Data Formatting Bit Extension */
-#define I2S_TXCTRL_EXTEND_Msk (_U_(0x3) << I2S_TXCTRL_EXTEND_Pos)
-#define I2S_TXCTRL_EXTEND(value) (I2S_TXCTRL_EXTEND_Msk & ((value) << I2S_TXCTRL_EXTEND_Pos))
-#define I2S_TXCTRL_EXTEND_ZERO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Extend with zeroes */
-#define I2S_TXCTRL_EXTEND_ONE_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Extend with ones */
-#define I2S_TXCTRL_EXTEND_MSBIT_Val _U_(0x2) /**< \brief (I2S_TXCTRL) Extend with Most Significant Bit */
-#define I2S_TXCTRL_EXTEND_LSBIT_Val _U_(0x3) /**< \brief (I2S_TXCTRL) Extend with Least Significant Bit */
-#define I2S_TXCTRL_EXTEND_ZERO (I2S_TXCTRL_EXTEND_ZERO_Val << I2S_TXCTRL_EXTEND_Pos)
-#define I2S_TXCTRL_EXTEND_ONE (I2S_TXCTRL_EXTEND_ONE_Val << I2S_TXCTRL_EXTEND_Pos)
-#define I2S_TXCTRL_EXTEND_MSBIT (I2S_TXCTRL_EXTEND_MSBIT_Val << I2S_TXCTRL_EXTEND_Pos)
-#define I2S_TXCTRL_EXTEND_LSBIT (I2S_TXCTRL_EXTEND_LSBIT_Val << I2S_TXCTRL_EXTEND_Pos)
-#define I2S_TXCTRL_BITREV_Pos 15 /**< \brief (I2S_TXCTRL) Data Formatting Bit Reverse */
-#define I2S_TXCTRL_BITREV (_U_(0x1) << I2S_TXCTRL_BITREV_Pos)
-#define I2S_TXCTRL_BITREV_MSBIT_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
-#define I2S_TXCTRL_BITREV_LSBIT_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Transfer Data Least Significant Bit (LSB) first */
-#define I2S_TXCTRL_BITREV_MSBIT (I2S_TXCTRL_BITREV_MSBIT_Val << I2S_TXCTRL_BITREV_Pos)
-#define I2S_TXCTRL_BITREV_LSBIT (I2S_TXCTRL_BITREV_LSBIT_Val << I2S_TXCTRL_BITREV_Pos)
-#define I2S_TXCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_TXCTRL) Slot 0 Disabled for this Serializer */
-#define I2S_TXCTRL_SLOTDIS0 (_U_(1) << I2S_TXCTRL_SLOTDIS0_Pos)
-#define I2S_TXCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_TXCTRL) Slot 1 Disabled for this Serializer */
-#define I2S_TXCTRL_SLOTDIS1 (_U_(1) << I2S_TXCTRL_SLOTDIS1_Pos)
-#define I2S_TXCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_TXCTRL) Slot 2 Disabled for this Serializer */
-#define I2S_TXCTRL_SLOTDIS2 (_U_(1) << I2S_TXCTRL_SLOTDIS2_Pos)
-#define I2S_TXCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_TXCTRL) Slot 3 Disabled for this Serializer */
-#define I2S_TXCTRL_SLOTDIS3 (_U_(1) << I2S_TXCTRL_SLOTDIS3_Pos)
-#define I2S_TXCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_TXCTRL) Slot 4 Disabled for this Serializer */
-#define I2S_TXCTRL_SLOTDIS4 (_U_(1) << I2S_TXCTRL_SLOTDIS4_Pos)
-#define I2S_TXCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_TXCTRL) Slot 5 Disabled for this Serializer */
-#define I2S_TXCTRL_SLOTDIS5 (_U_(1) << I2S_TXCTRL_SLOTDIS5_Pos)
-#define I2S_TXCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_TXCTRL) Slot 6 Disabled for this Serializer */
-#define I2S_TXCTRL_SLOTDIS6 (_U_(1) << I2S_TXCTRL_SLOTDIS6_Pos)
-#define I2S_TXCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_TXCTRL) Slot 7 Disabled for this Serializer */
-#define I2S_TXCTRL_SLOTDIS7 (_U_(1) << I2S_TXCTRL_SLOTDIS7_Pos)
-#define I2S_TXCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_TXCTRL) Slot x Disabled for this Serializer */
-#define I2S_TXCTRL_SLOTDIS_Msk (_U_(0xFF) << I2S_TXCTRL_SLOTDIS_Pos)
-#define I2S_TXCTRL_SLOTDIS(value) (I2S_TXCTRL_SLOTDIS_Msk & ((value) << I2S_TXCTRL_SLOTDIS_Pos))
-#define I2S_TXCTRL_MONO_Pos 24 /**< \brief (I2S_TXCTRL) Mono Mode */
-#define I2S_TXCTRL_MONO (_U_(0x1) << I2S_TXCTRL_MONO_Pos)
-#define I2S_TXCTRL_MONO_STEREO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Normal mode */
-#define I2S_TXCTRL_MONO_MONO_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Left channel data is duplicated to right channel */
-#define I2S_TXCTRL_MONO_STEREO (I2S_TXCTRL_MONO_STEREO_Val << I2S_TXCTRL_MONO_Pos)
-#define I2S_TXCTRL_MONO_MONO (I2S_TXCTRL_MONO_MONO_Val << I2S_TXCTRL_MONO_Pos)
-#define I2S_TXCTRL_DMA_Pos 25 /**< \brief (I2S_TXCTRL) Single or Multiple DMA Channels */
-#define I2S_TXCTRL_DMA (_U_(0x1) << I2S_TXCTRL_DMA_Pos)
-#define I2S_TXCTRL_DMA_SINGLE_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Single DMA channel */
-#define I2S_TXCTRL_DMA_MULTIPLE_Val _U_(0x1) /**< \brief (I2S_TXCTRL) One DMA channel per data channel */
-#define I2S_TXCTRL_DMA_SINGLE (I2S_TXCTRL_DMA_SINGLE_Val << I2S_TXCTRL_DMA_Pos)
-#define I2S_TXCTRL_DMA_MULTIPLE (I2S_TXCTRL_DMA_MULTIPLE_Val << I2S_TXCTRL_DMA_Pos)
-#define I2S_TXCTRL_MASK _U_(0x03FFF79C) /**< \brief (I2S_TXCTRL) MASK Register */
-
-/* -------- I2S_RXCTRL : (I2S Offset: 0x24) (R/W 32) Rx Serializer Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
- uint32_t :3; /*!< bit: 2.. 4 Reserved */
- uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
- uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
- uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
- uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
- uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
- uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
- uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
- uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
- uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
- uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
- uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
- uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
- uint32_t MONO:1; /*!< bit: 24 Mono Mode */
- uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
- uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} I2S_RXCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_RXCTRL_OFFSET 0x24 /**< \brief (I2S_RXCTRL offset) Rx Serializer Control */
-#define I2S_RXCTRL_RESETVALUE _U_(0x00000000) /**< \brief (I2S_RXCTRL reset_value) Rx Serializer Control */
-
-#define I2S_RXCTRL_SERMODE_Pos 0 /**< \brief (I2S_RXCTRL) Serializer Mode */
-#define I2S_RXCTRL_SERMODE_Msk (_U_(0x3) << I2S_RXCTRL_SERMODE_Pos)
-#define I2S_RXCTRL_SERMODE(value) (I2S_RXCTRL_SERMODE_Msk & ((value) << I2S_RXCTRL_SERMODE_Pos))
-#define I2S_RXCTRL_SERMODE_RX_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Receive */
-#define I2S_RXCTRL_SERMODE_PDM2_Val _U_(0x2) /**< \brief (I2S_RXCTRL) Receive one PDM data on each serial clock edge */
-#define I2S_RXCTRL_SERMODE_RX (I2S_RXCTRL_SERMODE_RX_Val << I2S_RXCTRL_SERMODE_Pos)
-#define I2S_RXCTRL_SERMODE_PDM2 (I2S_RXCTRL_SERMODE_PDM2_Val << I2S_RXCTRL_SERMODE_Pos)
-#define I2S_RXCTRL_CLKSEL_Pos 5 /**< \brief (I2S_RXCTRL) Clock Unit Selection */
-#define I2S_RXCTRL_CLKSEL (_U_(0x1) << I2S_RXCTRL_CLKSEL_Pos)
-#define I2S_RXCTRL_CLKSEL_CLK0_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Use Clock Unit 0 */
-#define I2S_RXCTRL_CLKSEL_CLK1_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Use Clock Unit 1 */
-#define I2S_RXCTRL_CLKSEL_CLK0 (I2S_RXCTRL_CLKSEL_CLK0_Val << I2S_RXCTRL_CLKSEL_Pos)
-#define I2S_RXCTRL_CLKSEL_CLK1 (I2S_RXCTRL_CLKSEL_CLK1_Val << I2S_RXCTRL_CLKSEL_Pos)
-#define I2S_RXCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_RXCTRL) Data Slot Formatting Adjust */
-#define I2S_RXCTRL_SLOTADJ (_U_(0x1) << I2S_RXCTRL_SLOTADJ_Pos)
-#define I2S_RXCTRL_SLOTADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Data is right adjusted in slot */
-#define I2S_RXCTRL_SLOTADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Data is left adjusted in slot */
-#define I2S_RXCTRL_SLOTADJ_RIGHT (I2S_RXCTRL_SLOTADJ_RIGHT_Val << I2S_RXCTRL_SLOTADJ_Pos)
-#define I2S_RXCTRL_SLOTADJ_LEFT (I2S_RXCTRL_SLOTADJ_LEFT_Val << I2S_RXCTRL_SLOTADJ_Pos)
-#define I2S_RXCTRL_DATASIZE_Pos 8 /**< \brief (I2S_RXCTRL) Data Word Size */
-#define I2S_RXCTRL_DATASIZE_Msk (_U_(0x7) << I2S_RXCTRL_DATASIZE_Pos)
-#define I2S_RXCTRL_DATASIZE(value) (I2S_RXCTRL_DATASIZE_Msk & ((value) << I2S_RXCTRL_DATASIZE_Pos))
-#define I2S_RXCTRL_DATASIZE_32_Val _U_(0x0) /**< \brief (I2S_RXCTRL) 32 bits */
-#define I2S_RXCTRL_DATASIZE_24_Val _U_(0x1) /**< \brief (I2S_RXCTRL) 24 bits */
-#define I2S_RXCTRL_DATASIZE_20_Val _U_(0x2) /**< \brief (I2S_RXCTRL) 20 bits */
-#define I2S_RXCTRL_DATASIZE_18_Val _U_(0x3) /**< \brief (I2S_RXCTRL) 18 bits */
-#define I2S_RXCTRL_DATASIZE_16_Val _U_(0x4) /**< \brief (I2S_RXCTRL) 16 bits */
-#define I2S_RXCTRL_DATASIZE_16C_Val _U_(0x5) /**< \brief (I2S_RXCTRL) 16 bits compact stereo */
-#define I2S_RXCTRL_DATASIZE_8_Val _U_(0x6) /**< \brief (I2S_RXCTRL) 8 bits */
-#define I2S_RXCTRL_DATASIZE_8C_Val _U_(0x7) /**< \brief (I2S_RXCTRL) 8 bits compact stereo */
-#define I2S_RXCTRL_DATASIZE_32 (I2S_RXCTRL_DATASIZE_32_Val << I2S_RXCTRL_DATASIZE_Pos)
-#define I2S_RXCTRL_DATASIZE_24 (I2S_RXCTRL_DATASIZE_24_Val << I2S_RXCTRL_DATASIZE_Pos)
-#define I2S_RXCTRL_DATASIZE_20 (I2S_RXCTRL_DATASIZE_20_Val << I2S_RXCTRL_DATASIZE_Pos)
-#define I2S_RXCTRL_DATASIZE_18 (I2S_RXCTRL_DATASIZE_18_Val << I2S_RXCTRL_DATASIZE_Pos)
-#define I2S_RXCTRL_DATASIZE_16 (I2S_RXCTRL_DATASIZE_16_Val << I2S_RXCTRL_DATASIZE_Pos)
-#define I2S_RXCTRL_DATASIZE_16C (I2S_RXCTRL_DATASIZE_16C_Val << I2S_RXCTRL_DATASIZE_Pos)
-#define I2S_RXCTRL_DATASIZE_8 (I2S_RXCTRL_DATASIZE_8_Val << I2S_RXCTRL_DATASIZE_Pos)
-#define I2S_RXCTRL_DATASIZE_8C (I2S_RXCTRL_DATASIZE_8C_Val << I2S_RXCTRL_DATASIZE_Pos)
-#define I2S_RXCTRL_WORDADJ_Pos 12 /**< \brief (I2S_RXCTRL) Data Word Formatting Adjust */
-#define I2S_RXCTRL_WORDADJ (_U_(0x1) << I2S_RXCTRL_WORDADJ_Pos)
-#define I2S_RXCTRL_WORDADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Data is right adjusted in word */
-#define I2S_RXCTRL_WORDADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Data is left adjusted in word */
-#define I2S_RXCTRL_WORDADJ_RIGHT (I2S_RXCTRL_WORDADJ_RIGHT_Val << I2S_RXCTRL_WORDADJ_Pos)
-#define I2S_RXCTRL_WORDADJ_LEFT (I2S_RXCTRL_WORDADJ_LEFT_Val << I2S_RXCTRL_WORDADJ_Pos)
-#define I2S_RXCTRL_EXTEND_Pos 13 /**< \brief (I2S_RXCTRL) Data Formatting Bit Extension */
-#define I2S_RXCTRL_EXTEND_Msk (_U_(0x3) << I2S_RXCTRL_EXTEND_Pos)
-#define I2S_RXCTRL_EXTEND(value) (I2S_RXCTRL_EXTEND_Msk & ((value) << I2S_RXCTRL_EXTEND_Pos))
-#define I2S_RXCTRL_EXTEND_ZERO_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Extend with zeroes */
-#define I2S_RXCTRL_EXTEND_ONE_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Extend with ones */
-#define I2S_RXCTRL_EXTEND_MSBIT_Val _U_(0x2) /**< \brief (I2S_RXCTRL) Extend with Most Significant Bit */
-#define I2S_RXCTRL_EXTEND_LSBIT_Val _U_(0x3) /**< \brief (I2S_RXCTRL) Extend with Least Significant Bit */
-#define I2S_RXCTRL_EXTEND_ZERO (I2S_RXCTRL_EXTEND_ZERO_Val << I2S_RXCTRL_EXTEND_Pos)
-#define I2S_RXCTRL_EXTEND_ONE (I2S_RXCTRL_EXTEND_ONE_Val << I2S_RXCTRL_EXTEND_Pos)
-#define I2S_RXCTRL_EXTEND_MSBIT (I2S_RXCTRL_EXTEND_MSBIT_Val << I2S_RXCTRL_EXTEND_Pos)
-#define I2S_RXCTRL_EXTEND_LSBIT (I2S_RXCTRL_EXTEND_LSBIT_Val << I2S_RXCTRL_EXTEND_Pos)
-#define I2S_RXCTRL_BITREV_Pos 15 /**< \brief (I2S_RXCTRL) Data Formatting Bit Reverse */
-#define I2S_RXCTRL_BITREV (_U_(0x1) << I2S_RXCTRL_BITREV_Pos)
-#define I2S_RXCTRL_BITREV_MSBIT_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
-#define I2S_RXCTRL_BITREV_LSBIT_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Transfer Data Least Significant Bit (LSB) first */
-#define I2S_RXCTRL_BITREV_MSBIT (I2S_RXCTRL_BITREV_MSBIT_Val << I2S_RXCTRL_BITREV_Pos)
-#define I2S_RXCTRL_BITREV_LSBIT (I2S_RXCTRL_BITREV_LSBIT_Val << I2S_RXCTRL_BITREV_Pos)
-#define I2S_RXCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_RXCTRL) Slot 0 Disabled for this Serializer */
-#define I2S_RXCTRL_SLOTDIS0 (_U_(1) << I2S_RXCTRL_SLOTDIS0_Pos)
-#define I2S_RXCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_RXCTRL) Slot 1 Disabled for this Serializer */
-#define I2S_RXCTRL_SLOTDIS1 (_U_(1) << I2S_RXCTRL_SLOTDIS1_Pos)
-#define I2S_RXCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_RXCTRL) Slot 2 Disabled for this Serializer */
-#define I2S_RXCTRL_SLOTDIS2 (_U_(1) << I2S_RXCTRL_SLOTDIS2_Pos)
-#define I2S_RXCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_RXCTRL) Slot 3 Disabled for this Serializer */
-#define I2S_RXCTRL_SLOTDIS3 (_U_(1) << I2S_RXCTRL_SLOTDIS3_Pos)
-#define I2S_RXCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_RXCTRL) Slot 4 Disabled for this Serializer */
-#define I2S_RXCTRL_SLOTDIS4 (_U_(1) << I2S_RXCTRL_SLOTDIS4_Pos)
-#define I2S_RXCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_RXCTRL) Slot 5 Disabled for this Serializer */
-#define I2S_RXCTRL_SLOTDIS5 (_U_(1) << I2S_RXCTRL_SLOTDIS5_Pos)
-#define I2S_RXCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_RXCTRL) Slot 6 Disabled for this Serializer */
-#define I2S_RXCTRL_SLOTDIS6 (_U_(1) << I2S_RXCTRL_SLOTDIS6_Pos)
-#define I2S_RXCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_RXCTRL) Slot 7 Disabled for this Serializer */
-#define I2S_RXCTRL_SLOTDIS7 (_U_(1) << I2S_RXCTRL_SLOTDIS7_Pos)
-#define I2S_RXCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_RXCTRL) Slot x Disabled for this Serializer */
-#define I2S_RXCTRL_SLOTDIS_Msk (_U_(0xFF) << I2S_RXCTRL_SLOTDIS_Pos)
-#define I2S_RXCTRL_SLOTDIS(value) (I2S_RXCTRL_SLOTDIS_Msk & ((value) << I2S_RXCTRL_SLOTDIS_Pos))
-#define I2S_RXCTRL_MONO_Pos 24 /**< \brief (I2S_RXCTRL) Mono Mode */
-#define I2S_RXCTRL_MONO (_U_(0x1) << I2S_RXCTRL_MONO_Pos)
-#define I2S_RXCTRL_MONO_STEREO_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Normal mode */
-#define I2S_RXCTRL_MONO_MONO_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Left channel data is duplicated to right channel */
-#define I2S_RXCTRL_MONO_STEREO (I2S_RXCTRL_MONO_STEREO_Val << I2S_RXCTRL_MONO_Pos)
-#define I2S_RXCTRL_MONO_MONO (I2S_RXCTRL_MONO_MONO_Val << I2S_RXCTRL_MONO_Pos)
-#define I2S_RXCTRL_DMA_Pos 25 /**< \brief (I2S_RXCTRL) Single or Multiple DMA Channels */
-#define I2S_RXCTRL_DMA (_U_(0x1) << I2S_RXCTRL_DMA_Pos)
-#define I2S_RXCTRL_DMA_SINGLE_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Single DMA channel */
-#define I2S_RXCTRL_DMA_MULTIPLE_Val _U_(0x1) /**< \brief (I2S_RXCTRL) One DMA channel per data channel */
-#define I2S_RXCTRL_DMA_SINGLE (I2S_RXCTRL_DMA_SINGLE_Val << I2S_RXCTRL_DMA_Pos)
-#define I2S_RXCTRL_DMA_MULTIPLE (I2S_RXCTRL_DMA_MULTIPLE_Val << I2S_RXCTRL_DMA_Pos)
-#define I2S_RXCTRL_RXLOOP_Pos 26 /**< \brief (I2S_RXCTRL) Loop-back Test Mode */
-#define I2S_RXCTRL_RXLOOP (_U_(0x1) << I2S_RXCTRL_RXLOOP_Pos)
-#define I2S_RXCTRL_MASK _U_(0x07FFF7A3) /**< \brief (I2S_RXCTRL) MASK Register */
-
-/* -------- I2S_TXDATA : (I2S Offset: 0x30) ( /W 32) Tx Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} I2S_TXDATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_TXDATA_OFFSET 0x30 /**< \brief (I2S_TXDATA offset) Tx Data */
-#define I2S_TXDATA_RESETVALUE _U_(0x00000000) /**< \brief (I2S_TXDATA reset_value) Tx Data */
-
-#define I2S_TXDATA_DATA_Pos 0 /**< \brief (I2S_TXDATA) Sample Data */
-#define I2S_TXDATA_DATA_Msk (_U_(0xFFFFFFFF) << I2S_TXDATA_DATA_Pos)
-#define I2S_TXDATA_DATA(value) (I2S_TXDATA_DATA_Msk & ((value) << I2S_TXDATA_DATA_Pos))
-#define I2S_TXDATA_MASK _U_(0xFFFFFFFF) /**< \brief (I2S_TXDATA) MASK Register */
-
-/* -------- I2S_RXDATA : (I2S Offset: 0x34) (R/ 32) Rx Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} I2S_RXDATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_RXDATA_OFFSET 0x34 /**< \brief (I2S_RXDATA offset) Rx Data */
-#define I2S_RXDATA_RESETVALUE _U_(0x00000000) /**< \brief (I2S_RXDATA reset_value) Rx Data */
-
-#define I2S_RXDATA_DATA_Pos 0 /**< \brief (I2S_RXDATA) Sample Data */
-#define I2S_RXDATA_DATA_Msk (_U_(0xFFFFFFFF) << I2S_RXDATA_DATA_Pos)
-#define I2S_RXDATA_DATA(value) (I2S_RXDATA_DATA_Msk & ((value) << I2S_RXDATA_DATA_Pos))
-#define I2S_RXDATA_MASK _U_(0xFFFFFFFF) /**< \brief (I2S_RXDATA) MASK Register */
-
-/** \brief I2S hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
- RoReg8 Reserved1[0x3];
- __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
- __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
- RoReg8 Reserved2[0x2];
- __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
- RoReg8 Reserved3[0x2];
- __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x2];
- __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
- RoReg8 Reserved5[0x6];
- __IO I2S_TXCTRL_Type TXCTRL; /**< \brief Offset: 0x20 (R/W 32) Tx Serializer Control */
- __IO I2S_RXCTRL_Type RXCTRL; /**< \brief Offset: 0x24 (R/W 32) Rx Serializer Control */
- RoReg8 Reserved6[0x8];
- __O I2S_TXDATA_Type TXDATA; /**< \brief Offset: 0x30 ( /W 32) Tx Data */
- __I I2S_RXDATA_Type RXDATA; /**< \brief Offset: 0x34 (R/ 32) Rx Data */
-} I2s;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_I2S_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for I2S
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_I2S_COMPONENT_
+#define _SAME54_I2S_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR I2S */
+/* ========================================================================== */
+/** \addtogroup SAME54_I2S Inter-IC Sound Interface */
+/*@{*/
+
+#define I2S_U2224
+#define REV_I2S 0x200
+
+/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
+ uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
+ uint8_t TXEN:1; /*!< bit: 4 Tx Serializer Enable */
+ uint8_t RXEN:1; /*!< bit: 5 Rx Serializer Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} I2S_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_CTRLA_OFFSET 0x00 /**< \brief (I2S_CTRLA offset) Control A */
+#define I2S_CTRLA_RESETVALUE _U_(0x00) /**< \brief (I2S_CTRLA reset_value) Control A */
+
+#define I2S_CTRLA_SWRST_Pos 0 /**< \brief (I2S_CTRLA) Software Reset */
+#define I2S_CTRLA_SWRST (_U_(0x1) << I2S_CTRLA_SWRST_Pos)
+#define I2S_CTRLA_ENABLE_Pos 1 /**< \brief (I2S_CTRLA) Enable */
+#define I2S_CTRLA_ENABLE (_U_(0x1) << I2S_CTRLA_ENABLE_Pos)
+#define I2S_CTRLA_CKEN0_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
+#define I2S_CTRLA_CKEN0 (_U_(1) << I2S_CTRLA_CKEN0_Pos)
+#define I2S_CTRLA_CKEN1_Pos 3 /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
+#define I2S_CTRLA_CKEN1 (_U_(1) << I2S_CTRLA_CKEN1_Pos)
+#define I2S_CTRLA_CKEN_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit x Enable */
+#define I2S_CTRLA_CKEN_Msk (_U_(0x3) << I2S_CTRLA_CKEN_Pos)
+#define I2S_CTRLA_CKEN(value) (I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos))
+#define I2S_CTRLA_TXEN_Pos 4 /**< \brief (I2S_CTRLA) Tx Serializer Enable */
+#define I2S_CTRLA_TXEN (_U_(0x1) << I2S_CTRLA_TXEN_Pos)
+#define I2S_CTRLA_RXEN_Pos 5 /**< \brief (I2S_CTRLA) Rx Serializer Enable */
+#define I2S_CTRLA_RXEN (_U_(0x1) << I2S_CTRLA_RXEN_Pos)
+#define I2S_CTRLA_MASK _U_(0x3F) /**< \brief (I2S_CTRLA) MASK Register */
+
+/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
+ uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
+ uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
+ uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
+ uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
+ uint32_t FSINV:1; /*!< bit: 9 Frame Sync Invert */
+ uint32_t FSOUTINV:1; /*!< bit: 10 Frame Sync Output Invert */
+ uint32_t SCKSEL:1; /*!< bit: 11 Serial Clock Select */
+ uint32_t SCKOUTINV:1; /*!< bit: 12 Serial Clock Output Invert */
+ uint32_t MCKSEL:1; /*!< bit: 13 Master Clock Select */
+ uint32_t MCKEN:1; /*!< bit: 14 Master Clock Enable */
+ uint32_t MCKOUTINV:1; /*!< bit: 15 Master Clock Output Invert */
+ uint32_t MCKDIV:6; /*!< bit: 16..21 Master Clock Division Factor */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t MCKOUTDIV:6; /*!< bit: 24..29 Master Clock Output Division Factor */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_CLKCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_CLKCTRL_OFFSET 0x04 /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
+#define I2S_CLKCTRL_RESETVALUE _U_(0x00000000) /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
+
+#define I2S_CLKCTRL_SLOTSIZE_Pos 0 /**< \brief (I2S_CLKCTRL) Slot Size */
+#define I2S_CLKCTRL_SLOTSIZE_Msk (_U_(0x3) << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE(value) (I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))
+#define I2S_CLKCTRL_SLOTSIZE_8_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_16_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_24_Val _U_(0x2) /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_32_Val _U_(0x3) /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_NBSLOTS_Pos 2 /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
+#define I2S_CLKCTRL_NBSLOTS_Msk (_U_(0x7) << I2S_CLKCTRL_NBSLOTS_Pos)
+#define I2S_CLKCTRL_NBSLOTS(value) (I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))
+#define I2S_CLKCTRL_FSWIDTH_Pos 5 /**< \brief (I2S_CLKCTRL) Frame Sync Width */
+#define I2S_CLKCTRL_FSWIDTH_Msk (_U_(0x3) << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH(value) (I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))
+#define I2S_CLKCTRL_FSWIDTH_SLOT_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
+#define I2S_CLKCTRL_FSWIDTH_HALF_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
+#define I2S_CLKCTRL_FSWIDTH_BIT_Val _U_(0x2) /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
+#define I2S_CLKCTRL_FSWIDTH_BURST_Val _U_(0x3) /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
+#define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_BITDELAY_Pos 7 /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
+#define I2S_CLKCTRL_BITDELAY (_U_(0x1) << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_BITDELAY_LJ_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
+#define I2S_CLKCTRL_BITDELAY_I2S_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
+#define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_FSSEL_Pos 8 /**< \brief (I2S_CLKCTRL) Frame Sync Select */
+#define I2S_CLKCTRL_FSSEL (_U_(0x1) << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSSEL_SCKDIV_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
+#define I2S_CLKCTRL_FSSEL_FSPIN_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
+#define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSINV_Pos 9 /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
+#define I2S_CLKCTRL_FSINV (_U_(0x1) << I2S_CLKCTRL_FSINV_Pos)
+#define I2S_CLKCTRL_FSOUTINV_Pos 10 /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
+#define I2S_CLKCTRL_FSOUTINV (_U_(0x1) << I2S_CLKCTRL_FSOUTINV_Pos)
+#define I2S_CLKCTRL_SCKSEL_Pos 11 /**< \brief (I2S_CLKCTRL) Serial Clock Select */
+#define I2S_CLKCTRL_SCKSEL (_U_(0x1) << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_SCKSEL_MCKDIV_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
+#define I2S_CLKCTRL_SCKSEL_SCKPIN_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
+#define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_SCKOUTINV_Pos 12 /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
+#define I2S_CLKCTRL_SCKOUTINV (_U_(0x1) << I2S_CLKCTRL_SCKOUTINV_Pos)
+#define I2S_CLKCTRL_MCKSEL_Pos 13 /**< \brief (I2S_CLKCTRL) Master Clock Select */
+#define I2S_CLKCTRL_MCKSEL (_U_(0x1) << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_GCLK_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
+#define I2S_CLKCTRL_MCKSEL_MCKPIN_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
+#define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKEN_Pos 14 /**< \brief (I2S_CLKCTRL) Master Clock Enable */
+#define I2S_CLKCTRL_MCKEN (_U_(0x1) << I2S_CLKCTRL_MCKEN_Pos)
+#define I2S_CLKCTRL_MCKOUTINV_Pos 15 /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
+#define I2S_CLKCTRL_MCKOUTINV (_U_(0x1) << I2S_CLKCTRL_MCKOUTINV_Pos)
+#define I2S_CLKCTRL_MCKDIV_Pos 16 /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
+#define I2S_CLKCTRL_MCKDIV_Msk (_U_(0x3F) << I2S_CLKCTRL_MCKDIV_Pos)
+#define I2S_CLKCTRL_MCKDIV(value) (I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))
+#define I2S_CLKCTRL_MCKOUTDIV_Pos 24 /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
+#define I2S_CLKCTRL_MCKOUTDIV_Msk (_U_(0x3F) << I2S_CLKCTRL_MCKOUTDIV_Pos)
+#define I2S_CLKCTRL_MCKOUTDIV(value) (I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))
+#define I2S_CLKCTRL_MASK _U_(0x3F3FFFFF) /**< \brief (I2S_CLKCTRL) MASK Register */
+
+/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
+ uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
+ uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
+ uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
+ uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTENCLR_OFFSET 0x0C /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
+#define I2S_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define I2S_INTENCLR_RXRDY0_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
+#define I2S_INTENCLR_RXRDY0 (_U_(1) << I2S_INTENCLR_RXRDY0_Pos)
+#define I2S_INTENCLR_RXRDY1_Pos 1 /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
+#define I2S_INTENCLR_RXRDY1 (_U_(1) << I2S_INTENCLR_RXRDY1_Pos)
+#define I2S_INTENCLR_RXRDY_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
+#define I2S_INTENCLR_RXRDY_Msk (_U_(0x3) << I2S_INTENCLR_RXRDY_Pos)
+#define I2S_INTENCLR_RXRDY(value) (I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos))
+#define I2S_INTENCLR_RXOR0_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
+#define I2S_INTENCLR_RXOR0 (_U_(1) << I2S_INTENCLR_RXOR0_Pos)
+#define I2S_INTENCLR_RXOR1_Pos 5 /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
+#define I2S_INTENCLR_RXOR1 (_U_(1) << I2S_INTENCLR_RXOR1_Pos)
+#define I2S_INTENCLR_RXOR_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
+#define I2S_INTENCLR_RXOR_Msk (_U_(0x3) << I2S_INTENCLR_RXOR_Pos)
+#define I2S_INTENCLR_RXOR(value) (I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos))
+#define I2S_INTENCLR_TXRDY0_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
+#define I2S_INTENCLR_TXRDY0 (_U_(1) << I2S_INTENCLR_TXRDY0_Pos)
+#define I2S_INTENCLR_TXRDY1_Pos 9 /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
+#define I2S_INTENCLR_TXRDY1 (_U_(1) << I2S_INTENCLR_TXRDY1_Pos)
+#define I2S_INTENCLR_TXRDY_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
+#define I2S_INTENCLR_TXRDY_Msk (_U_(0x3) << I2S_INTENCLR_TXRDY_Pos)
+#define I2S_INTENCLR_TXRDY(value) (I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos))
+#define I2S_INTENCLR_TXUR0_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
+#define I2S_INTENCLR_TXUR0 (_U_(1) << I2S_INTENCLR_TXUR0_Pos)
+#define I2S_INTENCLR_TXUR1_Pos 13 /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
+#define I2S_INTENCLR_TXUR1 (_U_(1) << I2S_INTENCLR_TXUR1_Pos)
+#define I2S_INTENCLR_TXUR_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
+#define I2S_INTENCLR_TXUR_Msk (_U_(0x3) << I2S_INTENCLR_TXUR_Pos)
+#define I2S_INTENCLR_TXUR(value) (I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos))
+#define I2S_INTENCLR_MASK _U_(0x3333) /**< \brief (I2S_INTENCLR) MASK Register */
+
+/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
+ uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
+ uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
+ uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
+ uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTENSET_OFFSET 0x10 /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
+#define I2S_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
+
+#define I2S_INTENSET_RXRDY0_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
+#define I2S_INTENSET_RXRDY0 (_U_(1) << I2S_INTENSET_RXRDY0_Pos)
+#define I2S_INTENSET_RXRDY1_Pos 1 /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
+#define I2S_INTENSET_RXRDY1 (_U_(1) << I2S_INTENSET_RXRDY1_Pos)
+#define I2S_INTENSET_RXRDY_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
+#define I2S_INTENSET_RXRDY_Msk (_U_(0x3) << I2S_INTENSET_RXRDY_Pos)
+#define I2S_INTENSET_RXRDY(value) (I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos))
+#define I2S_INTENSET_RXOR0_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
+#define I2S_INTENSET_RXOR0 (_U_(1) << I2S_INTENSET_RXOR0_Pos)
+#define I2S_INTENSET_RXOR1_Pos 5 /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
+#define I2S_INTENSET_RXOR1 (_U_(1) << I2S_INTENSET_RXOR1_Pos)
+#define I2S_INTENSET_RXOR_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
+#define I2S_INTENSET_RXOR_Msk (_U_(0x3) << I2S_INTENSET_RXOR_Pos)
+#define I2S_INTENSET_RXOR(value) (I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos))
+#define I2S_INTENSET_TXRDY0_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
+#define I2S_INTENSET_TXRDY0 (_U_(1) << I2S_INTENSET_TXRDY0_Pos)
+#define I2S_INTENSET_TXRDY1_Pos 9 /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
+#define I2S_INTENSET_TXRDY1 (_U_(1) << I2S_INTENSET_TXRDY1_Pos)
+#define I2S_INTENSET_TXRDY_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
+#define I2S_INTENSET_TXRDY_Msk (_U_(0x3) << I2S_INTENSET_TXRDY_Pos)
+#define I2S_INTENSET_TXRDY(value) (I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos))
+#define I2S_INTENSET_TXUR0_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
+#define I2S_INTENSET_TXUR0 (_U_(1) << I2S_INTENSET_TXUR0_Pos)
+#define I2S_INTENSET_TXUR1_Pos 13 /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
+#define I2S_INTENSET_TXUR1 (_U_(1) << I2S_INTENSET_TXUR1_Pos)
+#define I2S_INTENSET_TXUR_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
+#define I2S_INTENSET_TXUR_Msk (_U_(0x3) << I2S_INTENSET_TXUR_Pos)
+#define I2S_INTENSET_TXUR(value) (I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos))
+#define I2S_INTENSET_MASK _U_(0x3333) /**< \brief (I2S_INTENSET) MASK Register */
+
+/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
+ __I uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
+ __I uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
+ __I uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
+ __I uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ __I uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
+ __I uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
+ __I uint16_t :2; /*!< bit: 10..11 Reserved */
+ __I uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
+ __I uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
+ __I uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
+ __I uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
+ __I uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ __I uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
+ __I uint16_t :2; /*!< bit: 10..11 Reserved */
+ __I uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
+ __I uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTFLAG_OFFSET 0x14 /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
+#define I2S_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define I2S_INTFLAG_RXRDY0_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready 0 */
+#define I2S_INTFLAG_RXRDY0 (_U_(1) << I2S_INTFLAG_RXRDY0_Pos)
+#define I2S_INTFLAG_RXRDY1_Pos 1 /**< \brief (I2S_INTFLAG) Receive Ready 1 */
+#define I2S_INTFLAG_RXRDY1 (_U_(1) << I2S_INTFLAG_RXRDY1_Pos)
+#define I2S_INTFLAG_RXRDY_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready x */
+#define I2S_INTFLAG_RXRDY_Msk (_U_(0x3) << I2S_INTFLAG_RXRDY_Pos)
+#define I2S_INTFLAG_RXRDY(value) (I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos))
+#define I2S_INTFLAG_RXOR0_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
+#define I2S_INTFLAG_RXOR0 (_U_(1) << I2S_INTFLAG_RXOR0_Pos)
+#define I2S_INTFLAG_RXOR1_Pos 5 /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
+#define I2S_INTFLAG_RXOR1 (_U_(1) << I2S_INTFLAG_RXOR1_Pos)
+#define I2S_INTFLAG_RXOR_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun x */
+#define I2S_INTFLAG_RXOR_Msk (_U_(0x3) << I2S_INTFLAG_RXOR_Pos)
+#define I2S_INTFLAG_RXOR(value) (I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos))
+#define I2S_INTFLAG_TXRDY0_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
+#define I2S_INTFLAG_TXRDY0 (_U_(1) << I2S_INTFLAG_TXRDY0_Pos)
+#define I2S_INTFLAG_TXRDY1_Pos 9 /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
+#define I2S_INTFLAG_TXRDY1 (_U_(1) << I2S_INTFLAG_TXRDY1_Pos)
+#define I2S_INTFLAG_TXRDY_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready x */
+#define I2S_INTFLAG_TXRDY_Msk (_U_(0x3) << I2S_INTFLAG_TXRDY_Pos)
+#define I2S_INTFLAG_TXRDY(value) (I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos))
+#define I2S_INTFLAG_TXUR0_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
+#define I2S_INTFLAG_TXUR0 (_U_(1) << I2S_INTFLAG_TXUR0_Pos)
+#define I2S_INTFLAG_TXUR1_Pos 13 /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
+#define I2S_INTFLAG_TXUR1 (_U_(1) << I2S_INTFLAG_TXUR1_Pos)
+#define I2S_INTFLAG_TXUR_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun x */
+#define I2S_INTFLAG_TXUR_Msk (_U_(0x3) << I2S_INTFLAG_TXUR_Pos)
+#define I2S_INTFLAG_TXUR(value) (I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos))
+#define I2S_INTFLAG_MASK _U_(0x3333) /**< \brief (I2S_INTFLAG) MASK Register */
+
+/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
+ uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
+ uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
+ uint16_t TXEN:1; /*!< bit: 4 Tx Serializer Enable Synchronization Status */
+ uint16_t RXEN:1; /*!< bit: 5 Rx Serializer Enable Synchronization Status */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXDATA:1; /*!< bit: 8 Tx Data Synchronization Status */
+ uint16_t RXDATA:1; /*!< bit: 9 Rx Data Synchronization Status */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
+ uint16_t :12; /*!< bit: 4..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_SYNCBUSY_OFFSET 0x18 /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
+#define I2S_SYNCBUSY_RESETVALUE _U_(0x0000) /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
+
+#define I2S_SYNCBUSY_SWRST_Pos 0 /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
+#define I2S_SYNCBUSY_SWRST (_U_(0x1) << I2S_SYNCBUSY_SWRST_Pos)
+#define I2S_SYNCBUSY_ENABLE_Pos 1 /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
+#define I2S_SYNCBUSY_ENABLE (_U_(0x1) << I2S_SYNCBUSY_ENABLE_Pos)
+#define I2S_SYNCBUSY_CKEN0_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN0 (_U_(1) << I2S_SYNCBUSY_CKEN0_Pos)
+#define I2S_SYNCBUSY_CKEN1_Pos 3 /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN1 (_U_(1) << I2S_SYNCBUSY_CKEN1_Pos)
+#define I2S_SYNCBUSY_CKEN_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN_Msk (_U_(0x3) << I2S_SYNCBUSY_CKEN_Pos)
+#define I2S_SYNCBUSY_CKEN(value) (I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos))
+#define I2S_SYNCBUSY_TXEN_Pos 4 /**< \brief (I2S_SYNCBUSY) Tx Serializer Enable Synchronization Status */
+#define I2S_SYNCBUSY_TXEN (_U_(0x1) << I2S_SYNCBUSY_TXEN_Pos)
+#define I2S_SYNCBUSY_RXEN_Pos 5 /**< \brief (I2S_SYNCBUSY) Rx Serializer Enable Synchronization Status */
+#define I2S_SYNCBUSY_RXEN (_U_(0x1) << I2S_SYNCBUSY_RXEN_Pos)
+#define I2S_SYNCBUSY_TXDATA_Pos 8 /**< \brief (I2S_SYNCBUSY) Tx Data Synchronization Status */
+#define I2S_SYNCBUSY_TXDATA (_U_(0x1) << I2S_SYNCBUSY_TXDATA_Pos)
+#define I2S_SYNCBUSY_RXDATA_Pos 9 /**< \brief (I2S_SYNCBUSY) Rx Data Synchronization Status */
+#define I2S_SYNCBUSY_RXDATA (_U_(0x1) << I2S_SYNCBUSY_RXDATA_Pos)
+#define I2S_SYNCBUSY_MASK _U_(0x033F) /**< \brief (I2S_SYNCBUSY) MASK Register */
+
+/* -------- I2S_TXCTRL : (I2S Offset: 0x20) (R/W 32) Tx Serializer Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
+ uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
+ uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
+ uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
+ uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
+ uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
+ uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
+ uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
+ uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
+ uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
+ uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
+ uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
+ uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
+ uint32_t MONO:1; /*!< bit: 24 Mono Mode */
+ uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_TXCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_TXCTRL_OFFSET 0x20 /**< \brief (I2S_TXCTRL offset) Tx Serializer Control */
+#define I2S_TXCTRL_RESETVALUE _U_(0x00000000) /**< \brief (I2S_TXCTRL reset_value) Tx Serializer Control */
+
+#define I2S_TXCTRL_TXDEFAULT_Pos 2 /**< \brief (I2S_TXCTRL) Line Default Line when Slot Disabled */
+#define I2S_TXCTRL_TXDEFAULT_Msk (_U_(0x3) << I2S_TXCTRL_TXDEFAULT_Pos)
+#define I2S_TXCTRL_TXDEFAULT(value) (I2S_TXCTRL_TXDEFAULT_Msk & ((value) << I2S_TXCTRL_TXDEFAULT_Pos))
+#define I2S_TXCTRL_TXDEFAULT_ZERO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Output Default Value is 0 */
+#define I2S_TXCTRL_TXDEFAULT_ONE_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Output Default Value is 1 */
+#define I2S_TXCTRL_TXDEFAULT_HIZ_Val _U_(0x3) /**< \brief (I2S_TXCTRL) Output Default Value is high impedance */
+#define I2S_TXCTRL_TXDEFAULT_ZERO (I2S_TXCTRL_TXDEFAULT_ZERO_Val << I2S_TXCTRL_TXDEFAULT_Pos)
+#define I2S_TXCTRL_TXDEFAULT_ONE (I2S_TXCTRL_TXDEFAULT_ONE_Val << I2S_TXCTRL_TXDEFAULT_Pos)
+#define I2S_TXCTRL_TXDEFAULT_HIZ (I2S_TXCTRL_TXDEFAULT_HIZ_Val << I2S_TXCTRL_TXDEFAULT_Pos)
+#define I2S_TXCTRL_TXSAME_Pos 4 /**< \brief (I2S_TXCTRL) Transmit Data when Underrun */
+#define I2S_TXCTRL_TXSAME (_U_(0x1) << I2S_TXCTRL_TXSAME_Pos)
+#define I2S_TXCTRL_TXSAME_ZERO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Zero data transmitted in case of underrun */
+#define I2S_TXCTRL_TXSAME_SAME_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Last data transmitted in case of underrun */
+#define I2S_TXCTRL_TXSAME_ZERO (I2S_TXCTRL_TXSAME_ZERO_Val << I2S_TXCTRL_TXSAME_Pos)
+#define I2S_TXCTRL_TXSAME_SAME (I2S_TXCTRL_TXSAME_SAME_Val << I2S_TXCTRL_TXSAME_Pos)
+#define I2S_TXCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_TXCTRL) Data Slot Formatting Adjust */
+#define I2S_TXCTRL_SLOTADJ (_U_(0x1) << I2S_TXCTRL_SLOTADJ_Pos)
+#define I2S_TXCTRL_SLOTADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Data is right adjusted in slot */
+#define I2S_TXCTRL_SLOTADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Data is left adjusted in slot */
+#define I2S_TXCTRL_SLOTADJ_RIGHT (I2S_TXCTRL_SLOTADJ_RIGHT_Val << I2S_TXCTRL_SLOTADJ_Pos)
+#define I2S_TXCTRL_SLOTADJ_LEFT (I2S_TXCTRL_SLOTADJ_LEFT_Val << I2S_TXCTRL_SLOTADJ_Pos)
+#define I2S_TXCTRL_DATASIZE_Pos 8 /**< \brief (I2S_TXCTRL) Data Word Size */
+#define I2S_TXCTRL_DATASIZE_Msk (_U_(0x7) << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE(value) (I2S_TXCTRL_DATASIZE_Msk & ((value) << I2S_TXCTRL_DATASIZE_Pos))
+#define I2S_TXCTRL_DATASIZE_32_Val _U_(0x0) /**< \brief (I2S_TXCTRL) 32 bits */
+#define I2S_TXCTRL_DATASIZE_24_Val _U_(0x1) /**< \brief (I2S_TXCTRL) 24 bits */
+#define I2S_TXCTRL_DATASIZE_20_Val _U_(0x2) /**< \brief (I2S_TXCTRL) 20 bits */
+#define I2S_TXCTRL_DATASIZE_18_Val _U_(0x3) /**< \brief (I2S_TXCTRL) 18 bits */
+#define I2S_TXCTRL_DATASIZE_16_Val _U_(0x4) /**< \brief (I2S_TXCTRL) 16 bits */
+#define I2S_TXCTRL_DATASIZE_16C_Val _U_(0x5) /**< \brief (I2S_TXCTRL) 16 bits compact stereo */
+#define I2S_TXCTRL_DATASIZE_8_Val _U_(0x6) /**< \brief (I2S_TXCTRL) 8 bits */
+#define I2S_TXCTRL_DATASIZE_8C_Val _U_(0x7) /**< \brief (I2S_TXCTRL) 8 bits compact stereo */
+#define I2S_TXCTRL_DATASIZE_32 (I2S_TXCTRL_DATASIZE_32_Val << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_24 (I2S_TXCTRL_DATASIZE_24_Val << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_20 (I2S_TXCTRL_DATASIZE_20_Val << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_18 (I2S_TXCTRL_DATASIZE_18_Val << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_16 (I2S_TXCTRL_DATASIZE_16_Val << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_16C (I2S_TXCTRL_DATASIZE_16C_Val << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_8 (I2S_TXCTRL_DATASIZE_8_Val << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_8C (I2S_TXCTRL_DATASIZE_8C_Val << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_WORDADJ_Pos 12 /**< \brief (I2S_TXCTRL) Data Word Formatting Adjust */
+#define I2S_TXCTRL_WORDADJ (_U_(0x1) << I2S_TXCTRL_WORDADJ_Pos)
+#define I2S_TXCTRL_WORDADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Data is right adjusted in word */
+#define I2S_TXCTRL_WORDADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Data is left adjusted in word */
+#define I2S_TXCTRL_WORDADJ_RIGHT (I2S_TXCTRL_WORDADJ_RIGHT_Val << I2S_TXCTRL_WORDADJ_Pos)
+#define I2S_TXCTRL_WORDADJ_LEFT (I2S_TXCTRL_WORDADJ_LEFT_Val << I2S_TXCTRL_WORDADJ_Pos)
+#define I2S_TXCTRL_EXTEND_Pos 13 /**< \brief (I2S_TXCTRL) Data Formatting Bit Extension */
+#define I2S_TXCTRL_EXTEND_Msk (_U_(0x3) << I2S_TXCTRL_EXTEND_Pos)
+#define I2S_TXCTRL_EXTEND(value) (I2S_TXCTRL_EXTEND_Msk & ((value) << I2S_TXCTRL_EXTEND_Pos))
+#define I2S_TXCTRL_EXTEND_ZERO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Extend with zeroes */
+#define I2S_TXCTRL_EXTEND_ONE_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Extend with ones */
+#define I2S_TXCTRL_EXTEND_MSBIT_Val _U_(0x2) /**< \brief (I2S_TXCTRL) Extend with Most Significant Bit */
+#define I2S_TXCTRL_EXTEND_LSBIT_Val _U_(0x3) /**< \brief (I2S_TXCTRL) Extend with Least Significant Bit */
+#define I2S_TXCTRL_EXTEND_ZERO (I2S_TXCTRL_EXTEND_ZERO_Val << I2S_TXCTRL_EXTEND_Pos)
+#define I2S_TXCTRL_EXTEND_ONE (I2S_TXCTRL_EXTEND_ONE_Val << I2S_TXCTRL_EXTEND_Pos)
+#define I2S_TXCTRL_EXTEND_MSBIT (I2S_TXCTRL_EXTEND_MSBIT_Val << I2S_TXCTRL_EXTEND_Pos)
+#define I2S_TXCTRL_EXTEND_LSBIT (I2S_TXCTRL_EXTEND_LSBIT_Val << I2S_TXCTRL_EXTEND_Pos)
+#define I2S_TXCTRL_BITREV_Pos 15 /**< \brief (I2S_TXCTRL) Data Formatting Bit Reverse */
+#define I2S_TXCTRL_BITREV (_U_(0x1) << I2S_TXCTRL_BITREV_Pos)
+#define I2S_TXCTRL_BITREV_MSBIT_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
+#define I2S_TXCTRL_BITREV_LSBIT_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Transfer Data Least Significant Bit (LSB) first */
+#define I2S_TXCTRL_BITREV_MSBIT (I2S_TXCTRL_BITREV_MSBIT_Val << I2S_TXCTRL_BITREV_Pos)
+#define I2S_TXCTRL_BITREV_LSBIT (I2S_TXCTRL_BITREV_LSBIT_Val << I2S_TXCTRL_BITREV_Pos)
+#define I2S_TXCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_TXCTRL) Slot 0 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS0 (_U_(1) << I2S_TXCTRL_SLOTDIS0_Pos)
+#define I2S_TXCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_TXCTRL) Slot 1 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS1 (_U_(1) << I2S_TXCTRL_SLOTDIS1_Pos)
+#define I2S_TXCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_TXCTRL) Slot 2 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS2 (_U_(1) << I2S_TXCTRL_SLOTDIS2_Pos)
+#define I2S_TXCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_TXCTRL) Slot 3 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS3 (_U_(1) << I2S_TXCTRL_SLOTDIS3_Pos)
+#define I2S_TXCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_TXCTRL) Slot 4 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS4 (_U_(1) << I2S_TXCTRL_SLOTDIS4_Pos)
+#define I2S_TXCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_TXCTRL) Slot 5 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS5 (_U_(1) << I2S_TXCTRL_SLOTDIS5_Pos)
+#define I2S_TXCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_TXCTRL) Slot 6 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS6 (_U_(1) << I2S_TXCTRL_SLOTDIS6_Pos)
+#define I2S_TXCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_TXCTRL) Slot 7 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS7 (_U_(1) << I2S_TXCTRL_SLOTDIS7_Pos)
+#define I2S_TXCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_TXCTRL) Slot x Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS_Msk (_U_(0xFF) << I2S_TXCTRL_SLOTDIS_Pos)
+#define I2S_TXCTRL_SLOTDIS(value) (I2S_TXCTRL_SLOTDIS_Msk & ((value) << I2S_TXCTRL_SLOTDIS_Pos))
+#define I2S_TXCTRL_MONO_Pos 24 /**< \brief (I2S_TXCTRL) Mono Mode */
+#define I2S_TXCTRL_MONO (_U_(0x1) << I2S_TXCTRL_MONO_Pos)
+#define I2S_TXCTRL_MONO_STEREO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Normal mode */
+#define I2S_TXCTRL_MONO_MONO_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Left channel data is duplicated to right channel */
+#define I2S_TXCTRL_MONO_STEREO (I2S_TXCTRL_MONO_STEREO_Val << I2S_TXCTRL_MONO_Pos)
+#define I2S_TXCTRL_MONO_MONO (I2S_TXCTRL_MONO_MONO_Val << I2S_TXCTRL_MONO_Pos)
+#define I2S_TXCTRL_DMA_Pos 25 /**< \brief (I2S_TXCTRL) Single or Multiple DMA Channels */
+#define I2S_TXCTRL_DMA (_U_(0x1) << I2S_TXCTRL_DMA_Pos)
+#define I2S_TXCTRL_DMA_SINGLE_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Single DMA channel */
+#define I2S_TXCTRL_DMA_MULTIPLE_Val _U_(0x1) /**< \brief (I2S_TXCTRL) One DMA channel per data channel */
+#define I2S_TXCTRL_DMA_SINGLE (I2S_TXCTRL_DMA_SINGLE_Val << I2S_TXCTRL_DMA_Pos)
+#define I2S_TXCTRL_DMA_MULTIPLE (I2S_TXCTRL_DMA_MULTIPLE_Val << I2S_TXCTRL_DMA_Pos)
+#define I2S_TXCTRL_MASK _U_(0x03FFF79C) /**< \brief (I2S_TXCTRL) MASK Register */
+
+/* -------- I2S_RXCTRL : (I2S Offset: 0x24) (R/W 32) Rx Serializer Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
+ uint32_t :3; /*!< bit: 2.. 4 Reserved */
+ uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
+ uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
+ uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
+ uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
+ uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
+ uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
+ uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
+ uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
+ uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
+ uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
+ uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
+ uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
+ uint32_t MONO:1; /*!< bit: 24 Mono Mode */
+ uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
+ uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_RXCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_RXCTRL_OFFSET 0x24 /**< \brief (I2S_RXCTRL offset) Rx Serializer Control */
+#define I2S_RXCTRL_RESETVALUE _U_(0x00000000) /**< \brief (I2S_RXCTRL reset_value) Rx Serializer Control */
+
+#define I2S_RXCTRL_SERMODE_Pos 0 /**< \brief (I2S_RXCTRL) Serializer Mode */
+#define I2S_RXCTRL_SERMODE_Msk (_U_(0x3) << I2S_RXCTRL_SERMODE_Pos)
+#define I2S_RXCTRL_SERMODE(value) (I2S_RXCTRL_SERMODE_Msk & ((value) << I2S_RXCTRL_SERMODE_Pos))
+#define I2S_RXCTRL_SERMODE_RX_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Receive */
+#define I2S_RXCTRL_SERMODE_PDM2_Val _U_(0x2) /**< \brief (I2S_RXCTRL) Receive one PDM data on each serial clock edge */
+#define I2S_RXCTRL_SERMODE_RX (I2S_RXCTRL_SERMODE_RX_Val << I2S_RXCTRL_SERMODE_Pos)
+#define I2S_RXCTRL_SERMODE_PDM2 (I2S_RXCTRL_SERMODE_PDM2_Val << I2S_RXCTRL_SERMODE_Pos)
+#define I2S_RXCTRL_CLKSEL_Pos 5 /**< \brief (I2S_RXCTRL) Clock Unit Selection */
+#define I2S_RXCTRL_CLKSEL (_U_(0x1) << I2S_RXCTRL_CLKSEL_Pos)
+#define I2S_RXCTRL_CLKSEL_CLK0_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Use Clock Unit 0 */
+#define I2S_RXCTRL_CLKSEL_CLK1_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Use Clock Unit 1 */
+#define I2S_RXCTRL_CLKSEL_CLK0 (I2S_RXCTRL_CLKSEL_CLK0_Val << I2S_RXCTRL_CLKSEL_Pos)
+#define I2S_RXCTRL_CLKSEL_CLK1 (I2S_RXCTRL_CLKSEL_CLK1_Val << I2S_RXCTRL_CLKSEL_Pos)
+#define I2S_RXCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_RXCTRL) Data Slot Formatting Adjust */
+#define I2S_RXCTRL_SLOTADJ (_U_(0x1) << I2S_RXCTRL_SLOTADJ_Pos)
+#define I2S_RXCTRL_SLOTADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Data is right adjusted in slot */
+#define I2S_RXCTRL_SLOTADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Data is left adjusted in slot */
+#define I2S_RXCTRL_SLOTADJ_RIGHT (I2S_RXCTRL_SLOTADJ_RIGHT_Val << I2S_RXCTRL_SLOTADJ_Pos)
+#define I2S_RXCTRL_SLOTADJ_LEFT (I2S_RXCTRL_SLOTADJ_LEFT_Val << I2S_RXCTRL_SLOTADJ_Pos)
+#define I2S_RXCTRL_DATASIZE_Pos 8 /**< \brief (I2S_RXCTRL) Data Word Size */
+#define I2S_RXCTRL_DATASIZE_Msk (_U_(0x7) << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE(value) (I2S_RXCTRL_DATASIZE_Msk & ((value) << I2S_RXCTRL_DATASIZE_Pos))
+#define I2S_RXCTRL_DATASIZE_32_Val _U_(0x0) /**< \brief (I2S_RXCTRL) 32 bits */
+#define I2S_RXCTRL_DATASIZE_24_Val _U_(0x1) /**< \brief (I2S_RXCTRL) 24 bits */
+#define I2S_RXCTRL_DATASIZE_20_Val _U_(0x2) /**< \brief (I2S_RXCTRL) 20 bits */
+#define I2S_RXCTRL_DATASIZE_18_Val _U_(0x3) /**< \brief (I2S_RXCTRL) 18 bits */
+#define I2S_RXCTRL_DATASIZE_16_Val _U_(0x4) /**< \brief (I2S_RXCTRL) 16 bits */
+#define I2S_RXCTRL_DATASIZE_16C_Val _U_(0x5) /**< \brief (I2S_RXCTRL) 16 bits compact stereo */
+#define I2S_RXCTRL_DATASIZE_8_Val _U_(0x6) /**< \brief (I2S_RXCTRL) 8 bits */
+#define I2S_RXCTRL_DATASIZE_8C_Val _U_(0x7) /**< \brief (I2S_RXCTRL) 8 bits compact stereo */
+#define I2S_RXCTRL_DATASIZE_32 (I2S_RXCTRL_DATASIZE_32_Val << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_24 (I2S_RXCTRL_DATASIZE_24_Val << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_20 (I2S_RXCTRL_DATASIZE_20_Val << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_18 (I2S_RXCTRL_DATASIZE_18_Val << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_16 (I2S_RXCTRL_DATASIZE_16_Val << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_16C (I2S_RXCTRL_DATASIZE_16C_Val << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_8 (I2S_RXCTRL_DATASIZE_8_Val << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_8C (I2S_RXCTRL_DATASIZE_8C_Val << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_WORDADJ_Pos 12 /**< \brief (I2S_RXCTRL) Data Word Formatting Adjust */
+#define I2S_RXCTRL_WORDADJ (_U_(0x1) << I2S_RXCTRL_WORDADJ_Pos)
+#define I2S_RXCTRL_WORDADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Data is right adjusted in word */
+#define I2S_RXCTRL_WORDADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Data is left adjusted in word */
+#define I2S_RXCTRL_WORDADJ_RIGHT (I2S_RXCTRL_WORDADJ_RIGHT_Val << I2S_RXCTRL_WORDADJ_Pos)
+#define I2S_RXCTRL_WORDADJ_LEFT (I2S_RXCTRL_WORDADJ_LEFT_Val << I2S_RXCTRL_WORDADJ_Pos)
+#define I2S_RXCTRL_EXTEND_Pos 13 /**< \brief (I2S_RXCTRL) Data Formatting Bit Extension */
+#define I2S_RXCTRL_EXTEND_Msk (_U_(0x3) << I2S_RXCTRL_EXTEND_Pos)
+#define I2S_RXCTRL_EXTEND(value) (I2S_RXCTRL_EXTEND_Msk & ((value) << I2S_RXCTRL_EXTEND_Pos))
+#define I2S_RXCTRL_EXTEND_ZERO_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Extend with zeroes */
+#define I2S_RXCTRL_EXTEND_ONE_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Extend with ones */
+#define I2S_RXCTRL_EXTEND_MSBIT_Val _U_(0x2) /**< \brief (I2S_RXCTRL) Extend with Most Significant Bit */
+#define I2S_RXCTRL_EXTEND_LSBIT_Val _U_(0x3) /**< \brief (I2S_RXCTRL) Extend with Least Significant Bit */
+#define I2S_RXCTRL_EXTEND_ZERO (I2S_RXCTRL_EXTEND_ZERO_Val << I2S_RXCTRL_EXTEND_Pos)
+#define I2S_RXCTRL_EXTEND_ONE (I2S_RXCTRL_EXTEND_ONE_Val << I2S_RXCTRL_EXTEND_Pos)
+#define I2S_RXCTRL_EXTEND_MSBIT (I2S_RXCTRL_EXTEND_MSBIT_Val << I2S_RXCTRL_EXTEND_Pos)
+#define I2S_RXCTRL_EXTEND_LSBIT (I2S_RXCTRL_EXTEND_LSBIT_Val << I2S_RXCTRL_EXTEND_Pos)
+#define I2S_RXCTRL_BITREV_Pos 15 /**< \brief (I2S_RXCTRL) Data Formatting Bit Reverse */
+#define I2S_RXCTRL_BITREV (_U_(0x1) << I2S_RXCTRL_BITREV_Pos)
+#define I2S_RXCTRL_BITREV_MSBIT_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
+#define I2S_RXCTRL_BITREV_LSBIT_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Transfer Data Least Significant Bit (LSB) first */
+#define I2S_RXCTRL_BITREV_MSBIT (I2S_RXCTRL_BITREV_MSBIT_Val << I2S_RXCTRL_BITREV_Pos)
+#define I2S_RXCTRL_BITREV_LSBIT (I2S_RXCTRL_BITREV_LSBIT_Val << I2S_RXCTRL_BITREV_Pos)
+#define I2S_RXCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_RXCTRL) Slot 0 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS0 (_U_(1) << I2S_RXCTRL_SLOTDIS0_Pos)
+#define I2S_RXCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_RXCTRL) Slot 1 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS1 (_U_(1) << I2S_RXCTRL_SLOTDIS1_Pos)
+#define I2S_RXCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_RXCTRL) Slot 2 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS2 (_U_(1) << I2S_RXCTRL_SLOTDIS2_Pos)
+#define I2S_RXCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_RXCTRL) Slot 3 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS3 (_U_(1) << I2S_RXCTRL_SLOTDIS3_Pos)
+#define I2S_RXCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_RXCTRL) Slot 4 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS4 (_U_(1) << I2S_RXCTRL_SLOTDIS4_Pos)
+#define I2S_RXCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_RXCTRL) Slot 5 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS5 (_U_(1) << I2S_RXCTRL_SLOTDIS5_Pos)
+#define I2S_RXCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_RXCTRL) Slot 6 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS6 (_U_(1) << I2S_RXCTRL_SLOTDIS6_Pos)
+#define I2S_RXCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_RXCTRL) Slot 7 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS7 (_U_(1) << I2S_RXCTRL_SLOTDIS7_Pos)
+#define I2S_RXCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_RXCTRL) Slot x Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS_Msk (_U_(0xFF) << I2S_RXCTRL_SLOTDIS_Pos)
+#define I2S_RXCTRL_SLOTDIS(value) (I2S_RXCTRL_SLOTDIS_Msk & ((value) << I2S_RXCTRL_SLOTDIS_Pos))
+#define I2S_RXCTRL_MONO_Pos 24 /**< \brief (I2S_RXCTRL) Mono Mode */
+#define I2S_RXCTRL_MONO (_U_(0x1) << I2S_RXCTRL_MONO_Pos)
+#define I2S_RXCTRL_MONO_STEREO_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Normal mode */
+#define I2S_RXCTRL_MONO_MONO_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Left channel data is duplicated to right channel */
+#define I2S_RXCTRL_MONO_STEREO (I2S_RXCTRL_MONO_STEREO_Val << I2S_RXCTRL_MONO_Pos)
+#define I2S_RXCTRL_MONO_MONO (I2S_RXCTRL_MONO_MONO_Val << I2S_RXCTRL_MONO_Pos)
+#define I2S_RXCTRL_DMA_Pos 25 /**< \brief (I2S_RXCTRL) Single or Multiple DMA Channels */
+#define I2S_RXCTRL_DMA (_U_(0x1) << I2S_RXCTRL_DMA_Pos)
+#define I2S_RXCTRL_DMA_SINGLE_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Single DMA channel */
+#define I2S_RXCTRL_DMA_MULTIPLE_Val _U_(0x1) /**< \brief (I2S_RXCTRL) One DMA channel per data channel */
+#define I2S_RXCTRL_DMA_SINGLE (I2S_RXCTRL_DMA_SINGLE_Val << I2S_RXCTRL_DMA_Pos)
+#define I2S_RXCTRL_DMA_MULTIPLE (I2S_RXCTRL_DMA_MULTIPLE_Val << I2S_RXCTRL_DMA_Pos)
+#define I2S_RXCTRL_RXLOOP_Pos 26 /**< \brief (I2S_RXCTRL) Loop-back Test Mode */
+#define I2S_RXCTRL_RXLOOP (_U_(0x1) << I2S_RXCTRL_RXLOOP_Pos)
+#define I2S_RXCTRL_MASK _U_(0x07FFF7A3) /**< \brief (I2S_RXCTRL) MASK Register */
+
+/* -------- I2S_TXDATA : (I2S Offset: 0x30) ( /W 32) Tx Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_TXDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_TXDATA_OFFSET 0x30 /**< \brief (I2S_TXDATA offset) Tx Data */
+#define I2S_TXDATA_RESETVALUE _U_(0x00000000) /**< \brief (I2S_TXDATA reset_value) Tx Data */
+
+#define I2S_TXDATA_DATA_Pos 0 /**< \brief (I2S_TXDATA) Sample Data */
+#define I2S_TXDATA_DATA_Msk (_U_(0xFFFFFFFF) << I2S_TXDATA_DATA_Pos)
+#define I2S_TXDATA_DATA(value) (I2S_TXDATA_DATA_Msk & ((value) << I2S_TXDATA_DATA_Pos))
+#define I2S_TXDATA_MASK _U_(0xFFFFFFFF) /**< \brief (I2S_TXDATA) MASK Register */
+
+/* -------- I2S_RXDATA : (I2S Offset: 0x34) (R/ 32) Rx Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_RXDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_RXDATA_OFFSET 0x34 /**< \brief (I2S_RXDATA offset) Rx Data */
+#define I2S_RXDATA_RESETVALUE _U_(0x00000000) /**< \brief (I2S_RXDATA reset_value) Rx Data */
+
+#define I2S_RXDATA_DATA_Pos 0 /**< \brief (I2S_RXDATA) Sample Data */
+#define I2S_RXDATA_DATA_Msk (_U_(0xFFFFFFFF) << I2S_RXDATA_DATA_Pos)
+#define I2S_RXDATA_DATA(value) (I2S_RXDATA_DATA_Msk & ((value) << I2S_RXDATA_DATA_Pos))
+#define I2S_RXDATA_MASK _U_(0xFFFFFFFF) /**< \brief (I2S_RXDATA) MASK Register */
+
+/** \brief I2S hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ RoReg8 Reserved1[0x3];
+ __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
+ __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
+ RoReg8 Reserved2[0x2];
+ __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
+ RoReg8 Reserved3[0x2];
+ __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x2];
+ __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
+ RoReg8 Reserved5[0x6];
+ __IO I2S_TXCTRL_Type TXCTRL; /**< \brief Offset: 0x20 (R/W 32) Tx Serializer Control */
+ __IO I2S_RXCTRL_Type RXCTRL; /**< \brief Offset: 0x24 (R/W 32) Rx Serializer Control */
+ RoReg8 Reserved6[0x8];
+ __O I2S_TXDATA_Type TXDATA; /**< \brief Offset: 0x30 ( /W 32) Tx Data */
+ __I I2S_RXDATA_Type RXDATA; /**< \brief Offset: 0x34 (R/ 32) Rx Data */
+} I2s;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_I2S_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/icm.h b/sysmoOCTSIM/include/component/icm.h
index 9cc267e..c75fc94 100644
--- a/sysmoOCTSIM/include/component/icm.h
+++ b/sysmoOCTSIM/include/component/icm.h
@@ -1,582 +1,582 @@
-/**
- * \file
- *
- * \brief Component description for ICM
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_ICM_COMPONENT_
-#define _SAME54_ICM_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR ICM */
-/* ========================================================================== */
-/** \addtogroup SAME54_ICM Integrity Check Monitor */
-/*@{*/
-
-#define ICM_U2010
-#define REV_ICM 0x120
-
-/* -------- ICM_CFG : (ICM Offset: 0x00) (R/W 32) Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t WBDIS:1; /*!< bit: 0 Write Back Disable */
- uint32_t EOMDIS:1; /*!< bit: 1 End of Monitoring Disable */
- uint32_t SLBDIS:1; /*!< bit: 2 Secondary List Branching Disable */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t BBC:4; /*!< bit: 4.. 7 Bus Burden Control */
- uint32_t ASCD:1; /*!< bit: 8 Automatic Switch To Compare Digest */
- uint32_t DUALBUFF:1; /*!< bit: 9 Dual Input Buffer */
- uint32_t :2; /*!< bit: 10..11 Reserved */
- uint32_t UIHASH:1; /*!< bit: 12 User Initial Hash Value */
- uint32_t UALGO:3; /*!< bit: 13..15 User SHA Algorithm */
- uint32_t HAPROT:6; /*!< bit: 16..21 Region Hash Area Protection */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t DAPROT:6; /*!< bit: 24..29 Region Descriptor Area Protection */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ICM_CFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_CFG_OFFSET 0x00 /**< \brief (ICM_CFG offset) Configuration */
-#define ICM_CFG_RESETVALUE _U_(0x00000000) /**< \brief (ICM_CFG reset_value) Configuration */
-
-#define ICM_CFG_WBDIS_Pos 0 /**< \brief (ICM_CFG) Write Back Disable */
-#define ICM_CFG_WBDIS (_U_(0x1) << ICM_CFG_WBDIS_Pos)
-#define ICM_CFG_EOMDIS_Pos 1 /**< \brief (ICM_CFG) End of Monitoring Disable */
-#define ICM_CFG_EOMDIS (_U_(0x1) << ICM_CFG_EOMDIS_Pos)
-#define ICM_CFG_SLBDIS_Pos 2 /**< \brief (ICM_CFG) Secondary List Branching Disable */
-#define ICM_CFG_SLBDIS (_U_(0x1) << ICM_CFG_SLBDIS_Pos)
-#define ICM_CFG_BBC_Pos 4 /**< \brief (ICM_CFG) Bus Burden Control */
-#define ICM_CFG_BBC_Msk (_U_(0xF) << ICM_CFG_BBC_Pos)
-#define ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))
-#define ICM_CFG_ASCD_Pos 8 /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */
-#define ICM_CFG_ASCD (_U_(0x1) << ICM_CFG_ASCD_Pos)
-#define ICM_CFG_DUALBUFF_Pos 9 /**< \brief (ICM_CFG) Dual Input Buffer */
-#define ICM_CFG_DUALBUFF (_U_(0x1) << ICM_CFG_DUALBUFF_Pos)
-#define ICM_CFG_UIHASH_Pos 12 /**< \brief (ICM_CFG) User Initial Hash Value */
-#define ICM_CFG_UIHASH (_U_(0x1) << ICM_CFG_UIHASH_Pos)
-#define ICM_CFG_UALGO_Pos 13 /**< \brief (ICM_CFG) User SHA Algorithm */
-#define ICM_CFG_UALGO_Msk (_U_(0x7) << ICM_CFG_UALGO_Pos)
-#define ICM_CFG_UALGO(value) (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))
-#define ICM_CFG_UALGO_SHA1_Val _U_(0x0) /**< \brief (ICM_CFG) SHA1 Algorithm */
-#define ICM_CFG_UALGO_SHA256_Val _U_(0x1) /**< \brief (ICM_CFG) SHA256 Algorithm */
-#define ICM_CFG_UALGO_SHA224_Val _U_(0x4) /**< \brief (ICM_CFG) SHA224 Algorithm */
-#define ICM_CFG_UALGO_SHA1 (ICM_CFG_UALGO_SHA1_Val << ICM_CFG_UALGO_Pos)
-#define ICM_CFG_UALGO_SHA256 (ICM_CFG_UALGO_SHA256_Val << ICM_CFG_UALGO_Pos)
-#define ICM_CFG_UALGO_SHA224 (ICM_CFG_UALGO_SHA224_Val << ICM_CFG_UALGO_Pos)
-#define ICM_CFG_HAPROT_Pos 16 /**< \brief (ICM_CFG) Region Hash Area Protection */
-#define ICM_CFG_HAPROT_Msk (_U_(0x3F) << ICM_CFG_HAPROT_Pos)
-#define ICM_CFG_HAPROT(value) (ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos))
-#define ICM_CFG_DAPROT_Pos 24 /**< \brief (ICM_CFG) Region Descriptor Area Protection */
-#define ICM_CFG_DAPROT_Msk (_U_(0x3F) << ICM_CFG_DAPROT_Pos)
-#define ICM_CFG_DAPROT(value) (ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos))
-#define ICM_CFG_MASK _U_(0x3F3FF3F7) /**< \brief (ICM_CFG) MASK Register */
-
-/* -------- ICM_CTRL : (ICM Offset: 0x04) ( /W 32) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ENABLE:1; /*!< bit: 0 ICM Enable */
- uint32_t DISABLE:1; /*!< bit: 1 ICM Disable Register */
- uint32_t SWRST:1; /*!< bit: 2 Software Reset */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t REHASH:4; /*!< bit: 4.. 7 Recompute Internal Hash */
- uint32_t RMDIS:4; /*!< bit: 8..11 Region Monitoring Disable */
- uint32_t RMEN:4; /*!< bit: 12..15 Region Monitoring Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ICM_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_CTRL_OFFSET 0x04 /**< \brief (ICM_CTRL offset) Control */
-
-#define ICM_CTRL_ENABLE_Pos 0 /**< \brief (ICM_CTRL) ICM Enable */
-#define ICM_CTRL_ENABLE (_U_(0x1) << ICM_CTRL_ENABLE_Pos)
-#define ICM_CTRL_DISABLE_Pos 1 /**< \brief (ICM_CTRL) ICM Disable Register */
-#define ICM_CTRL_DISABLE (_U_(0x1) << ICM_CTRL_DISABLE_Pos)
-#define ICM_CTRL_SWRST_Pos 2 /**< \brief (ICM_CTRL) Software Reset */
-#define ICM_CTRL_SWRST (_U_(0x1) << ICM_CTRL_SWRST_Pos)
-#define ICM_CTRL_REHASH_Pos 4 /**< \brief (ICM_CTRL) Recompute Internal Hash */
-#define ICM_CTRL_REHASH_Msk (_U_(0xF) << ICM_CTRL_REHASH_Pos)
-#define ICM_CTRL_REHASH(value) (ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))
-#define ICM_CTRL_RMDIS_Pos 8 /**< \brief (ICM_CTRL) Region Monitoring Disable */
-#define ICM_CTRL_RMDIS_Msk (_U_(0xF) << ICM_CTRL_RMDIS_Pos)
-#define ICM_CTRL_RMDIS(value) (ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))
-#define ICM_CTRL_RMEN_Pos 12 /**< \brief (ICM_CTRL) Region Monitoring Enable */
-#define ICM_CTRL_RMEN_Msk (_U_(0xF) << ICM_CTRL_RMEN_Pos)
-#define ICM_CTRL_RMEN(value) (ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))
-#define ICM_CTRL_MASK _U_(0x0000FFF7) /**< \brief (ICM_CTRL) MASK Register */
-
-/* -------- ICM_SR : (ICM Offset: 0x08) (R/ 32) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ENABLE:1; /*!< bit: 0 ICM Controller Enable Register */
- uint32_t :7; /*!< bit: 1.. 7 Reserved */
- uint32_t RAWRMDIS:4; /*!< bit: 8..11 RAW Region Monitoring Disabled Status */
- uint32_t RMDIS:4; /*!< bit: 12..15 Region Monitoring Disabled Status */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ICM_SR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_SR_OFFSET 0x08 /**< \brief (ICM_SR offset) Status */
-#define ICM_SR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_SR reset_value) Status */
-
-#define ICM_SR_ENABLE_Pos 0 /**< \brief (ICM_SR) ICM Controller Enable Register */
-#define ICM_SR_ENABLE (_U_(0x1) << ICM_SR_ENABLE_Pos)
-#define ICM_SR_RAWRMDIS_Pos 8 /**< \brief (ICM_SR) RAW Region Monitoring Disabled Status */
-#define ICM_SR_RAWRMDIS_Msk (_U_(0xF) << ICM_SR_RAWRMDIS_Pos)
-#define ICM_SR_RAWRMDIS(value) (ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))
-#define ICM_SR_RMDIS_Pos 12 /**< \brief (ICM_SR) Region Monitoring Disabled Status */
-#define ICM_SR_RMDIS_Msk (_U_(0xF) << ICM_SR_RMDIS_Pos)
-#define ICM_SR_RMDIS(value) (ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))
-#define ICM_SR_MASK _U_(0x0000FF01) /**< \brief (ICM_SR) MASK Register */
-
-/* -------- ICM_IER : (ICM Offset: 0x10) ( /W 32) Interrupt Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed Interrupt Enable */
- uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch Interrupt Enable */
- uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error Interrupt Enable */
- uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition detected Interrupt Enable */
- uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition Detected Interrupt Enable */
- uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Interrupt Disable */
- uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Interrupt Enable */
- uint32_t :7; /*!< bit: 25..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ICM_IER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_IER_OFFSET 0x10 /**< \brief (ICM_IER offset) Interrupt Enable */
-
-#define ICM_IER_RHC_Pos 0 /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */
-#define ICM_IER_RHC_Msk (_U_(0xF) << ICM_IER_RHC_Pos)
-#define ICM_IER_RHC(value) (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))
-#define ICM_IER_RDM_Pos 4 /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */
-#define ICM_IER_RDM_Msk (_U_(0xF) << ICM_IER_RDM_Pos)
-#define ICM_IER_RDM(value) (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))
-#define ICM_IER_RBE_Pos 8 /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */
-#define ICM_IER_RBE_Msk (_U_(0xF) << ICM_IER_RBE_Pos)
-#define ICM_IER_RBE(value) (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))
-#define ICM_IER_RWC_Pos 12 /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */
-#define ICM_IER_RWC_Msk (_U_(0xF) << ICM_IER_RWC_Pos)
-#define ICM_IER_RWC(value) (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))
-#define ICM_IER_REC_Pos 16 /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */
-#define ICM_IER_REC_Msk (_U_(0xF) << ICM_IER_REC_Pos)
-#define ICM_IER_REC(value) (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))
-#define ICM_IER_RSU_Pos 20 /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */
-#define ICM_IER_RSU_Msk (_U_(0xF) << ICM_IER_RSU_Pos)
-#define ICM_IER_RSU(value) (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))
-#define ICM_IER_URAD_Pos 24 /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */
-#define ICM_IER_URAD (_U_(0x1) << ICM_IER_URAD_Pos)
-#define ICM_IER_MASK _U_(0x01FFFFFF) /**< \brief (ICM_IER) MASK Register */
-
-/* -------- ICM_IDR : (ICM Offset: 0x14) ( /W 32) Interrupt Disable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed Interrupt Disable */
- uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch Interrupt Disable */
- uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error Interrupt Disable */
- uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition Detected Interrupt Disable */
- uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition detected Interrupt Disable */
- uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Interrupt Disable */
- uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Interrupt Disable */
- uint32_t :7; /*!< bit: 25..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ICM_IDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_IDR_OFFSET 0x14 /**< \brief (ICM_IDR offset) Interrupt Disable */
-#define ICM_IDR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_IDR reset_value) Interrupt Disable */
-
-#define ICM_IDR_RHC_Pos 0 /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */
-#define ICM_IDR_RHC_Msk (_U_(0xF) << ICM_IDR_RHC_Pos)
-#define ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))
-#define ICM_IDR_RDM_Pos 4 /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */
-#define ICM_IDR_RDM_Msk (_U_(0xF) << ICM_IDR_RDM_Pos)
-#define ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))
-#define ICM_IDR_RBE_Pos 8 /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */
-#define ICM_IDR_RBE_Msk (_U_(0xF) << ICM_IDR_RBE_Pos)
-#define ICM_IDR_RBE(value) (ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))
-#define ICM_IDR_RWC_Pos 12 /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */
-#define ICM_IDR_RWC_Msk (_U_(0xF) << ICM_IDR_RWC_Pos)
-#define ICM_IDR_RWC(value) (ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))
-#define ICM_IDR_REC_Pos 16 /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */
-#define ICM_IDR_REC_Msk (_U_(0xF) << ICM_IDR_REC_Pos)
-#define ICM_IDR_REC(value) (ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))
-#define ICM_IDR_RSU_Pos 20 /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */
-#define ICM_IDR_RSU_Msk (_U_(0xF) << ICM_IDR_RSU_Pos)
-#define ICM_IDR_RSU(value) (ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))
-#define ICM_IDR_URAD_Pos 24 /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */
-#define ICM_IDR_URAD (_U_(0x1) << ICM_IDR_URAD_Pos)
-#define ICM_IDR_MASK _U_(0x01FFFFFF) /**< \brief (ICM_IDR) MASK Register */
-
-/* -------- ICM_IMR : (ICM Offset: 0x18) (R/ 32) Interrupt Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed Interrupt Mask */
- uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch Interrupt Mask */
- uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error Interrupt Mask */
- uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition Detected Interrupt Mask */
- uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition Detected Interrupt Mask */
- uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Interrupt Mask */
- uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Interrupt Mask */
- uint32_t :7; /*!< bit: 25..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ICM_IMR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_IMR_OFFSET 0x18 /**< \brief (ICM_IMR offset) Interrupt Mask */
-#define ICM_IMR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_IMR reset_value) Interrupt Mask */
-
-#define ICM_IMR_RHC_Pos 0 /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */
-#define ICM_IMR_RHC_Msk (_U_(0xF) << ICM_IMR_RHC_Pos)
-#define ICM_IMR_RHC(value) (ICM_IMR_RHC_Msk & ((value) << ICM_IMR_RHC_Pos))
-#define ICM_IMR_RDM_Pos 4 /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */
-#define ICM_IMR_RDM_Msk (_U_(0xF) << ICM_IMR_RDM_Pos)
-#define ICM_IMR_RDM(value) (ICM_IMR_RDM_Msk & ((value) << ICM_IMR_RDM_Pos))
-#define ICM_IMR_RBE_Pos 8 /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */
-#define ICM_IMR_RBE_Msk (_U_(0xF) << ICM_IMR_RBE_Pos)
-#define ICM_IMR_RBE(value) (ICM_IMR_RBE_Msk & ((value) << ICM_IMR_RBE_Pos))
-#define ICM_IMR_RWC_Pos 12 /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */
-#define ICM_IMR_RWC_Msk (_U_(0xF) << ICM_IMR_RWC_Pos)
-#define ICM_IMR_RWC(value) (ICM_IMR_RWC_Msk & ((value) << ICM_IMR_RWC_Pos))
-#define ICM_IMR_REC_Pos 16 /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */
-#define ICM_IMR_REC_Msk (_U_(0xF) << ICM_IMR_REC_Pos)
-#define ICM_IMR_REC(value) (ICM_IMR_REC_Msk & ((value) << ICM_IMR_REC_Pos))
-#define ICM_IMR_RSU_Pos 20 /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */
-#define ICM_IMR_RSU_Msk (_U_(0xF) << ICM_IMR_RSU_Pos)
-#define ICM_IMR_RSU(value) (ICM_IMR_RSU_Msk & ((value) << ICM_IMR_RSU_Pos))
-#define ICM_IMR_URAD_Pos 24 /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */
-#define ICM_IMR_URAD (_U_(0x1) << ICM_IMR_URAD_Pos)
-#define ICM_IMR_MASK _U_(0x01FFFFFF) /**< \brief (ICM_IMR) MASK Register */
-
-/* -------- ICM_ISR : (ICM Offset: 0x1C) (R/ 32) Interrupt Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed */
- uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch */
- uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error */
- uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition Detected */
- uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition Detected */
- uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Detected */
- uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Status */
- uint32_t :7; /*!< bit: 25..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ICM_ISR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_ISR_OFFSET 0x1C /**< \brief (ICM_ISR offset) Interrupt Status */
-#define ICM_ISR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_ISR reset_value) Interrupt Status */
-
-#define ICM_ISR_RHC_Pos 0 /**< \brief (ICM_ISR) Region Hash Completed */
-#define ICM_ISR_RHC_Msk (_U_(0xF) << ICM_ISR_RHC_Pos)
-#define ICM_ISR_RHC(value) (ICM_ISR_RHC_Msk & ((value) << ICM_ISR_RHC_Pos))
-#define ICM_ISR_RDM_Pos 4 /**< \brief (ICM_ISR) Region Digest Mismatch */
-#define ICM_ISR_RDM_Msk (_U_(0xF) << ICM_ISR_RDM_Pos)
-#define ICM_ISR_RDM(value) (ICM_ISR_RDM_Msk & ((value) << ICM_ISR_RDM_Pos))
-#define ICM_ISR_RBE_Pos 8 /**< \brief (ICM_ISR) Region Bus Error */
-#define ICM_ISR_RBE_Msk (_U_(0xF) << ICM_ISR_RBE_Pos)
-#define ICM_ISR_RBE(value) (ICM_ISR_RBE_Msk & ((value) << ICM_ISR_RBE_Pos))
-#define ICM_ISR_RWC_Pos 12 /**< \brief (ICM_ISR) Region Wrap Condition Detected */
-#define ICM_ISR_RWC_Msk (_U_(0xF) << ICM_ISR_RWC_Pos)
-#define ICM_ISR_RWC(value) (ICM_ISR_RWC_Msk & ((value) << ICM_ISR_RWC_Pos))
-#define ICM_ISR_REC_Pos 16 /**< \brief (ICM_ISR) Region End bit Condition Detected */
-#define ICM_ISR_REC_Msk (_U_(0xF) << ICM_ISR_REC_Pos)
-#define ICM_ISR_REC(value) (ICM_ISR_REC_Msk & ((value) << ICM_ISR_REC_Pos))
-#define ICM_ISR_RSU_Pos 20 /**< \brief (ICM_ISR) Region Status Updated Detected */
-#define ICM_ISR_RSU_Msk (_U_(0xF) << ICM_ISR_RSU_Pos)
-#define ICM_ISR_RSU(value) (ICM_ISR_RSU_Msk & ((value) << ICM_ISR_RSU_Pos))
-#define ICM_ISR_URAD_Pos 24 /**< \brief (ICM_ISR) Undefined Register Access Detection Status */
-#define ICM_ISR_URAD (_U_(0x1) << ICM_ISR_URAD_Pos)
-#define ICM_ISR_MASK _U_(0x01FFFFFF) /**< \brief (ICM_ISR) MASK Register */
-
-/* -------- ICM_UASR : (ICM Offset: 0x20) (R/ 32) Undefined Access Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t URAT:3; /*!< bit: 0.. 2 Undefined Register Access Trace */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ICM_UASR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_UASR_OFFSET 0x20 /**< \brief (ICM_UASR offset) Undefined Access Status */
-#define ICM_UASR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_UASR reset_value) Undefined Access Status */
-
-#define ICM_UASR_URAT_Pos 0 /**< \brief (ICM_UASR) Undefined Register Access Trace */
-#define ICM_UASR_URAT_Msk (_U_(0x7) << ICM_UASR_URAT_Pos)
-#define ICM_UASR_URAT(value) (ICM_UASR_URAT_Msk & ((value) << ICM_UASR_URAT_Pos))
-#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val _U_(0x0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded */
-#define ICM_UASR_URAT_CFG_MODIFIED_Val _U_(0x1) /**< \brief (ICM_UASR) CFG modified during active monitoring */
-#define ICM_UASR_URAT_DSCR_MODIFIED_Val _U_(0x2) /**< \brief (ICM_UASR) DSCR modified during active monitoring */
-#define ICM_UASR_URAT_HASH_MODIFIED_Val _U_(0x3) /**< \brief (ICM_UASR) HASH modified during active monitoring */
-#define ICM_UASR_URAT_READ_ACCESS_Val _U_(0x4) /**< \brief (ICM_UASR) Write-only register read access */
-#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val << ICM_UASR_URAT_Pos)
-#define ICM_UASR_URAT_CFG_MODIFIED (ICM_UASR_URAT_CFG_MODIFIED_Val << ICM_UASR_URAT_Pos)
-#define ICM_UASR_URAT_DSCR_MODIFIED (ICM_UASR_URAT_DSCR_MODIFIED_Val << ICM_UASR_URAT_Pos)
-#define ICM_UASR_URAT_HASH_MODIFIED (ICM_UASR_URAT_HASH_MODIFIED_Val << ICM_UASR_URAT_Pos)
-#define ICM_UASR_URAT_READ_ACCESS (ICM_UASR_URAT_READ_ACCESS_Val << ICM_UASR_URAT_Pos)
-#define ICM_UASR_MASK _U_(0x00000007) /**< \brief (ICM_UASR) MASK Register */
-
-/* -------- ICM_DSCR : (ICM Offset: 0x30) (R/W 32) Region Descriptor Area Start Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :6; /*!< bit: 0.. 5 Reserved */
- uint32_t DASA:26; /*!< bit: 6..31 Descriptor Area Start Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ICM_DSCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_DSCR_OFFSET 0x30 /**< \brief (ICM_DSCR offset) Region Descriptor Area Start Address */
-#define ICM_DSCR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_DSCR reset_value) Region Descriptor Area Start Address */
-
-#define ICM_DSCR_DASA_Pos 6 /**< \brief (ICM_DSCR) Descriptor Area Start Address */
-#define ICM_DSCR_DASA_Msk (_U_(0x3FFFFFF) << ICM_DSCR_DASA_Pos)
-#define ICM_DSCR_DASA(value) (ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))
-#define ICM_DSCR_MASK _U_(0xFFFFFFC0) /**< \brief (ICM_DSCR) MASK Register */
-
-/* -------- ICM_HASH : (ICM Offset: 0x34) (R/W 32) Region Hash Area Start Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :7; /*!< bit: 0.. 6 Reserved */
- uint32_t HASA:25; /*!< bit: 7..31 Hash Area Start Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ICM_HASH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_HASH_OFFSET 0x34 /**< \brief (ICM_HASH offset) Region Hash Area Start Address */
-#define ICM_HASH_RESETVALUE _U_(0x00000000) /**< \brief (ICM_HASH reset_value) Region Hash Area Start Address */
-
-#define ICM_HASH_HASA_Pos 7 /**< \brief (ICM_HASH) Hash Area Start Address */
-#define ICM_HASH_HASA_Msk (_U_(0x1FFFFFF) << ICM_HASH_HASA_Pos)
-#define ICM_HASH_HASA(value) (ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))
-#define ICM_HASH_MASK _U_(0xFFFFFF80) /**< \brief (ICM_HASH) MASK Register */
-
-/* -------- ICM_UIHVAL : (ICM Offset: 0x38) ( /W 32) User Initial Hash Value n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t VAL:32; /*!< bit: 0..31 Initial Hash Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ICM_UIHVAL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_UIHVAL_OFFSET 0x38 /**< \brief (ICM_UIHVAL offset) User Initial Hash Value n */
-#define ICM_UIHVAL_RESETVALUE _U_(0x00000000) /**< \brief (ICM_UIHVAL reset_value) User Initial Hash Value n */
-
-#define ICM_UIHVAL_VAL_Pos 0 /**< \brief (ICM_UIHVAL) Initial Hash Value */
-#define ICM_UIHVAL_VAL_Msk (_U_(0xFFFFFFFF) << ICM_UIHVAL_VAL_Pos)
-#define ICM_UIHVAL_VAL(value) (ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))
-#define ICM_UIHVAL_MASK _U_(0xFFFFFFFF) /**< \brief (ICM_UIHVAL) MASK Register */
-
-/* -------- ICM_RADDR : (ICM Offset: 0x00) (R/W 32) Region Start Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint32_t reg; /*!< Type used for register access */
-} ICM_RADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_RADDR_OFFSET 0x00 /**< \brief (ICM_RADDR offset) Region Start Address */
-#define ICM_RADDR_MASK _U_(0xFFFFFFFF) /**< \brief (ICM_RADDR) MASK Register */
-
-/* -------- ICM_RCFG : (ICM Offset: 0x04) (R/W 32) Region Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CDWBN:1; /*!< bit: 0 Compare Digest Write Back */
- uint32_t WRAP:1; /*!< bit: 1 Region Wrap */
- uint32_t EOM:1; /*!< bit: 2 End of Monitoring */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t RHIEN:1; /*!< bit: 4 Region Hash Interrupt Enable */
- uint32_t DMIEN:1; /*!< bit: 5 Region Digest Mismatch Interrupt Enable */
- uint32_t BEIEN:1; /*!< bit: 6 Region Bus Error Interrupt Enable */
- uint32_t WCIEN:1; /*!< bit: 7 Region Wrap Condition Detected Interrupt Enable */
- uint32_t ECIEN:1; /*!< bit: 8 Region End bit Condition detected Interrupt Enable */
- uint32_t SUIEN:1; /*!< bit: 9 Region Status Updated Interrupt Enable */
- uint32_t PROCDLY:1; /*!< bit: 10 SHA Processing Delay */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t ALGO:3; /*!< bit: 12..14 SHA Algorithm */
- uint32_t :9; /*!< bit: 15..23 Reserved */
- uint32_t MRPROT:6; /*!< bit: 24..29 Memory Region AHB Protection */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ICM_RCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_RCFG_OFFSET 0x04 /**< \brief (ICM_RCFG offset) Region Configuration */
-#define ICM_RCFG_RESETVALUE _U_(0x00000000) /**< \brief (ICM_RCFG reset_value) Region Configuration */
-
-#define ICM_RCFG_CDWBN_Pos 0 /**< \brief (ICM_RCFG) Compare Digest Write Back */
-#define ICM_RCFG_CDWBN (_U_(0x1) << ICM_RCFG_CDWBN_Pos)
-#define ICM_RCFG_CDWBN_WRBA_Val _U_(0x0) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_CDWBN_COMP_Val _U_(0x1) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_CDWBN_WRBA (ICM_RCFG_CDWBN_WRBA_Val << ICM_RCFG_CDWBN_Pos)
-#define ICM_RCFG_CDWBN_COMP (ICM_RCFG_CDWBN_COMP_Val << ICM_RCFG_CDWBN_Pos)
-#define ICM_RCFG_WRAP_Pos 1 /**< \brief (ICM_RCFG) Region Wrap */
-#define ICM_RCFG_WRAP (_U_(0x1) << ICM_RCFG_WRAP_Pos)
-#define ICM_RCFG_WRAP_NO_Val _U_(0x0) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_WRAP_YES_Val _U_(0x1) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_WRAP_NO (ICM_RCFG_WRAP_NO_Val << ICM_RCFG_WRAP_Pos)
-#define ICM_RCFG_WRAP_YES (ICM_RCFG_WRAP_YES_Val << ICM_RCFG_WRAP_Pos)
-#define ICM_RCFG_EOM_Pos 2 /**< \brief (ICM_RCFG) End of Monitoring */
-#define ICM_RCFG_EOM (_U_(0x1) << ICM_RCFG_EOM_Pos)
-#define ICM_RCFG_EOM_NO_Val _U_(0x0) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_EOM_YES_Val _U_(0x1) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_EOM_NO (ICM_RCFG_EOM_NO_Val << ICM_RCFG_EOM_Pos)
-#define ICM_RCFG_EOM_YES (ICM_RCFG_EOM_YES_Val << ICM_RCFG_EOM_Pos)
-#define ICM_RCFG_RHIEN_Pos 4 /**< \brief (ICM_RCFG) Region Hash Interrupt Enable */
-#define ICM_RCFG_RHIEN (_U_(0x1) << ICM_RCFG_RHIEN_Pos)
-#define ICM_RCFG_RHIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_RHIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_RHIEN_EN (ICM_RCFG_RHIEN_EN_Val << ICM_RCFG_RHIEN_Pos)
-#define ICM_RCFG_RHIEN_DIS (ICM_RCFG_RHIEN_DIS_Val << ICM_RCFG_RHIEN_Pos)
-#define ICM_RCFG_DMIEN_Pos 5 /**< \brief (ICM_RCFG) Region Digest Mismatch Interrupt Enable */
-#define ICM_RCFG_DMIEN (_U_(0x1) << ICM_RCFG_DMIEN_Pos)
-#define ICM_RCFG_DMIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_DMIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_DMIEN_EN (ICM_RCFG_DMIEN_EN_Val << ICM_RCFG_DMIEN_Pos)
-#define ICM_RCFG_DMIEN_DIS (ICM_RCFG_DMIEN_DIS_Val << ICM_RCFG_DMIEN_Pos)
-#define ICM_RCFG_BEIEN_Pos 6 /**< \brief (ICM_RCFG) Region Bus Error Interrupt Enable */
-#define ICM_RCFG_BEIEN (_U_(0x1) << ICM_RCFG_BEIEN_Pos)
-#define ICM_RCFG_BEIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_BEIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_BEIEN_EN (ICM_RCFG_BEIEN_EN_Val << ICM_RCFG_BEIEN_Pos)
-#define ICM_RCFG_BEIEN_DIS (ICM_RCFG_BEIEN_DIS_Val << ICM_RCFG_BEIEN_Pos)
-#define ICM_RCFG_WCIEN_Pos 7 /**< \brief (ICM_RCFG) Region Wrap Condition Detected Interrupt Enable */
-#define ICM_RCFG_WCIEN (_U_(0x1) << ICM_RCFG_WCIEN_Pos)
-#define ICM_RCFG_WCIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_WCIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_WCIEN_EN (ICM_RCFG_WCIEN_EN_Val << ICM_RCFG_WCIEN_Pos)
-#define ICM_RCFG_WCIEN_DIS (ICM_RCFG_WCIEN_DIS_Val << ICM_RCFG_WCIEN_Pos)
-#define ICM_RCFG_ECIEN_Pos 8 /**< \brief (ICM_RCFG) Region End bit Condition detected Interrupt Enable */
-#define ICM_RCFG_ECIEN (_U_(0x1) << ICM_RCFG_ECIEN_Pos)
-#define ICM_RCFG_ECIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_ECIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_ECIEN_EN (ICM_RCFG_ECIEN_EN_Val << ICM_RCFG_ECIEN_Pos)
-#define ICM_RCFG_ECIEN_DIS (ICM_RCFG_ECIEN_DIS_Val << ICM_RCFG_ECIEN_Pos)
-#define ICM_RCFG_SUIEN_Pos 9 /**< \brief (ICM_RCFG) Region Status Updated Interrupt Enable */
-#define ICM_RCFG_SUIEN (_U_(0x1) << ICM_RCFG_SUIEN_Pos)
-#define ICM_RCFG_SUIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_SUIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_SUIEN_EN (ICM_RCFG_SUIEN_EN_Val << ICM_RCFG_SUIEN_Pos)
-#define ICM_RCFG_SUIEN_DIS (ICM_RCFG_SUIEN_DIS_Val << ICM_RCFG_SUIEN_Pos)
-#define ICM_RCFG_PROCDLY_Pos 10 /**< \brief (ICM_RCFG) SHA Processing Delay */
-#define ICM_RCFG_PROCDLY (_U_(0x1) << ICM_RCFG_PROCDLY_Pos)
-#define ICM_RCFG_PROCDLY_SHORT_Val _U_(0x0) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_PROCDLY_LONG_Val _U_(0x1) /**< \brief (ICM_RCFG) */
-#define ICM_RCFG_PROCDLY_SHORT (ICM_RCFG_PROCDLY_SHORT_Val << ICM_RCFG_PROCDLY_Pos)
-#define ICM_RCFG_PROCDLY_LONG (ICM_RCFG_PROCDLY_LONG_Val << ICM_RCFG_PROCDLY_Pos)
-#define ICM_RCFG_ALGO_Pos 12 /**< \brief (ICM_RCFG) SHA Algorithm */
-#define ICM_RCFG_ALGO_Msk (_U_(0x7) << ICM_RCFG_ALGO_Pos)
-#define ICM_RCFG_ALGO(value) (ICM_RCFG_ALGO_Msk & ((value) << ICM_RCFG_ALGO_Pos))
-#define ICM_RCFG_MRPROT_Pos 24 /**< \brief (ICM_RCFG) Memory Region AHB Protection */
-#define ICM_RCFG_MRPROT_Msk (_U_(0x3F) << ICM_RCFG_MRPROT_Pos)
-#define ICM_RCFG_MRPROT(value) (ICM_RCFG_MRPROT_Msk & ((value) << ICM_RCFG_MRPROT_Pos))
-#define ICM_RCFG_MASK _U_(0x3F0077F7) /**< \brief (ICM_RCFG) MASK Register */
-
-/* -------- ICM_RCTRL : (ICM Offset: 0x08) (R/W 32) Region Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TRSIZE:16; /*!< bit: 0..15 Transfer Size */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ICM_RCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_RCTRL_OFFSET 0x08 /**< \brief (ICM_RCTRL offset) Region Control */
-
-#define ICM_RCTRL_TRSIZE_Pos 0 /**< \brief (ICM_RCTRL) Transfer Size */
-#define ICM_RCTRL_TRSIZE_Msk (_U_(0xFFFF) << ICM_RCTRL_TRSIZE_Pos)
-#define ICM_RCTRL_TRSIZE(value) (ICM_RCTRL_TRSIZE_Msk & ((value) << ICM_RCTRL_TRSIZE_Pos))
-#define ICM_RCTRL_MASK _U_(0x0000FFFF) /**< \brief (ICM_RCTRL) MASK Register */
-
-/* -------- ICM_RNEXT : (ICM Offset: 0x0C) (R/W 32) Region Next Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint32_t reg; /*!< Type used for register access */
-} ICM_RNEXT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_RNEXT_OFFSET 0x0C /**< \brief (ICM_RNEXT offset) Region Next Address */
-#define ICM_RNEXT_MASK _U_(0xFFFFFFFF) /**< \brief (ICM_RNEXT) MASK Register */
-
-/** \brief ICM APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO ICM_CFG_Type CFG; /**< \brief Offset: 0x00 (R/W 32) Configuration */
- __O ICM_CTRL_Type CTRL; /**< \brief Offset: 0x04 ( /W 32) Control */
- __I ICM_SR_Type SR; /**< \brief Offset: 0x08 (R/ 32) Status */
- RoReg8 Reserved1[0x4];
- __O ICM_IER_Type IER; /**< \brief Offset: 0x10 ( /W 32) Interrupt Enable */
- __O ICM_IDR_Type IDR; /**< \brief Offset: 0x14 ( /W 32) Interrupt Disable */
- __I ICM_IMR_Type IMR; /**< \brief Offset: 0x18 (R/ 32) Interrupt Mask */
- __I ICM_ISR_Type ISR; /**< \brief Offset: 0x1C (R/ 32) Interrupt Status */
- __I ICM_UASR_Type UASR; /**< \brief Offset: 0x20 (R/ 32) Undefined Access Status */
- RoReg8 Reserved2[0xC];
- __IO ICM_DSCR_Type DSCR; /**< \brief Offset: 0x30 (R/W 32) Region Descriptor Area Start Address */
- __IO ICM_HASH_Type HASH; /**< \brief Offset: 0x34 (R/W 32) Region Hash Area Start Address */
- __O ICM_UIHVAL_Type UIHVAL[8]; /**< \brief Offset: 0x38 ( /W 32) User Initial Hash Value n */
-} Icm;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief ICM Descriptor SRAM registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO ICM_RADDR_Type RADDR; /**< \brief Offset: 0x00 (R/W 32) Region Start Address */
- __IO ICM_RCFG_Type RCFG; /**< \brief Offset: 0x04 (R/W 32) Region Configuration */
- __IO ICM_RCTRL_Type RCTRL; /**< \brief Offset: 0x08 (R/W 32) Region Control */
- __IO ICM_RNEXT_Type RNEXT; /**< \brief Offset: 0x0C (R/W 32) Region Next Address */
-} IcmDescriptor;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SECTION_ICM_DESCRIPTOR
-
-/*@}*/
-
-#endif /* _SAME54_ICM_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for ICM
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_ICM_COMPONENT_
+#define _SAME54_ICM_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR ICM */
+/* ========================================================================== */
+/** \addtogroup SAME54_ICM Integrity Check Monitor */
+/*@{*/
+
+#define ICM_U2010
+#define REV_ICM 0x120
+
+/* -------- ICM_CFG : (ICM Offset: 0x00) (R/W 32) Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WBDIS:1; /*!< bit: 0 Write Back Disable */
+ uint32_t EOMDIS:1; /*!< bit: 1 End of Monitoring Disable */
+ uint32_t SLBDIS:1; /*!< bit: 2 Secondary List Branching Disable */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t BBC:4; /*!< bit: 4.. 7 Bus Burden Control */
+ uint32_t ASCD:1; /*!< bit: 8 Automatic Switch To Compare Digest */
+ uint32_t DUALBUFF:1; /*!< bit: 9 Dual Input Buffer */
+ uint32_t :2; /*!< bit: 10..11 Reserved */
+ uint32_t UIHASH:1; /*!< bit: 12 User Initial Hash Value */
+ uint32_t UALGO:3; /*!< bit: 13..15 User SHA Algorithm */
+ uint32_t HAPROT:6; /*!< bit: 16..21 Region Hash Area Protection */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t DAPROT:6; /*!< bit: 24..29 Region Descriptor Area Protection */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_CFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_CFG_OFFSET 0x00 /**< \brief (ICM_CFG offset) Configuration */
+#define ICM_CFG_RESETVALUE _U_(0x00000000) /**< \brief (ICM_CFG reset_value) Configuration */
+
+#define ICM_CFG_WBDIS_Pos 0 /**< \brief (ICM_CFG) Write Back Disable */
+#define ICM_CFG_WBDIS (_U_(0x1) << ICM_CFG_WBDIS_Pos)
+#define ICM_CFG_EOMDIS_Pos 1 /**< \brief (ICM_CFG) End of Monitoring Disable */
+#define ICM_CFG_EOMDIS (_U_(0x1) << ICM_CFG_EOMDIS_Pos)
+#define ICM_CFG_SLBDIS_Pos 2 /**< \brief (ICM_CFG) Secondary List Branching Disable */
+#define ICM_CFG_SLBDIS (_U_(0x1) << ICM_CFG_SLBDIS_Pos)
+#define ICM_CFG_BBC_Pos 4 /**< \brief (ICM_CFG) Bus Burden Control */
+#define ICM_CFG_BBC_Msk (_U_(0xF) << ICM_CFG_BBC_Pos)
+#define ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))
+#define ICM_CFG_ASCD_Pos 8 /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */
+#define ICM_CFG_ASCD (_U_(0x1) << ICM_CFG_ASCD_Pos)
+#define ICM_CFG_DUALBUFF_Pos 9 /**< \brief (ICM_CFG) Dual Input Buffer */
+#define ICM_CFG_DUALBUFF (_U_(0x1) << ICM_CFG_DUALBUFF_Pos)
+#define ICM_CFG_UIHASH_Pos 12 /**< \brief (ICM_CFG) User Initial Hash Value */
+#define ICM_CFG_UIHASH (_U_(0x1) << ICM_CFG_UIHASH_Pos)
+#define ICM_CFG_UALGO_Pos 13 /**< \brief (ICM_CFG) User SHA Algorithm */
+#define ICM_CFG_UALGO_Msk (_U_(0x7) << ICM_CFG_UALGO_Pos)
+#define ICM_CFG_UALGO(value) (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))
+#define ICM_CFG_UALGO_SHA1_Val _U_(0x0) /**< \brief (ICM_CFG) SHA1 Algorithm */
+#define ICM_CFG_UALGO_SHA256_Val _U_(0x1) /**< \brief (ICM_CFG) SHA256 Algorithm */
+#define ICM_CFG_UALGO_SHA224_Val _U_(0x4) /**< \brief (ICM_CFG) SHA224 Algorithm */
+#define ICM_CFG_UALGO_SHA1 (ICM_CFG_UALGO_SHA1_Val << ICM_CFG_UALGO_Pos)
+#define ICM_CFG_UALGO_SHA256 (ICM_CFG_UALGO_SHA256_Val << ICM_CFG_UALGO_Pos)
+#define ICM_CFG_UALGO_SHA224 (ICM_CFG_UALGO_SHA224_Val << ICM_CFG_UALGO_Pos)
+#define ICM_CFG_HAPROT_Pos 16 /**< \brief (ICM_CFG) Region Hash Area Protection */
+#define ICM_CFG_HAPROT_Msk (_U_(0x3F) << ICM_CFG_HAPROT_Pos)
+#define ICM_CFG_HAPROT(value) (ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos))
+#define ICM_CFG_DAPROT_Pos 24 /**< \brief (ICM_CFG) Region Descriptor Area Protection */
+#define ICM_CFG_DAPROT_Msk (_U_(0x3F) << ICM_CFG_DAPROT_Pos)
+#define ICM_CFG_DAPROT(value) (ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos))
+#define ICM_CFG_MASK _U_(0x3F3FF3F7) /**< \brief (ICM_CFG) MASK Register */
+
+/* -------- ICM_CTRL : (ICM Offset: 0x04) ( /W 32) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ENABLE:1; /*!< bit: 0 ICM Enable */
+ uint32_t DISABLE:1; /*!< bit: 1 ICM Disable Register */
+ uint32_t SWRST:1; /*!< bit: 2 Software Reset */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t REHASH:4; /*!< bit: 4.. 7 Recompute Internal Hash */
+ uint32_t RMDIS:4; /*!< bit: 8..11 Region Monitoring Disable */
+ uint32_t RMEN:4; /*!< bit: 12..15 Region Monitoring Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_CTRL_OFFSET 0x04 /**< \brief (ICM_CTRL offset) Control */
+
+#define ICM_CTRL_ENABLE_Pos 0 /**< \brief (ICM_CTRL) ICM Enable */
+#define ICM_CTRL_ENABLE (_U_(0x1) << ICM_CTRL_ENABLE_Pos)
+#define ICM_CTRL_DISABLE_Pos 1 /**< \brief (ICM_CTRL) ICM Disable Register */
+#define ICM_CTRL_DISABLE (_U_(0x1) << ICM_CTRL_DISABLE_Pos)
+#define ICM_CTRL_SWRST_Pos 2 /**< \brief (ICM_CTRL) Software Reset */
+#define ICM_CTRL_SWRST (_U_(0x1) << ICM_CTRL_SWRST_Pos)
+#define ICM_CTRL_REHASH_Pos 4 /**< \brief (ICM_CTRL) Recompute Internal Hash */
+#define ICM_CTRL_REHASH_Msk (_U_(0xF) << ICM_CTRL_REHASH_Pos)
+#define ICM_CTRL_REHASH(value) (ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))
+#define ICM_CTRL_RMDIS_Pos 8 /**< \brief (ICM_CTRL) Region Monitoring Disable */
+#define ICM_CTRL_RMDIS_Msk (_U_(0xF) << ICM_CTRL_RMDIS_Pos)
+#define ICM_CTRL_RMDIS(value) (ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))
+#define ICM_CTRL_RMEN_Pos 12 /**< \brief (ICM_CTRL) Region Monitoring Enable */
+#define ICM_CTRL_RMEN_Msk (_U_(0xF) << ICM_CTRL_RMEN_Pos)
+#define ICM_CTRL_RMEN(value) (ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))
+#define ICM_CTRL_MASK _U_(0x0000FFF7) /**< \brief (ICM_CTRL) MASK Register */
+
+/* -------- ICM_SR : (ICM Offset: 0x08) (R/ 32) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ENABLE:1; /*!< bit: 0 ICM Controller Enable Register */
+ uint32_t :7; /*!< bit: 1.. 7 Reserved */
+ uint32_t RAWRMDIS:4; /*!< bit: 8..11 RAW Region Monitoring Disabled Status */
+ uint32_t RMDIS:4; /*!< bit: 12..15 Region Monitoring Disabled Status */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_SR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_SR_OFFSET 0x08 /**< \brief (ICM_SR offset) Status */
+#define ICM_SR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_SR reset_value) Status */
+
+#define ICM_SR_ENABLE_Pos 0 /**< \brief (ICM_SR) ICM Controller Enable Register */
+#define ICM_SR_ENABLE (_U_(0x1) << ICM_SR_ENABLE_Pos)
+#define ICM_SR_RAWRMDIS_Pos 8 /**< \brief (ICM_SR) RAW Region Monitoring Disabled Status */
+#define ICM_SR_RAWRMDIS_Msk (_U_(0xF) << ICM_SR_RAWRMDIS_Pos)
+#define ICM_SR_RAWRMDIS(value) (ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))
+#define ICM_SR_RMDIS_Pos 12 /**< \brief (ICM_SR) Region Monitoring Disabled Status */
+#define ICM_SR_RMDIS_Msk (_U_(0xF) << ICM_SR_RMDIS_Pos)
+#define ICM_SR_RMDIS(value) (ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))
+#define ICM_SR_MASK _U_(0x0000FF01) /**< \brief (ICM_SR) MASK Register */
+
+/* -------- ICM_IER : (ICM Offset: 0x10) ( /W 32) Interrupt Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed Interrupt Enable */
+ uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch Interrupt Enable */
+ uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error Interrupt Enable */
+ uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition detected Interrupt Enable */
+ uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition Detected Interrupt Enable */
+ uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Interrupt Disable */
+ uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Interrupt Enable */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_IER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_IER_OFFSET 0x10 /**< \brief (ICM_IER offset) Interrupt Enable */
+
+#define ICM_IER_RHC_Pos 0 /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */
+#define ICM_IER_RHC_Msk (_U_(0xF) << ICM_IER_RHC_Pos)
+#define ICM_IER_RHC(value) (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))
+#define ICM_IER_RDM_Pos 4 /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */
+#define ICM_IER_RDM_Msk (_U_(0xF) << ICM_IER_RDM_Pos)
+#define ICM_IER_RDM(value) (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))
+#define ICM_IER_RBE_Pos 8 /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */
+#define ICM_IER_RBE_Msk (_U_(0xF) << ICM_IER_RBE_Pos)
+#define ICM_IER_RBE(value) (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))
+#define ICM_IER_RWC_Pos 12 /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */
+#define ICM_IER_RWC_Msk (_U_(0xF) << ICM_IER_RWC_Pos)
+#define ICM_IER_RWC(value) (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))
+#define ICM_IER_REC_Pos 16 /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */
+#define ICM_IER_REC_Msk (_U_(0xF) << ICM_IER_REC_Pos)
+#define ICM_IER_REC(value) (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))
+#define ICM_IER_RSU_Pos 20 /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */
+#define ICM_IER_RSU_Msk (_U_(0xF) << ICM_IER_RSU_Pos)
+#define ICM_IER_RSU(value) (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))
+#define ICM_IER_URAD_Pos 24 /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */
+#define ICM_IER_URAD (_U_(0x1) << ICM_IER_URAD_Pos)
+#define ICM_IER_MASK _U_(0x01FFFFFF) /**< \brief (ICM_IER) MASK Register */
+
+/* -------- ICM_IDR : (ICM Offset: 0x14) ( /W 32) Interrupt Disable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed Interrupt Disable */
+ uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch Interrupt Disable */
+ uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error Interrupt Disable */
+ uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition Detected Interrupt Disable */
+ uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition detected Interrupt Disable */
+ uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Interrupt Disable */
+ uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Interrupt Disable */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_IDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_IDR_OFFSET 0x14 /**< \brief (ICM_IDR offset) Interrupt Disable */
+#define ICM_IDR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_IDR reset_value) Interrupt Disable */
+
+#define ICM_IDR_RHC_Pos 0 /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */
+#define ICM_IDR_RHC_Msk (_U_(0xF) << ICM_IDR_RHC_Pos)
+#define ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))
+#define ICM_IDR_RDM_Pos 4 /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */
+#define ICM_IDR_RDM_Msk (_U_(0xF) << ICM_IDR_RDM_Pos)
+#define ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))
+#define ICM_IDR_RBE_Pos 8 /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */
+#define ICM_IDR_RBE_Msk (_U_(0xF) << ICM_IDR_RBE_Pos)
+#define ICM_IDR_RBE(value) (ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))
+#define ICM_IDR_RWC_Pos 12 /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */
+#define ICM_IDR_RWC_Msk (_U_(0xF) << ICM_IDR_RWC_Pos)
+#define ICM_IDR_RWC(value) (ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))
+#define ICM_IDR_REC_Pos 16 /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */
+#define ICM_IDR_REC_Msk (_U_(0xF) << ICM_IDR_REC_Pos)
+#define ICM_IDR_REC(value) (ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))
+#define ICM_IDR_RSU_Pos 20 /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */
+#define ICM_IDR_RSU_Msk (_U_(0xF) << ICM_IDR_RSU_Pos)
+#define ICM_IDR_RSU(value) (ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))
+#define ICM_IDR_URAD_Pos 24 /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */
+#define ICM_IDR_URAD (_U_(0x1) << ICM_IDR_URAD_Pos)
+#define ICM_IDR_MASK _U_(0x01FFFFFF) /**< \brief (ICM_IDR) MASK Register */
+
+/* -------- ICM_IMR : (ICM Offset: 0x18) (R/ 32) Interrupt Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed Interrupt Mask */
+ uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch Interrupt Mask */
+ uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error Interrupt Mask */
+ uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition Detected Interrupt Mask */
+ uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition Detected Interrupt Mask */
+ uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Interrupt Mask */
+ uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Interrupt Mask */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_IMR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_IMR_OFFSET 0x18 /**< \brief (ICM_IMR offset) Interrupt Mask */
+#define ICM_IMR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_IMR reset_value) Interrupt Mask */
+
+#define ICM_IMR_RHC_Pos 0 /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */
+#define ICM_IMR_RHC_Msk (_U_(0xF) << ICM_IMR_RHC_Pos)
+#define ICM_IMR_RHC(value) (ICM_IMR_RHC_Msk & ((value) << ICM_IMR_RHC_Pos))
+#define ICM_IMR_RDM_Pos 4 /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */
+#define ICM_IMR_RDM_Msk (_U_(0xF) << ICM_IMR_RDM_Pos)
+#define ICM_IMR_RDM(value) (ICM_IMR_RDM_Msk & ((value) << ICM_IMR_RDM_Pos))
+#define ICM_IMR_RBE_Pos 8 /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */
+#define ICM_IMR_RBE_Msk (_U_(0xF) << ICM_IMR_RBE_Pos)
+#define ICM_IMR_RBE(value) (ICM_IMR_RBE_Msk & ((value) << ICM_IMR_RBE_Pos))
+#define ICM_IMR_RWC_Pos 12 /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */
+#define ICM_IMR_RWC_Msk (_U_(0xF) << ICM_IMR_RWC_Pos)
+#define ICM_IMR_RWC(value) (ICM_IMR_RWC_Msk & ((value) << ICM_IMR_RWC_Pos))
+#define ICM_IMR_REC_Pos 16 /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */
+#define ICM_IMR_REC_Msk (_U_(0xF) << ICM_IMR_REC_Pos)
+#define ICM_IMR_REC(value) (ICM_IMR_REC_Msk & ((value) << ICM_IMR_REC_Pos))
+#define ICM_IMR_RSU_Pos 20 /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */
+#define ICM_IMR_RSU_Msk (_U_(0xF) << ICM_IMR_RSU_Pos)
+#define ICM_IMR_RSU(value) (ICM_IMR_RSU_Msk & ((value) << ICM_IMR_RSU_Pos))
+#define ICM_IMR_URAD_Pos 24 /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */
+#define ICM_IMR_URAD (_U_(0x1) << ICM_IMR_URAD_Pos)
+#define ICM_IMR_MASK _U_(0x01FFFFFF) /**< \brief (ICM_IMR) MASK Register */
+
+/* -------- ICM_ISR : (ICM Offset: 0x1C) (R/ 32) Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed */
+ uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch */
+ uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error */
+ uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition Detected */
+ uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition Detected */
+ uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Detected */
+ uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Status */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_ISR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_ISR_OFFSET 0x1C /**< \brief (ICM_ISR offset) Interrupt Status */
+#define ICM_ISR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_ISR reset_value) Interrupt Status */
+
+#define ICM_ISR_RHC_Pos 0 /**< \brief (ICM_ISR) Region Hash Completed */
+#define ICM_ISR_RHC_Msk (_U_(0xF) << ICM_ISR_RHC_Pos)
+#define ICM_ISR_RHC(value) (ICM_ISR_RHC_Msk & ((value) << ICM_ISR_RHC_Pos))
+#define ICM_ISR_RDM_Pos 4 /**< \brief (ICM_ISR) Region Digest Mismatch */
+#define ICM_ISR_RDM_Msk (_U_(0xF) << ICM_ISR_RDM_Pos)
+#define ICM_ISR_RDM(value) (ICM_ISR_RDM_Msk & ((value) << ICM_ISR_RDM_Pos))
+#define ICM_ISR_RBE_Pos 8 /**< \brief (ICM_ISR) Region Bus Error */
+#define ICM_ISR_RBE_Msk (_U_(0xF) << ICM_ISR_RBE_Pos)
+#define ICM_ISR_RBE(value) (ICM_ISR_RBE_Msk & ((value) << ICM_ISR_RBE_Pos))
+#define ICM_ISR_RWC_Pos 12 /**< \brief (ICM_ISR) Region Wrap Condition Detected */
+#define ICM_ISR_RWC_Msk (_U_(0xF) << ICM_ISR_RWC_Pos)
+#define ICM_ISR_RWC(value) (ICM_ISR_RWC_Msk & ((value) << ICM_ISR_RWC_Pos))
+#define ICM_ISR_REC_Pos 16 /**< \brief (ICM_ISR) Region End bit Condition Detected */
+#define ICM_ISR_REC_Msk (_U_(0xF) << ICM_ISR_REC_Pos)
+#define ICM_ISR_REC(value) (ICM_ISR_REC_Msk & ((value) << ICM_ISR_REC_Pos))
+#define ICM_ISR_RSU_Pos 20 /**< \brief (ICM_ISR) Region Status Updated Detected */
+#define ICM_ISR_RSU_Msk (_U_(0xF) << ICM_ISR_RSU_Pos)
+#define ICM_ISR_RSU(value) (ICM_ISR_RSU_Msk & ((value) << ICM_ISR_RSU_Pos))
+#define ICM_ISR_URAD_Pos 24 /**< \brief (ICM_ISR) Undefined Register Access Detection Status */
+#define ICM_ISR_URAD (_U_(0x1) << ICM_ISR_URAD_Pos)
+#define ICM_ISR_MASK _U_(0x01FFFFFF) /**< \brief (ICM_ISR) MASK Register */
+
+/* -------- ICM_UASR : (ICM Offset: 0x20) (R/ 32) Undefined Access Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t URAT:3; /*!< bit: 0.. 2 Undefined Register Access Trace */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_UASR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_UASR_OFFSET 0x20 /**< \brief (ICM_UASR offset) Undefined Access Status */
+#define ICM_UASR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_UASR reset_value) Undefined Access Status */
+
+#define ICM_UASR_URAT_Pos 0 /**< \brief (ICM_UASR) Undefined Register Access Trace */
+#define ICM_UASR_URAT_Msk (_U_(0x7) << ICM_UASR_URAT_Pos)
+#define ICM_UASR_URAT(value) (ICM_UASR_URAT_Msk & ((value) << ICM_UASR_URAT_Pos))
+#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val _U_(0x0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded */
+#define ICM_UASR_URAT_CFG_MODIFIED_Val _U_(0x1) /**< \brief (ICM_UASR) CFG modified during active monitoring */
+#define ICM_UASR_URAT_DSCR_MODIFIED_Val _U_(0x2) /**< \brief (ICM_UASR) DSCR modified during active monitoring */
+#define ICM_UASR_URAT_HASH_MODIFIED_Val _U_(0x3) /**< \brief (ICM_UASR) HASH modified during active monitoring */
+#define ICM_UASR_URAT_READ_ACCESS_Val _U_(0x4) /**< \brief (ICM_UASR) Write-only register read access */
+#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val << ICM_UASR_URAT_Pos)
+#define ICM_UASR_URAT_CFG_MODIFIED (ICM_UASR_URAT_CFG_MODIFIED_Val << ICM_UASR_URAT_Pos)
+#define ICM_UASR_URAT_DSCR_MODIFIED (ICM_UASR_URAT_DSCR_MODIFIED_Val << ICM_UASR_URAT_Pos)
+#define ICM_UASR_URAT_HASH_MODIFIED (ICM_UASR_URAT_HASH_MODIFIED_Val << ICM_UASR_URAT_Pos)
+#define ICM_UASR_URAT_READ_ACCESS (ICM_UASR_URAT_READ_ACCESS_Val << ICM_UASR_URAT_Pos)
+#define ICM_UASR_MASK _U_(0x00000007) /**< \brief (ICM_UASR) MASK Register */
+
+/* -------- ICM_DSCR : (ICM Offset: 0x30) (R/W 32) Region Descriptor Area Start Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :6; /*!< bit: 0.. 5 Reserved */
+ uint32_t DASA:26; /*!< bit: 6..31 Descriptor Area Start Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_DSCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_DSCR_OFFSET 0x30 /**< \brief (ICM_DSCR offset) Region Descriptor Area Start Address */
+#define ICM_DSCR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_DSCR reset_value) Region Descriptor Area Start Address */
+
+#define ICM_DSCR_DASA_Pos 6 /**< \brief (ICM_DSCR) Descriptor Area Start Address */
+#define ICM_DSCR_DASA_Msk (_U_(0x3FFFFFF) << ICM_DSCR_DASA_Pos)
+#define ICM_DSCR_DASA(value) (ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))
+#define ICM_DSCR_MASK _U_(0xFFFFFFC0) /**< \brief (ICM_DSCR) MASK Register */
+
+/* -------- ICM_HASH : (ICM Offset: 0x34) (R/W 32) Region Hash Area Start Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :7; /*!< bit: 0.. 6 Reserved */
+ uint32_t HASA:25; /*!< bit: 7..31 Hash Area Start Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_HASH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_HASH_OFFSET 0x34 /**< \brief (ICM_HASH offset) Region Hash Area Start Address */
+#define ICM_HASH_RESETVALUE _U_(0x00000000) /**< \brief (ICM_HASH reset_value) Region Hash Area Start Address */
+
+#define ICM_HASH_HASA_Pos 7 /**< \brief (ICM_HASH) Hash Area Start Address */
+#define ICM_HASH_HASA_Msk (_U_(0x1FFFFFF) << ICM_HASH_HASA_Pos)
+#define ICM_HASH_HASA(value) (ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))
+#define ICM_HASH_MASK _U_(0xFFFFFF80) /**< \brief (ICM_HASH) MASK Register */
+
+/* -------- ICM_UIHVAL : (ICM Offset: 0x38) ( /W 32) User Initial Hash Value n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t VAL:32; /*!< bit: 0..31 Initial Hash Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_UIHVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_UIHVAL_OFFSET 0x38 /**< \brief (ICM_UIHVAL offset) User Initial Hash Value n */
+#define ICM_UIHVAL_RESETVALUE _U_(0x00000000) /**< \brief (ICM_UIHVAL reset_value) User Initial Hash Value n */
+
+#define ICM_UIHVAL_VAL_Pos 0 /**< \brief (ICM_UIHVAL) Initial Hash Value */
+#define ICM_UIHVAL_VAL_Msk (_U_(0xFFFFFFFF) << ICM_UIHVAL_VAL_Pos)
+#define ICM_UIHVAL_VAL(value) (ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))
+#define ICM_UIHVAL_MASK _U_(0xFFFFFFFF) /**< \brief (ICM_UIHVAL) MASK Register */
+
+/* -------- ICM_RADDR : (ICM Offset: 0x00) (R/W 32) Region Start Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} ICM_RADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_RADDR_OFFSET 0x00 /**< \brief (ICM_RADDR offset) Region Start Address */
+#define ICM_RADDR_MASK _U_(0xFFFFFFFF) /**< \brief (ICM_RADDR) MASK Register */
+
+/* -------- ICM_RCFG : (ICM Offset: 0x04) (R/W 32) Region Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CDWBN:1; /*!< bit: 0 Compare Digest Write Back */
+ uint32_t WRAP:1; /*!< bit: 1 Region Wrap */
+ uint32_t EOM:1; /*!< bit: 2 End of Monitoring */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RHIEN:1; /*!< bit: 4 Region Hash Interrupt Enable */
+ uint32_t DMIEN:1; /*!< bit: 5 Region Digest Mismatch Interrupt Enable */
+ uint32_t BEIEN:1; /*!< bit: 6 Region Bus Error Interrupt Enable */
+ uint32_t WCIEN:1; /*!< bit: 7 Region Wrap Condition Detected Interrupt Enable */
+ uint32_t ECIEN:1; /*!< bit: 8 Region End bit Condition detected Interrupt Enable */
+ uint32_t SUIEN:1; /*!< bit: 9 Region Status Updated Interrupt Enable */
+ uint32_t PROCDLY:1; /*!< bit: 10 SHA Processing Delay */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t ALGO:3; /*!< bit: 12..14 SHA Algorithm */
+ uint32_t :9; /*!< bit: 15..23 Reserved */
+ uint32_t MRPROT:6; /*!< bit: 24..29 Memory Region AHB Protection */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_RCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_RCFG_OFFSET 0x04 /**< \brief (ICM_RCFG offset) Region Configuration */
+#define ICM_RCFG_RESETVALUE _U_(0x00000000) /**< \brief (ICM_RCFG reset_value) Region Configuration */
+
+#define ICM_RCFG_CDWBN_Pos 0 /**< \brief (ICM_RCFG) Compare Digest Write Back */
+#define ICM_RCFG_CDWBN (_U_(0x1) << ICM_RCFG_CDWBN_Pos)
+#define ICM_RCFG_CDWBN_WRBA_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_CDWBN_COMP_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_CDWBN_WRBA (ICM_RCFG_CDWBN_WRBA_Val << ICM_RCFG_CDWBN_Pos)
+#define ICM_RCFG_CDWBN_COMP (ICM_RCFG_CDWBN_COMP_Val << ICM_RCFG_CDWBN_Pos)
+#define ICM_RCFG_WRAP_Pos 1 /**< \brief (ICM_RCFG) Region Wrap */
+#define ICM_RCFG_WRAP (_U_(0x1) << ICM_RCFG_WRAP_Pos)
+#define ICM_RCFG_WRAP_NO_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_WRAP_YES_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_WRAP_NO (ICM_RCFG_WRAP_NO_Val << ICM_RCFG_WRAP_Pos)
+#define ICM_RCFG_WRAP_YES (ICM_RCFG_WRAP_YES_Val << ICM_RCFG_WRAP_Pos)
+#define ICM_RCFG_EOM_Pos 2 /**< \brief (ICM_RCFG) End of Monitoring */
+#define ICM_RCFG_EOM (_U_(0x1) << ICM_RCFG_EOM_Pos)
+#define ICM_RCFG_EOM_NO_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_EOM_YES_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_EOM_NO (ICM_RCFG_EOM_NO_Val << ICM_RCFG_EOM_Pos)
+#define ICM_RCFG_EOM_YES (ICM_RCFG_EOM_YES_Val << ICM_RCFG_EOM_Pos)
+#define ICM_RCFG_RHIEN_Pos 4 /**< \brief (ICM_RCFG) Region Hash Interrupt Enable */
+#define ICM_RCFG_RHIEN (_U_(0x1) << ICM_RCFG_RHIEN_Pos)
+#define ICM_RCFG_RHIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_RHIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_RHIEN_EN (ICM_RCFG_RHIEN_EN_Val << ICM_RCFG_RHIEN_Pos)
+#define ICM_RCFG_RHIEN_DIS (ICM_RCFG_RHIEN_DIS_Val << ICM_RCFG_RHIEN_Pos)
+#define ICM_RCFG_DMIEN_Pos 5 /**< \brief (ICM_RCFG) Region Digest Mismatch Interrupt Enable */
+#define ICM_RCFG_DMIEN (_U_(0x1) << ICM_RCFG_DMIEN_Pos)
+#define ICM_RCFG_DMIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_DMIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_DMIEN_EN (ICM_RCFG_DMIEN_EN_Val << ICM_RCFG_DMIEN_Pos)
+#define ICM_RCFG_DMIEN_DIS (ICM_RCFG_DMIEN_DIS_Val << ICM_RCFG_DMIEN_Pos)
+#define ICM_RCFG_BEIEN_Pos 6 /**< \brief (ICM_RCFG) Region Bus Error Interrupt Enable */
+#define ICM_RCFG_BEIEN (_U_(0x1) << ICM_RCFG_BEIEN_Pos)
+#define ICM_RCFG_BEIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_BEIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_BEIEN_EN (ICM_RCFG_BEIEN_EN_Val << ICM_RCFG_BEIEN_Pos)
+#define ICM_RCFG_BEIEN_DIS (ICM_RCFG_BEIEN_DIS_Val << ICM_RCFG_BEIEN_Pos)
+#define ICM_RCFG_WCIEN_Pos 7 /**< \brief (ICM_RCFG) Region Wrap Condition Detected Interrupt Enable */
+#define ICM_RCFG_WCIEN (_U_(0x1) << ICM_RCFG_WCIEN_Pos)
+#define ICM_RCFG_WCIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_WCIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_WCIEN_EN (ICM_RCFG_WCIEN_EN_Val << ICM_RCFG_WCIEN_Pos)
+#define ICM_RCFG_WCIEN_DIS (ICM_RCFG_WCIEN_DIS_Val << ICM_RCFG_WCIEN_Pos)
+#define ICM_RCFG_ECIEN_Pos 8 /**< \brief (ICM_RCFG) Region End bit Condition detected Interrupt Enable */
+#define ICM_RCFG_ECIEN (_U_(0x1) << ICM_RCFG_ECIEN_Pos)
+#define ICM_RCFG_ECIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_ECIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_ECIEN_EN (ICM_RCFG_ECIEN_EN_Val << ICM_RCFG_ECIEN_Pos)
+#define ICM_RCFG_ECIEN_DIS (ICM_RCFG_ECIEN_DIS_Val << ICM_RCFG_ECIEN_Pos)
+#define ICM_RCFG_SUIEN_Pos 9 /**< \brief (ICM_RCFG) Region Status Updated Interrupt Enable */
+#define ICM_RCFG_SUIEN (_U_(0x1) << ICM_RCFG_SUIEN_Pos)
+#define ICM_RCFG_SUIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_SUIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_SUIEN_EN (ICM_RCFG_SUIEN_EN_Val << ICM_RCFG_SUIEN_Pos)
+#define ICM_RCFG_SUIEN_DIS (ICM_RCFG_SUIEN_DIS_Val << ICM_RCFG_SUIEN_Pos)
+#define ICM_RCFG_PROCDLY_Pos 10 /**< \brief (ICM_RCFG) SHA Processing Delay */
+#define ICM_RCFG_PROCDLY (_U_(0x1) << ICM_RCFG_PROCDLY_Pos)
+#define ICM_RCFG_PROCDLY_SHORT_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_PROCDLY_LONG_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_PROCDLY_SHORT (ICM_RCFG_PROCDLY_SHORT_Val << ICM_RCFG_PROCDLY_Pos)
+#define ICM_RCFG_PROCDLY_LONG (ICM_RCFG_PROCDLY_LONG_Val << ICM_RCFG_PROCDLY_Pos)
+#define ICM_RCFG_ALGO_Pos 12 /**< \brief (ICM_RCFG) SHA Algorithm */
+#define ICM_RCFG_ALGO_Msk (_U_(0x7) << ICM_RCFG_ALGO_Pos)
+#define ICM_RCFG_ALGO(value) (ICM_RCFG_ALGO_Msk & ((value) << ICM_RCFG_ALGO_Pos))
+#define ICM_RCFG_MRPROT_Pos 24 /**< \brief (ICM_RCFG) Memory Region AHB Protection */
+#define ICM_RCFG_MRPROT_Msk (_U_(0x3F) << ICM_RCFG_MRPROT_Pos)
+#define ICM_RCFG_MRPROT(value) (ICM_RCFG_MRPROT_Msk & ((value) << ICM_RCFG_MRPROT_Pos))
+#define ICM_RCFG_MASK _U_(0x3F0077F7) /**< \brief (ICM_RCFG) MASK Register */
+
+/* -------- ICM_RCTRL : (ICM Offset: 0x08) (R/W 32) Region Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TRSIZE:16; /*!< bit: 0..15 Transfer Size */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_RCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_RCTRL_OFFSET 0x08 /**< \brief (ICM_RCTRL offset) Region Control */
+
+#define ICM_RCTRL_TRSIZE_Pos 0 /**< \brief (ICM_RCTRL) Transfer Size */
+#define ICM_RCTRL_TRSIZE_Msk (_U_(0xFFFF) << ICM_RCTRL_TRSIZE_Pos)
+#define ICM_RCTRL_TRSIZE(value) (ICM_RCTRL_TRSIZE_Msk & ((value) << ICM_RCTRL_TRSIZE_Pos))
+#define ICM_RCTRL_MASK _U_(0x0000FFFF) /**< \brief (ICM_RCTRL) MASK Register */
+
+/* -------- ICM_RNEXT : (ICM Offset: 0x0C) (R/W 32) Region Next Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} ICM_RNEXT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_RNEXT_OFFSET 0x0C /**< \brief (ICM_RNEXT offset) Region Next Address */
+#define ICM_RNEXT_MASK _U_(0xFFFFFFFF) /**< \brief (ICM_RNEXT) MASK Register */
+
+/** \brief ICM APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO ICM_CFG_Type CFG; /**< \brief Offset: 0x00 (R/W 32) Configuration */
+ __O ICM_CTRL_Type CTRL; /**< \brief Offset: 0x04 ( /W 32) Control */
+ __I ICM_SR_Type SR; /**< \brief Offset: 0x08 (R/ 32) Status */
+ RoReg8 Reserved1[0x4];
+ __O ICM_IER_Type IER; /**< \brief Offset: 0x10 ( /W 32) Interrupt Enable */
+ __O ICM_IDR_Type IDR; /**< \brief Offset: 0x14 ( /W 32) Interrupt Disable */
+ __I ICM_IMR_Type IMR; /**< \brief Offset: 0x18 (R/ 32) Interrupt Mask */
+ __I ICM_ISR_Type ISR; /**< \brief Offset: 0x1C (R/ 32) Interrupt Status */
+ __I ICM_UASR_Type UASR; /**< \brief Offset: 0x20 (R/ 32) Undefined Access Status */
+ RoReg8 Reserved2[0xC];
+ __IO ICM_DSCR_Type DSCR; /**< \brief Offset: 0x30 (R/W 32) Region Descriptor Area Start Address */
+ __IO ICM_HASH_Type HASH; /**< \brief Offset: 0x34 (R/W 32) Region Hash Area Start Address */
+ __O ICM_UIHVAL_Type UIHVAL[8]; /**< \brief Offset: 0x38 ( /W 32) User Initial Hash Value n */
+} Icm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief ICM Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO ICM_RADDR_Type RADDR; /**< \brief Offset: 0x00 (R/W 32) Region Start Address */
+ __IO ICM_RCFG_Type RCFG; /**< \brief Offset: 0x04 (R/W 32) Region Configuration */
+ __IO ICM_RCTRL_Type RCTRL; /**< \brief Offset: 0x08 (R/W 32) Region Control */
+ __IO ICM_RNEXT_Type RNEXT; /**< \brief Offset: 0x0C (R/W 32) Region Next Address */
+} IcmDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_ICM_DESCRIPTOR
+
+/*@}*/
+
+#endif /* _SAME54_ICM_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/mclk.h b/sysmoOCTSIM/include/component/mclk.h
index d4cf0c4..4bb8b84 100644
--- a/sysmoOCTSIM/include/component/mclk.h
+++ b/sysmoOCTSIM/include/component/mclk.h
@@ -1,482 +1,482 @@
-/**
- * \file
- *
- * \brief Component description for MCLK
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_MCLK_COMPONENT_
-#define _SAME54_MCLK_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR MCLK */
-/* ========================================================================== */
-/** \addtogroup SAME54_MCLK Main Clock */
-/*@{*/
-
-#define MCLK_U2408
-#define REV_MCLK 0x100
-
-/* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W 8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} MCLK_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_INTENCLR_OFFSET 0x01 /**< \brief (MCLK_INTENCLR offset) Interrupt Enable Clear */
-#define MCLK_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (MCLK_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define MCLK_INTENCLR_CKRDY_Pos 0 /**< \brief (MCLK_INTENCLR) Clock Ready Interrupt Enable */
-#define MCLK_INTENCLR_CKRDY (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos)
-#define MCLK_INTENCLR_MASK _U_(0x01) /**< \brief (MCLK_INTENCLR) MASK Register */
-
-/* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W 8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} MCLK_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_INTENSET_OFFSET 0x02 /**< \brief (MCLK_INTENSET offset) Interrupt Enable Set */
-#define MCLK_INTENSET_RESETVALUE _U_(0x00) /**< \brief (MCLK_INTENSET reset_value) Interrupt Enable Set */
-
-#define MCLK_INTENSET_CKRDY_Pos 0 /**< \brief (MCLK_INTENSET) Clock Ready Interrupt Enable */
-#define MCLK_INTENSET_CKRDY (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos)
-#define MCLK_INTENSET_MASK _U_(0x01) /**< \brief (MCLK_INTENSET) MASK Register */
-
-/* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W 8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
- __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} MCLK_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_INTFLAG_OFFSET 0x03 /**< \brief (MCLK_INTFLAG offset) Interrupt Flag Status and Clear */
-#define MCLK_INTFLAG_RESETVALUE _U_(0x01) /**< \brief (MCLK_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define MCLK_INTFLAG_CKRDY_Pos 0 /**< \brief (MCLK_INTFLAG) Clock Ready */
-#define MCLK_INTFLAG_CKRDY (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos)
-#define MCLK_INTFLAG_MASK _U_(0x01) /**< \brief (MCLK_INTFLAG) MASK Register */
-
-/* -------- MCLK_HSDIV : (MCLK Offset: 0x04) (R/ 8) HS Clock Division -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DIV:8; /*!< bit: 0.. 7 CPU Clock Division Factor */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} MCLK_HSDIV_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_HSDIV_OFFSET 0x04 /**< \brief (MCLK_HSDIV offset) HS Clock Division */
-#define MCLK_HSDIV_RESETVALUE _U_(0x01) /**< \brief (MCLK_HSDIV reset_value) HS Clock Division */
-
-#define MCLK_HSDIV_DIV_Pos 0 /**< \brief (MCLK_HSDIV) CPU Clock Division Factor */
-#define MCLK_HSDIV_DIV_Msk (_U_(0xFF) << MCLK_HSDIV_DIV_Pos)
-#define MCLK_HSDIV_DIV(value) (MCLK_HSDIV_DIV_Msk & ((value) << MCLK_HSDIV_DIV_Pos))
-#define MCLK_HSDIV_DIV_DIV1_Val _U_(0x1) /**< \brief (MCLK_HSDIV) Divide by 1 */
-#define MCLK_HSDIV_DIV_DIV1 (MCLK_HSDIV_DIV_DIV1_Val << MCLK_HSDIV_DIV_Pos)
-#define MCLK_HSDIV_MASK _U_(0xFF) /**< \brief (MCLK_HSDIV) MASK Register */
-
-/* -------- MCLK_CPUDIV : (MCLK Offset: 0x05) (R/W 8) CPU Clock Division -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DIV:8; /*!< bit: 0.. 7 Low-Power Clock Division Factor */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} MCLK_CPUDIV_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_CPUDIV_OFFSET 0x05 /**< \brief (MCLK_CPUDIV offset) CPU Clock Division */
-#define MCLK_CPUDIV_RESETVALUE _U_(0x01) /**< \brief (MCLK_CPUDIV reset_value) CPU Clock Division */
-
-#define MCLK_CPUDIV_DIV_Pos 0 /**< \brief (MCLK_CPUDIV) Low-Power Clock Division Factor */
-#define MCLK_CPUDIV_DIV_Msk (_U_(0xFF) << MCLK_CPUDIV_DIV_Pos)
-#define MCLK_CPUDIV_DIV(value) (MCLK_CPUDIV_DIV_Msk & ((value) << MCLK_CPUDIV_DIV_Pos))
-#define MCLK_CPUDIV_DIV_DIV1_Val _U_(0x1) /**< \brief (MCLK_CPUDIV) Divide by 1 */
-#define MCLK_CPUDIV_DIV_DIV2_Val _U_(0x2) /**< \brief (MCLK_CPUDIV) Divide by 2 */
-#define MCLK_CPUDIV_DIV_DIV4_Val _U_(0x4) /**< \brief (MCLK_CPUDIV) Divide by 4 */
-#define MCLK_CPUDIV_DIV_DIV8_Val _U_(0x8) /**< \brief (MCLK_CPUDIV) Divide by 8 */
-#define MCLK_CPUDIV_DIV_DIV16_Val _U_(0x10) /**< \brief (MCLK_CPUDIV) Divide by 16 */
-#define MCLK_CPUDIV_DIV_DIV32_Val _U_(0x20) /**< \brief (MCLK_CPUDIV) Divide by 32 */
-#define MCLK_CPUDIV_DIV_DIV64_Val _U_(0x40) /**< \brief (MCLK_CPUDIV) Divide by 64 */
-#define MCLK_CPUDIV_DIV_DIV128_Val _U_(0x80) /**< \brief (MCLK_CPUDIV) Divide by 128 */
-#define MCLK_CPUDIV_DIV_DIV1 (MCLK_CPUDIV_DIV_DIV1_Val << MCLK_CPUDIV_DIV_Pos)
-#define MCLK_CPUDIV_DIV_DIV2 (MCLK_CPUDIV_DIV_DIV2_Val << MCLK_CPUDIV_DIV_Pos)
-#define MCLK_CPUDIV_DIV_DIV4 (MCLK_CPUDIV_DIV_DIV4_Val << MCLK_CPUDIV_DIV_Pos)
-#define MCLK_CPUDIV_DIV_DIV8 (MCLK_CPUDIV_DIV_DIV8_Val << MCLK_CPUDIV_DIV_Pos)
-#define MCLK_CPUDIV_DIV_DIV16 (MCLK_CPUDIV_DIV_DIV16_Val << MCLK_CPUDIV_DIV_Pos)
-#define MCLK_CPUDIV_DIV_DIV32 (MCLK_CPUDIV_DIV_DIV32_Val << MCLK_CPUDIV_DIV_Pos)
-#define MCLK_CPUDIV_DIV_DIV64 (MCLK_CPUDIV_DIV_DIV64_Val << MCLK_CPUDIV_DIV_Pos)
-#define MCLK_CPUDIV_DIV_DIV128 (MCLK_CPUDIV_DIV_DIV128_Val << MCLK_CPUDIV_DIV_Pos)
-#define MCLK_CPUDIV_MASK _U_(0xFF) /**< \brief (MCLK_CPUDIV) MASK Register */
-
-/* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
- uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
- uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
- uint32_t HPB3_:1; /*!< bit: 3 HPB3 AHB Clock Mask */
- uint32_t DSU_:1; /*!< bit: 4 DSU AHB Clock Mask */
- uint32_t HMATRIX_:1; /*!< bit: 5 HMATRIX AHB Clock Mask */
- uint32_t NVMCTRL_:1; /*!< bit: 6 NVMCTRL AHB Clock Mask */
- uint32_t HSRAM_:1; /*!< bit: 7 HSRAM AHB Clock Mask */
- uint32_t CMCC_:1; /*!< bit: 8 CMCC AHB Clock Mask */
- uint32_t DMAC_:1; /*!< bit: 9 DMAC AHB Clock Mask */
- uint32_t USB_:1; /*!< bit: 10 USB AHB Clock Mask */
- uint32_t BKUPRAM_:1; /*!< bit: 11 BKUPRAM AHB Clock Mask */
- uint32_t PAC_:1; /*!< bit: 12 PAC AHB Clock Mask */
- uint32_t QSPI_:1; /*!< bit: 13 QSPI AHB Clock Mask */
- uint32_t GMAC_:1; /*!< bit: 14 GMAC AHB Clock Mask */
- uint32_t SDHC0_:1; /*!< bit: 15 SDHC0 AHB Clock Mask */
- uint32_t SDHC1_:1; /*!< bit: 16 SDHC1 AHB Clock Mask */
- uint32_t CAN0_:1; /*!< bit: 17 CAN0 AHB Clock Mask */
- uint32_t CAN1_:1; /*!< bit: 18 CAN1 AHB Clock Mask */
- uint32_t ICM_:1; /*!< bit: 19 ICM AHB Clock Mask */
- uint32_t PUKCC_:1; /*!< bit: 20 PUKCC AHB Clock Mask */
- uint32_t QSPI_2X_:1; /*!< bit: 21 QSPI_2X AHB Clock Mask */
- uint32_t NVMCTRL_SMEEPROM_:1; /*!< bit: 22 NVMCTRL_SMEEPROM AHB Clock Mask */
- uint32_t NVMCTRL_CACHE_:1; /*!< bit: 23 NVMCTRL_CACHE AHB Clock Mask */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} MCLK_AHBMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_AHBMASK_OFFSET 0x10 /**< \brief (MCLK_AHBMASK offset) AHB Mask */
-#define MCLK_AHBMASK_RESETVALUE _U_(0x00FFFFFF) /**< \brief (MCLK_AHBMASK reset_value) AHB Mask */
-
-#define MCLK_AHBMASK_HPB0_Pos 0 /**< \brief (MCLK_AHBMASK) HPB0 AHB Clock Mask */
-#define MCLK_AHBMASK_HPB0 (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos)
-#define MCLK_AHBMASK_HPB1_Pos 1 /**< \brief (MCLK_AHBMASK) HPB1 AHB Clock Mask */
-#define MCLK_AHBMASK_HPB1 (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos)
-#define MCLK_AHBMASK_HPB2_Pos 2 /**< \brief (MCLK_AHBMASK) HPB2 AHB Clock Mask */
-#define MCLK_AHBMASK_HPB2 (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos)
-#define MCLK_AHBMASK_HPB3_Pos 3 /**< \brief (MCLK_AHBMASK) HPB3 AHB Clock Mask */
-#define MCLK_AHBMASK_HPB3 (_U_(0x1) << MCLK_AHBMASK_HPB3_Pos)
-#define MCLK_AHBMASK_DSU_Pos 4 /**< \brief (MCLK_AHBMASK) DSU AHB Clock Mask */
-#define MCLK_AHBMASK_DSU (_U_(0x1) << MCLK_AHBMASK_DSU_Pos)
-#define MCLK_AHBMASK_HMATRIX_Pos 5 /**< \brief (MCLK_AHBMASK) HMATRIX AHB Clock Mask */
-#define MCLK_AHBMASK_HMATRIX (_U_(0x1) << MCLK_AHBMASK_HMATRIX_Pos)
-#define MCLK_AHBMASK_NVMCTRL_Pos 6 /**< \brief (MCLK_AHBMASK) NVMCTRL AHB Clock Mask */
-#define MCLK_AHBMASK_NVMCTRL (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos)
-#define MCLK_AHBMASK_HSRAM_Pos 7 /**< \brief (MCLK_AHBMASK) HSRAM AHB Clock Mask */
-#define MCLK_AHBMASK_HSRAM (_U_(0x1) << MCLK_AHBMASK_HSRAM_Pos)
-#define MCLK_AHBMASK_CMCC_Pos 8 /**< \brief (MCLK_AHBMASK) CMCC AHB Clock Mask */
-#define MCLK_AHBMASK_CMCC (_U_(0x1) << MCLK_AHBMASK_CMCC_Pos)
-#define MCLK_AHBMASK_DMAC_Pos 9 /**< \brief (MCLK_AHBMASK) DMAC AHB Clock Mask */
-#define MCLK_AHBMASK_DMAC (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos)
-#define MCLK_AHBMASK_USB_Pos 10 /**< \brief (MCLK_AHBMASK) USB AHB Clock Mask */
-#define MCLK_AHBMASK_USB (_U_(0x1) << MCLK_AHBMASK_USB_Pos)
-#define MCLK_AHBMASK_BKUPRAM_Pos 11 /**< \brief (MCLK_AHBMASK) BKUPRAM AHB Clock Mask */
-#define MCLK_AHBMASK_BKUPRAM (_U_(0x1) << MCLK_AHBMASK_BKUPRAM_Pos)
-#define MCLK_AHBMASK_PAC_Pos 12 /**< \brief (MCLK_AHBMASK) PAC AHB Clock Mask */
-#define MCLK_AHBMASK_PAC (_U_(0x1) << MCLK_AHBMASK_PAC_Pos)
-#define MCLK_AHBMASK_QSPI_Pos 13 /**< \brief (MCLK_AHBMASK) QSPI AHB Clock Mask */
-#define MCLK_AHBMASK_QSPI (_U_(0x1) << MCLK_AHBMASK_QSPI_Pos)
-#define MCLK_AHBMASK_GMAC_Pos 14 /**< \brief (MCLK_AHBMASK) GMAC AHB Clock Mask */
-#define MCLK_AHBMASK_GMAC (_U_(0x1) << MCLK_AHBMASK_GMAC_Pos)
-#define MCLK_AHBMASK_SDHC0_Pos 15 /**< \brief (MCLK_AHBMASK) SDHC0 AHB Clock Mask */
-#define MCLK_AHBMASK_SDHC0 (_U_(0x1) << MCLK_AHBMASK_SDHC0_Pos)
-#define MCLK_AHBMASK_SDHC1_Pos 16 /**< \brief (MCLK_AHBMASK) SDHC1 AHB Clock Mask */
-#define MCLK_AHBMASK_SDHC1 (_U_(0x1) << MCLK_AHBMASK_SDHC1_Pos)
-#define MCLK_AHBMASK_CAN0_Pos 17 /**< \brief (MCLK_AHBMASK) CAN0 AHB Clock Mask */
-#define MCLK_AHBMASK_CAN0 (_U_(0x1) << MCLK_AHBMASK_CAN0_Pos)
-#define MCLK_AHBMASK_CAN1_Pos 18 /**< \brief (MCLK_AHBMASK) CAN1 AHB Clock Mask */
-#define MCLK_AHBMASK_CAN1 (_U_(0x1) << MCLK_AHBMASK_CAN1_Pos)
-#define MCLK_AHBMASK_ICM_Pos 19 /**< \brief (MCLK_AHBMASK) ICM AHB Clock Mask */
-#define MCLK_AHBMASK_ICM (_U_(0x1) << MCLK_AHBMASK_ICM_Pos)
-#define MCLK_AHBMASK_PUKCC_Pos 20 /**< \brief (MCLK_AHBMASK) PUKCC AHB Clock Mask */
-#define MCLK_AHBMASK_PUKCC (_U_(0x1) << MCLK_AHBMASK_PUKCC_Pos)
-#define MCLK_AHBMASK_QSPI_2X_Pos 21 /**< \brief (MCLK_AHBMASK) QSPI_2X AHB Clock Mask */
-#define MCLK_AHBMASK_QSPI_2X (_U_(0x1) << MCLK_AHBMASK_QSPI_2X_Pos)
-#define MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos 22 /**< \brief (MCLK_AHBMASK) NVMCTRL_SMEEPROM AHB Clock Mask */
-#define MCLK_AHBMASK_NVMCTRL_SMEEPROM (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos)
-#define MCLK_AHBMASK_NVMCTRL_CACHE_Pos 23 /**< \brief (MCLK_AHBMASK) NVMCTRL_CACHE AHB Clock Mask */
-#define MCLK_AHBMASK_NVMCTRL_CACHE (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_CACHE_Pos)
-#define MCLK_AHBMASK_MASK _U_(0x00FFFFFF) /**< \brief (MCLK_AHBMASK) MASK Register */
-
-/* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t PAC_:1; /*!< bit: 0 PAC APB Clock Enable */
- uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
- uint32_t MCLK_:1; /*!< bit: 2 MCLK APB Clock Enable */
- uint32_t RSTC_:1; /*!< bit: 3 RSTC APB Clock Enable */
- uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL APB Clock Enable */
- uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL APB Clock Enable */
- uint32_t SUPC_:1; /*!< bit: 6 SUPC APB Clock Enable */
- uint32_t GCLK_:1; /*!< bit: 7 GCLK APB Clock Enable */
- uint32_t WDT_:1; /*!< bit: 8 WDT APB Clock Enable */
- uint32_t RTC_:1; /*!< bit: 9 RTC APB Clock Enable */
- uint32_t EIC_:1; /*!< bit: 10 EIC APB Clock Enable */
- uint32_t FREQM_:1; /*!< bit: 11 FREQM APB Clock Enable */
- uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 APB Clock Enable */
- uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 APB Clock Enable */
- uint32_t TC0_:1; /*!< bit: 14 TC0 APB Clock Enable */
- uint32_t TC1_:1; /*!< bit: 15 TC1 APB Clock Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} MCLK_APBAMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_APBAMASK_OFFSET 0x14 /**< \brief (MCLK_APBAMASK offset) APBA Mask */
-#define MCLK_APBAMASK_RESETVALUE _U_(0x000007FF) /**< \brief (MCLK_APBAMASK reset_value) APBA Mask */
-
-#define MCLK_APBAMASK_PAC_Pos 0 /**< \brief (MCLK_APBAMASK) PAC APB Clock Enable */
-#define MCLK_APBAMASK_PAC (_U_(0x1) << MCLK_APBAMASK_PAC_Pos)
-#define MCLK_APBAMASK_PM_Pos 1 /**< \brief (MCLK_APBAMASK) PM APB Clock Enable */
-#define MCLK_APBAMASK_PM (_U_(0x1) << MCLK_APBAMASK_PM_Pos)
-#define MCLK_APBAMASK_MCLK_Pos 2 /**< \brief (MCLK_APBAMASK) MCLK APB Clock Enable */
-#define MCLK_APBAMASK_MCLK (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos)
-#define MCLK_APBAMASK_RSTC_Pos 3 /**< \brief (MCLK_APBAMASK) RSTC APB Clock Enable */
-#define MCLK_APBAMASK_RSTC (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos)
-#define MCLK_APBAMASK_OSCCTRL_Pos 4 /**< \brief (MCLK_APBAMASK) OSCCTRL APB Clock Enable */
-#define MCLK_APBAMASK_OSCCTRL (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos)
-#define MCLK_APBAMASK_OSC32KCTRL_Pos 5 /**< \brief (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable */
-#define MCLK_APBAMASK_OSC32KCTRL (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos)
-#define MCLK_APBAMASK_SUPC_Pos 6 /**< \brief (MCLK_APBAMASK) SUPC APB Clock Enable */
-#define MCLK_APBAMASK_SUPC (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos)
-#define MCLK_APBAMASK_GCLK_Pos 7 /**< \brief (MCLK_APBAMASK) GCLK APB Clock Enable */
-#define MCLK_APBAMASK_GCLK (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos)
-#define MCLK_APBAMASK_WDT_Pos 8 /**< \brief (MCLK_APBAMASK) WDT APB Clock Enable */
-#define MCLK_APBAMASK_WDT (_U_(0x1) << MCLK_APBAMASK_WDT_Pos)
-#define MCLK_APBAMASK_RTC_Pos 9 /**< \brief (MCLK_APBAMASK) RTC APB Clock Enable */
-#define MCLK_APBAMASK_RTC (_U_(0x1) << MCLK_APBAMASK_RTC_Pos)
-#define MCLK_APBAMASK_EIC_Pos 10 /**< \brief (MCLK_APBAMASK) EIC APB Clock Enable */
-#define MCLK_APBAMASK_EIC (_U_(0x1) << MCLK_APBAMASK_EIC_Pos)
-#define MCLK_APBAMASK_FREQM_Pos 11 /**< \brief (MCLK_APBAMASK) FREQM APB Clock Enable */
-#define MCLK_APBAMASK_FREQM (_U_(0x1) << MCLK_APBAMASK_FREQM_Pos)
-#define MCLK_APBAMASK_SERCOM0_Pos 12 /**< \brief (MCLK_APBAMASK) SERCOM0 APB Clock Enable */
-#define MCLK_APBAMASK_SERCOM0 (_U_(0x1) << MCLK_APBAMASK_SERCOM0_Pos)
-#define MCLK_APBAMASK_SERCOM1_Pos 13 /**< \brief (MCLK_APBAMASK) SERCOM1 APB Clock Enable */
-#define MCLK_APBAMASK_SERCOM1 (_U_(0x1) << MCLK_APBAMASK_SERCOM1_Pos)
-#define MCLK_APBAMASK_TC0_Pos 14 /**< \brief (MCLK_APBAMASK) TC0 APB Clock Enable */
-#define MCLK_APBAMASK_TC0 (_U_(0x1) << MCLK_APBAMASK_TC0_Pos)
-#define MCLK_APBAMASK_TC1_Pos 15 /**< \brief (MCLK_APBAMASK) TC1 APB Clock Enable */
-#define MCLK_APBAMASK_TC1 (_U_(0x1) << MCLK_APBAMASK_TC1_Pos)
-#define MCLK_APBAMASK_MASK _U_(0x0000FFFF) /**< \brief (MCLK_APBAMASK) MASK Register */
-
-/* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t USB_:1; /*!< bit: 0 USB APB Clock Enable */
- uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
- uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t PORT_:1; /*!< bit: 4 PORT APB Clock Enable */
- uint32_t :1; /*!< bit: 5 Reserved */
- uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
- uint32_t EVSYS_:1; /*!< bit: 7 EVSYS APB Clock Enable */
- uint32_t :1; /*!< bit: 8 Reserved */
- uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 APB Clock Enable */
- uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 APB Clock Enable */
- uint32_t TCC0_:1; /*!< bit: 11 TCC0 APB Clock Enable */
- uint32_t TCC1_:1; /*!< bit: 12 TCC1 APB Clock Enable */
- uint32_t TC2_:1; /*!< bit: 13 TC2 APB Clock Enable */
- uint32_t TC3_:1; /*!< bit: 14 TC3 APB Clock Enable */
- uint32_t :1; /*!< bit: 15 Reserved */
- uint32_t RAMECC_:1; /*!< bit: 16 RAMECC APB Clock Enable */
- uint32_t :15; /*!< bit: 17..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} MCLK_APBBMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_APBBMASK_OFFSET 0x18 /**< \brief (MCLK_APBBMASK offset) APBB Mask */
-#define MCLK_APBBMASK_RESETVALUE _U_(0x00018056) /**< \brief (MCLK_APBBMASK reset_value) APBB Mask */
-
-#define MCLK_APBBMASK_USB_Pos 0 /**< \brief (MCLK_APBBMASK) USB APB Clock Enable */
-#define MCLK_APBBMASK_USB (_U_(0x1) << MCLK_APBBMASK_USB_Pos)
-#define MCLK_APBBMASK_DSU_Pos 1 /**< \brief (MCLK_APBBMASK) DSU APB Clock Enable */
-#define MCLK_APBBMASK_DSU (_U_(0x1) << MCLK_APBBMASK_DSU_Pos)
-#define MCLK_APBBMASK_NVMCTRL_Pos 2 /**< \brief (MCLK_APBBMASK) NVMCTRL APB Clock Enable */
-#define MCLK_APBBMASK_NVMCTRL (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos)
-#define MCLK_APBBMASK_PORT_Pos 4 /**< \brief (MCLK_APBBMASK) PORT APB Clock Enable */
-#define MCLK_APBBMASK_PORT (_U_(0x1) << MCLK_APBBMASK_PORT_Pos)
-#define MCLK_APBBMASK_HMATRIX_Pos 6 /**< \brief (MCLK_APBBMASK) HMATRIX APB Clock Enable */
-#define MCLK_APBBMASK_HMATRIX (_U_(0x1) << MCLK_APBBMASK_HMATRIX_Pos)
-#define MCLK_APBBMASK_EVSYS_Pos 7 /**< \brief (MCLK_APBBMASK) EVSYS APB Clock Enable */
-#define MCLK_APBBMASK_EVSYS (_U_(0x1) << MCLK_APBBMASK_EVSYS_Pos)
-#define MCLK_APBBMASK_SERCOM2_Pos 9 /**< \brief (MCLK_APBBMASK) SERCOM2 APB Clock Enable */
-#define MCLK_APBBMASK_SERCOM2 (_U_(0x1) << MCLK_APBBMASK_SERCOM2_Pos)
-#define MCLK_APBBMASK_SERCOM3_Pos 10 /**< \brief (MCLK_APBBMASK) SERCOM3 APB Clock Enable */
-#define MCLK_APBBMASK_SERCOM3 (_U_(0x1) << MCLK_APBBMASK_SERCOM3_Pos)
-#define MCLK_APBBMASK_TCC0_Pos 11 /**< \brief (MCLK_APBBMASK) TCC0 APB Clock Enable */
-#define MCLK_APBBMASK_TCC0 (_U_(0x1) << MCLK_APBBMASK_TCC0_Pos)
-#define MCLK_APBBMASK_TCC1_Pos 12 /**< \brief (MCLK_APBBMASK) TCC1 APB Clock Enable */
-#define MCLK_APBBMASK_TCC1 (_U_(0x1) << MCLK_APBBMASK_TCC1_Pos)
-#define MCLK_APBBMASK_TC2_Pos 13 /**< \brief (MCLK_APBBMASK) TC2 APB Clock Enable */
-#define MCLK_APBBMASK_TC2 (_U_(0x1) << MCLK_APBBMASK_TC2_Pos)
-#define MCLK_APBBMASK_TC3_Pos 14 /**< \brief (MCLK_APBBMASK) TC3 APB Clock Enable */
-#define MCLK_APBBMASK_TC3 (_U_(0x1) << MCLK_APBBMASK_TC3_Pos)
-#define MCLK_APBBMASK_RAMECC_Pos 16 /**< \brief (MCLK_APBBMASK) RAMECC APB Clock Enable */
-#define MCLK_APBBMASK_RAMECC (_U_(0x1) << MCLK_APBBMASK_RAMECC_Pos)
-#define MCLK_APBBMASK_MASK _U_(0x00017ED7) /**< \brief (MCLK_APBBMASK) MASK Register */
-
-/* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t GMAC_:1; /*!< bit: 2 GMAC APB Clock Enable */
- uint32_t TCC2_:1; /*!< bit: 3 TCC2 APB Clock Enable */
- uint32_t TCC3_:1; /*!< bit: 4 TCC3 APB Clock Enable */
- uint32_t TC4_:1; /*!< bit: 5 TC4 APB Clock Enable */
- uint32_t TC5_:1; /*!< bit: 6 TC5 APB Clock Enable */
- uint32_t PDEC_:1; /*!< bit: 7 PDEC APB Clock Enable */
- uint32_t AC_:1; /*!< bit: 8 AC APB Clock Enable */
- uint32_t AES_:1; /*!< bit: 9 AES APB Clock Enable */
- uint32_t TRNG_:1; /*!< bit: 10 TRNG APB Clock Enable */
- uint32_t ICM_:1; /*!< bit: 11 ICM APB Clock Enable */
- uint32_t :1; /*!< bit: 12 Reserved */
- uint32_t QSPI_:1; /*!< bit: 13 QSPI APB Clock Enable */
- uint32_t CCL_:1; /*!< bit: 14 CCL APB Clock Enable */
- uint32_t :17; /*!< bit: 15..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} MCLK_APBCMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_APBCMASK_OFFSET 0x1C /**< \brief (MCLK_APBCMASK offset) APBC Mask */
-#define MCLK_APBCMASK_RESETVALUE _U_(0x00002000) /**< \brief (MCLK_APBCMASK reset_value) APBC Mask */
-
-#define MCLK_APBCMASK_GMAC_Pos 2 /**< \brief (MCLK_APBCMASK) GMAC APB Clock Enable */
-#define MCLK_APBCMASK_GMAC (_U_(0x1) << MCLK_APBCMASK_GMAC_Pos)
-#define MCLK_APBCMASK_TCC2_Pos 3 /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable */
-#define MCLK_APBCMASK_TCC2 (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos)
-#define MCLK_APBCMASK_TCC3_Pos 4 /**< \brief (MCLK_APBCMASK) TCC3 APB Clock Enable */
-#define MCLK_APBCMASK_TCC3 (_U_(0x1) << MCLK_APBCMASK_TCC3_Pos)
-#define MCLK_APBCMASK_TC4_Pos 5 /**< \brief (MCLK_APBCMASK) TC4 APB Clock Enable */
-#define MCLK_APBCMASK_TC4 (_U_(0x1) << MCLK_APBCMASK_TC4_Pos)
-#define MCLK_APBCMASK_TC5_Pos 6 /**< \brief (MCLK_APBCMASK) TC5 APB Clock Enable */
-#define MCLK_APBCMASK_TC5 (_U_(0x1) << MCLK_APBCMASK_TC5_Pos)
-#define MCLK_APBCMASK_PDEC_Pos 7 /**< \brief (MCLK_APBCMASK) PDEC APB Clock Enable */
-#define MCLK_APBCMASK_PDEC (_U_(0x1) << MCLK_APBCMASK_PDEC_Pos)
-#define MCLK_APBCMASK_AC_Pos 8 /**< \brief (MCLK_APBCMASK) AC APB Clock Enable */
-#define MCLK_APBCMASK_AC (_U_(0x1) << MCLK_APBCMASK_AC_Pos)
-#define MCLK_APBCMASK_AES_Pos 9 /**< \brief (MCLK_APBCMASK) AES APB Clock Enable */
-#define MCLK_APBCMASK_AES (_U_(0x1) << MCLK_APBCMASK_AES_Pos)
-#define MCLK_APBCMASK_TRNG_Pos 10 /**< \brief (MCLK_APBCMASK) TRNG APB Clock Enable */
-#define MCLK_APBCMASK_TRNG (_U_(0x1) << MCLK_APBCMASK_TRNG_Pos)
-#define MCLK_APBCMASK_ICM_Pos 11 /**< \brief (MCLK_APBCMASK) ICM APB Clock Enable */
-#define MCLK_APBCMASK_ICM (_U_(0x1) << MCLK_APBCMASK_ICM_Pos)
-#define MCLK_APBCMASK_QSPI_Pos 13 /**< \brief (MCLK_APBCMASK) QSPI APB Clock Enable */
-#define MCLK_APBCMASK_QSPI (_U_(0x1) << MCLK_APBCMASK_QSPI_Pos)
-#define MCLK_APBCMASK_CCL_Pos 14 /**< \brief (MCLK_APBCMASK) CCL APB Clock Enable */
-#define MCLK_APBCMASK_CCL (_U_(0x1) << MCLK_APBCMASK_CCL_Pos)
-#define MCLK_APBCMASK_MASK _U_(0x00006FFC) /**< \brief (MCLK_APBCMASK) MASK Register */
-
-/* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 APB Clock Enable */
- uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Clock Enable */
- uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 APB Clock Enable */
- uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 APB Clock Enable */
- uint32_t TCC4_:1; /*!< bit: 4 TCC4 APB Clock Enable */
- uint32_t TC6_:1; /*!< bit: 5 TC6 APB Clock Enable */
- uint32_t TC7_:1; /*!< bit: 6 TC7 APB Clock Enable */
- uint32_t ADC0_:1; /*!< bit: 7 ADC0 APB Clock Enable */
- uint32_t ADC1_:1; /*!< bit: 8 ADC1 APB Clock Enable */
- uint32_t DAC_:1; /*!< bit: 9 DAC APB Clock Enable */
- uint32_t I2S_:1; /*!< bit: 10 I2S APB Clock Enable */
- uint32_t PCC_:1; /*!< bit: 11 PCC APB Clock Enable */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} MCLK_APBDMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_APBDMASK_OFFSET 0x20 /**< \brief (MCLK_APBDMASK offset) APBD Mask */
-#define MCLK_APBDMASK_RESETVALUE _U_(0x00000000) /**< \brief (MCLK_APBDMASK reset_value) APBD Mask */
-
-#define MCLK_APBDMASK_SERCOM4_Pos 0 /**< \brief (MCLK_APBDMASK) SERCOM4 APB Clock Enable */
-#define MCLK_APBDMASK_SERCOM4 (_U_(0x1) << MCLK_APBDMASK_SERCOM4_Pos)
-#define MCLK_APBDMASK_SERCOM5_Pos 1 /**< \brief (MCLK_APBDMASK) SERCOM5 APB Clock Enable */
-#define MCLK_APBDMASK_SERCOM5 (_U_(0x1) << MCLK_APBDMASK_SERCOM5_Pos)
-#define MCLK_APBDMASK_SERCOM6_Pos 2 /**< \brief (MCLK_APBDMASK) SERCOM6 APB Clock Enable */
-#define MCLK_APBDMASK_SERCOM6 (_U_(0x1) << MCLK_APBDMASK_SERCOM6_Pos)
-#define MCLK_APBDMASK_SERCOM7_Pos 3 /**< \brief (MCLK_APBDMASK) SERCOM7 APB Clock Enable */
-#define MCLK_APBDMASK_SERCOM7 (_U_(0x1) << MCLK_APBDMASK_SERCOM7_Pos)
-#define MCLK_APBDMASK_TCC4_Pos 4 /**< \brief (MCLK_APBDMASK) TCC4 APB Clock Enable */
-#define MCLK_APBDMASK_TCC4 (_U_(0x1) << MCLK_APBDMASK_TCC4_Pos)
-#define MCLK_APBDMASK_TC6_Pos 5 /**< \brief (MCLK_APBDMASK) TC6 APB Clock Enable */
-#define MCLK_APBDMASK_TC6 (_U_(0x1) << MCLK_APBDMASK_TC6_Pos)
-#define MCLK_APBDMASK_TC7_Pos 6 /**< \brief (MCLK_APBDMASK) TC7 APB Clock Enable */
-#define MCLK_APBDMASK_TC7 (_U_(0x1) << MCLK_APBDMASK_TC7_Pos)
-#define MCLK_APBDMASK_ADC0_Pos 7 /**< \brief (MCLK_APBDMASK) ADC0 APB Clock Enable */
-#define MCLK_APBDMASK_ADC0 (_U_(0x1) << MCLK_APBDMASK_ADC0_Pos)
-#define MCLK_APBDMASK_ADC1_Pos 8 /**< \brief (MCLK_APBDMASK) ADC1 APB Clock Enable */
-#define MCLK_APBDMASK_ADC1 (_U_(0x1) << MCLK_APBDMASK_ADC1_Pos)
-#define MCLK_APBDMASK_DAC_Pos 9 /**< \brief (MCLK_APBDMASK) DAC APB Clock Enable */
-#define MCLK_APBDMASK_DAC (_U_(0x1) << MCLK_APBDMASK_DAC_Pos)
-#define MCLK_APBDMASK_I2S_Pos 10 /**< \brief (MCLK_APBDMASK) I2S APB Clock Enable */
-#define MCLK_APBDMASK_I2S (_U_(0x1) << MCLK_APBDMASK_I2S_Pos)
-#define MCLK_APBDMASK_PCC_Pos 11 /**< \brief (MCLK_APBDMASK) PCC APB Clock Enable */
-#define MCLK_APBDMASK_PCC (_U_(0x1) << MCLK_APBDMASK_PCC_Pos)
-#define MCLK_APBDMASK_MASK _U_(0x00000FFF) /**< \brief (MCLK_APBDMASK) MASK Register */
-
-/** \brief MCLK hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- RoReg8 Reserved1[0x1];
- __IO MCLK_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x01 (R/W 8) Interrupt Enable Clear */
- __IO MCLK_INTENSET_Type INTENSET; /**< \brief Offset: 0x02 (R/W 8) Interrupt Enable Set */
- __IO MCLK_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x03 (R/W 8) Interrupt Flag Status and Clear */
- __I MCLK_HSDIV_Type HSDIV; /**< \brief Offset: 0x04 (R/ 8) HS Clock Division */
- __IO MCLK_CPUDIV_Type CPUDIV; /**< \brief Offset: 0x05 (R/W 8) CPU Clock Division */
- RoReg8 Reserved2[0xA];
- __IO MCLK_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x10 (R/W 32) AHB Mask */
- __IO MCLK_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x14 (R/W 32) APBA Mask */
- __IO MCLK_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x18 (R/W 32) APBB Mask */
- __IO MCLK_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x1C (R/W 32) APBC Mask */
- __IO MCLK_APBDMASK_Type APBDMASK; /**< \brief Offset: 0x20 (R/W 32) APBD Mask */
-} Mclk;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_MCLK_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for MCLK
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_MCLK_COMPONENT_
+#define _SAME54_MCLK_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR MCLK */
+/* ========================================================================== */
+/** \addtogroup SAME54_MCLK Main Clock */
+/*@{*/
+
+#define MCLK_U2408
+#define REV_MCLK 0x100
+
+/* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} MCLK_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_INTENCLR_OFFSET 0x01 /**< \brief (MCLK_INTENCLR offset) Interrupt Enable Clear */
+#define MCLK_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (MCLK_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define MCLK_INTENCLR_CKRDY_Pos 0 /**< \brief (MCLK_INTENCLR) Clock Ready Interrupt Enable */
+#define MCLK_INTENCLR_CKRDY (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos)
+#define MCLK_INTENCLR_MASK _U_(0x01) /**< \brief (MCLK_INTENCLR) MASK Register */
+
+/* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} MCLK_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_INTENSET_OFFSET 0x02 /**< \brief (MCLK_INTENSET offset) Interrupt Enable Set */
+#define MCLK_INTENSET_RESETVALUE _U_(0x00) /**< \brief (MCLK_INTENSET reset_value) Interrupt Enable Set */
+
+#define MCLK_INTENSET_CKRDY_Pos 0 /**< \brief (MCLK_INTENSET) Clock Ready Interrupt Enable */
+#define MCLK_INTENSET_CKRDY (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos)
+#define MCLK_INTENSET_MASK _U_(0x01) /**< \brief (MCLK_INTENSET) MASK Register */
+
+/* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} MCLK_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_INTFLAG_OFFSET 0x03 /**< \brief (MCLK_INTFLAG offset) Interrupt Flag Status and Clear */
+#define MCLK_INTFLAG_RESETVALUE _U_(0x01) /**< \brief (MCLK_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define MCLK_INTFLAG_CKRDY_Pos 0 /**< \brief (MCLK_INTFLAG) Clock Ready */
+#define MCLK_INTFLAG_CKRDY (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos)
+#define MCLK_INTFLAG_MASK _U_(0x01) /**< \brief (MCLK_INTFLAG) MASK Register */
+
+/* -------- MCLK_HSDIV : (MCLK Offset: 0x04) (R/ 8) HS Clock Division -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIV:8; /*!< bit: 0.. 7 CPU Clock Division Factor */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} MCLK_HSDIV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_HSDIV_OFFSET 0x04 /**< \brief (MCLK_HSDIV offset) HS Clock Division */
+#define MCLK_HSDIV_RESETVALUE _U_(0x01) /**< \brief (MCLK_HSDIV reset_value) HS Clock Division */
+
+#define MCLK_HSDIV_DIV_Pos 0 /**< \brief (MCLK_HSDIV) CPU Clock Division Factor */
+#define MCLK_HSDIV_DIV_Msk (_U_(0xFF) << MCLK_HSDIV_DIV_Pos)
+#define MCLK_HSDIV_DIV(value) (MCLK_HSDIV_DIV_Msk & ((value) << MCLK_HSDIV_DIV_Pos))
+#define MCLK_HSDIV_DIV_DIV1_Val _U_(0x1) /**< \brief (MCLK_HSDIV) Divide by 1 */
+#define MCLK_HSDIV_DIV_DIV1 (MCLK_HSDIV_DIV_DIV1_Val << MCLK_HSDIV_DIV_Pos)
+#define MCLK_HSDIV_MASK _U_(0xFF) /**< \brief (MCLK_HSDIV) MASK Register */
+
+/* -------- MCLK_CPUDIV : (MCLK Offset: 0x05) (R/W 8) CPU Clock Division -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIV:8; /*!< bit: 0.. 7 Low-Power Clock Division Factor */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} MCLK_CPUDIV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_CPUDIV_OFFSET 0x05 /**< \brief (MCLK_CPUDIV offset) CPU Clock Division */
+#define MCLK_CPUDIV_RESETVALUE _U_(0x01) /**< \brief (MCLK_CPUDIV reset_value) CPU Clock Division */
+
+#define MCLK_CPUDIV_DIV_Pos 0 /**< \brief (MCLK_CPUDIV) Low-Power Clock Division Factor */
+#define MCLK_CPUDIV_DIV_Msk (_U_(0xFF) << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV(value) (MCLK_CPUDIV_DIV_Msk & ((value) << MCLK_CPUDIV_DIV_Pos))
+#define MCLK_CPUDIV_DIV_DIV1_Val _U_(0x1) /**< \brief (MCLK_CPUDIV) Divide by 1 */
+#define MCLK_CPUDIV_DIV_DIV2_Val _U_(0x2) /**< \brief (MCLK_CPUDIV) Divide by 2 */
+#define MCLK_CPUDIV_DIV_DIV4_Val _U_(0x4) /**< \brief (MCLK_CPUDIV) Divide by 4 */
+#define MCLK_CPUDIV_DIV_DIV8_Val _U_(0x8) /**< \brief (MCLK_CPUDIV) Divide by 8 */
+#define MCLK_CPUDIV_DIV_DIV16_Val _U_(0x10) /**< \brief (MCLK_CPUDIV) Divide by 16 */
+#define MCLK_CPUDIV_DIV_DIV32_Val _U_(0x20) /**< \brief (MCLK_CPUDIV) Divide by 32 */
+#define MCLK_CPUDIV_DIV_DIV64_Val _U_(0x40) /**< \brief (MCLK_CPUDIV) Divide by 64 */
+#define MCLK_CPUDIV_DIV_DIV128_Val _U_(0x80) /**< \brief (MCLK_CPUDIV) Divide by 128 */
+#define MCLK_CPUDIV_DIV_DIV1 (MCLK_CPUDIV_DIV_DIV1_Val << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV2 (MCLK_CPUDIV_DIV_DIV2_Val << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV4 (MCLK_CPUDIV_DIV_DIV4_Val << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV8 (MCLK_CPUDIV_DIV_DIV8_Val << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV16 (MCLK_CPUDIV_DIV_DIV16_Val << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV32 (MCLK_CPUDIV_DIV_DIV32_Val << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV64 (MCLK_CPUDIV_DIV_DIV64_Val << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV128 (MCLK_CPUDIV_DIV_DIV128_Val << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_MASK _U_(0xFF) /**< \brief (MCLK_CPUDIV) MASK Register */
+
+/* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
+ uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
+ uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
+ uint32_t HPB3_:1; /*!< bit: 3 HPB3 AHB Clock Mask */
+ uint32_t DSU_:1; /*!< bit: 4 DSU AHB Clock Mask */
+ uint32_t HMATRIX_:1; /*!< bit: 5 HMATRIX AHB Clock Mask */
+ uint32_t NVMCTRL_:1; /*!< bit: 6 NVMCTRL AHB Clock Mask */
+ uint32_t HSRAM_:1; /*!< bit: 7 HSRAM AHB Clock Mask */
+ uint32_t CMCC_:1; /*!< bit: 8 CMCC AHB Clock Mask */
+ uint32_t DMAC_:1; /*!< bit: 9 DMAC AHB Clock Mask */
+ uint32_t USB_:1; /*!< bit: 10 USB AHB Clock Mask */
+ uint32_t BKUPRAM_:1; /*!< bit: 11 BKUPRAM AHB Clock Mask */
+ uint32_t PAC_:1; /*!< bit: 12 PAC AHB Clock Mask */
+ uint32_t QSPI_:1; /*!< bit: 13 QSPI AHB Clock Mask */
+ uint32_t GMAC_:1; /*!< bit: 14 GMAC AHB Clock Mask */
+ uint32_t SDHC0_:1; /*!< bit: 15 SDHC0 AHB Clock Mask */
+ uint32_t SDHC1_:1; /*!< bit: 16 SDHC1 AHB Clock Mask */
+ uint32_t CAN0_:1; /*!< bit: 17 CAN0 AHB Clock Mask */
+ uint32_t CAN1_:1; /*!< bit: 18 CAN1 AHB Clock Mask */
+ uint32_t ICM_:1; /*!< bit: 19 ICM AHB Clock Mask */
+ uint32_t PUKCC_:1; /*!< bit: 20 PUKCC AHB Clock Mask */
+ uint32_t QSPI_2X_:1; /*!< bit: 21 QSPI_2X AHB Clock Mask */
+ uint32_t NVMCTRL_SMEEPROM_:1; /*!< bit: 22 NVMCTRL_SMEEPROM AHB Clock Mask */
+ uint32_t NVMCTRL_CACHE_:1; /*!< bit: 23 NVMCTRL_CACHE AHB Clock Mask */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MCLK_AHBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_AHBMASK_OFFSET 0x10 /**< \brief (MCLK_AHBMASK offset) AHB Mask */
+#define MCLK_AHBMASK_RESETVALUE _U_(0x00FFFFFF) /**< \brief (MCLK_AHBMASK reset_value) AHB Mask */
+
+#define MCLK_AHBMASK_HPB0_Pos 0 /**< \brief (MCLK_AHBMASK) HPB0 AHB Clock Mask */
+#define MCLK_AHBMASK_HPB0 (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos)
+#define MCLK_AHBMASK_HPB1_Pos 1 /**< \brief (MCLK_AHBMASK) HPB1 AHB Clock Mask */
+#define MCLK_AHBMASK_HPB1 (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos)
+#define MCLK_AHBMASK_HPB2_Pos 2 /**< \brief (MCLK_AHBMASK) HPB2 AHB Clock Mask */
+#define MCLK_AHBMASK_HPB2 (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos)
+#define MCLK_AHBMASK_HPB3_Pos 3 /**< \brief (MCLK_AHBMASK) HPB3 AHB Clock Mask */
+#define MCLK_AHBMASK_HPB3 (_U_(0x1) << MCLK_AHBMASK_HPB3_Pos)
+#define MCLK_AHBMASK_DSU_Pos 4 /**< \brief (MCLK_AHBMASK) DSU AHB Clock Mask */
+#define MCLK_AHBMASK_DSU (_U_(0x1) << MCLK_AHBMASK_DSU_Pos)
+#define MCLK_AHBMASK_HMATRIX_Pos 5 /**< \brief (MCLK_AHBMASK) HMATRIX AHB Clock Mask */
+#define MCLK_AHBMASK_HMATRIX (_U_(0x1) << MCLK_AHBMASK_HMATRIX_Pos)
+#define MCLK_AHBMASK_NVMCTRL_Pos 6 /**< \brief (MCLK_AHBMASK) NVMCTRL AHB Clock Mask */
+#define MCLK_AHBMASK_NVMCTRL (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos)
+#define MCLK_AHBMASK_HSRAM_Pos 7 /**< \brief (MCLK_AHBMASK) HSRAM AHB Clock Mask */
+#define MCLK_AHBMASK_HSRAM (_U_(0x1) << MCLK_AHBMASK_HSRAM_Pos)
+#define MCLK_AHBMASK_CMCC_Pos 8 /**< \brief (MCLK_AHBMASK) CMCC AHB Clock Mask */
+#define MCLK_AHBMASK_CMCC (_U_(0x1) << MCLK_AHBMASK_CMCC_Pos)
+#define MCLK_AHBMASK_DMAC_Pos 9 /**< \brief (MCLK_AHBMASK) DMAC AHB Clock Mask */
+#define MCLK_AHBMASK_DMAC (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos)
+#define MCLK_AHBMASK_USB_Pos 10 /**< \brief (MCLK_AHBMASK) USB AHB Clock Mask */
+#define MCLK_AHBMASK_USB (_U_(0x1) << MCLK_AHBMASK_USB_Pos)
+#define MCLK_AHBMASK_BKUPRAM_Pos 11 /**< \brief (MCLK_AHBMASK) BKUPRAM AHB Clock Mask */
+#define MCLK_AHBMASK_BKUPRAM (_U_(0x1) << MCLK_AHBMASK_BKUPRAM_Pos)
+#define MCLK_AHBMASK_PAC_Pos 12 /**< \brief (MCLK_AHBMASK) PAC AHB Clock Mask */
+#define MCLK_AHBMASK_PAC (_U_(0x1) << MCLK_AHBMASK_PAC_Pos)
+#define MCLK_AHBMASK_QSPI_Pos 13 /**< \brief (MCLK_AHBMASK) QSPI AHB Clock Mask */
+#define MCLK_AHBMASK_QSPI (_U_(0x1) << MCLK_AHBMASK_QSPI_Pos)
+#define MCLK_AHBMASK_GMAC_Pos 14 /**< \brief (MCLK_AHBMASK) GMAC AHB Clock Mask */
+#define MCLK_AHBMASK_GMAC (_U_(0x1) << MCLK_AHBMASK_GMAC_Pos)
+#define MCLK_AHBMASK_SDHC0_Pos 15 /**< \brief (MCLK_AHBMASK) SDHC0 AHB Clock Mask */
+#define MCLK_AHBMASK_SDHC0 (_U_(0x1) << MCLK_AHBMASK_SDHC0_Pos)
+#define MCLK_AHBMASK_SDHC1_Pos 16 /**< \brief (MCLK_AHBMASK) SDHC1 AHB Clock Mask */
+#define MCLK_AHBMASK_SDHC1 (_U_(0x1) << MCLK_AHBMASK_SDHC1_Pos)
+#define MCLK_AHBMASK_CAN0_Pos 17 /**< \brief (MCLK_AHBMASK) CAN0 AHB Clock Mask */
+#define MCLK_AHBMASK_CAN0 (_U_(0x1) << MCLK_AHBMASK_CAN0_Pos)
+#define MCLK_AHBMASK_CAN1_Pos 18 /**< \brief (MCLK_AHBMASK) CAN1 AHB Clock Mask */
+#define MCLK_AHBMASK_CAN1 (_U_(0x1) << MCLK_AHBMASK_CAN1_Pos)
+#define MCLK_AHBMASK_ICM_Pos 19 /**< \brief (MCLK_AHBMASK) ICM AHB Clock Mask */
+#define MCLK_AHBMASK_ICM (_U_(0x1) << MCLK_AHBMASK_ICM_Pos)
+#define MCLK_AHBMASK_PUKCC_Pos 20 /**< \brief (MCLK_AHBMASK) PUKCC AHB Clock Mask */
+#define MCLK_AHBMASK_PUKCC (_U_(0x1) << MCLK_AHBMASK_PUKCC_Pos)
+#define MCLK_AHBMASK_QSPI_2X_Pos 21 /**< \brief (MCLK_AHBMASK) QSPI_2X AHB Clock Mask */
+#define MCLK_AHBMASK_QSPI_2X (_U_(0x1) << MCLK_AHBMASK_QSPI_2X_Pos)
+#define MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos 22 /**< \brief (MCLK_AHBMASK) NVMCTRL_SMEEPROM AHB Clock Mask */
+#define MCLK_AHBMASK_NVMCTRL_SMEEPROM (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos)
+#define MCLK_AHBMASK_NVMCTRL_CACHE_Pos 23 /**< \brief (MCLK_AHBMASK) NVMCTRL_CACHE AHB Clock Mask */
+#define MCLK_AHBMASK_NVMCTRL_CACHE (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_CACHE_Pos)
+#define MCLK_AHBMASK_MASK _U_(0x00FFFFFF) /**< \brief (MCLK_AHBMASK) MASK Register */
+
+/* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PAC_:1; /*!< bit: 0 PAC APB Clock Enable */
+ uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
+ uint32_t MCLK_:1; /*!< bit: 2 MCLK APB Clock Enable */
+ uint32_t RSTC_:1; /*!< bit: 3 RSTC APB Clock Enable */
+ uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL APB Clock Enable */
+ uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL APB Clock Enable */
+ uint32_t SUPC_:1; /*!< bit: 6 SUPC APB Clock Enable */
+ uint32_t GCLK_:1; /*!< bit: 7 GCLK APB Clock Enable */
+ uint32_t WDT_:1; /*!< bit: 8 WDT APB Clock Enable */
+ uint32_t RTC_:1; /*!< bit: 9 RTC APB Clock Enable */
+ uint32_t EIC_:1; /*!< bit: 10 EIC APB Clock Enable */
+ uint32_t FREQM_:1; /*!< bit: 11 FREQM APB Clock Enable */
+ uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 APB Clock Enable */
+ uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 APB Clock Enable */
+ uint32_t TC0_:1; /*!< bit: 14 TC0 APB Clock Enable */
+ uint32_t TC1_:1; /*!< bit: 15 TC1 APB Clock Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MCLK_APBAMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_APBAMASK_OFFSET 0x14 /**< \brief (MCLK_APBAMASK offset) APBA Mask */
+#define MCLK_APBAMASK_RESETVALUE _U_(0x000007FF) /**< \brief (MCLK_APBAMASK reset_value) APBA Mask */
+
+#define MCLK_APBAMASK_PAC_Pos 0 /**< \brief (MCLK_APBAMASK) PAC APB Clock Enable */
+#define MCLK_APBAMASK_PAC (_U_(0x1) << MCLK_APBAMASK_PAC_Pos)
+#define MCLK_APBAMASK_PM_Pos 1 /**< \brief (MCLK_APBAMASK) PM APB Clock Enable */
+#define MCLK_APBAMASK_PM (_U_(0x1) << MCLK_APBAMASK_PM_Pos)
+#define MCLK_APBAMASK_MCLK_Pos 2 /**< \brief (MCLK_APBAMASK) MCLK APB Clock Enable */
+#define MCLK_APBAMASK_MCLK (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos)
+#define MCLK_APBAMASK_RSTC_Pos 3 /**< \brief (MCLK_APBAMASK) RSTC APB Clock Enable */
+#define MCLK_APBAMASK_RSTC (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos)
+#define MCLK_APBAMASK_OSCCTRL_Pos 4 /**< \brief (MCLK_APBAMASK) OSCCTRL APB Clock Enable */
+#define MCLK_APBAMASK_OSCCTRL (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos)
+#define MCLK_APBAMASK_OSC32KCTRL_Pos 5 /**< \brief (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable */
+#define MCLK_APBAMASK_OSC32KCTRL (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos)
+#define MCLK_APBAMASK_SUPC_Pos 6 /**< \brief (MCLK_APBAMASK) SUPC APB Clock Enable */
+#define MCLK_APBAMASK_SUPC (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos)
+#define MCLK_APBAMASK_GCLK_Pos 7 /**< \brief (MCLK_APBAMASK) GCLK APB Clock Enable */
+#define MCLK_APBAMASK_GCLK (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos)
+#define MCLK_APBAMASK_WDT_Pos 8 /**< \brief (MCLK_APBAMASK) WDT APB Clock Enable */
+#define MCLK_APBAMASK_WDT (_U_(0x1) << MCLK_APBAMASK_WDT_Pos)
+#define MCLK_APBAMASK_RTC_Pos 9 /**< \brief (MCLK_APBAMASK) RTC APB Clock Enable */
+#define MCLK_APBAMASK_RTC (_U_(0x1) << MCLK_APBAMASK_RTC_Pos)
+#define MCLK_APBAMASK_EIC_Pos 10 /**< \brief (MCLK_APBAMASK) EIC APB Clock Enable */
+#define MCLK_APBAMASK_EIC (_U_(0x1) << MCLK_APBAMASK_EIC_Pos)
+#define MCLK_APBAMASK_FREQM_Pos 11 /**< \brief (MCLK_APBAMASK) FREQM APB Clock Enable */
+#define MCLK_APBAMASK_FREQM (_U_(0x1) << MCLK_APBAMASK_FREQM_Pos)
+#define MCLK_APBAMASK_SERCOM0_Pos 12 /**< \brief (MCLK_APBAMASK) SERCOM0 APB Clock Enable */
+#define MCLK_APBAMASK_SERCOM0 (_U_(0x1) << MCLK_APBAMASK_SERCOM0_Pos)
+#define MCLK_APBAMASK_SERCOM1_Pos 13 /**< \brief (MCLK_APBAMASK) SERCOM1 APB Clock Enable */
+#define MCLK_APBAMASK_SERCOM1 (_U_(0x1) << MCLK_APBAMASK_SERCOM1_Pos)
+#define MCLK_APBAMASK_TC0_Pos 14 /**< \brief (MCLK_APBAMASK) TC0 APB Clock Enable */
+#define MCLK_APBAMASK_TC0 (_U_(0x1) << MCLK_APBAMASK_TC0_Pos)
+#define MCLK_APBAMASK_TC1_Pos 15 /**< \brief (MCLK_APBAMASK) TC1 APB Clock Enable */
+#define MCLK_APBAMASK_TC1 (_U_(0x1) << MCLK_APBAMASK_TC1_Pos)
+#define MCLK_APBAMASK_MASK _U_(0x0000FFFF) /**< \brief (MCLK_APBAMASK) MASK Register */
+
+/* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t USB_:1; /*!< bit: 0 USB APB Clock Enable */
+ uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
+ uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t PORT_:1; /*!< bit: 4 PORT APB Clock Enable */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
+ uint32_t EVSYS_:1; /*!< bit: 7 EVSYS APB Clock Enable */
+ uint32_t :1; /*!< bit: 8 Reserved */
+ uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 APB Clock Enable */
+ uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 APB Clock Enable */
+ uint32_t TCC0_:1; /*!< bit: 11 TCC0 APB Clock Enable */
+ uint32_t TCC1_:1; /*!< bit: 12 TCC1 APB Clock Enable */
+ uint32_t TC2_:1; /*!< bit: 13 TC2 APB Clock Enable */
+ uint32_t TC3_:1; /*!< bit: 14 TC3 APB Clock Enable */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t RAMECC_:1; /*!< bit: 16 RAMECC APB Clock Enable */
+ uint32_t :15; /*!< bit: 17..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MCLK_APBBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_APBBMASK_OFFSET 0x18 /**< \brief (MCLK_APBBMASK offset) APBB Mask */
+#define MCLK_APBBMASK_RESETVALUE _U_(0x00018056) /**< \brief (MCLK_APBBMASK reset_value) APBB Mask */
+
+#define MCLK_APBBMASK_USB_Pos 0 /**< \brief (MCLK_APBBMASK) USB APB Clock Enable */
+#define MCLK_APBBMASK_USB (_U_(0x1) << MCLK_APBBMASK_USB_Pos)
+#define MCLK_APBBMASK_DSU_Pos 1 /**< \brief (MCLK_APBBMASK) DSU APB Clock Enable */
+#define MCLK_APBBMASK_DSU (_U_(0x1) << MCLK_APBBMASK_DSU_Pos)
+#define MCLK_APBBMASK_NVMCTRL_Pos 2 /**< \brief (MCLK_APBBMASK) NVMCTRL APB Clock Enable */
+#define MCLK_APBBMASK_NVMCTRL (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos)
+#define MCLK_APBBMASK_PORT_Pos 4 /**< \brief (MCLK_APBBMASK) PORT APB Clock Enable */
+#define MCLK_APBBMASK_PORT (_U_(0x1) << MCLK_APBBMASK_PORT_Pos)
+#define MCLK_APBBMASK_HMATRIX_Pos 6 /**< \brief (MCLK_APBBMASK) HMATRIX APB Clock Enable */
+#define MCLK_APBBMASK_HMATRIX (_U_(0x1) << MCLK_APBBMASK_HMATRIX_Pos)
+#define MCLK_APBBMASK_EVSYS_Pos 7 /**< \brief (MCLK_APBBMASK) EVSYS APB Clock Enable */
+#define MCLK_APBBMASK_EVSYS (_U_(0x1) << MCLK_APBBMASK_EVSYS_Pos)
+#define MCLK_APBBMASK_SERCOM2_Pos 9 /**< \brief (MCLK_APBBMASK) SERCOM2 APB Clock Enable */
+#define MCLK_APBBMASK_SERCOM2 (_U_(0x1) << MCLK_APBBMASK_SERCOM2_Pos)
+#define MCLK_APBBMASK_SERCOM3_Pos 10 /**< \brief (MCLK_APBBMASK) SERCOM3 APB Clock Enable */
+#define MCLK_APBBMASK_SERCOM3 (_U_(0x1) << MCLK_APBBMASK_SERCOM3_Pos)
+#define MCLK_APBBMASK_TCC0_Pos 11 /**< \brief (MCLK_APBBMASK) TCC0 APB Clock Enable */
+#define MCLK_APBBMASK_TCC0 (_U_(0x1) << MCLK_APBBMASK_TCC0_Pos)
+#define MCLK_APBBMASK_TCC1_Pos 12 /**< \brief (MCLK_APBBMASK) TCC1 APB Clock Enable */
+#define MCLK_APBBMASK_TCC1 (_U_(0x1) << MCLK_APBBMASK_TCC1_Pos)
+#define MCLK_APBBMASK_TC2_Pos 13 /**< \brief (MCLK_APBBMASK) TC2 APB Clock Enable */
+#define MCLK_APBBMASK_TC2 (_U_(0x1) << MCLK_APBBMASK_TC2_Pos)
+#define MCLK_APBBMASK_TC3_Pos 14 /**< \brief (MCLK_APBBMASK) TC3 APB Clock Enable */
+#define MCLK_APBBMASK_TC3 (_U_(0x1) << MCLK_APBBMASK_TC3_Pos)
+#define MCLK_APBBMASK_RAMECC_Pos 16 /**< \brief (MCLK_APBBMASK) RAMECC APB Clock Enable */
+#define MCLK_APBBMASK_RAMECC (_U_(0x1) << MCLK_APBBMASK_RAMECC_Pos)
+#define MCLK_APBBMASK_MASK _U_(0x00017ED7) /**< \brief (MCLK_APBBMASK) MASK Register */
+
+/* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t GMAC_:1; /*!< bit: 2 GMAC APB Clock Enable */
+ uint32_t TCC2_:1; /*!< bit: 3 TCC2 APB Clock Enable */
+ uint32_t TCC3_:1; /*!< bit: 4 TCC3 APB Clock Enable */
+ uint32_t TC4_:1; /*!< bit: 5 TC4 APB Clock Enable */
+ uint32_t TC5_:1; /*!< bit: 6 TC5 APB Clock Enable */
+ uint32_t PDEC_:1; /*!< bit: 7 PDEC APB Clock Enable */
+ uint32_t AC_:1; /*!< bit: 8 AC APB Clock Enable */
+ uint32_t AES_:1; /*!< bit: 9 AES APB Clock Enable */
+ uint32_t TRNG_:1; /*!< bit: 10 TRNG APB Clock Enable */
+ uint32_t ICM_:1; /*!< bit: 11 ICM APB Clock Enable */
+ uint32_t :1; /*!< bit: 12 Reserved */
+ uint32_t QSPI_:1; /*!< bit: 13 QSPI APB Clock Enable */
+ uint32_t CCL_:1; /*!< bit: 14 CCL APB Clock Enable */
+ uint32_t :17; /*!< bit: 15..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MCLK_APBCMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_APBCMASK_OFFSET 0x1C /**< \brief (MCLK_APBCMASK offset) APBC Mask */
+#define MCLK_APBCMASK_RESETVALUE _U_(0x00002000) /**< \brief (MCLK_APBCMASK reset_value) APBC Mask */
+
+#define MCLK_APBCMASK_GMAC_Pos 2 /**< \brief (MCLK_APBCMASK) GMAC APB Clock Enable */
+#define MCLK_APBCMASK_GMAC (_U_(0x1) << MCLK_APBCMASK_GMAC_Pos)
+#define MCLK_APBCMASK_TCC2_Pos 3 /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable */
+#define MCLK_APBCMASK_TCC2 (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos)
+#define MCLK_APBCMASK_TCC3_Pos 4 /**< \brief (MCLK_APBCMASK) TCC3 APB Clock Enable */
+#define MCLK_APBCMASK_TCC3 (_U_(0x1) << MCLK_APBCMASK_TCC3_Pos)
+#define MCLK_APBCMASK_TC4_Pos 5 /**< \brief (MCLK_APBCMASK) TC4 APB Clock Enable */
+#define MCLK_APBCMASK_TC4 (_U_(0x1) << MCLK_APBCMASK_TC4_Pos)
+#define MCLK_APBCMASK_TC5_Pos 6 /**< \brief (MCLK_APBCMASK) TC5 APB Clock Enable */
+#define MCLK_APBCMASK_TC5 (_U_(0x1) << MCLK_APBCMASK_TC5_Pos)
+#define MCLK_APBCMASK_PDEC_Pos 7 /**< \brief (MCLK_APBCMASK) PDEC APB Clock Enable */
+#define MCLK_APBCMASK_PDEC (_U_(0x1) << MCLK_APBCMASK_PDEC_Pos)
+#define MCLK_APBCMASK_AC_Pos 8 /**< \brief (MCLK_APBCMASK) AC APB Clock Enable */
+#define MCLK_APBCMASK_AC (_U_(0x1) << MCLK_APBCMASK_AC_Pos)
+#define MCLK_APBCMASK_AES_Pos 9 /**< \brief (MCLK_APBCMASK) AES APB Clock Enable */
+#define MCLK_APBCMASK_AES (_U_(0x1) << MCLK_APBCMASK_AES_Pos)
+#define MCLK_APBCMASK_TRNG_Pos 10 /**< \brief (MCLK_APBCMASK) TRNG APB Clock Enable */
+#define MCLK_APBCMASK_TRNG (_U_(0x1) << MCLK_APBCMASK_TRNG_Pos)
+#define MCLK_APBCMASK_ICM_Pos 11 /**< \brief (MCLK_APBCMASK) ICM APB Clock Enable */
+#define MCLK_APBCMASK_ICM (_U_(0x1) << MCLK_APBCMASK_ICM_Pos)
+#define MCLK_APBCMASK_QSPI_Pos 13 /**< \brief (MCLK_APBCMASK) QSPI APB Clock Enable */
+#define MCLK_APBCMASK_QSPI (_U_(0x1) << MCLK_APBCMASK_QSPI_Pos)
+#define MCLK_APBCMASK_CCL_Pos 14 /**< \brief (MCLK_APBCMASK) CCL APB Clock Enable */
+#define MCLK_APBCMASK_CCL (_U_(0x1) << MCLK_APBCMASK_CCL_Pos)
+#define MCLK_APBCMASK_MASK _U_(0x00006FFC) /**< \brief (MCLK_APBCMASK) MASK Register */
+
+/* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 APB Clock Enable */
+ uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Clock Enable */
+ uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 APB Clock Enable */
+ uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 APB Clock Enable */
+ uint32_t TCC4_:1; /*!< bit: 4 TCC4 APB Clock Enable */
+ uint32_t TC6_:1; /*!< bit: 5 TC6 APB Clock Enable */
+ uint32_t TC7_:1; /*!< bit: 6 TC7 APB Clock Enable */
+ uint32_t ADC0_:1; /*!< bit: 7 ADC0 APB Clock Enable */
+ uint32_t ADC1_:1; /*!< bit: 8 ADC1 APB Clock Enable */
+ uint32_t DAC_:1; /*!< bit: 9 DAC APB Clock Enable */
+ uint32_t I2S_:1; /*!< bit: 10 I2S APB Clock Enable */
+ uint32_t PCC_:1; /*!< bit: 11 PCC APB Clock Enable */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MCLK_APBDMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_APBDMASK_OFFSET 0x20 /**< \brief (MCLK_APBDMASK offset) APBD Mask */
+#define MCLK_APBDMASK_RESETVALUE _U_(0x00000000) /**< \brief (MCLK_APBDMASK reset_value) APBD Mask */
+
+#define MCLK_APBDMASK_SERCOM4_Pos 0 /**< \brief (MCLK_APBDMASK) SERCOM4 APB Clock Enable */
+#define MCLK_APBDMASK_SERCOM4 (_U_(0x1) << MCLK_APBDMASK_SERCOM4_Pos)
+#define MCLK_APBDMASK_SERCOM5_Pos 1 /**< \brief (MCLK_APBDMASK) SERCOM5 APB Clock Enable */
+#define MCLK_APBDMASK_SERCOM5 (_U_(0x1) << MCLK_APBDMASK_SERCOM5_Pos)
+#define MCLK_APBDMASK_SERCOM6_Pos 2 /**< \brief (MCLK_APBDMASK) SERCOM6 APB Clock Enable */
+#define MCLK_APBDMASK_SERCOM6 (_U_(0x1) << MCLK_APBDMASK_SERCOM6_Pos)
+#define MCLK_APBDMASK_SERCOM7_Pos 3 /**< \brief (MCLK_APBDMASK) SERCOM7 APB Clock Enable */
+#define MCLK_APBDMASK_SERCOM7 (_U_(0x1) << MCLK_APBDMASK_SERCOM7_Pos)
+#define MCLK_APBDMASK_TCC4_Pos 4 /**< \brief (MCLK_APBDMASK) TCC4 APB Clock Enable */
+#define MCLK_APBDMASK_TCC4 (_U_(0x1) << MCLK_APBDMASK_TCC4_Pos)
+#define MCLK_APBDMASK_TC6_Pos 5 /**< \brief (MCLK_APBDMASK) TC6 APB Clock Enable */
+#define MCLK_APBDMASK_TC6 (_U_(0x1) << MCLK_APBDMASK_TC6_Pos)
+#define MCLK_APBDMASK_TC7_Pos 6 /**< \brief (MCLK_APBDMASK) TC7 APB Clock Enable */
+#define MCLK_APBDMASK_TC7 (_U_(0x1) << MCLK_APBDMASK_TC7_Pos)
+#define MCLK_APBDMASK_ADC0_Pos 7 /**< \brief (MCLK_APBDMASK) ADC0 APB Clock Enable */
+#define MCLK_APBDMASK_ADC0 (_U_(0x1) << MCLK_APBDMASK_ADC0_Pos)
+#define MCLK_APBDMASK_ADC1_Pos 8 /**< \brief (MCLK_APBDMASK) ADC1 APB Clock Enable */
+#define MCLK_APBDMASK_ADC1 (_U_(0x1) << MCLK_APBDMASK_ADC1_Pos)
+#define MCLK_APBDMASK_DAC_Pos 9 /**< \brief (MCLK_APBDMASK) DAC APB Clock Enable */
+#define MCLK_APBDMASK_DAC (_U_(0x1) << MCLK_APBDMASK_DAC_Pos)
+#define MCLK_APBDMASK_I2S_Pos 10 /**< \brief (MCLK_APBDMASK) I2S APB Clock Enable */
+#define MCLK_APBDMASK_I2S (_U_(0x1) << MCLK_APBDMASK_I2S_Pos)
+#define MCLK_APBDMASK_PCC_Pos 11 /**< \brief (MCLK_APBDMASK) PCC APB Clock Enable */
+#define MCLK_APBDMASK_PCC (_U_(0x1) << MCLK_APBDMASK_PCC_Pos)
+#define MCLK_APBDMASK_MASK _U_(0x00000FFF) /**< \brief (MCLK_APBDMASK) MASK Register */
+
+/** \brief MCLK hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ RoReg8 Reserved1[0x1];
+ __IO MCLK_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x01 (R/W 8) Interrupt Enable Clear */
+ __IO MCLK_INTENSET_Type INTENSET; /**< \brief Offset: 0x02 (R/W 8) Interrupt Enable Set */
+ __IO MCLK_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x03 (R/W 8) Interrupt Flag Status and Clear */
+ __I MCLK_HSDIV_Type HSDIV; /**< \brief Offset: 0x04 (R/ 8) HS Clock Division */
+ __IO MCLK_CPUDIV_Type CPUDIV; /**< \brief Offset: 0x05 (R/W 8) CPU Clock Division */
+ RoReg8 Reserved2[0xA];
+ __IO MCLK_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x10 (R/W 32) AHB Mask */
+ __IO MCLK_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x14 (R/W 32) APBA Mask */
+ __IO MCLK_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x18 (R/W 32) APBB Mask */
+ __IO MCLK_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x1C (R/W 32) APBC Mask */
+ __IO MCLK_APBDMASK_Type APBDMASK; /**< \brief Offset: 0x20 (R/W 32) APBD Mask */
+} Mclk;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_MCLK_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/osc32kctrl.h b/sysmoOCTSIM/include/component/osc32kctrl.h
index e29e532..a2172c1 100644
--- a/sysmoOCTSIM/include/component/osc32kctrl.h
+++ b/sysmoOCTSIM/include/component/osc32kctrl.h
@@ -1,303 +1,303 @@
-/**
- * \file
- *
- * \brief Component description for OSC32KCTRL
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_OSC32KCTRL_COMPONENT_
-#define _SAME54_OSC32KCTRL_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR OSC32KCTRL */
-/* ========================================================================== */
-/** \addtogroup SAME54_OSC32KCTRL 32kHz Oscillators Control */
-/*@{*/
-
-#define OSC32KCTRL_U2400
-#define REV_OSC32KCTRL 0x100
-
-/* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */
- uint32_t :1; /*!< bit: 1 Reserved */
- uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector Interrupt Enable */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} OSC32KCTRL_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSC32KCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSC32KCTRL_INTENCLR offset) Interrupt Enable Clear */
-#define OSC32KCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
-#define OSC32KCTRL_INTENCLR_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos)
-#define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable */
-#define OSC32KCTRL_INTENCLR_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos)
-#define OSC32KCTRL_INTENCLR_MASK _U_(0x00000005) /**< \brief (OSC32KCTRL_INTENCLR) MASK Register */
-
-/* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */
- uint32_t :1; /*!< bit: 1 Reserved */
- uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector Interrupt Enable */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} OSC32KCTRL_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSC32KCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSC32KCTRL_INTENSET offset) Interrupt Enable Set */
-#define OSC32KCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENSET reset_value) Interrupt Enable Set */
-
-#define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
-#define OSC32KCTRL_INTENSET_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos)
-#define OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable */
-#define OSC32KCTRL_INTENSET_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos)
-#define OSC32KCTRL_INTENSET_MASK _U_(0x00000005) /**< \brief (OSC32KCTRL_INTENSET) MASK Register */
-
-/* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */
- __I uint32_t :1; /*!< bit: 1 Reserved */
- __I uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector */
- __I uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} OSC32KCTRL_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSC32KCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSC32KCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
-#define OSC32KCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Ready */
-#define OSC32KCTRL_INTFLAG_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos)
-#define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector */
-#define OSC32KCTRL_INTFLAG_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos)
-#define OSC32KCTRL_INTFLAG_MASK _U_(0x00000005) /**< \brief (OSC32KCTRL_INTFLAG) MASK Register */
-
-/* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */
- uint32_t :1; /*!< bit: 1 Reserved */
- uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector */
- uint32_t XOSC32KSW:1; /*!< bit: 3 XOSC32K Clock switch */
- uint32_t :28; /*!< bit: 4..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} OSC32KCTRL_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSC32KCTRL_STATUS_OFFSET 0x0C /**< \brief (OSC32KCTRL_STATUS offset) Power and Clocks Status */
-#define OSC32KCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_STATUS reset_value) Power and Clocks Status */
-
-#define OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Ready */
-#define OSC32KCTRL_STATUS_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos)
-#define OSC32KCTRL_STATUS_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector */
-#define OSC32KCTRL_STATUS_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos)
-#define OSC32KCTRL_STATUS_XOSC32KSW_Pos 3 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock switch */
-#define OSC32KCTRL_STATUS_XOSC32KSW (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KSW_Pos)
-#define OSC32KCTRL_STATUS_MASK _U_(0x0000000D) /**< \brief (OSC32KCTRL_STATUS) MASK Register */
-
-/* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 8) RTC Clock Selection -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t RTCSEL:3; /*!< bit: 0.. 2 RTC Clock Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} OSC32KCTRL_RTCCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSC32KCTRL_RTCCTRL_OFFSET 0x10 /**< \brief (OSC32KCTRL_RTCCTRL offset) RTC Clock Selection */
-#define OSC32KCTRL_RTCCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_RTCCTRL reset_value) RTC Clock Selection */
-
-#define OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0 /**< \brief (OSC32KCTRL_RTCCTRL) RTC Clock Selection */
-#define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
-#define OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))
-#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */
-#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */
-#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */
-#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */
-#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
-#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
-#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
-#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
-#define OSC32KCTRL_RTCCTRL_MASK _U_(0x07) /**< \brief (OSC32KCTRL_RTCCTRL) MASK Register */
-
-/* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t :1; /*!< bit: 0 Reserved */
- uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
- uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
- uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
- uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
- uint16_t :1; /*!< bit: 5 Reserved */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
- uint16_t :1; /*!< bit: 11 Reserved */
- uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
- uint16_t CGM:2; /*!< bit: 13..14 Control Gain Mode */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} OSC32KCTRL_XOSC32K_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSC32KCTRL_XOSC32K_OFFSET 0x14 /**< \brief (OSC32KCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
-#define OSC32KCTRL_XOSC32K_RESETVALUE _U_(0x2080) /**< \brief (OSC32KCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
-
-#define OSC32KCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Enable */
-#define OSC32KCTRL_XOSC32K_ENABLE (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos)
-#define OSC32KCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable */
-#define OSC32KCTRL_XOSC32K_XTALEN (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos)
-#define OSC32KCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (OSC32KCTRL_XOSC32K) 32kHz Output Enable */
-#define OSC32KCTRL_XOSC32K_EN32K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos)
-#define OSC32KCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (OSC32KCTRL_XOSC32K) 1kHz Output Enable */
-#define OSC32KCTRL_XOSC32K_EN1K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos)
-#define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_XOSC32K) Run in Standby */
-#define OSC32KCTRL_XOSC32K_RUNSTDBY (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)
-#define OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_XOSC32K) On Demand Control */
-#define OSC32KCTRL_XOSC32K_ONDEMAND (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)
-#define OSC32KCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time */
-#define OSC32KCTRL_XOSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos)
-#define OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))
-#define OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_XOSC32K) Write Lock */
-#define OSC32KCTRL_XOSC32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos)
-#define OSC32KCTRL_XOSC32K_CGM_Pos 13 /**< \brief (OSC32KCTRL_XOSC32K) Control Gain Mode */
-#define OSC32KCTRL_XOSC32K_CGM_Msk (_U_(0x3) << OSC32KCTRL_XOSC32K_CGM_Pos)
-#define OSC32KCTRL_XOSC32K_CGM(value) (OSC32KCTRL_XOSC32K_CGM_Msk & ((value) << OSC32KCTRL_XOSC32K_CGM_Pos))
-#define OSC32KCTRL_XOSC32K_CGM_XT_Val _U_(0x1) /**< \brief (OSC32KCTRL_XOSC32K) Standard mode */
-#define OSC32KCTRL_XOSC32K_CGM_HS_Val _U_(0x2) /**< \brief (OSC32KCTRL_XOSC32K) High Speed mode */
-#define OSC32KCTRL_XOSC32K_CGM_XT (OSC32KCTRL_XOSC32K_CGM_XT_Val << OSC32KCTRL_XOSC32K_CGM_Pos)
-#define OSC32KCTRL_XOSC32K_CGM_HS (OSC32KCTRL_XOSC32K_CGM_HS_Val << OSC32KCTRL_XOSC32K_CGM_Pos)
-#define OSC32KCTRL_XOSC32K_MASK _U_(0x77DE) /**< \brief (OSC32KCTRL_XOSC32K) MASK Register */
-
-/* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x16) (R/W 8) Clock Failure Detector Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t CFDEN:1; /*!< bit: 0 Clock Failure Detector Enable */
- uint8_t SWBACK:1; /*!< bit: 1 Clock Switch Back */
- uint8_t CFDPRESC:1; /*!< bit: 2 Clock Failure Detector Prescaler */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} OSC32KCTRL_CFDCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSC32KCTRL_CFDCTRL_OFFSET 0x16 /**< \brief (OSC32KCTRL_CFDCTRL offset) Clock Failure Detector Control */
-#define OSC32KCTRL_CFDCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_CFDCTRL reset_value) Clock Failure Detector Control */
-
-#define OSC32KCTRL_CFDCTRL_CFDEN_Pos 0 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable */
-#define OSC32KCTRL_CFDCTRL_CFDEN (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos)
-#define OSC32KCTRL_CFDCTRL_SWBACK_Pos 1 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Switch Back */
-#define OSC32KCTRL_CFDCTRL_SWBACK (_U_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos)
-#define OSC32KCTRL_CFDCTRL_CFDPRESC_Pos 2 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler */
-#define OSC32KCTRL_CFDCTRL_CFDPRESC (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos)
-#define OSC32KCTRL_CFDCTRL_MASK _U_(0x07) /**< \brief (OSC32KCTRL_CFDCTRL) MASK Register */
-
-/* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x17) (R/W 8) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t CFDEO:1; /*!< bit: 0 Clock Failure Detector Event Output Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} OSC32KCTRL_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSC32KCTRL_EVCTRL_OFFSET 0x17 /**< \brief (OSC32KCTRL_EVCTRL offset) Event Control */
-#define OSC32KCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_EVCTRL reset_value) Event Control */
-
-#define OSC32KCTRL_EVCTRL_CFDEO_Pos 0 /**< \brief (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable */
-#define OSC32KCTRL_EVCTRL_CFDEO (_U_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos)
-#define OSC32KCTRL_EVCTRL_MASK _U_(0x01) /**< \brief (OSC32KCTRL_EVCTRL) MASK Register */
-
-/* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t EN32K:1; /*!< bit: 1 Enable Out 32k */
- uint32_t EN1K:1; /*!< bit: 2 Enable Out 1k */
- uint32_t :5; /*!< bit: 3.. 7 Reserved */
- uint32_t CALIB:6; /*!< bit: 8..13 Oscillator Calibration */
- uint32_t :1; /*!< bit: 14 Reserved */
- uint32_t WRTLOCK:1; /*!< bit: 15 Write Lock */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} OSC32KCTRL_OSCULP32K_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSC32KCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (OSC32KCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
-#define OSC32KCTRL_OSCULP32K_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
-
-#define OSC32KCTRL_OSCULP32K_EN32K_Pos 1 /**< \brief (OSC32KCTRL_OSCULP32K) Enable Out 32k */
-#define OSC32KCTRL_OSCULP32K_EN32K (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN32K_Pos)
-#define OSC32KCTRL_OSCULP32K_EN1K_Pos 2 /**< \brief (OSC32KCTRL_OSCULP32K) Enable Out 1k */
-#define OSC32KCTRL_OSCULP32K_EN1K (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN1K_Pos)
-#define OSC32KCTRL_OSCULP32K_CALIB_Pos 8 /**< \brief (OSC32KCTRL_OSCULP32K) Oscillator Calibration */
-#define OSC32KCTRL_OSCULP32K_CALIB_Msk (_U_(0x3F) << OSC32KCTRL_OSCULP32K_CALIB_Pos)
-#define OSC32KCTRL_OSCULP32K_CALIB(value) (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))
-#define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15 /**< \brief (OSC32KCTRL_OSCULP32K) Write Lock */
-#define OSC32KCTRL_OSCULP32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos)
-#define OSC32KCTRL_OSCULP32K_MASK _U_(0x0000BF06) /**< \brief (OSC32KCTRL_OSCULP32K) MASK Register */
-
-/** \brief OSC32KCTRL hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO OSC32KCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
- __IO OSC32KCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
- __IO OSC32KCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
- __I OSC32KCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
- __IO OSC32KCTRL_RTCCTRL_Type RTCCTRL; /**< \brief Offset: 0x10 (R/W 8) RTC Clock Selection */
- RoReg8 Reserved1[0x3];
- __IO OSC32KCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
- __IO OSC32KCTRL_CFDCTRL_Type CFDCTRL; /**< \brief Offset: 0x16 (R/W 8) Clock Failure Detector Control */
- __IO OSC32KCTRL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x17 (R/W 8) Event Control */
- RoReg8 Reserved2[0x4];
- __IO OSC32KCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
-} Osc32kctrl;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_OSC32KCTRL_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for OSC32KCTRL
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_OSC32KCTRL_COMPONENT_
+#define _SAME54_OSC32KCTRL_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR OSC32KCTRL */
+/* ========================================================================== */
+/** \addtogroup SAME54_OSC32KCTRL 32kHz Oscillators Control */
+/*@{*/
+
+#define OSC32KCTRL_U2400
+#define REV_OSC32KCTRL 0x100
+
+/* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */
+ uint32_t :1; /*!< bit: 1 Reserved */
+ uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector Interrupt Enable */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSC32KCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSC32KCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define OSC32KCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
+#define OSC32KCTRL_INTENCLR_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos)
+#define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable */
+#define OSC32KCTRL_INTENCLR_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos)
+#define OSC32KCTRL_INTENCLR_MASK _U_(0x00000005) /**< \brief (OSC32KCTRL_INTENCLR) MASK Register */
+
+/* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */
+ uint32_t :1; /*!< bit: 1 Reserved */
+ uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector Interrupt Enable */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSC32KCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSC32KCTRL_INTENSET offset) Interrupt Enable Set */
+#define OSC32KCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
+#define OSC32KCTRL_INTENSET_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos)
+#define OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable */
+#define OSC32KCTRL_INTENSET_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos)
+#define OSC32KCTRL_INTENSET_MASK _U_(0x00000005) /**< \brief (OSC32KCTRL_INTENSET) MASK Register */
+
+/* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */
+ __I uint32_t :1; /*!< bit: 1 Reserved */
+ __I uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector */
+ __I uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSC32KCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSC32KCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define OSC32KCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Ready */
+#define OSC32KCTRL_INTFLAG_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos)
+#define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector */
+#define OSC32KCTRL_INTFLAG_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos)
+#define OSC32KCTRL_INTFLAG_MASK _U_(0x00000005) /**< \brief (OSC32KCTRL_INTFLAG) MASK Register */
+
+/* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */
+ uint32_t :1; /*!< bit: 1 Reserved */
+ uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector */
+ uint32_t XOSC32KSW:1; /*!< bit: 3 XOSC32K Clock switch */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSC32KCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_STATUS_OFFSET 0x0C /**< \brief (OSC32KCTRL_STATUS offset) Power and Clocks Status */
+#define OSC32KCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_STATUS reset_value) Power and Clocks Status */
+
+#define OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Ready */
+#define OSC32KCTRL_STATUS_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos)
+#define OSC32KCTRL_STATUS_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector */
+#define OSC32KCTRL_STATUS_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos)
+#define OSC32KCTRL_STATUS_XOSC32KSW_Pos 3 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock switch */
+#define OSC32KCTRL_STATUS_XOSC32KSW (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KSW_Pos)
+#define OSC32KCTRL_STATUS_MASK _U_(0x0000000D) /**< \brief (OSC32KCTRL_STATUS) MASK Register */
+
+/* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 8) RTC Clock Selection -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RTCSEL:3; /*!< bit: 0.. 2 RTC Clock Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} OSC32KCTRL_RTCCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_RTCCTRL_OFFSET 0x10 /**< \brief (OSC32KCTRL_RTCCTRL offset) RTC Clock Selection */
+#define OSC32KCTRL_RTCCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_RTCCTRL reset_value) RTC Clock Selection */
+
+#define OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0 /**< \brief (OSC32KCTRL_RTCCTRL) RTC Clock Selection */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))
+#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_MASK _U_(0x07) /**< \brief (OSC32KCTRL_RTCCTRL) MASK Register */
+
+/* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
+ uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
+ uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
+ uint16_t CGM:2; /*!< bit: 13..14 Control Gain Mode */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} OSC32KCTRL_XOSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_XOSC32K_OFFSET 0x14 /**< \brief (OSC32KCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define OSC32KCTRL_XOSC32K_RESETVALUE _U_(0x2080) /**< \brief (OSC32KCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
+
+#define OSC32KCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Enable */
+#define OSC32KCTRL_XOSC32K_ENABLE (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos)
+#define OSC32KCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable */
+#define OSC32KCTRL_XOSC32K_XTALEN (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos)
+#define OSC32KCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (OSC32KCTRL_XOSC32K) 32kHz Output Enable */
+#define OSC32KCTRL_XOSC32K_EN32K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos)
+#define OSC32KCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (OSC32KCTRL_XOSC32K) 1kHz Output Enable */
+#define OSC32KCTRL_XOSC32K_EN1K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos)
+#define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_XOSC32K) Run in Standby */
+#define OSC32KCTRL_XOSC32K_RUNSTDBY (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)
+#define OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_XOSC32K) On Demand Control */
+#define OSC32KCTRL_XOSC32K_ONDEMAND (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)
+#define OSC32KCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time */
+#define OSC32KCTRL_XOSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos)
+#define OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))
+#define OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_XOSC32K) Write Lock */
+#define OSC32KCTRL_XOSC32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos)
+#define OSC32KCTRL_XOSC32K_CGM_Pos 13 /**< \brief (OSC32KCTRL_XOSC32K) Control Gain Mode */
+#define OSC32KCTRL_XOSC32K_CGM_Msk (_U_(0x3) << OSC32KCTRL_XOSC32K_CGM_Pos)
+#define OSC32KCTRL_XOSC32K_CGM(value) (OSC32KCTRL_XOSC32K_CGM_Msk & ((value) << OSC32KCTRL_XOSC32K_CGM_Pos))
+#define OSC32KCTRL_XOSC32K_CGM_XT_Val _U_(0x1) /**< \brief (OSC32KCTRL_XOSC32K) Standard mode */
+#define OSC32KCTRL_XOSC32K_CGM_HS_Val _U_(0x2) /**< \brief (OSC32KCTRL_XOSC32K) High Speed mode */
+#define OSC32KCTRL_XOSC32K_CGM_XT (OSC32KCTRL_XOSC32K_CGM_XT_Val << OSC32KCTRL_XOSC32K_CGM_Pos)
+#define OSC32KCTRL_XOSC32K_CGM_HS (OSC32KCTRL_XOSC32K_CGM_HS_Val << OSC32KCTRL_XOSC32K_CGM_Pos)
+#define OSC32KCTRL_XOSC32K_MASK _U_(0x77DE) /**< \brief (OSC32KCTRL_XOSC32K) MASK Register */
+
+/* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x16) (R/W 8) Clock Failure Detector Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CFDEN:1; /*!< bit: 0 Clock Failure Detector Enable */
+ uint8_t SWBACK:1; /*!< bit: 1 Clock Switch Back */
+ uint8_t CFDPRESC:1; /*!< bit: 2 Clock Failure Detector Prescaler */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} OSC32KCTRL_CFDCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_CFDCTRL_OFFSET 0x16 /**< \brief (OSC32KCTRL_CFDCTRL offset) Clock Failure Detector Control */
+#define OSC32KCTRL_CFDCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_CFDCTRL reset_value) Clock Failure Detector Control */
+
+#define OSC32KCTRL_CFDCTRL_CFDEN_Pos 0 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable */
+#define OSC32KCTRL_CFDCTRL_CFDEN (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos)
+#define OSC32KCTRL_CFDCTRL_SWBACK_Pos 1 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Switch Back */
+#define OSC32KCTRL_CFDCTRL_SWBACK (_U_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos)
+#define OSC32KCTRL_CFDCTRL_CFDPRESC_Pos 2 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler */
+#define OSC32KCTRL_CFDCTRL_CFDPRESC (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos)
+#define OSC32KCTRL_CFDCTRL_MASK _U_(0x07) /**< \brief (OSC32KCTRL_CFDCTRL) MASK Register */
+
+/* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x17) (R/W 8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CFDEO:1; /*!< bit: 0 Clock Failure Detector Event Output Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} OSC32KCTRL_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_EVCTRL_OFFSET 0x17 /**< \brief (OSC32KCTRL_EVCTRL offset) Event Control */
+#define OSC32KCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_EVCTRL reset_value) Event Control */
+
+#define OSC32KCTRL_EVCTRL_CFDEO_Pos 0 /**< \brief (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable */
+#define OSC32KCTRL_EVCTRL_CFDEO (_U_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos)
+#define OSC32KCTRL_EVCTRL_MASK _U_(0x01) /**< \brief (OSC32KCTRL_EVCTRL) MASK Register */
+
+/* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t EN32K:1; /*!< bit: 1 Enable Out 32k */
+ uint32_t EN1K:1; /*!< bit: 2 Enable Out 1k */
+ uint32_t :5; /*!< bit: 3.. 7 Reserved */
+ uint32_t CALIB:6; /*!< bit: 8..13 Oscillator Calibration */
+ uint32_t :1; /*!< bit: 14 Reserved */
+ uint32_t WRTLOCK:1; /*!< bit: 15 Write Lock */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSC32KCTRL_OSCULP32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (OSC32KCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define OSC32KCTRL_OSCULP32K_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+
+#define OSC32KCTRL_OSCULP32K_EN32K_Pos 1 /**< \brief (OSC32KCTRL_OSCULP32K) Enable Out 32k */
+#define OSC32KCTRL_OSCULP32K_EN32K (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN32K_Pos)
+#define OSC32KCTRL_OSCULP32K_EN1K_Pos 2 /**< \brief (OSC32KCTRL_OSCULP32K) Enable Out 1k */
+#define OSC32KCTRL_OSCULP32K_EN1K (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN1K_Pos)
+#define OSC32KCTRL_OSCULP32K_CALIB_Pos 8 /**< \brief (OSC32KCTRL_OSCULP32K) Oscillator Calibration */
+#define OSC32KCTRL_OSCULP32K_CALIB_Msk (_U_(0x3F) << OSC32KCTRL_OSCULP32K_CALIB_Pos)
+#define OSC32KCTRL_OSCULP32K_CALIB(value) (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))
+#define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15 /**< \brief (OSC32KCTRL_OSCULP32K) Write Lock */
+#define OSC32KCTRL_OSCULP32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos)
+#define OSC32KCTRL_OSCULP32K_MASK _U_(0x0000BF06) /**< \brief (OSC32KCTRL_OSCULP32K) MASK Register */
+
+/** \brief OSC32KCTRL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO OSC32KCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
+ __IO OSC32KCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
+ __IO OSC32KCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
+ __I OSC32KCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
+ __IO OSC32KCTRL_RTCCTRL_Type RTCCTRL; /**< \brief Offset: 0x10 (R/W 8) RTC Clock Selection */
+ RoReg8 Reserved1[0x3];
+ __IO OSC32KCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
+ __IO OSC32KCTRL_CFDCTRL_Type CFDCTRL; /**< \brief Offset: 0x16 (R/W 8) Clock Failure Detector Control */
+ __IO OSC32KCTRL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x17 (R/W 8) Event Control */
+ RoReg8 Reserved2[0x4];
+ __IO OSC32KCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+} Osc32kctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_OSC32KCTRL_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/oscctrl.h b/sysmoOCTSIM/include/component/oscctrl.h
index 61cc042..039612d 100644
--- a/sysmoOCTSIM/include/component/oscctrl.h
+++ b/sysmoOCTSIM/include/component/oscctrl.h
@@ -1,793 +1,793 @@
-/**
- * \file
- *
- * \brief Component description for OSCCTRL
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_OSCCTRL_COMPONENT_
-#define _SAME54_OSCCTRL_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR OSCCTRL */
-/* ========================================================================== */
-/** \addtogroup SAME54_OSCCTRL Oscillators Control */
-/*@{*/
-
-#define OSCCTRL_U2401
-#define REV_OSCCTRL 0x100
-
-/* -------- OSCCTRL_EVCTRL : (OSCCTRL Offset: 0x00) (R/W 8) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t CFDEO0:1; /*!< bit: 0 Clock 0 Failure Detector Event Output Enable */
- uint8_t CFDEO1:1; /*!< bit: 1 Clock 1 Failure Detector Event Output Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CFDEO:2; /*!< bit: 0.. 1 Clock x Failure Detector Event Output Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} OSCCTRL_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_EVCTRL_OFFSET 0x00 /**< \brief (OSCCTRL_EVCTRL offset) Event Control */
-#define OSCCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_EVCTRL reset_value) Event Control */
-
-#define OSCCTRL_EVCTRL_CFDEO0_Pos 0 /**< \brief (OSCCTRL_EVCTRL) Clock 0 Failure Detector Event Output Enable */
-#define OSCCTRL_EVCTRL_CFDEO0 (_U_(1) << OSCCTRL_EVCTRL_CFDEO0_Pos)
-#define OSCCTRL_EVCTRL_CFDEO1_Pos 1 /**< \brief (OSCCTRL_EVCTRL) Clock 1 Failure Detector Event Output Enable */
-#define OSCCTRL_EVCTRL_CFDEO1 (_U_(1) << OSCCTRL_EVCTRL_CFDEO1_Pos)
-#define OSCCTRL_EVCTRL_CFDEO_Pos 0 /**< \brief (OSCCTRL_EVCTRL) Clock x Failure Detector Event Output Enable */
-#define OSCCTRL_EVCTRL_CFDEO_Msk (_U_(0x3) << OSCCTRL_EVCTRL_CFDEO_Pos)
-#define OSCCTRL_EVCTRL_CFDEO(value) (OSCCTRL_EVCTRL_CFDEO_Msk & ((value) << OSCCTRL_EVCTRL_CFDEO_Pos))
-#define OSCCTRL_EVCTRL_MASK _U_(0x03) /**< \brief (OSCCTRL_EVCTRL) MASK Register */
-
-/* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready Interrupt Enable */
- uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready Interrupt Enable */
- uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector Interrupt Enable */
- uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector Interrupt Enable */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */
- uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */
- uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */
- uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */
- uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise Interrupt Enable */
- uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall Interrupt Enable */
- uint32_t DPLL0LTO:1; /*!< bit: 18 DPLL0 Lock Timeout Interrupt Enable */
- uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise Interrupt Enable */
- uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall Interrupt Enable */
- uint32_t DPLL1LTO:1; /*!< bit: 26 DPLL1 Lock Timeout Interrupt Enable */
- uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready Interrupt Enable */
- uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector Interrupt Enable */
- uint32_t :28; /*!< bit: 4..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} OSCCTRL_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_INTENCLR_OFFSET 0x04 /**< \brief (OSCCTRL_INTENCLR offset) Interrupt Enable Clear */
-#define OSCCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define OSCCTRL_INTENCLR_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_INTENCLR) XOSC 0 Ready Interrupt Enable */
-#define OSCCTRL_INTENCLR_XOSCRDY0 (_U_(1) << OSCCTRL_INTENCLR_XOSCRDY0_Pos)
-#define OSCCTRL_INTENCLR_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_INTENCLR) XOSC 1 Ready Interrupt Enable */
-#define OSCCTRL_INTENCLR_XOSCRDY1 (_U_(1) << OSCCTRL_INTENCLR_XOSCRDY1_Pos)
-#define OSCCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENCLR) XOSC x Ready Interrupt Enable */
-#define OSCCTRL_INTENCLR_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCRDY_Pos)
-#define OSCCTRL_INTENCLR_XOSCRDY(value) (OSCCTRL_INTENCLR_XOSCRDY_Msk & ((value) << OSCCTRL_INTENCLR_XOSCRDY_Pos))
-#define OSCCTRL_INTENCLR_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_INTENCLR) XOSC 0 Clock Failure Detector Interrupt Enable */
-#define OSCCTRL_INTENCLR_XOSCFAIL0 (_U_(1) << OSCCTRL_INTENCLR_XOSCFAIL0_Pos)
-#define OSCCTRL_INTENCLR_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_INTENCLR) XOSC 1 Clock Failure Detector Interrupt Enable */
-#define OSCCTRL_INTENCLR_XOSCFAIL1 (_U_(1) << OSCCTRL_INTENCLR_XOSCFAIL1_Pos)
-#define OSCCTRL_INTENCLR_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_INTENCLR) XOSC x Clock Failure Detector Interrupt Enable */
-#define OSCCTRL_INTENCLR_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCFAIL_Pos)
-#define OSCCTRL_INTENCLR_XOSCFAIL(value) (OSCCTRL_INTENCLR_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENCLR_XOSCFAIL_Pos))
-#define OSCCTRL_INTENCLR_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable */
-#define OSCCTRL_INTENCLR_DFLLRDY (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRDY_Pos)
-#define OSCCTRL_INTENCLR_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */
-#define OSCCTRL_INTENCLR_DFLLOOB (_U_(0x1) << OSCCTRL_INTENCLR_DFLLOOB_Pos)
-#define OSCCTRL_INTENCLR_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */
-#define OSCCTRL_INTENCLR_DFLLLCKF (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKF_Pos)
-#define OSCCTRL_INTENCLR_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */
-#define OSCCTRL_INTENCLR_DFLLLCKC (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKC_Pos)
-#define OSCCTRL_INTENCLR_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */
-#define OSCCTRL_INTENCLR_DFLLRCS (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRCS_Pos)
-#define OSCCTRL_INTENCLR_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Rise Interrupt Enable */
-#define OSCCTRL_INTENCLR_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKR_Pos)
-#define OSCCTRL_INTENCLR_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Fall Interrupt Enable */
-#define OSCCTRL_INTENCLR_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKF_Pos)
-#define OSCCTRL_INTENCLR_DPLL0LTO_Pos 18 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Timeout Interrupt Enable */
-#define OSCCTRL_INTENCLR_DPLL0LTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LTO_Pos)
-#define OSCCTRL_INTENCLR_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
-#define OSCCTRL_INTENCLR_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LDRTO_Pos)
-#define OSCCTRL_INTENCLR_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Rise Interrupt Enable */
-#define OSCCTRL_INTENCLR_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKR_Pos)
-#define OSCCTRL_INTENCLR_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Fall Interrupt Enable */
-#define OSCCTRL_INTENCLR_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKF_Pos)
-#define OSCCTRL_INTENCLR_DPLL1LTO_Pos 26 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Timeout Interrupt Enable */
-#define OSCCTRL_INTENCLR_DPLL1LTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LTO_Pos)
-#define OSCCTRL_INTENCLR_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
-#define OSCCTRL_INTENCLR_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LDRTO_Pos)
-#define OSCCTRL_INTENCLR_MASK _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTENCLR) MASK Register */
-
-/* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready Interrupt Enable */
- uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready Interrupt Enable */
- uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector Interrupt Enable */
- uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector Interrupt Enable */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */
- uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */
- uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */
- uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */
- uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise Interrupt Enable */
- uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall Interrupt Enable */
- uint32_t DPLL0LTO:1; /*!< bit: 18 DPLL0 Lock Timeout Interrupt Enable */
- uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise Interrupt Enable */
- uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall Interrupt Enable */
- uint32_t DPLL1LTO:1; /*!< bit: 26 DPLL1 Lock Timeout Interrupt Enable */
- uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready Interrupt Enable */
- uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector Interrupt Enable */
- uint32_t :28; /*!< bit: 4..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} OSCCTRL_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_INTENSET_OFFSET 0x08 /**< \brief (OSCCTRL_INTENSET offset) Interrupt Enable Set */
-#define OSCCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENSET reset_value) Interrupt Enable Set */
-
-#define OSCCTRL_INTENSET_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_INTENSET) XOSC 0 Ready Interrupt Enable */
-#define OSCCTRL_INTENSET_XOSCRDY0 (_U_(1) << OSCCTRL_INTENSET_XOSCRDY0_Pos)
-#define OSCCTRL_INTENSET_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_INTENSET) XOSC 1 Ready Interrupt Enable */
-#define OSCCTRL_INTENSET_XOSCRDY1 (_U_(1) << OSCCTRL_INTENSET_XOSCRDY1_Pos)
-#define OSCCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENSET) XOSC x Ready Interrupt Enable */
-#define OSCCTRL_INTENSET_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCRDY_Pos)
-#define OSCCTRL_INTENSET_XOSCRDY(value) (OSCCTRL_INTENSET_XOSCRDY_Msk & ((value) << OSCCTRL_INTENSET_XOSCRDY_Pos))
-#define OSCCTRL_INTENSET_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_INTENSET) XOSC 0 Clock Failure Detector Interrupt Enable */
-#define OSCCTRL_INTENSET_XOSCFAIL0 (_U_(1) << OSCCTRL_INTENSET_XOSCFAIL0_Pos)
-#define OSCCTRL_INTENSET_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_INTENSET) XOSC 1 Clock Failure Detector Interrupt Enable */
-#define OSCCTRL_INTENSET_XOSCFAIL1 (_U_(1) << OSCCTRL_INTENSET_XOSCFAIL1_Pos)
-#define OSCCTRL_INTENSET_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_INTENSET) XOSC x Clock Failure Detector Interrupt Enable */
-#define OSCCTRL_INTENSET_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCFAIL_Pos)
-#define OSCCTRL_INTENSET_XOSCFAIL(value) (OSCCTRL_INTENSET_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENSET_XOSCFAIL_Pos))
-#define OSCCTRL_INTENSET_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable */
-#define OSCCTRL_INTENSET_DFLLRDY (_U_(0x1) << OSCCTRL_INTENSET_DFLLRDY_Pos)
-#define OSCCTRL_INTENSET_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */
-#define OSCCTRL_INTENSET_DFLLOOB (_U_(0x1) << OSCCTRL_INTENSET_DFLLOOB_Pos)
-#define OSCCTRL_INTENSET_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */
-#define OSCCTRL_INTENSET_DFLLLCKF (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKF_Pos)
-#define OSCCTRL_INTENSET_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */
-#define OSCCTRL_INTENSET_DFLLLCKC (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKC_Pos)
-#define OSCCTRL_INTENSET_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */
-#define OSCCTRL_INTENSET_DFLLRCS (_U_(0x1) << OSCCTRL_INTENSET_DFLLRCS_Pos)
-#define OSCCTRL_INTENSET_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Rise Interrupt Enable */
-#define OSCCTRL_INTENSET_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKR_Pos)
-#define OSCCTRL_INTENSET_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Fall Interrupt Enable */
-#define OSCCTRL_INTENSET_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKF_Pos)
-#define OSCCTRL_INTENSET_DPLL0LTO_Pos 18 /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Timeout Interrupt Enable */
-#define OSCCTRL_INTENSET_DPLL0LTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LTO_Pos)
-#define OSCCTRL_INTENSET_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_INTENSET) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
-#define OSCCTRL_INTENSET_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LDRTO_Pos)
-#define OSCCTRL_INTENSET_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Rise Interrupt Enable */
-#define OSCCTRL_INTENSET_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKR_Pos)
-#define OSCCTRL_INTENSET_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Fall Interrupt Enable */
-#define OSCCTRL_INTENSET_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKF_Pos)
-#define OSCCTRL_INTENSET_DPLL1LTO_Pos 26 /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Timeout Interrupt Enable */
-#define OSCCTRL_INTENSET_DPLL1LTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LTO_Pos)
-#define OSCCTRL_INTENSET_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_INTENSET) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
-#define OSCCTRL_INTENSET_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LDRTO_Pos)
-#define OSCCTRL_INTENSET_MASK _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTENSET) MASK Register */
-
-/* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x0C) (R/W 32) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready */
- __I uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready */
- __I uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector */
- __I uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector */
- __I uint32_t :4; /*!< bit: 4.. 7 Reserved */
- __I uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */
- __I uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */
- __I uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */
- __I uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */
- __I uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */
- __I uint32_t :3; /*!< bit: 13..15 Reserved */
- __I uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise */
- __I uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall */
- __I uint32_t DPLL0LTO:1; /*!< bit: 18 DPLL0 Lock Timeout */
- __I uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete */
- __I uint32_t :4; /*!< bit: 20..23 Reserved */
- __I uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise */
- __I uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall */
- __I uint32_t DPLL1LTO:1; /*!< bit: 26 DPLL1 Lock Timeout */
- __I uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete */
- __I uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready */
- __I uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector */
- __I uint32_t :28; /*!< bit: 4..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} OSCCTRL_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_INTFLAG_OFFSET 0x0C /**< \brief (OSCCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
-#define OSCCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define OSCCTRL_INTFLAG_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_INTFLAG) XOSC 0 Ready */
-#define OSCCTRL_INTFLAG_XOSCRDY0 (_U_(1) << OSCCTRL_INTFLAG_XOSCRDY0_Pos)
-#define OSCCTRL_INTFLAG_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_INTFLAG) XOSC 1 Ready */
-#define OSCCTRL_INTFLAG_XOSCRDY1 (_U_(1) << OSCCTRL_INTFLAG_XOSCRDY1_Pos)
-#define OSCCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTFLAG) XOSC x Ready */
-#define OSCCTRL_INTFLAG_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCRDY_Pos)
-#define OSCCTRL_INTFLAG_XOSCRDY(value) (OSCCTRL_INTFLAG_XOSCRDY_Msk & ((value) << OSCCTRL_INTFLAG_XOSCRDY_Pos))
-#define OSCCTRL_INTFLAG_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_INTFLAG) XOSC 0 Clock Failure Detector */
-#define OSCCTRL_INTFLAG_XOSCFAIL0 (_U_(1) << OSCCTRL_INTFLAG_XOSCFAIL0_Pos)
-#define OSCCTRL_INTFLAG_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_INTFLAG) XOSC 1 Clock Failure Detector */
-#define OSCCTRL_INTFLAG_XOSCFAIL1 (_U_(1) << OSCCTRL_INTFLAG_XOSCFAIL1_Pos)
-#define OSCCTRL_INTFLAG_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_INTFLAG) XOSC x Clock Failure Detector */
-#define OSCCTRL_INTFLAG_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCFAIL_Pos)
-#define OSCCTRL_INTFLAG_XOSCFAIL(value) (OSCCTRL_INTFLAG_XOSCFAIL_Msk & ((value) << OSCCTRL_INTFLAG_XOSCFAIL_Pos))
-#define OSCCTRL_INTFLAG_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTFLAG) DFLL Ready */
-#define OSCCTRL_INTFLAG_DFLLRDY (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRDY_Pos)
-#define OSCCTRL_INTFLAG_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTFLAG) DFLL Out Of Bounds */
-#define OSCCTRL_INTFLAG_DFLLOOB (_U_(0x1) << OSCCTRL_INTFLAG_DFLLOOB_Pos)
-#define OSCCTRL_INTFLAG_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Fine */
-#define OSCCTRL_INTFLAG_DFLLLCKF (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKF_Pos)
-#define OSCCTRL_INTFLAG_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Coarse */
-#define OSCCTRL_INTFLAG_DFLLLCKC (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKC_Pos)
-#define OSCCTRL_INTFLAG_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped */
-#define OSCCTRL_INTFLAG_DFLLRCS (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRCS_Pos)
-#define OSCCTRL_INTFLAG_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Rise */
-#define OSCCTRL_INTFLAG_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKR_Pos)
-#define OSCCTRL_INTFLAG_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Fall */
-#define OSCCTRL_INTFLAG_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKF_Pos)
-#define OSCCTRL_INTFLAG_DPLL0LTO_Pos 18 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Timeout */
-#define OSCCTRL_INTFLAG_DPLL0LTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LTO_Pos)
-#define OSCCTRL_INTFLAG_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Loop Divider Ratio Update Complete */
-#define OSCCTRL_INTFLAG_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LDRTO_Pos)
-#define OSCCTRL_INTFLAG_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Rise */
-#define OSCCTRL_INTFLAG_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKR_Pos)
-#define OSCCTRL_INTFLAG_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Fall */
-#define OSCCTRL_INTFLAG_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKF_Pos)
-#define OSCCTRL_INTFLAG_DPLL1LTO_Pos 26 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Timeout */
-#define OSCCTRL_INTFLAG_DPLL1LTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LTO_Pos)
-#define OSCCTRL_INTFLAG_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Loop Divider Ratio Update Complete */
-#define OSCCTRL_INTFLAG_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LDRTO_Pos)
-#define OSCCTRL_INTFLAG_MASK _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTFLAG) MASK Register */
-
-/* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x10) (R/ 32) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready */
- uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready */
- uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector */
- uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector */
- uint32_t XOSCCKSW0:1; /*!< bit: 4 XOSC 0 Clock Switch */
- uint32_t XOSCCKSW1:1; /*!< bit: 5 XOSC 1 Clock Switch */
- uint32_t :2; /*!< bit: 6.. 7 Reserved */
- uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */
- uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */
- uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */
- uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */
- uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise */
- uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall */
- uint32_t DPLL0TO:1; /*!< bit: 18 DPLL0 Timeout */
- uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise */
- uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall */
- uint32_t DPLL1TO:1; /*!< bit: 26 DPLL1 Timeout */
- uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready */
- uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector */
- uint32_t XOSCCKSW:2; /*!< bit: 4.. 5 XOSC x Clock Switch */
- uint32_t :26; /*!< bit: 6..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} OSCCTRL_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_STATUS_OFFSET 0x10 /**< \brief (OSCCTRL_STATUS offset) Status */
-#define OSCCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_STATUS reset_value) Status */
-
-#define OSCCTRL_STATUS_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_STATUS) XOSC 0 Ready */
-#define OSCCTRL_STATUS_XOSCRDY0 (_U_(1) << OSCCTRL_STATUS_XOSCRDY0_Pos)
-#define OSCCTRL_STATUS_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_STATUS) XOSC 1 Ready */
-#define OSCCTRL_STATUS_XOSCRDY1 (_U_(1) << OSCCTRL_STATUS_XOSCRDY1_Pos)
-#define OSCCTRL_STATUS_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_STATUS) XOSC x Ready */
-#define OSCCTRL_STATUS_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCRDY_Pos)
-#define OSCCTRL_STATUS_XOSCRDY(value) (OSCCTRL_STATUS_XOSCRDY_Msk & ((value) << OSCCTRL_STATUS_XOSCRDY_Pos))
-#define OSCCTRL_STATUS_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_STATUS) XOSC 0 Clock Failure Detector */
-#define OSCCTRL_STATUS_XOSCFAIL0 (_U_(1) << OSCCTRL_STATUS_XOSCFAIL0_Pos)
-#define OSCCTRL_STATUS_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_STATUS) XOSC 1 Clock Failure Detector */
-#define OSCCTRL_STATUS_XOSCFAIL1 (_U_(1) << OSCCTRL_STATUS_XOSCFAIL1_Pos)
-#define OSCCTRL_STATUS_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_STATUS) XOSC x Clock Failure Detector */
-#define OSCCTRL_STATUS_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCFAIL_Pos)
-#define OSCCTRL_STATUS_XOSCFAIL(value) (OSCCTRL_STATUS_XOSCFAIL_Msk & ((value) << OSCCTRL_STATUS_XOSCFAIL_Pos))
-#define OSCCTRL_STATUS_XOSCCKSW0_Pos 4 /**< \brief (OSCCTRL_STATUS) XOSC 0 Clock Switch */
-#define OSCCTRL_STATUS_XOSCCKSW0 (_U_(1) << OSCCTRL_STATUS_XOSCCKSW0_Pos)
-#define OSCCTRL_STATUS_XOSCCKSW1_Pos 5 /**< \brief (OSCCTRL_STATUS) XOSC 1 Clock Switch */
-#define OSCCTRL_STATUS_XOSCCKSW1 (_U_(1) << OSCCTRL_STATUS_XOSCCKSW1_Pos)
-#define OSCCTRL_STATUS_XOSCCKSW_Pos 4 /**< \brief (OSCCTRL_STATUS) XOSC x Clock Switch */
-#define OSCCTRL_STATUS_XOSCCKSW_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCCKSW_Pos)
-#define OSCCTRL_STATUS_XOSCCKSW(value) (OSCCTRL_STATUS_XOSCCKSW_Msk & ((value) << OSCCTRL_STATUS_XOSCCKSW_Pos))
-#define OSCCTRL_STATUS_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_STATUS) DFLL Ready */
-#define OSCCTRL_STATUS_DFLLRDY (_U_(0x1) << OSCCTRL_STATUS_DFLLRDY_Pos)
-#define OSCCTRL_STATUS_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_STATUS) DFLL Out Of Bounds */
-#define OSCCTRL_STATUS_DFLLOOB (_U_(0x1) << OSCCTRL_STATUS_DFLLOOB_Pos)
-#define OSCCTRL_STATUS_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_STATUS) DFLL Lock Fine */
-#define OSCCTRL_STATUS_DFLLLCKF (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKF_Pos)
-#define OSCCTRL_STATUS_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_STATUS) DFLL Lock Coarse */
-#define OSCCTRL_STATUS_DFLLLCKC (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKC_Pos)
-#define OSCCTRL_STATUS_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_STATUS) DFLL Reference Clock Stopped */
-#define OSCCTRL_STATUS_DFLLRCS (_U_(0x1) << OSCCTRL_STATUS_DFLLRCS_Pos)
-#define OSCCTRL_STATUS_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_STATUS) DPLL0 Lock Rise */
-#define OSCCTRL_STATUS_DPLL0LCKR (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKR_Pos)
-#define OSCCTRL_STATUS_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_STATUS) DPLL0 Lock Fall */
-#define OSCCTRL_STATUS_DPLL0LCKF (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKF_Pos)
-#define OSCCTRL_STATUS_DPLL0TO_Pos 18 /**< \brief (OSCCTRL_STATUS) DPLL0 Timeout */
-#define OSCCTRL_STATUS_DPLL0TO (_U_(0x1) << OSCCTRL_STATUS_DPLL0TO_Pos)
-#define OSCCTRL_STATUS_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_STATUS) DPLL0 Loop Divider Ratio Update Complete */
-#define OSCCTRL_STATUS_DPLL0LDRTO (_U_(0x1) << OSCCTRL_STATUS_DPLL0LDRTO_Pos)
-#define OSCCTRL_STATUS_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_STATUS) DPLL1 Lock Rise */
-#define OSCCTRL_STATUS_DPLL1LCKR (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKR_Pos)
-#define OSCCTRL_STATUS_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_STATUS) DPLL1 Lock Fall */
-#define OSCCTRL_STATUS_DPLL1LCKF (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKF_Pos)
-#define OSCCTRL_STATUS_DPLL1TO_Pos 26 /**< \brief (OSCCTRL_STATUS) DPLL1 Timeout */
-#define OSCCTRL_STATUS_DPLL1TO (_U_(0x1) << OSCCTRL_STATUS_DPLL1TO_Pos)
-#define OSCCTRL_STATUS_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_STATUS) DPLL1 Loop Divider Ratio Update Complete */
-#define OSCCTRL_STATUS_DPLL1LDRTO (_U_(0x1) << OSCCTRL_STATUS_DPLL1LDRTO_Pos)
-#define OSCCTRL_STATUS_MASK _U_(0x0F0F1F3F) /**< \brief (OSCCTRL_STATUS) MASK Register */
-
-/* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x14) (R/W 32) External Multipurpose Crystal Oscillator Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
- uint32_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
- uint32_t :3; /*!< bit: 3.. 5 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint32_t LOWBUFGAIN:1; /*!< bit: 8 Low Buffer Gain Enable */
- uint32_t IPTAT:2; /*!< bit: 9..10 Oscillator Current Reference */
- uint32_t IMULT:4; /*!< bit: 11..14 Oscillator Current Multiplier */
- uint32_t ENALC:1; /*!< bit: 15 Automatic Loop Control Enable */
- uint32_t CFDEN:1; /*!< bit: 16 Clock Failure Detector Enable */
- uint32_t SWBEN:1; /*!< bit: 17 Xosc Clock Switch Enable */
- uint32_t :2; /*!< bit: 18..19 Reserved */
- uint32_t STARTUP:4; /*!< bit: 20..23 Start-Up Time */
- uint32_t CFDPRESC:4; /*!< bit: 24..27 Clock Failure Detector Prescaler */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} OSCCTRL_XOSCCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_XOSCCTRL_OFFSET 0x14 /**< \brief (OSCCTRL_XOSCCTRL offset) External Multipurpose Crystal Oscillator Control */
-#define OSCCTRL_XOSCCTRL_RESETVALUE _U_(0x00000080) /**< \brief (OSCCTRL_XOSCCTRL reset_value) External Multipurpose Crystal Oscillator Control */
-
-#define OSCCTRL_XOSCCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Enable */
-#define OSCCTRL_XOSCCTRL_ENABLE (_U_(0x1) << OSCCTRL_XOSCCTRL_ENABLE_Pos)
-#define OSCCTRL_XOSCCTRL_XTALEN_Pos 2 /**< \brief (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable */
-#define OSCCTRL_XOSCCTRL_XTALEN (_U_(0x1) << OSCCTRL_XOSCCTRL_XTALEN_Pos)
-#define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_XOSCCTRL) Run in Standby */
-#define OSCCTRL_XOSCCTRL_RUNSTDBY (_U_(0x1) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos)
-#define OSCCTRL_XOSCCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_XOSCCTRL) On Demand Control */
-#define OSCCTRL_XOSCCTRL_ONDEMAND (_U_(0x1) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos)
-#define OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos 8 /**< \brief (OSCCTRL_XOSCCTRL) Low Buffer Gain Enable */
-#define OSCCTRL_XOSCCTRL_LOWBUFGAIN (_U_(0x1) << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos)
-#define OSCCTRL_XOSCCTRL_IPTAT_Pos 9 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Current Reference */
-#define OSCCTRL_XOSCCTRL_IPTAT_Msk (_U_(0x3) << OSCCTRL_XOSCCTRL_IPTAT_Pos)
-#define OSCCTRL_XOSCCTRL_IPTAT(value) (OSCCTRL_XOSCCTRL_IPTAT_Msk & ((value) << OSCCTRL_XOSCCTRL_IPTAT_Pos))
-#define OSCCTRL_XOSCCTRL_IMULT_Pos 11 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Current Multiplier */
-#define OSCCTRL_XOSCCTRL_IMULT_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_IMULT_Pos)
-#define OSCCTRL_XOSCCTRL_IMULT(value) (OSCCTRL_XOSCCTRL_IMULT_Msk & ((value) << OSCCTRL_XOSCCTRL_IMULT_Pos))
-#define OSCCTRL_XOSCCTRL_ENALC_Pos 15 /**< \brief (OSCCTRL_XOSCCTRL) Automatic Loop Control Enable */
-#define OSCCTRL_XOSCCTRL_ENALC (_U_(0x1) << OSCCTRL_XOSCCTRL_ENALC_Pos)
-#define OSCCTRL_XOSCCTRL_CFDEN_Pos 16 /**< \brief (OSCCTRL_XOSCCTRL) Clock Failure Detector Enable */
-#define OSCCTRL_XOSCCTRL_CFDEN (_U_(0x1) << OSCCTRL_XOSCCTRL_CFDEN_Pos)
-#define OSCCTRL_XOSCCTRL_SWBEN_Pos 17 /**< \brief (OSCCTRL_XOSCCTRL) Xosc Clock Switch Enable */
-#define OSCCTRL_XOSCCTRL_SWBEN (_U_(0x1) << OSCCTRL_XOSCCTRL_SWBEN_Pos)
-#define OSCCTRL_XOSCCTRL_STARTUP_Pos 20 /**< \brief (OSCCTRL_XOSCCTRL) Start-Up Time */
-#define OSCCTRL_XOSCCTRL_STARTUP_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_STARTUP_Pos)
-#define OSCCTRL_XOSCCTRL_STARTUP(value) (OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos))
-#define OSCCTRL_XOSCCTRL_CFDPRESC_Pos 24 /**< \brief (OSCCTRL_XOSCCTRL) Clock Failure Detector Prescaler */
-#define OSCCTRL_XOSCCTRL_CFDPRESC_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos)
-#define OSCCTRL_XOSCCTRL_CFDPRESC(value) (OSCCTRL_XOSCCTRL_CFDPRESC_Msk & ((value) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos))
-#define OSCCTRL_XOSCCTRL_MASK _U_(0x0FF3FFC6) /**< \brief (OSCCTRL_XOSCCTRL) MASK Register */
-
-/* -------- OSCCTRL_DFLLCTRLA : (OSCCTRL Offset: 0x1C) (R/W 8) DFLL48M Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t :1; /*!< bit: 0 Reserved */
- uint8_t ENABLE:1; /*!< bit: 1 DFLL Enable */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} OSCCTRL_DFLLCTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DFLLCTRLA_OFFSET 0x1C /**< \brief (OSCCTRL_DFLLCTRLA offset) DFLL48M Control A */
-#define OSCCTRL_DFLLCTRLA_RESETVALUE _U_(0x82) /**< \brief (OSCCTRL_DFLLCTRLA reset_value) DFLL48M Control A */
-
-#define OSCCTRL_DFLLCTRLA_ENABLE_Pos 1 /**< \brief (OSCCTRL_DFLLCTRLA) DFLL Enable */
-#define OSCCTRL_DFLLCTRLA_ENABLE (_U_(0x1) << OSCCTRL_DFLLCTRLA_ENABLE_Pos)
-#define OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DFLLCTRLA) Run in Standby */
-#define OSCCTRL_DFLLCTRLA_RUNSTDBY (_U_(0x1) << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos)
-#define OSCCTRL_DFLLCTRLA_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DFLLCTRLA) On Demand Control */
-#define OSCCTRL_DFLLCTRLA_ONDEMAND (_U_(0x1) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos)
-#define OSCCTRL_DFLLCTRLA_MASK _U_(0xC2) /**< \brief (OSCCTRL_DFLLCTRLA) MASK Register */
-
-/* -------- OSCCTRL_DFLLCTRLB : (OSCCTRL Offset: 0x20) (R/W 8) DFLL48M Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t MODE:1; /*!< bit: 0 Operating Mode Selection */
- uint8_t STABLE:1; /*!< bit: 1 Stable DFLL Frequency */
- uint8_t LLAW:1; /*!< bit: 2 Lose Lock After Wake */
- uint8_t USBCRM:1; /*!< bit: 3 USB Clock Recovery Mode */
- uint8_t CCDIS:1; /*!< bit: 4 Chill Cycle Disable */
- uint8_t QLDIS:1; /*!< bit: 5 Quick Lock Disable */
- uint8_t BPLCKC:1; /*!< bit: 6 Bypass Coarse Lock */
- uint8_t WAITLOCK:1; /*!< bit: 7 Wait Lock */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} OSCCTRL_DFLLCTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DFLLCTRLB_OFFSET 0x20 /**< \brief (OSCCTRL_DFLLCTRLB offset) DFLL48M Control B */
-#define OSCCTRL_DFLLCTRLB_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DFLLCTRLB reset_value) DFLL48M Control B */
-
-#define OSCCTRL_DFLLCTRLB_MODE_Pos 0 /**< \brief (OSCCTRL_DFLLCTRLB) Operating Mode Selection */
-#define OSCCTRL_DFLLCTRLB_MODE (_U_(0x1) << OSCCTRL_DFLLCTRLB_MODE_Pos)
-#define OSCCTRL_DFLLCTRLB_STABLE_Pos 1 /**< \brief (OSCCTRL_DFLLCTRLB) Stable DFLL Frequency */
-#define OSCCTRL_DFLLCTRLB_STABLE (_U_(0x1) << OSCCTRL_DFLLCTRLB_STABLE_Pos)
-#define OSCCTRL_DFLLCTRLB_LLAW_Pos 2 /**< \brief (OSCCTRL_DFLLCTRLB) Lose Lock After Wake */
-#define OSCCTRL_DFLLCTRLB_LLAW (_U_(0x1) << OSCCTRL_DFLLCTRLB_LLAW_Pos)
-#define OSCCTRL_DFLLCTRLB_USBCRM_Pos 3 /**< \brief (OSCCTRL_DFLLCTRLB) USB Clock Recovery Mode */
-#define OSCCTRL_DFLLCTRLB_USBCRM (_U_(0x1) << OSCCTRL_DFLLCTRLB_USBCRM_Pos)
-#define OSCCTRL_DFLLCTRLB_CCDIS_Pos 4 /**< \brief (OSCCTRL_DFLLCTRLB) Chill Cycle Disable */
-#define OSCCTRL_DFLLCTRLB_CCDIS (_U_(0x1) << OSCCTRL_DFLLCTRLB_CCDIS_Pos)
-#define OSCCTRL_DFLLCTRLB_QLDIS_Pos 5 /**< \brief (OSCCTRL_DFLLCTRLB) Quick Lock Disable */
-#define OSCCTRL_DFLLCTRLB_QLDIS (_U_(0x1) << OSCCTRL_DFLLCTRLB_QLDIS_Pos)
-#define OSCCTRL_DFLLCTRLB_BPLCKC_Pos 6 /**< \brief (OSCCTRL_DFLLCTRLB) Bypass Coarse Lock */
-#define OSCCTRL_DFLLCTRLB_BPLCKC (_U_(0x1) << OSCCTRL_DFLLCTRLB_BPLCKC_Pos)
-#define OSCCTRL_DFLLCTRLB_WAITLOCK_Pos 7 /**< \brief (OSCCTRL_DFLLCTRLB) Wait Lock */
-#define OSCCTRL_DFLLCTRLB_WAITLOCK (_U_(0x1) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos)
-#define OSCCTRL_DFLLCTRLB_MASK _U_(0xFF) /**< \brief (OSCCTRL_DFLLCTRLB) MASK Register */
-
-/* -------- OSCCTRL_DFLLVAL : (OSCCTRL Offset: 0x24) (R/W 32) DFLL48M Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t FINE:8; /*!< bit: 0.. 7 Fine Value */
- uint32_t :2; /*!< bit: 8.. 9 Reserved */
- uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
- uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} OSCCTRL_DFLLVAL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DFLLVAL_OFFSET 0x24 /**< \brief (OSCCTRL_DFLLVAL offset) DFLL48M Value */
-#define OSCCTRL_DFLLVAL_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DFLLVAL reset_value) DFLL48M Value */
-
-#define OSCCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (OSCCTRL_DFLLVAL) Fine Value */
-#define OSCCTRL_DFLLVAL_FINE_Msk (_U_(0xFF) << OSCCTRL_DFLLVAL_FINE_Pos)
-#define OSCCTRL_DFLLVAL_FINE(value) (OSCCTRL_DFLLVAL_FINE_Msk & ((value) << OSCCTRL_DFLLVAL_FINE_Pos))
-#define OSCCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (OSCCTRL_DFLLVAL) Coarse Value */
-#define OSCCTRL_DFLLVAL_COARSE_Msk (_U_(0x3F) << OSCCTRL_DFLLVAL_COARSE_Pos)
-#define OSCCTRL_DFLLVAL_COARSE(value) (OSCCTRL_DFLLVAL_COARSE_Msk & ((value) << OSCCTRL_DFLLVAL_COARSE_Pos))
-#define OSCCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (OSCCTRL_DFLLVAL) Multiplication Ratio Difference */
-#define OSCCTRL_DFLLVAL_DIFF_Msk (_U_(0xFFFF) << OSCCTRL_DFLLVAL_DIFF_Pos)
-#define OSCCTRL_DFLLVAL_DIFF(value) (OSCCTRL_DFLLVAL_DIFF_Msk & ((value) << OSCCTRL_DFLLVAL_DIFF_Pos))
-#define OSCCTRL_DFLLVAL_MASK _U_(0xFFFFFCFF) /**< \brief (OSCCTRL_DFLLVAL) MASK Register */
-
-/* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x28) (R/W 32) DFLL48M Multiplier -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
- uint32_t FSTEP:8; /*!< bit: 16..23 Fine Maximum Step */
- uint32_t :2; /*!< bit: 24..25 Reserved */
- uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} OSCCTRL_DFLLMUL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DFLLMUL_OFFSET 0x28 /**< \brief (OSCCTRL_DFLLMUL offset) DFLL48M Multiplier */
-#define OSCCTRL_DFLLMUL_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DFLLMUL reset_value) DFLL48M Multiplier */
-
-#define OSCCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (OSCCTRL_DFLLMUL) DFLL Multiply Factor */
-#define OSCCTRL_DFLLMUL_MUL_Msk (_U_(0xFFFF) << OSCCTRL_DFLLMUL_MUL_Pos)
-#define OSCCTRL_DFLLMUL_MUL(value) (OSCCTRL_DFLLMUL_MUL_Msk & ((value) << OSCCTRL_DFLLMUL_MUL_Pos))
-#define OSCCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (OSCCTRL_DFLLMUL) Fine Maximum Step */
-#define OSCCTRL_DFLLMUL_FSTEP_Msk (_U_(0xFF) << OSCCTRL_DFLLMUL_FSTEP_Pos)
-#define OSCCTRL_DFLLMUL_FSTEP(value) (OSCCTRL_DFLLMUL_FSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_FSTEP_Pos))
-#define OSCCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (OSCCTRL_DFLLMUL) Coarse Maximum Step */
-#define OSCCTRL_DFLLMUL_CSTEP_Msk (_U_(0x3F) << OSCCTRL_DFLLMUL_CSTEP_Pos)
-#define OSCCTRL_DFLLMUL_CSTEP(value) (OSCCTRL_DFLLMUL_CSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_CSTEP_Pos))
-#define OSCCTRL_DFLLMUL_MASK _U_(0xFCFFFFFF) /**< \brief (OSCCTRL_DFLLMUL) MASK Register */
-
-/* -------- OSCCTRL_DFLLSYNC : (OSCCTRL Offset: 0x2C) (R/W 8) DFLL48M Synchronization -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t :1; /*!< bit: 0 Reserved */
- uint8_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */
- uint8_t DFLLCTRLB:1; /*!< bit: 2 DFLLCTRLB Synchronization Busy */
- uint8_t DFLLVAL:1; /*!< bit: 3 DFLLVAL Synchronization Busy */
- uint8_t DFLLMUL:1; /*!< bit: 4 DFLLMUL Synchronization Busy */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} OSCCTRL_DFLLSYNC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DFLLSYNC_OFFSET 0x2C /**< \brief (OSCCTRL_DFLLSYNC offset) DFLL48M Synchronization */
-#define OSCCTRL_DFLLSYNC_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */
-
-#define OSCCTRL_DFLLSYNC_ENABLE_Pos 1 /**< \brief (OSCCTRL_DFLLSYNC) ENABLE Synchronization Busy */
-#define OSCCTRL_DFLLSYNC_ENABLE (_U_(0x1) << OSCCTRL_DFLLSYNC_ENABLE_Pos)
-#define OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos 2 /**< \brief (OSCCTRL_DFLLSYNC) DFLLCTRLB Synchronization Busy */
-#define OSCCTRL_DFLLSYNC_DFLLCTRLB (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos)
-#define OSCCTRL_DFLLSYNC_DFLLVAL_Pos 3 /**< \brief (OSCCTRL_DFLLSYNC) DFLLVAL Synchronization Busy */
-#define OSCCTRL_DFLLSYNC_DFLLVAL (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLVAL_Pos)
-#define OSCCTRL_DFLLSYNC_DFLLMUL_Pos 4 /**< \brief (OSCCTRL_DFLLSYNC) DFLLMUL Synchronization Busy */
-#define OSCCTRL_DFLLSYNC_DFLLMUL (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLMUL_Pos)
-#define OSCCTRL_DFLLSYNC_MASK _U_(0x1E) /**< \brief (OSCCTRL_DFLLSYNC) MASK Register */
-
-/* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x30) (R/W 8) DPLL DPLL Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t :1; /*!< bit: 0 Reserved */
- uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} OSCCTRL_DPLLCTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DPLLCTRLA_OFFSET 0x30 /**< \brief (OSCCTRL_DPLLCTRLA offset) DPLL Control A */
-#define OSCCTRL_DPLLCTRLA_RESETVALUE _U_(0x80) /**< \brief (OSCCTRL_DPLLCTRLA reset_value) DPLL Control A */
-
-#define OSCCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLCTRLA) DPLL Enable */
-#define OSCCTRL_DPLLCTRLA_ENABLE (_U_(0x1) << OSCCTRL_DPLLCTRLA_ENABLE_Pos)
-#define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DPLLCTRLA) Run in Standby */
-#define OSCCTRL_DPLLCTRLA_RUNSTDBY (_U_(0x1) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)
-#define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DPLLCTRLA) On Demand Control */
-#define OSCCTRL_DPLLCTRLA_ONDEMAND (_U_(0x1) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos)
-#define OSCCTRL_DPLLCTRLA_MASK _U_(0xC2) /**< \brief (OSCCTRL_DPLLCTRLA) MASK Register */
-
-/* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x34) (R/W 32) DPLL DPLL Ratio Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t LDR:13; /*!< bit: 0..12 Loop Divider Ratio */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t LDRFRAC:5; /*!< bit: 16..20 Loop Divider Ratio Fractional Part */
- uint32_t :11; /*!< bit: 21..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} OSCCTRL_DPLLRATIO_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DPLLRATIO_OFFSET 0x34 /**< \brief (OSCCTRL_DPLLRATIO offset) DPLL Ratio Control */
-#define OSCCTRL_DPLLRATIO_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
-
-#define OSCCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio */
-#define OSCCTRL_DPLLRATIO_LDR_Msk (_U_(0x1FFF) << OSCCTRL_DPLLRATIO_LDR_Pos)
-#define OSCCTRL_DPLLRATIO_LDR(value) (OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos))
-#define OSCCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
-#define OSCCTRL_DPLLRATIO_LDRFRAC_Msk (_U_(0x1F) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos)
-#define OSCCTRL_DPLLRATIO_LDRFRAC(value) (OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos))
-#define OSCCTRL_DPLLRATIO_MASK _U_(0x001F1FFF) /**< \brief (OSCCTRL_DPLLRATIO) MASK Register */
-
-/* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x38) (R/W 32) DPLL DPLL Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t FILTER:4; /*!< bit: 0.. 3 Proportional Integral Filter Selection */
- uint32_t WUF:1; /*!< bit: 4 Wake Up Fast */
- uint32_t REFCLK:3; /*!< bit: 5.. 7 Reference Clock Selection */
- uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
- uint32_t LBYPASS:1; /*!< bit: 11 Lock Bypass */
- uint32_t DCOFILTER:3; /*!< bit: 12..14 Sigma-Delta DCO Filter Selection */
- uint32_t DCOEN:1; /*!< bit: 15 DCO Filter Enable */
- uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} OSCCTRL_DPLLCTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DPLLCTRLB_OFFSET 0x38 /**< \brief (OSCCTRL_DPLLCTRLB offset) DPLL Control B */
-#define OSCCTRL_DPLLCTRLB_RESETVALUE _U_(0x00000020) /**< \brief (OSCCTRL_DPLLCTRLB reset_value) DPLL Control B */
-
-#define OSCCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
-#define OSCCTRL_DPLLCTRLB_FILTER_Msk (_U_(0xF) << OSCCTRL_DPLLCTRLB_FILTER_Pos)
-#define OSCCTRL_DPLLCTRLB_FILTER(value) (OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos))
-#define OSCCTRL_DPLLCTRLB_WUF_Pos 4 /**< \brief (OSCCTRL_DPLLCTRLB) Wake Up Fast */
-#define OSCCTRL_DPLLCTRLB_WUF (_U_(0x1) << OSCCTRL_DPLLCTRLB_WUF_Pos)
-#define OSCCTRL_DPLLCTRLB_REFCLK_Pos 5 /**< \brief (OSCCTRL_DPLLCTRLB) Reference Clock Selection */
-#define OSCCTRL_DPLLCTRLB_REFCLK_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
-#define OSCCTRL_DPLLCTRLB_REFCLK(value) (OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos))
-#define OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val _U_(0x0) /**< \brief (OSCCTRL_DPLLCTRLB) Dedicated GCLK clock reference */
-#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val _U_(0x1) /**< \brief (OSCCTRL_DPLLCTRLB) XOSC32K clock reference */
-#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val _U_(0x2) /**< \brief (OSCCTRL_DPLLCTRLB) XOSC0 clock reference */
-#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val _U_(0x3) /**< \brief (OSCCTRL_DPLLCTRLB) XOSC1 clock reference */
-#define OSCCTRL_DPLLCTRLB_REFCLK_GCLK (OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
-#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
-#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
-#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
-#define OSCCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Time */
-#define OSCCTRL_DPLLCTRLB_LTIME_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_LTIME_Pos)
-#define OSCCTRL_DPLLCTRLB_LTIME(value) (OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos))
-#define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val _U_(0x0) /**< \brief (OSCCTRL_DPLLCTRLB) No time-out. Automatic lock */
-#define OSCCTRL_DPLLCTRLB_LTIME_800US_Val _U_(0x4) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 800us */
-#define OSCCTRL_DPLLCTRLB_LTIME_900US_Val _U_(0x5) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 900us */
-#define OSCCTRL_DPLLCTRLB_LTIME_1MS_Val _U_(0x6) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1ms */
-#define OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val _U_(0x7) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1.1ms */
-#define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT (OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
-#define OSCCTRL_DPLLCTRLB_LTIME_800US (OSCCTRL_DPLLCTRLB_LTIME_800US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
-#define OSCCTRL_DPLLCTRLB_LTIME_900US (OSCCTRL_DPLLCTRLB_LTIME_900US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
-#define OSCCTRL_DPLLCTRLB_LTIME_1MS (OSCCTRL_DPLLCTRLB_LTIME_1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
-#define OSCCTRL_DPLLCTRLB_LTIME_1P1MS (OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
-#define OSCCTRL_DPLLCTRLB_LBYPASS_Pos 11 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Bypass */
-#define OSCCTRL_DPLLCTRLB_LBYPASS (_U_(0x1) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos)
-#define OSCCTRL_DPLLCTRLB_DCOFILTER_Pos 12 /**< \brief (OSCCTRL_DPLLCTRLB) Sigma-Delta DCO Filter Selection */
-#define OSCCTRL_DPLLCTRLB_DCOFILTER_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos)
-#define OSCCTRL_DPLLCTRLB_DCOFILTER(value) (OSCCTRL_DPLLCTRLB_DCOFILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos))
-#define OSCCTRL_DPLLCTRLB_DCOEN_Pos 15 /**< \brief (OSCCTRL_DPLLCTRLB) DCO Filter Enable */
-#define OSCCTRL_DPLLCTRLB_DCOEN (_U_(0x1) << OSCCTRL_DPLLCTRLB_DCOEN_Pos)
-#define OSCCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (OSCCTRL_DPLLCTRLB) Clock Divider */
-#define OSCCTRL_DPLLCTRLB_DIV_Msk (_U_(0x7FF) << OSCCTRL_DPLLCTRLB_DIV_Pos)
-#define OSCCTRL_DPLLCTRLB_DIV(value) (OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos))
-#define OSCCTRL_DPLLCTRLB_MASK _U_(0x07FFFFFF) /**< \brief (OSCCTRL_DPLLCTRLB) MASK Register */
-
-/* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x3C) (R/ 32) DPLL DPLL Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 DPLL Enable Synchronization Status */
- uint32_t DPLLRATIO:1; /*!< bit: 2 DPLL Loop Divider Ratio Synchronization Status */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} OSCCTRL_DPLLSYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DPLLSYNCBUSY_OFFSET 0x3C /**< \brief (OSCCTRL_DPLLSYNCBUSY offset) DPLL Synchronization Busy */
-#define OSCCTRL_DPLLSYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLSYNCBUSY reset_value) DPLL Synchronization Busy */
-
-#define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status */
-#define OSCCTRL_DPLLSYNCBUSY_ENABLE (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos)
-#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos 2 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Loop Divider Ratio Synchronization Status */
-#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos)
-#define OSCCTRL_DPLLSYNCBUSY_MASK _U_(0x00000006) /**< \brief (OSCCTRL_DPLLSYNCBUSY) MASK Register */
-
-/* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x40) (R/ 32) DPLL DPLL Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
- uint32_t CLKRDY:1; /*!< bit: 1 DPLL Clock Ready */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} OSCCTRL_DPLLSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DPLLSTATUS_OFFSET 0x40 /**< \brief (OSCCTRL_DPLLSTATUS offset) DPLL Status */
-#define OSCCTRL_DPLLSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLSTATUS reset_value) DPLL Status */
-
-#define OSCCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Lock Status */
-#define OSCCTRL_DPLLSTATUS_LOCK (_U_(0x1) << OSCCTRL_DPLLSTATUS_LOCK_Pos)
-#define OSCCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Clock Ready */
-#define OSCCTRL_DPLLSTATUS_CLKRDY (_U_(0x1) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos)
-#define OSCCTRL_DPLLSTATUS_MASK _U_(0x00000003) /**< \brief (OSCCTRL_DPLLSTATUS) MASK Register */
-
-/** \brief OscctrlDpll hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO OSCCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x00 (R/W 8) DPLL Control A */
- RoReg8 Reserved1[0x3];
- __IO OSCCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x04 (R/W 32) DPLL Ratio Control */
- __IO OSCCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x08 (R/W 32) DPLL Control B */
- __I OSCCTRL_DPLLSYNCBUSY_Type DPLLSYNCBUSY; /**< \brief Offset: 0x0C (R/ 32) DPLL Synchronization Busy */
- __I OSCCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x10 (R/ 32) DPLL Status */
-} OscctrlDpll;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief OSCCTRL hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO OSCCTRL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x00 (R/W 8) Event Control */
- RoReg8 Reserved1[0x3];
- __IO OSCCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Clear */
- __IO OSCCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Set */
- __IO OSCCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 32) Interrupt Flag Status and Clear */
- __I OSCCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x10 (R/ 32) Status */
- __IO OSCCTRL_XOSCCTRL_Type XOSCCTRL[2]; /**< \brief Offset: 0x14 (R/W 32) External Multipurpose Crystal Oscillator Control */
- __IO OSCCTRL_DFLLCTRLA_Type DFLLCTRLA; /**< \brief Offset: 0x1C (R/W 8) DFLL48M Control A */
- RoReg8 Reserved2[0x3];
- __IO OSCCTRL_DFLLCTRLB_Type DFLLCTRLB; /**< \brief Offset: 0x20 (R/W 8) DFLL48M Control B */
- RoReg8 Reserved3[0x3];
- __IO OSCCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x24 (R/W 32) DFLL48M Value */
- __IO OSCCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Multiplier */
- __IO OSCCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x2C (R/W 8) DFLL48M Synchronization */
- RoReg8 Reserved4[0x3];
- OscctrlDpll Dpll[2]; /**< \brief Offset: 0x30 OscctrlDpll groups [DPLLS_NUM] */
-} Oscctrl;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_OSCCTRL_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for OSCCTRL
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_OSCCTRL_COMPONENT_
+#define _SAME54_OSCCTRL_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR OSCCTRL */
+/* ========================================================================== */
+/** \addtogroup SAME54_OSCCTRL Oscillators Control */
+/*@{*/
+
+#define OSCCTRL_U2401
+#define REV_OSCCTRL 0x100
+
+/* -------- OSCCTRL_EVCTRL : (OSCCTRL Offset: 0x00) (R/W 8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CFDEO0:1; /*!< bit: 0 Clock 0 Failure Detector Event Output Enable */
+ uint8_t CFDEO1:1; /*!< bit: 1 Clock 1 Failure Detector Event Output Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CFDEO:2; /*!< bit: 0.. 1 Clock x Failure Detector Event Output Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} OSCCTRL_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_EVCTRL_OFFSET 0x00 /**< \brief (OSCCTRL_EVCTRL offset) Event Control */
+#define OSCCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_EVCTRL reset_value) Event Control */
+
+#define OSCCTRL_EVCTRL_CFDEO0_Pos 0 /**< \brief (OSCCTRL_EVCTRL) Clock 0 Failure Detector Event Output Enable */
+#define OSCCTRL_EVCTRL_CFDEO0 (_U_(1) << OSCCTRL_EVCTRL_CFDEO0_Pos)
+#define OSCCTRL_EVCTRL_CFDEO1_Pos 1 /**< \brief (OSCCTRL_EVCTRL) Clock 1 Failure Detector Event Output Enable */
+#define OSCCTRL_EVCTRL_CFDEO1 (_U_(1) << OSCCTRL_EVCTRL_CFDEO1_Pos)
+#define OSCCTRL_EVCTRL_CFDEO_Pos 0 /**< \brief (OSCCTRL_EVCTRL) Clock x Failure Detector Event Output Enable */
+#define OSCCTRL_EVCTRL_CFDEO_Msk (_U_(0x3) << OSCCTRL_EVCTRL_CFDEO_Pos)
+#define OSCCTRL_EVCTRL_CFDEO(value) (OSCCTRL_EVCTRL_CFDEO_Msk & ((value) << OSCCTRL_EVCTRL_CFDEO_Pos))
+#define OSCCTRL_EVCTRL_MASK _U_(0x03) /**< \brief (OSCCTRL_EVCTRL) MASK Register */
+
+/* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready Interrupt Enable */
+ uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready Interrupt Enable */
+ uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector Interrupt Enable */
+ uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector Interrupt Enable */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */
+ uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */
+ uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */
+ uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */
+ uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise Interrupt Enable */
+ uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall Interrupt Enable */
+ uint32_t DPLL0LTO:1; /*!< bit: 18 DPLL0 Lock Timeout Interrupt Enable */
+ uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise Interrupt Enable */
+ uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall Interrupt Enable */
+ uint32_t DPLL1LTO:1; /*!< bit: 26 DPLL1 Lock Timeout Interrupt Enable */
+ uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready Interrupt Enable */
+ uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector Interrupt Enable */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_INTENCLR_OFFSET 0x04 /**< \brief (OSCCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define OSCCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define OSCCTRL_INTENCLR_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_INTENCLR) XOSC 0 Ready Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCRDY0 (_U_(1) << OSCCTRL_INTENCLR_XOSCRDY0_Pos)
+#define OSCCTRL_INTENCLR_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_INTENCLR) XOSC 1 Ready Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCRDY1 (_U_(1) << OSCCTRL_INTENCLR_XOSCRDY1_Pos)
+#define OSCCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENCLR) XOSC x Ready Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCRDY_Pos)
+#define OSCCTRL_INTENCLR_XOSCRDY(value) (OSCCTRL_INTENCLR_XOSCRDY_Msk & ((value) << OSCCTRL_INTENCLR_XOSCRDY_Pos))
+#define OSCCTRL_INTENCLR_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_INTENCLR) XOSC 0 Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCFAIL0 (_U_(1) << OSCCTRL_INTENCLR_XOSCFAIL0_Pos)
+#define OSCCTRL_INTENCLR_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_INTENCLR) XOSC 1 Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCFAIL1 (_U_(1) << OSCCTRL_INTENCLR_XOSCFAIL1_Pos)
+#define OSCCTRL_INTENCLR_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_INTENCLR) XOSC x Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCFAIL_Pos)
+#define OSCCTRL_INTENCLR_XOSCFAIL(value) (OSCCTRL_INTENCLR_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENCLR_XOSCFAIL_Pos))
+#define OSCCTRL_INTENCLR_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLRDY (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRDY_Pos)
+#define OSCCTRL_INTENCLR_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLOOB (_U_(0x1) << OSCCTRL_INTENCLR_DFLLOOB_Pos)
+#define OSCCTRL_INTENCLR_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLLCKF (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKF_Pos)
+#define OSCCTRL_INTENCLR_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLLCKC (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKC_Pos)
+#define OSCCTRL_INTENCLR_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLRCS (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRCS_Pos)
+#define OSCCTRL_INTENCLR_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Rise Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKR_Pos)
+#define OSCCTRL_INTENCLR_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Fall Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKF_Pos)
+#define OSCCTRL_INTENCLR_DPLL0LTO_Pos 18 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Timeout Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL0LTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LTO_Pos)
+#define OSCCTRL_INTENCLR_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LDRTO_Pos)
+#define OSCCTRL_INTENCLR_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Rise Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKR_Pos)
+#define OSCCTRL_INTENCLR_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Fall Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKF_Pos)
+#define OSCCTRL_INTENCLR_DPLL1LTO_Pos 26 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Timeout Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL1LTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LTO_Pos)
+#define OSCCTRL_INTENCLR_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LDRTO_Pos)
+#define OSCCTRL_INTENCLR_MASK _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTENCLR) MASK Register */
+
+/* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready Interrupt Enable */
+ uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready Interrupt Enable */
+ uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector Interrupt Enable */
+ uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector Interrupt Enable */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */
+ uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */
+ uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */
+ uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */
+ uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise Interrupt Enable */
+ uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall Interrupt Enable */
+ uint32_t DPLL0LTO:1; /*!< bit: 18 DPLL0 Lock Timeout Interrupt Enable */
+ uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise Interrupt Enable */
+ uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall Interrupt Enable */
+ uint32_t DPLL1LTO:1; /*!< bit: 26 DPLL1 Lock Timeout Interrupt Enable */
+ uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready Interrupt Enable */
+ uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector Interrupt Enable */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_INTENSET_OFFSET 0x08 /**< \brief (OSCCTRL_INTENSET offset) Interrupt Enable Set */
+#define OSCCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define OSCCTRL_INTENSET_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_INTENSET) XOSC 0 Ready Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCRDY0 (_U_(1) << OSCCTRL_INTENSET_XOSCRDY0_Pos)
+#define OSCCTRL_INTENSET_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_INTENSET) XOSC 1 Ready Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCRDY1 (_U_(1) << OSCCTRL_INTENSET_XOSCRDY1_Pos)
+#define OSCCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENSET) XOSC x Ready Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCRDY_Pos)
+#define OSCCTRL_INTENSET_XOSCRDY(value) (OSCCTRL_INTENSET_XOSCRDY_Msk & ((value) << OSCCTRL_INTENSET_XOSCRDY_Pos))
+#define OSCCTRL_INTENSET_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_INTENSET) XOSC 0 Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCFAIL0 (_U_(1) << OSCCTRL_INTENSET_XOSCFAIL0_Pos)
+#define OSCCTRL_INTENSET_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_INTENSET) XOSC 1 Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCFAIL1 (_U_(1) << OSCCTRL_INTENSET_XOSCFAIL1_Pos)
+#define OSCCTRL_INTENSET_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_INTENSET) XOSC x Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCFAIL_Pos)
+#define OSCCTRL_INTENSET_XOSCFAIL(value) (OSCCTRL_INTENSET_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENSET_XOSCFAIL_Pos))
+#define OSCCTRL_INTENSET_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLRDY (_U_(0x1) << OSCCTRL_INTENSET_DFLLRDY_Pos)
+#define OSCCTRL_INTENSET_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLOOB (_U_(0x1) << OSCCTRL_INTENSET_DFLLOOB_Pos)
+#define OSCCTRL_INTENSET_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLLCKF (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKF_Pos)
+#define OSCCTRL_INTENSET_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLLCKC (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKC_Pos)
+#define OSCCTRL_INTENSET_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLRCS (_U_(0x1) << OSCCTRL_INTENSET_DFLLRCS_Pos)
+#define OSCCTRL_INTENSET_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Rise Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKR_Pos)
+#define OSCCTRL_INTENSET_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Fall Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKF_Pos)
+#define OSCCTRL_INTENSET_DPLL0LTO_Pos 18 /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Timeout Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL0LTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LTO_Pos)
+#define OSCCTRL_INTENSET_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_INTENSET) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LDRTO_Pos)
+#define OSCCTRL_INTENSET_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Rise Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKR_Pos)
+#define OSCCTRL_INTENSET_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Fall Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKF_Pos)
+#define OSCCTRL_INTENSET_DPLL1LTO_Pos 26 /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Timeout Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL1LTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LTO_Pos)
+#define OSCCTRL_INTENSET_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_INTENSET) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LDRTO_Pos)
+#define OSCCTRL_INTENSET_MASK _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTENSET) MASK Register */
+
+/* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x0C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready */
+ __I uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready */
+ __I uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector */
+ __I uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector */
+ __I uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ __I uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */
+ __I uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */
+ __I uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */
+ __I uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */
+ __I uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */
+ __I uint32_t :3; /*!< bit: 13..15 Reserved */
+ __I uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise */
+ __I uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall */
+ __I uint32_t DPLL0LTO:1; /*!< bit: 18 DPLL0 Lock Timeout */
+ __I uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete */
+ __I uint32_t :4; /*!< bit: 20..23 Reserved */
+ __I uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise */
+ __I uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall */
+ __I uint32_t DPLL1LTO:1; /*!< bit: 26 DPLL1 Lock Timeout */
+ __I uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete */
+ __I uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready */
+ __I uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector */
+ __I uint32_t :28; /*!< bit: 4..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_INTFLAG_OFFSET 0x0C /**< \brief (OSCCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define OSCCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define OSCCTRL_INTFLAG_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_INTFLAG) XOSC 0 Ready */
+#define OSCCTRL_INTFLAG_XOSCRDY0 (_U_(1) << OSCCTRL_INTFLAG_XOSCRDY0_Pos)
+#define OSCCTRL_INTFLAG_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_INTFLAG) XOSC 1 Ready */
+#define OSCCTRL_INTFLAG_XOSCRDY1 (_U_(1) << OSCCTRL_INTFLAG_XOSCRDY1_Pos)
+#define OSCCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTFLAG) XOSC x Ready */
+#define OSCCTRL_INTFLAG_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCRDY_Pos)
+#define OSCCTRL_INTFLAG_XOSCRDY(value) (OSCCTRL_INTFLAG_XOSCRDY_Msk & ((value) << OSCCTRL_INTFLAG_XOSCRDY_Pos))
+#define OSCCTRL_INTFLAG_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_INTFLAG) XOSC 0 Clock Failure Detector */
+#define OSCCTRL_INTFLAG_XOSCFAIL0 (_U_(1) << OSCCTRL_INTFLAG_XOSCFAIL0_Pos)
+#define OSCCTRL_INTFLAG_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_INTFLAG) XOSC 1 Clock Failure Detector */
+#define OSCCTRL_INTFLAG_XOSCFAIL1 (_U_(1) << OSCCTRL_INTFLAG_XOSCFAIL1_Pos)
+#define OSCCTRL_INTFLAG_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_INTFLAG) XOSC x Clock Failure Detector */
+#define OSCCTRL_INTFLAG_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCFAIL_Pos)
+#define OSCCTRL_INTFLAG_XOSCFAIL(value) (OSCCTRL_INTFLAG_XOSCFAIL_Msk & ((value) << OSCCTRL_INTFLAG_XOSCFAIL_Pos))
+#define OSCCTRL_INTFLAG_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTFLAG) DFLL Ready */
+#define OSCCTRL_INTFLAG_DFLLRDY (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRDY_Pos)
+#define OSCCTRL_INTFLAG_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTFLAG) DFLL Out Of Bounds */
+#define OSCCTRL_INTFLAG_DFLLOOB (_U_(0x1) << OSCCTRL_INTFLAG_DFLLOOB_Pos)
+#define OSCCTRL_INTFLAG_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Fine */
+#define OSCCTRL_INTFLAG_DFLLLCKF (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKF_Pos)
+#define OSCCTRL_INTFLAG_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Coarse */
+#define OSCCTRL_INTFLAG_DFLLLCKC (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKC_Pos)
+#define OSCCTRL_INTFLAG_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped */
+#define OSCCTRL_INTFLAG_DFLLRCS (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRCS_Pos)
+#define OSCCTRL_INTFLAG_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Rise */
+#define OSCCTRL_INTFLAG_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKR_Pos)
+#define OSCCTRL_INTFLAG_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Fall */
+#define OSCCTRL_INTFLAG_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKF_Pos)
+#define OSCCTRL_INTFLAG_DPLL0LTO_Pos 18 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Timeout */
+#define OSCCTRL_INTFLAG_DPLL0LTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LTO_Pos)
+#define OSCCTRL_INTFLAG_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Loop Divider Ratio Update Complete */
+#define OSCCTRL_INTFLAG_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LDRTO_Pos)
+#define OSCCTRL_INTFLAG_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Rise */
+#define OSCCTRL_INTFLAG_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKR_Pos)
+#define OSCCTRL_INTFLAG_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Fall */
+#define OSCCTRL_INTFLAG_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKF_Pos)
+#define OSCCTRL_INTFLAG_DPLL1LTO_Pos 26 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Timeout */
+#define OSCCTRL_INTFLAG_DPLL1LTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LTO_Pos)
+#define OSCCTRL_INTFLAG_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Loop Divider Ratio Update Complete */
+#define OSCCTRL_INTFLAG_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LDRTO_Pos)
+#define OSCCTRL_INTFLAG_MASK _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTFLAG) MASK Register */
+
+/* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x10) (R/ 32) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready */
+ uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready */
+ uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector */
+ uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector */
+ uint32_t XOSCCKSW0:1; /*!< bit: 4 XOSC 0 Clock Switch */
+ uint32_t XOSCCKSW1:1; /*!< bit: 5 XOSC 1 Clock Switch */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */
+ uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */
+ uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */
+ uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */
+ uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise */
+ uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall */
+ uint32_t DPLL0TO:1; /*!< bit: 18 DPLL0 Timeout */
+ uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise */
+ uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall */
+ uint32_t DPLL1TO:1; /*!< bit: 26 DPLL1 Timeout */
+ uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready */
+ uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector */
+ uint32_t XOSCCKSW:2; /*!< bit: 4.. 5 XOSC x Clock Switch */
+ uint32_t :26; /*!< bit: 6..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_STATUS_OFFSET 0x10 /**< \brief (OSCCTRL_STATUS offset) Status */
+#define OSCCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_STATUS reset_value) Status */
+
+#define OSCCTRL_STATUS_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_STATUS) XOSC 0 Ready */
+#define OSCCTRL_STATUS_XOSCRDY0 (_U_(1) << OSCCTRL_STATUS_XOSCRDY0_Pos)
+#define OSCCTRL_STATUS_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_STATUS) XOSC 1 Ready */
+#define OSCCTRL_STATUS_XOSCRDY1 (_U_(1) << OSCCTRL_STATUS_XOSCRDY1_Pos)
+#define OSCCTRL_STATUS_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_STATUS) XOSC x Ready */
+#define OSCCTRL_STATUS_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCRDY_Pos)
+#define OSCCTRL_STATUS_XOSCRDY(value) (OSCCTRL_STATUS_XOSCRDY_Msk & ((value) << OSCCTRL_STATUS_XOSCRDY_Pos))
+#define OSCCTRL_STATUS_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_STATUS) XOSC 0 Clock Failure Detector */
+#define OSCCTRL_STATUS_XOSCFAIL0 (_U_(1) << OSCCTRL_STATUS_XOSCFAIL0_Pos)
+#define OSCCTRL_STATUS_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_STATUS) XOSC 1 Clock Failure Detector */
+#define OSCCTRL_STATUS_XOSCFAIL1 (_U_(1) << OSCCTRL_STATUS_XOSCFAIL1_Pos)
+#define OSCCTRL_STATUS_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_STATUS) XOSC x Clock Failure Detector */
+#define OSCCTRL_STATUS_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCFAIL_Pos)
+#define OSCCTRL_STATUS_XOSCFAIL(value) (OSCCTRL_STATUS_XOSCFAIL_Msk & ((value) << OSCCTRL_STATUS_XOSCFAIL_Pos))
+#define OSCCTRL_STATUS_XOSCCKSW0_Pos 4 /**< \brief (OSCCTRL_STATUS) XOSC 0 Clock Switch */
+#define OSCCTRL_STATUS_XOSCCKSW0 (_U_(1) << OSCCTRL_STATUS_XOSCCKSW0_Pos)
+#define OSCCTRL_STATUS_XOSCCKSW1_Pos 5 /**< \brief (OSCCTRL_STATUS) XOSC 1 Clock Switch */
+#define OSCCTRL_STATUS_XOSCCKSW1 (_U_(1) << OSCCTRL_STATUS_XOSCCKSW1_Pos)
+#define OSCCTRL_STATUS_XOSCCKSW_Pos 4 /**< \brief (OSCCTRL_STATUS) XOSC x Clock Switch */
+#define OSCCTRL_STATUS_XOSCCKSW_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCCKSW_Pos)
+#define OSCCTRL_STATUS_XOSCCKSW(value) (OSCCTRL_STATUS_XOSCCKSW_Msk & ((value) << OSCCTRL_STATUS_XOSCCKSW_Pos))
+#define OSCCTRL_STATUS_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_STATUS) DFLL Ready */
+#define OSCCTRL_STATUS_DFLLRDY (_U_(0x1) << OSCCTRL_STATUS_DFLLRDY_Pos)
+#define OSCCTRL_STATUS_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_STATUS) DFLL Out Of Bounds */
+#define OSCCTRL_STATUS_DFLLOOB (_U_(0x1) << OSCCTRL_STATUS_DFLLOOB_Pos)
+#define OSCCTRL_STATUS_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_STATUS) DFLL Lock Fine */
+#define OSCCTRL_STATUS_DFLLLCKF (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKF_Pos)
+#define OSCCTRL_STATUS_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_STATUS) DFLL Lock Coarse */
+#define OSCCTRL_STATUS_DFLLLCKC (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKC_Pos)
+#define OSCCTRL_STATUS_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_STATUS) DFLL Reference Clock Stopped */
+#define OSCCTRL_STATUS_DFLLRCS (_U_(0x1) << OSCCTRL_STATUS_DFLLRCS_Pos)
+#define OSCCTRL_STATUS_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_STATUS) DPLL0 Lock Rise */
+#define OSCCTRL_STATUS_DPLL0LCKR (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKR_Pos)
+#define OSCCTRL_STATUS_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_STATUS) DPLL0 Lock Fall */
+#define OSCCTRL_STATUS_DPLL0LCKF (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKF_Pos)
+#define OSCCTRL_STATUS_DPLL0TO_Pos 18 /**< \brief (OSCCTRL_STATUS) DPLL0 Timeout */
+#define OSCCTRL_STATUS_DPLL0TO (_U_(0x1) << OSCCTRL_STATUS_DPLL0TO_Pos)
+#define OSCCTRL_STATUS_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_STATUS) DPLL0 Loop Divider Ratio Update Complete */
+#define OSCCTRL_STATUS_DPLL0LDRTO (_U_(0x1) << OSCCTRL_STATUS_DPLL0LDRTO_Pos)
+#define OSCCTRL_STATUS_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_STATUS) DPLL1 Lock Rise */
+#define OSCCTRL_STATUS_DPLL1LCKR (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKR_Pos)
+#define OSCCTRL_STATUS_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_STATUS) DPLL1 Lock Fall */
+#define OSCCTRL_STATUS_DPLL1LCKF (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKF_Pos)
+#define OSCCTRL_STATUS_DPLL1TO_Pos 26 /**< \brief (OSCCTRL_STATUS) DPLL1 Timeout */
+#define OSCCTRL_STATUS_DPLL1TO (_U_(0x1) << OSCCTRL_STATUS_DPLL1TO_Pos)
+#define OSCCTRL_STATUS_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_STATUS) DPLL1 Loop Divider Ratio Update Complete */
+#define OSCCTRL_STATUS_DPLL1LDRTO (_U_(0x1) << OSCCTRL_STATUS_DPLL1LDRTO_Pos)
+#define OSCCTRL_STATUS_MASK _U_(0x0F0F1F3F) /**< \brief (OSCCTRL_STATUS) MASK Register */
+
+/* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x14) (R/W 32) External Multipurpose Crystal Oscillator Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint32_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint32_t LOWBUFGAIN:1; /*!< bit: 8 Low Buffer Gain Enable */
+ uint32_t IPTAT:2; /*!< bit: 9..10 Oscillator Current Reference */
+ uint32_t IMULT:4; /*!< bit: 11..14 Oscillator Current Multiplier */
+ uint32_t ENALC:1; /*!< bit: 15 Automatic Loop Control Enable */
+ uint32_t CFDEN:1; /*!< bit: 16 Clock Failure Detector Enable */
+ uint32_t SWBEN:1; /*!< bit: 17 Xosc Clock Switch Enable */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t STARTUP:4; /*!< bit: 20..23 Start-Up Time */
+ uint32_t CFDPRESC:4; /*!< bit: 24..27 Clock Failure Detector Prescaler */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_XOSCCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_XOSCCTRL_OFFSET 0x14 /**< \brief (OSCCTRL_XOSCCTRL offset) External Multipurpose Crystal Oscillator Control */
+#define OSCCTRL_XOSCCTRL_RESETVALUE _U_(0x00000080) /**< \brief (OSCCTRL_XOSCCTRL reset_value) External Multipurpose Crystal Oscillator Control */
+
+#define OSCCTRL_XOSCCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Enable */
+#define OSCCTRL_XOSCCTRL_ENABLE (_U_(0x1) << OSCCTRL_XOSCCTRL_ENABLE_Pos)
+#define OSCCTRL_XOSCCTRL_XTALEN_Pos 2 /**< \brief (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable */
+#define OSCCTRL_XOSCCTRL_XTALEN (_U_(0x1) << OSCCTRL_XOSCCTRL_XTALEN_Pos)
+#define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_XOSCCTRL) Run in Standby */
+#define OSCCTRL_XOSCCTRL_RUNSTDBY (_U_(0x1) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos)
+#define OSCCTRL_XOSCCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_XOSCCTRL) On Demand Control */
+#define OSCCTRL_XOSCCTRL_ONDEMAND (_U_(0x1) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos)
+#define OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos 8 /**< \brief (OSCCTRL_XOSCCTRL) Low Buffer Gain Enable */
+#define OSCCTRL_XOSCCTRL_LOWBUFGAIN (_U_(0x1) << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos)
+#define OSCCTRL_XOSCCTRL_IPTAT_Pos 9 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Current Reference */
+#define OSCCTRL_XOSCCTRL_IPTAT_Msk (_U_(0x3) << OSCCTRL_XOSCCTRL_IPTAT_Pos)
+#define OSCCTRL_XOSCCTRL_IPTAT(value) (OSCCTRL_XOSCCTRL_IPTAT_Msk & ((value) << OSCCTRL_XOSCCTRL_IPTAT_Pos))
+#define OSCCTRL_XOSCCTRL_IMULT_Pos 11 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Current Multiplier */
+#define OSCCTRL_XOSCCTRL_IMULT_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_IMULT_Pos)
+#define OSCCTRL_XOSCCTRL_IMULT(value) (OSCCTRL_XOSCCTRL_IMULT_Msk & ((value) << OSCCTRL_XOSCCTRL_IMULT_Pos))
+#define OSCCTRL_XOSCCTRL_ENALC_Pos 15 /**< \brief (OSCCTRL_XOSCCTRL) Automatic Loop Control Enable */
+#define OSCCTRL_XOSCCTRL_ENALC (_U_(0x1) << OSCCTRL_XOSCCTRL_ENALC_Pos)
+#define OSCCTRL_XOSCCTRL_CFDEN_Pos 16 /**< \brief (OSCCTRL_XOSCCTRL) Clock Failure Detector Enable */
+#define OSCCTRL_XOSCCTRL_CFDEN (_U_(0x1) << OSCCTRL_XOSCCTRL_CFDEN_Pos)
+#define OSCCTRL_XOSCCTRL_SWBEN_Pos 17 /**< \brief (OSCCTRL_XOSCCTRL) Xosc Clock Switch Enable */
+#define OSCCTRL_XOSCCTRL_SWBEN (_U_(0x1) << OSCCTRL_XOSCCTRL_SWBEN_Pos)
+#define OSCCTRL_XOSCCTRL_STARTUP_Pos 20 /**< \brief (OSCCTRL_XOSCCTRL) Start-Up Time */
+#define OSCCTRL_XOSCCTRL_STARTUP_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_STARTUP_Pos)
+#define OSCCTRL_XOSCCTRL_STARTUP(value) (OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos))
+#define OSCCTRL_XOSCCTRL_CFDPRESC_Pos 24 /**< \brief (OSCCTRL_XOSCCTRL) Clock Failure Detector Prescaler */
+#define OSCCTRL_XOSCCTRL_CFDPRESC_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos)
+#define OSCCTRL_XOSCCTRL_CFDPRESC(value) (OSCCTRL_XOSCCTRL_CFDPRESC_Msk & ((value) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos))
+#define OSCCTRL_XOSCCTRL_MASK _U_(0x0FF3FFC6) /**< \brief (OSCCTRL_XOSCCTRL) MASK Register */
+
+/* -------- OSCCTRL_DFLLCTRLA : (OSCCTRL Offset: 0x1C) (R/W 8) DFLL48M Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 DFLL Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} OSCCTRL_DFLLCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLCTRLA_OFFSET 0x1C /**< \brief (OSCCTRL_DFLLCTRLA offset) DFLL48M Control A */
+#define OSCCTRL_DFLLCTRLA_RESETVALUE _U_(0x82) /**< \brief (OSCCTRL_DFLLCTRLA reset_value) DFLL48M Control A */
+
+#define OSCCTRL_DFLLCTRLA_ENABLE_Pos 1 /**< \brief (OSCCTRL_DFLLCTRLA) DFLL Enable */
+#define OSCCTRL_DFLLCTRLA_ENABLE (_U_(0x1) << OSCCTRL_DFLLCTRLA_ENABLE_Pos)
+#define OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DFLLCTRLA) Run in Standby */
+#define OSCCTRL_DFLLCTRLA_RUNSTDBY (_U_(0x1) << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos)
+#define OSCCTRL_DFLLCTRLA_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DFLLCTRLA) On Demand Control */
+#define OSCCTRL_DFLLCTRLA_ONDEMAND (_U_(0x1) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos)
+#define OSCCTRL_DFLLCTRLA_MASK _U_(0xC2) /**< \brief (OSCCTRL_DFLLCTRLA) MASK Register */
+
+/* -------- OSCCTRL_DFLLCTRLB : (OSCCTRL Offset: 0x20) (R/W 8) DFLL48M Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t MODE:1; /*!< bit: 0 Operating Mode Selection */
+ uint8_t STABLE:1; /*!< bit: 1 Stable DFLL Frequency */
+ uint8_t LLAW:1; /*!< bit: 2 Lose Lock After Wake */
+ uint8_t USBCRM:1; /*!< bit: 3 USB Clock Recovery Mode */
+ uint8_t CCDIS:1; /*!< bit: 4 Chill Cycle Disable */
+ uint8_t QLDIS:1; /*!< bit: 5 Quick Lock Disable */
+ uint8_t BPLCKC:1; /*!< bit: 6 Bypass Coarse Lock */
+ uint8_t WAITLOCK:1; /*!< bit: 7 Wait Lock */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} OSCCTRL_DFLLCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLCTRLB_OFFSET 0x20 /**< \brief (OSCCTRL_DFLLCTRLB offset) DFLL48M Control B */
+#define OSCCTRL_DFLLCTRLB_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DFLLCTRLB reset_value) DFLL48M Control B */
+
+#define OSCCTRL_DFLLCTRLB_MODE_Pos 0 /**< \brief (OSCCTRL_DFLLCTRLB) Operating Mode Selection */
+#define OSCCTRL_DFLLCTRLB_MODE (_U_(0x1) << OSCCTRL_DFLLCTRLB_MODE_Pos)
+#define OSCCTRL_DFLLCTRLB_STABLE_Pos 1 /**< \brief (OSCCTRL_DFLLCTRLB) Stable DFLL Frequency */
+#define OSCCTRL_DFLLCTRLB_STABLE (_U_(0x1) << OSCCTRL_DFLLCTRLB_STABLE_Pos)
+#define OSCCTRL_DFLLCTRLB_LLAW_Pos 2 /**< \brief (OSCCTRL_DFLLCTRLB) Lose Lock After Wake */
+#define OSCCTRL_DFLLCTRLB_LLAW (_U_(0x1) << OSCCTRL_DFLLCTRLB_LLAW_Pos)
+#define OSCCTRL_DFLLCTRLB_USBCRM_Pos 3 /**< \brief (OSCCTRL_DFLLCTRLB) USB Clock Recovery Mode */
+#define OSCCTRL_DFLLCTRLB_USBCRM (_U_(0x1) << OSCCTRL_DFLLCTRLB_USBCRM_Pos)
+#define OSCCTRL_DFLLCTRLB_CCDIS_Pos 4 /**< \brief (OSCCTRL_DFLLCTRLB) Chill Cycle Disable */
+#define OSCCTRL_DFLLCTRLB_CCDIS (_U_(0x1) << OSCCTRL_DFLLCTRLB_CCDIS_Pos)
+#define OSCCTRL_DFLLCTRLB_QLDIS_Pos 5 /**< \brief (OSCCTRL_DFLLCTRLB) Quick Lock Disable */
+#define OSCCTRL_DFLLCTRLB_QLDIS (_U_(0x1) << OSCCTRL_DFLLCTRLB_QLDIS_Pos)
+#define OSCCTRL_DFLLCTRLB_BPLCKC_Pos 6 /**< \brief (OSCCTRL_DFLLCTRLB) Bypass Coarse Lock */
+#define OSCCTRL_DFLLCTRLB_BPLCKC (_U_(0x1) << OSCCTRL_DFLLCTRLB_BPLCKC_Pos)
+#define OSCCTRL_DFLLCTRLB_WAITLOCK_Pos 7 /**< \brief (OSCCTRL_DFLLCTRLB) Wait Lock */
+#define OSCCTRL_DFLLCTRLB_WAITLOCK (_U_(0x1) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos)
+#define OSCCTRL_DFLLCTRLB_MASK _U_(0xFF) /**< \brief (OSCCTRL_DFLLCTRLB) MASK Register */
+
+/* -------- OSCCTRL_DFLLVAL : (OSCCTRL Offset: 0x24) (R/W 32) DFLL48M Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FINE:8; /*!< bit: 0.. 7 Fine Value */
+ uint32_t :2; /*!< bit: 8.. 9 Reserved */
+ uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
+ uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_DFLLVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLVAL_OFFSET 0x24 /**< \brief (OSCCTRL_DFLLVAL offset) DFLL48M Value */
+#define OSCCTRL_DFLLVAL_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DFLLVAL reset_value) DFLL48M Value */
+
+#define OSCCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (OSCCTRL_DFLLVAL) Fine Value */
+#define OSCCTRL_DFLLVAL_FINE_Msk (_U_(0xFF) << OSCCTRL_DFLLVAL_FINE_Pos)
+#define OSCCTRL_DFLLVAL_FINE(value) (OSCCTRL_DFLLVAL_FINE_Msk & ((value) << OSCCTRL_DFLLVAL_FINE_Pos))
+#define OSCCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (OSCCTRL_DFLLVAL) Coarse Value */
+#define OSCCTRL_DFLLVAL_COARSE_Msk (_U_(0x3F) << OSCCTRL_DFLLVAL_COARSE_Pos)
+#define OSCCTRL_DFLLVAL_COARSE(value) (OSCCTRL_DFLLVAL_COARSE_Msk & ((value) << OSCCTRL_DFLLVAL_COARSE_Pos))
+#define OSCCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (OSCCTRL_DFLLVAL) Multiplication Ratio Difference */
+#define OSCCTRL_DFLLVAL_DIFF_Msk (_U_(0xFFFF) << OSCCTRL_DFLLVAL_DIFF_Pos)
+#define OSCCTRL_DFLLVAL_DIFF(value) (OSCCTRL_DFLLVAL_DIFF_Msk & ((value) << OSCCTRL_DFLLVAL_DIFF_Pos))
+#define OSCCTRL_DFLLVAL_MASK _U_(0xFFFFFCFF) /**< \brief (OSCCTRL_DFLLVAL) MASK Register */
+
+/* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x28) (R/W 32) DFLL48M Multiplier -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
+ uint32_t FSTEP:8; /*!< bit: 16..23 Fine Maximum Step */
+ uint32_t :2; /*!< bit: 24..25 Reserved */
+ uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_DFLLMUL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLMUL_OFFSET 0x28 /**< \brief (OSCCTRL_DFLLMUL offset) DFLL48M Multiplier */
+#define OSCCTRL_DFLLMUL_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DFLLMUL reset_value) DFLL48M Multiplier */
+
+#define OSCCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (OSCCTRL_DFLLMUL) DFLL Multiply Factor */
+#define OSCCTRL_DFLLMUL_MUL_Msk (_U_(0xFFFF) << OSCCTRL_DFLLMUL_MUL_Pos)
+#define OSCCTRL_DFLLMUL_MUL(value) (OSCCTRL_DFLLMUL_MUL_Msk & ((value) << OSCCTRL_DFLLMUL_MUL_Pos))
+#define OSCCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (OSCCTRL_DFLLMUL) Fine Maximum Step */
+#define OSCCTRL_DFLLMUL_FSTEP_Msk (_U_(0xFF) << OSCCTRL_DFLLMUL_FSTEP_Pos)
+#define OSCCTRL_DFLLMUL_FSTEP(value) (OSCCTRL_DFLLMUL_FSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_FSTEP_Pos))
+#define OSCCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (OSCCTRL_DFLLMUL) Coarse Maximum Step */
+#define OSCCTRL_DFLLMUL_CSTEP_Msk (_U_(0x3F) << OSCCTRL_DFLLMUL_CSTEP_Pos)
+#define OSCCTRL_DFLLMUL_CSTEP(value) (OSCCTRL_DFLLMUL_CSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_CSTEP_Pos))
+#define OSCCTRL_DFLLMUL_MASK _U_(0xFCFFFFFF) /**< \brief (OSCCTRL_DFLLMUL) MASK Register */
+
+/* -------- OSCCTRL_DFLLSYNC : (OSCCTRL Offset: 0x2C) (R/W 8) DFLL48M Synchronization -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */
+ uint8_t DFLLCTRLB:1; /*!< bit: 2 DFLLCTRLB Synchronization Busy */
+ uint8_t DFLLVAL:1; /*!< bit: 3 DFLLVAL Synchronization Busy */
+ uint8_t DFLLMUL:1; /*!< bit: 4 DFLLMUL Synchronization Busy */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} OSCCTRL_DFLLSYNC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLSYNC_OFFSET 0x2C /**< \brief (OSCCTRL_DFLLSYNC offset) DFLL48M Synchronization */
+#define OSCCTRL_DFLLSYNC_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */
+
+#define OSCCTRL_DFLLSYNC_ENABLE_Pos 1 /**< \brief (OSCCTRL_DFLLSYNC) ENABLE Synchronization Busy */
+#define OSCCTRL_DFLLSYNC_ENABLE (_U_(0x1) << OSCCTRL_DFLLSYNC_ENABLE_Pos)
+#define OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos 2 /**< \brief (OSCCTRL_DFLLSYNC) DFLLCTRLB Synchronization Busy */
+#define OSCCTRL_DFLLSYNC_DFLLCTRLB (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos)
+#define OSCCTRL_DFLLSYNC_DFLLVAL_Pos 3 /**< \brief (OSCCTRL_DFLLSYNC) DFLLVAL Synchronization Busy */
+#define OSCCTRL_DFLLSYNC_DFLLVAL (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLVAL_Pos)
+#define OSCCTRL_DFLLSYNC_DFLLMUL_Pos 4 /**< \brief (OSCCTRL_DFLLSYNC) DFLLMUL Synchronization Busy */
+#define OSCCTRL_DFLLSYNC_DFLLMUL (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLMUL_Pos)
+#define OSCCTRL_DFLLSYNC_MASK _U_(0x1E) /**< \brief (OSCCTRL_DFLLSYNC) MASK Register */
+
+/* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x30) (R/W 8) DPLL DPLL Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} OSCCTRL_DPLLCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLCTRLA_OFFSET 0x30 /**< \brief (OSCCTRL_DPLLCTRLA offset) DPLL Control A */
+#define OSCCTRL_DPLLCTRLA_RESETVALUE _U_(0x80) /**< \brief (OSCCTRL_DPLLCTRLA reset_value) DPLL Control A */
+
+#define OSCCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLCTRLA) DPLL Enable */
+#define OSCCTRL_DPLLCTRLA_ENABLE (_U_(0x1) << OSCCTRL_DPLLCTRLA_ENABLE_Pos)
+#define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DPLLCTRLA) Run in Standby */
+#define OSCCTRL_DPLLCTRLA_RUNSTDBY (_U_(0x1) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)
+#define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DPLLCTRLA) On Demand Control */
+#define OSCCTRL_DPLLCTRLA_ONDEMAND (_U_(0x1) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos)
+#define OSCCTRL_DPLLCTRLA_MASK _U_(0xC2) /**< \brief (OSCCTRL_DPLLCTRLA) MASK Register */
+
+/* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x34) (R/W 32) DPLL DPLL Ratio Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LDR:13; /*!< bit: 0..12 Loop Divider Ratio */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t LDRFRAC:5; /*!< bit: 16..20 Loop Divider Ratio Fractional Part */
+ uint32_t :11; /*!< bit: 21..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_DPLLRATIO_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLRATIO_OFFSET 0x34 /**< \brief (OSCCTRL_DPLLRATIO offset) DPLL Ratio Control */
+#define OSCCTRL_DPLLRATIO_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
+
+#define OSCCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio */
+#define OSCCTRL_DPLLRATIO_LDR_Msk (_U_(0x1FFF) << OSCCTRL_DPLLRATIO_LDR_Pos)
+#define OSCCTRL_DPLLRATIO_LDR(value) (OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos))
+#define OSCCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
+#define OSCCTRL_DPLLRATIO_LDRFRAC_Msk (_U_(0x1F) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos)
+#define OSCCTRL_DPLLRATIO_LDRFRAC(value) (OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos))
+#define OSCCTRL_DPLLRATIO_MASK _U_(0x001F1FFF) /**< \brief (OSCCTRL_DPLLRATIO) MASK Register */
+
+/* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x38) (R/W 32) DPLL DPLL Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FILTER:4; /*!< bit: 0.. 3 Proportional Integral Filter Selection */
+ uint32_t WUF:1; /*!< bit: 4 Wake Up Fast */
+ uint32_t REFCLK:3; /*!< bit: 5.. 7 Reference Clock Selection */
+ uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
+ uint32_t LBYPASS:1; /*!< bit: 11 Lock Bypass */
+ uint32_t DCOFILTER:3; /*!< bit: 12..14 Sigma-Delta DCO Filter Selection */
+ uint32_t DCOEN:1; /*!< bit: 15 DCO Filter Enable */
+ uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_DPLLCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLCTRLB_OFFSET 0x38 /**< \brief (OSCCTRL_DPLLCTRLB offset) DPLL Control B */
+#define OSCCTRL_DPLLCTRLB_RESETVALUE _U_(0x00000020) /**< \brief (OSCCTRL_DPLLCTRLB reset_value) DPLL Control B */
+
+#define OSCCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
+#define OSCCTRL_DPLLCTRLB_FILTER_Msk (_U_(0xF) << OSCCTRL_DPLLCTRLB_FILTER_Pos)
+#define OSCCTRL_DPLLCTRLB_FILTER(value) (OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos))
+#define OSCCTRL_DPLLCTRLB_WUF_Pos 4 /**< \brief (OSCCTRL_DPLLCTRLB) Wake Up Fast */
+#define OSCCTRL_DPLLCTRLB_WUF (_U_(0x1) << OSCCTRL_DPLLCTRLB_WUF_Pos)
+#define OSCCTRL_DPLLCTRLB_REFCLK_Pos 5 /**< \brief (OSCCTRL_DPLLCTRLB) Reference Clock Selection */
+#define OSCCTRL_DPLLCTRLB_REFCLK_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
+#define OSCCTRL_DPLLCTRLB_REFCLK(value) (OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos))
+#define OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val _U_(0x0) /**< \brief (OSCCTRL_DPLLCTRLB) Dedicated GCLK clock reference */
+#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val _U_(0x1) /**< \brief (OSCCTRL_DPLLCTRLB) XOSC32K clock reference */
+#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val _U_(0x2) /**< \brief (OSCCTRL_DPLLCTRLB) XOSC0 clock reference */
+#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val _U_(0x3) /**< \brief (OSCCTRL_DPLLCTRLB) XOSC1 clock reference */
+#define OSCCTRL_DPLLCTRLB_REFCLK_GCLK (OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
+#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
+#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
+#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Time */
+#define OSCCTRL_DPLLCTRLB_LTIME_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME(value) (OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos))
+#define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val _U_(0x0) /**< \brief (OSCCTRL_DPLLCTRLB) No time-out. Automatic lock */
+#define OSCCTRL_DPLLCTRLB_LTIME_800US_Val _U_(0x4) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 800us */
+#define OSCCTRL_DPLLCTRLB_LTIME_900US_Val _U_(0x5) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 900us */
+#define OSCCTRL_DPLLCTRLB_LTIME_1MS_Val _U_(0x6) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1ms */
+#define OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val _U_(0x7) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1.1ms */
+#define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT (OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME_800US (OSCCTRL_DPLLCTRLB_LTIME_800US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME_900US (OSCCTRL_DPLLCTRLB_LTIME_900US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME_1MS (OSCCTRL_DPLLCTRLB_LTIME_1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME_1P1MS (OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LBYPASS_Pos 11 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Bypass */
+#define OSCCTRL_DPLLCTRLB_LBYPASS (_U_(0x1) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos)
+#define OSCCTRL_DPLLCTRLB_DCOFILTER_Pos 12 /**< \brief (OSCCTRL_DPLLCTRLB) Sigma-Delta DCO Filter Selection */
+#define OSCCTRL_DPLLCTRLB_DCOFILTER_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos)
+#define OSCCTRL_DPLLCTRLB_DCOFILTER(value) (OSCCTRL_DPLLCTRLB_DCOFILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos))
+#define OSCCTRL_DPLLCTRLB_DCOEN_Pos 15 /**< \brief (OSCCTRL_DPLLCTRLB) DCO Filter Enable */
+#define OSCCTRL_DPLLCTRLB_DCOEN (_U_(0x1) << OSCCTRL_DPLLCTRLB_DCOEN_Pos)
+#define OSCCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (OSCCTRL_DPLLCTRLB) Clock Divider */
+#define OSCCTRL_DPLLCTRLB_DIV_Msk (_U_(0x7FF) << OSCCTRL_DPLLCTRLB_DIV_Pos)
+#define OSCCTRL_DPLLCTRLB_DIV(value) (OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos))
+#define OSCCTRL_DPLLCTRLB_MASK _U_(0x07FFFFFF) /**< \brief (OSCCTRL_DPLLCTRLB) MASK Register */
+
+/* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x3C) (R/ 32) DPLL DPLL Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 DPLL Enable Synchronization Status */
+ uint32_t DPLLRATIO:1; /*!< bit: 2 DPLL Loop Divider Ratio Synchronization Status */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_DPLLSYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLSYNCBUSY_OFFSET 0x3C /**< \brief (OSCCTRL_DPLLSYNCBUSY offset) DPLL Synchronization Busy */
+#define OSCCTRL_DPLLSYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLSYNCBUSY reset_value) DPLL Synchronization Busy */
+
+#define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status */
+#define OSCCTRL_DPLLSYNCBUSY_ENABLE (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos)
+#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos 2 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Loop Divider Ratio Synchronization Status */
+#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos)
+#define OSCCTRL_DPLLSYNCBUSY_MASK _U_(0x00000006) /**< \brief (OSCCTRL_DPLLSYNCBUSY) MASK Register */
+
+/* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x40) (R/ 32) DPLL DPLL Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
+ uint32_t CLKRDY:1; /*!< bit: 1 DPLL Clock Ready */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_DPLLSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLSTATUS_OFFSET 0x40 /**< \brief (OSCCTRL_DPLLSTATUS offset) DPLL Status */
+#define OSCCTRL_DPLLSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLSTATUS reset_value) DPLL Status */
+
+#define OSCCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Lock Status */
+#define OSCCTRL_DPLLSTATUS_LOCK (_U_(0x1) << OSCCTRL_DPLLSTATUS_LOCK_Pos)
+#define OSCCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Clock Ready */
+#define OSCCTRL_DPLLSTATUS_CLKRDY (_U_(0x1) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos)
+#define OSCCTRL_DPLLSTATUS_MASK _U_(0x00000003) /**< \brief (OSCCTRL_DPLLSTATUS) MASK Register */
+
+/** \brief OscctrlDpll hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO OSCCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x00 (R/W 8) DPLL Control A */
+ RoReg8 Reserved1[0x3];
+ __IO OSCCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x04 (R/W 32) DPLL Ratio Control */
+ __IO OSCCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x08 (R/W 32) DPLL Control B */
+ __I OSCCTRL_DPLLSYNCBUSY_Type DPLLSYNCBUSY; /**< \brief Offset: 0x0C (R/ 32) DPLL Synchronization Busy */
+ __I OSCCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x10 (R/ 32) DPLL Status */
+} OscctrlDpll;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief OSCCTRL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO OSCCTRL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x00 (R/W 8) Event Control */
+ RoReg8 Reserved1[0x3];
+ __IO OSCCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Clear */
+ __IO OSCCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Set */
+ __IO OSCCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 32) Interrupt Flag Status and Clear */
+ __I OSCCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x10 (R/ 32) Status */
+ __IO OSCCTRL_XOSCCTRL_Type XOSCCTRL[2]; /**< \brief Offset: 0x14 (R/W 32) External Multipurpose Crystal Oscillator Control */
+ __IO OSCCTRL_DFLLCTRLA_Type DFLLCTRLA; /**< \brief Offset: 0x1C (R/W 8) DFLL48M Control A */
+ RoReg8 Reserved2[0x3];
+ __IO OSCCTRL_DFLLCTRLB_Type DFLLCTRLB; /**< \brief Offset: 0x20 (R/W 8) DFLL48M Control B */
+ RoReg8 Reserved3[0x3];
+ __IO OSCCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x24 (R/W 32) DFLL48M Value */
+ __IO OSCCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Multiplier */
+ __IO OSCCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x2C (R/W 8) DFLL48M Synchronization */
+ RoReg8 Reserved4[0x3];
+ OscctrlDpll Dpll[2]; /**< \brief Offset: 0x30 OscctrlDpll groups [DPLLS_NUM] */
+} Oscctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_OSCCTRL_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/pac.h b/sysmoOCTSIM/include/component/pac.h
index ab4be4b..0d2d11e 100644
--- a/sysmoOCTSIM/include/component/pac.h
+++ b/sysmoOCTSIM/include/component/pac.h
@@ -1,686 +1,686 @@
-/**
- * \file
- *
- * \brief Component description for PAC
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_PAC_COMPONENT_
-#define _SAME54_PAC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR PAC */
-/* ========================================================================== */
-/** \addtogroup SAME54_PAC Peripheral Access Controller */
-/*@{*/
-
-#define PAC_U2120
-#define REV_PAC 0x120
-
-/* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t PERID:16; /*!< bit: 0..15 Peripheral identifier */
- uint32_t KEY:8; /*!< bit: 16..23 Peripheral access control key */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PAC_WRCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_WRCTRL_OFFSET 0x00 /**< \brief (PAC_WRCTRL offset) Write control */
-#define PAC_WRCTRL_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WRCTRL reset_value) Write control */
-
-#define PAC_WRCTRL_PERID_Pos 0 /**< \brief (PAC_WRCTRL) Peripheral identifier */
-#define PAC_WRCTRL_PERID_Msk (_U_(0xFFFF) << PAC_WRCTRL_PERID_Pos)
-#define PAC_WRCTRL_PERID(value) (PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos))
-#define PAC_WRCTRL_KEY_Pos 16 /**< \brief (PAC_WRCTRL) Peripheral access control key */
-#define PAC_WRCTRL_KEY_Msk (_U_(0xFF) << PAC_WRCTRL_KEY_Pos)
-#define PAC_WRCTRL_KEY(value) (PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos))
-#define PAC_WRCTRL_KEY_OFF_Val _U_(0x0) /**< \brief (PAC_WRCTRL) No action */
-#define PAC_WRCTRL_KEY_CLR_Val _U_(0x1) /**< \brief (PAC_WRCTRL) Clear protection */
-#define PAC_WRCTRL_KEY_SET_Val _U_(0x2) /**< \brief (PAC_WRCTRL) Set protection */
-#define PAC_WRCTRL_KEY_SETLCK_Val _U_(0x3) /**< \brief (PAC_WRCTRL) Set and lock protection */
-#define PAC_WRCTRL_KEY_OFF (PAC_WRCTRL_KEY_OFF_Val << PAC_WRCTRL_KEY_Pos)
-#define PAC_WRCTRL_KEY_CLR (PAC_WRCTRL_KEY_CLR_Val << PAC_WRCTRL_KEY_Pos)
-#define PAC_WRCTRL_KEY_SET (PAC_WRCTRL_KEY_SET_Val << PAC_WRCTRL_KEY_Pos)
-#define PAC_WRCTRL_KEY_SETLCK (PAC_WRCTRL_KEY_SETLCK_Val << PAC_WRCTRL_KEY_Pos)
-#define PAC_WRCTRL_MASK _U_(0x00FFFFFF) /**< \brief (PAC_WRCTRL) MASK Register */
-
-/* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W 8) Event control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t ERREO:1; /*!< bit: 0 Peripheral acess error event output */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PAC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_EVCTRL_OFFSET 0x04 /**< \brief (PAC_EVCTRL offset) Event control */
-#define PAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (PAC_EVCTRL reset_value) Event control */
-
-#define PAC_EVCTRL_ERREO_Pos 0 /**< \brief (PAC_EVCTRL) Peripheral acess error event output */
-#define PAC_EVCTRL_ERREO (_U_(0x1) << PAC_EVCTRL_ERREO_Pos)
-#define PAC_EVCTRL_MASK _U_(0x01) /**< \brief (PAC_EVCTRL) MASK Register */
-
-/* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W 8) Interrupt enable clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt disable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PAC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_INTENCLR_OFFSET 0x08 /**< \brief (PAC_INTENCLR offset) Interrupt enable clear */
-#define PAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PAC_INTENCLR reset_value) Interrupt enable clear */
-
-#define PAC_INTENCLR_ERR_Pos 0 /**< \brief (PAC_INTENCLR) Peripheral access error interrupt disable */
-#define PAC_INTENCLR_ERR (_U_(0x1) << PAC_INTENCLR_ERR_Pos)
-#define PAC_INTENCLR_MASK _U_(0x01) /**< \brief (PAC_INTENCLR) MASK Register */
-
-/* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W 8) Interrupt enable set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PAC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_INTENSET_OFFSET 0x09 /**< \brief (PAC_INTENSET offset) Interrupt enable set */
-#define PAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PAC_INTENSET reset_value) Interrupt enable set */
-
-#define PAC_INTENSET_ERR_Pos 0 /**< \brief (PAC_INTENSET) Peripheral access error interrupt enable */
-#define PAC_INTENSET_ERR (_U_(0x1) << PAC_INTENSET_ERR_Pos)
-#define PAC_INTENSET_MASK _U_(0x01) /**< \brief (PAC_INTENSET) MASK Register */
-
-/* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint32_t FLASH_:1; /*!< bit: 0 FLASH */
- __I uint32_t FLASH_ALT_:1; /*!< bit: 1 FLASH_ALT */
- __I uint32_t SEEPROM_:1; /*!< bit: 2 SEEPROM */
- __I uint32_t RAMCM4S_:1; /*!< bit: 3 RAMCM4S */
- __I uint32_t RAMPPPDSU_:1; /*!< bit: 4 RAMPPPDSU */
- __I uint32_t RAMDMAWR_:1; /*!< bit: 5 RAMDMAWR */
- __I uint32_t RAMDMACICM_:1; /*!< bit: 6 RAMDMACICM */
- __I uint32_t HPB0_:1; /*!< bit: 7 HPB0 */
- __I uint32_t HPB1_:1; /*!< bit: 8 HPB1 */
- __I uint32_t HPB2_:1; /*!< bit: 9 HPB2 */
- __I uint32_t HPB3_:1; /*!< bit: 10 HPB3 */
- __I uint32_t PUKCC_:1; /*!< bit: 11 PUKCC */
- __I uint32_t SDHC0_:1; /*!< bit: 12 SDHC0 */
- __I uint32_t SDHC1_:1; /*!< bit: 13 SDHC1 */
- __I uint32_t QSPI_:1; /*!< bit: 14 QSPI */
- __I uint32_t BKUPRAM_:1; /*!< bit: 15 BKUPRAM */
- __I uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PAC_INTFLAGAHB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_INTFLAGAHB_OFFSET 0x10 /**< \brief (PAC_INTFLAGAHB offset) Bridge interrupt flag status */
-#define PAC_INTFLAGAHB_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGAHB reset_value) Bridge interrupt flag status */
-
-#define PAC_INTFLAGAHB_FLASH_Pos 0 /**< \brief (PAC_INTFLAGAHB) FLASH */
-#define PAC_INTFLAGAHB_FLASH (_U_(0x1) << PAC_INTFLAGAHB_FLASH_Pos)
-#define PAC_INTFLAGAHB_FLASH_ALT_Pos 1 /**< \brief (PAC_INTFLAGAHB) FLASH_ALT */
-#define PAC_INTFLAGAHB_FLASH_ALT (_U_(0x1) << PAC_INTFLAGAHB_FLASH_ALT_Pos)
-#define PAC_INTFLAGAHB_SEEPROM_Pos 2 /**< \brief (PAC_INTFLAGAHB) SEEPROM */
-#define PAC_INTFLAGAHB_SEEPROM (_U_(0x1) << PAC_INTFLAGAHB_SEEPROM_Pos)
-#define PAC_INTFLAGAHB_RAMCM4S_Pos 3 /**< \brief (PAC_INTFLAGAHB) RAMCM4S */
-#define PAC_INTFLAGAHB_RAMCM4S (_U_(0x1) << PAC_INTFLAGAHB_RAMCM4S_Pos)
-#define PAC_INTFLAGAHB_RAMPPPDSU_Pos 4 /**< \brief (PAC_INTFLAGAHB) RAMPPPDSU */
-#define PAC_INTFLAGAHB_RAMPPPDSU (_U_(0x1) << PAC_INTFLAGAHB_RAMPPPDSU_Pos)
-#define PAC_INTFLAGAHB_RAMDMAWR_Pos 5 /**< \brief (PAC_INTFLAGAHB) RAMDMAWR */
-#define PAC_INTFLAGAHB_RAMDMAWR (_U_(0x1) << PAC_INTFLAGAHB_RAMDMAWR_Pos)
-#define PAC_INTFLAGAHB_RAMDMACICM_Pos 6 /**< \brief (PAC_INTFLAGAHB) RAMDMACICM */
-#define PAC_INTFLAGAHB_RAMDMACICM (_U_(0x1) << PAC_INTFLAGAHB_RAMDMACICM_Pos)
-#define PAC_INTFLAGAHB_HPB0_Pos 7 /**< \brief (PAC_INTFLAGAHB) HPB0 */
-#define PAC_INTFLAGAHB_HPB0 (_U_(0x1) << PAC_INTFLAGAHB_HPB0_Pos)
-#define PAC_INTFLAGAHB_HPB1_Pos 8 /**< \brief (PAC_INTFLAGAHB) HPB1 */
-#define PAC_INTFLAGAHB_HPB1 (_U_(0x1) << PAC_INTFLAGAHB_HPB1_Pos)
-#define PAC_INTFLAGAHB_HPB2_Pos 9 /**< \brief (PAC_INTFLAGAHB) HPB2 */
-#define PAC_INTFLAGAHB_HPB2 (_U_(0x1) << PAC_INTFLAGAHB_HPB2_Pos)
-#define PAC_INTFLAGAHB_HPB3_Pos 10 /**< \brief (PAC_INTFLAGAHB) HPB3 */
-#define PAC_INTFLAGAHB_HPB3 (_U_(0x1) << PAC_INTFLAGAHB_HPB3_Pos)
-#define PAC_INTFLAGAHB_PUKCC_Pos 11 /**< \brief (PAC_INTFLAGAHB) PUKCC */
-#define PAC_INTFLAGAHB_PUKCC (_U_(0x1) << PAC_INTFLAGAHB_PUKCC_Pos)
-#define PAC_INTFLAGAHB_SDHC0_Pos 12 /**< \brief (PAC_INTFLAGAHB) SDHC0 */
-#define PAC_INTFLAGAHB_SDHC0 (_U_(0x1) << PAC_INTFLAGAHB_SDHC0_Pos)
-#define PAC_INTFLAGAHB_SDHC1_Pos 13 /**< \brief (PAC_INTFLAGAHB) SDHC1 */
-#define PAC_INTFLAGAHB_SDHC1 (_U_(0x1) << PAC_INTFLAGAHB_SDHC1_Pos)
-#define PAC_INTFLAGAHB_QSPI_Pos 14 /**< \brief (PAC_INTFLAGAHB) QSPI */
-#define PAC_INTFLAGAHB_QSPI (_U_(0x1) << PAC_INTFLAGAHB_QSPI_Pos)
-#define PAC_INTFLAGAHB_BKUPRAM_Pos 15 /**< \brief (PAC_INTFLAGAHB) BKUPRAM */
-#define PAC_INTFLAGAHB_BKUPRAM (_U_(0x1) << PAC_INTFLAGAHB_BKUPRAM_Pos)
-#define PAC_INTFLAGAHB_MASK _U_(0x0000FFFF) /**< \brief (PAC_INTFLAGAHB) MASK Register */
-
-/* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint32_t PAC_:1; /*!< bit: 0 PAC */
- __I uint32_t PM_:1; /*!< bit: 1 PM */
- __I uint32_t MCLK_:1; /*!< bit: 2 MCLK */
- __I uint32_t RSTC_:1; /*!< bit: 3 RSTC */
- __I uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL */
- __I uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL */
- __I uint32_t SUPC_:1; /*!< bit: 6 SUPC */
- __I uint32_t GCLK_:1; /*!< bit: 7 GCLK */
- __I uint32_t WDT_:1; /*!< bit: 8 WDT */
- __I uint32_t RTC_:1; /*!< bit: 9 RTC */
- __I uint32_t EIC_:1; /*!< bit: 10 EIC */
- __I uint32_t FREQM_:1; /*!< bit: 11 FREQM */
- __I uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 */
- __I uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 */
- __I uint32_t TC0_:1; /*!< bit: 14 TC0 */
- __I uint32_t TC1_:1; /*!< bit: 15 TC1 */
- __I uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PAC_INTFLAGA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_INTFLAGA_OFFSET 0x14 /**< \brief (PAC_INTFLAGA offset) Peripheral interrupt flag status - Bridge A */
-#define PAC_INTFLAGA_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGA reset_value) Peripheral interrupt flag status - Bridge A */
-
-#define PAC_INTFLAGA_PAC_Pos 0 /**< \brief (PAC_INTFLAGA) PAC */
-#define PAC_INTFLAGA_PAC (_U_(0x1) << PAC_INTFLAGA_PAC_Pos)
-#define PAC_INTFLAGA_PM_Pos 1 /**< \brief (PAC_INTFLAGA) PM */
-#define PAC_INTFLAGA_PM (_U_(0x1) << PAC_INTFLAGA_PM_Pos)
-#define PAC_INTFLAGA_MCLK_Pos 2 /**< \brief (PAC_INTFLAGA) MCLK */
-#define PAC_INTFLAGA_MCLK (_U_(0x1) << PAC_INTFLAGA_MCLK_Pos)
-#define PAC_INTFLAGA_RSTC_Pos 3 /**< \brief (PAC_INTFLAGA) RSTC */
-#define PAC_INTFLAGA_RSTC (_U_(0x1) << PAC_INTFLAGA_RSTC_Pos)
-#define PAC_INTFLAGA_OSCCTRL_Pos 4 /**< \brief (PAC_INTFLAGA) OSCCTRL */
-#define PAC_INTFLAGA_OSCCTRL (_U_(0x1) << PAC_INTFLAGA_OSCCTRL_Pos)
-#define PAC_INTFLAGA_OSC32KCTRL_Pos 5 /**< \brief (PAC_INTFLAGA) OSC32KCTRL */
-#define PAC_INTFLAGA_OSC32KCTRL (_U_(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos)
-#define PAC_INTFLAGA_SUPC_Pos 6 /**< \brief (PAC_INTFLAGA) SUPC */
-#define PAC_INTFLAGA_SUPC (_U_(0x1) << PAC_INTFLAGA_SUPC_Pos)
-#define PAC_INTFLAGA_GCLK_Pos 7 /**< \brief (PAC_INTFLAGA) GCLK */
-#define PAC_INTFLAGA_GCLK (_U_(0x1) << PAC_INTFLAGA_GCLK_Pos)
-#define PAC_INTFLAGA_WDT_Pos 8 /**< \brief (PAC_INTFLAGA) WDT */
-#define PAC_INTFLAGA_WDT (_U_(0x1) << PAC_INTFLAGA_WDT_Pos)
-#define PAC_INTFLAGA_RTC_Pos 9 /**< \brief (PAC_INTFLAGA) RTC */
-#define PAC_INTFLAGA_RTC (_U_(0x1) << PAC_INTFLAGA_RTC_Pos)
-#define PAC_INTFLAGA_EIC_Pos 10 /**< \brief (PAC_INTFLAGA) EIC */
-#define PAC_INTFLAGA_EIC (_U_(0x1) << PAC_INTFLAGA_EIC_Pos)
-#define PAC_INTFLAGA_FREQM_Pos 11 /**< \brief (PAC_INTFLAGA) FREQM */
-#define PAC_INTFLAGA_FREQM (_U_(0x1) << PAC_INTFLAGA_FREQM_Pos)
-#define PAC_INTFLAGA_SERCOM0_Pos 12 /**< \brief (PAC_INTFLAGA) SERCOM0 */
-#define PAC_INTFLAGA_SERCOM0 (_U_(0x1) << PAC_INTFLAGA_SERCOM0_Pos)
-#define PAC_INTFLAGA_SERCOM1_Pos 13 /**< \brief (PAC_INTFLAGA) SERCOM1 */
-#define PAC_INTFLAGA_SERCOM1 (_U_(0x1) << PAC_INTFLAGA_SERCOM1_Pos)
-#define PAC_INTFLAGA_TC0_Pos 14 /**< \brief (PAC_INTFLAGA) TC0 */
-#define PAC_INTFLAGA_TC0 (_U_(0x1) << PAC_INTFLAGA_TC0_Pos)
-#define PAC_INTFLAGA_TC1_Pos 15 /**< \brief (PAC_INTFLAGA) TC1 */
-#define PAC_INTFLAGA_TC1 (_U_(0x1) << PAC_INTFLAGA_TC1_Pos)
-#define PAC_INTFLAGA_MASK _U_(0x0000FFFF) /**< \brief (PAC_INTFLAGA) MASK Register */
-
-/* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint32_t USB_:1; /*!< bit: 0 USB */
- __I uint32_t DSU_:1; /*!< bit: 1 DSU */
- __I uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL */
- __I uint32_t CMCC_:1; /*!< bit: 3 CMCC */
- __I uint32_t PORT_:1; /*!< bit: 4 PORT */
- __I uint32_t DMAC_:1; /*!< bit: 5 DMAC */
- __I uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX */
- __I uint32_t EVSYS_:1; /*!< bit: 7 EVSYS */
- __I uint32_t :1; /*!< bit: 8 Reserved */
- __I uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 */
- __I uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 */
- __I uint32_t TCC0_:1; /*!< bit: 11 TCC0 */
- __I uint32_t TCC1_:1; /*!< bit: 12 TCC1 */
- __I uint32_t TC2_:1; /*!< bit: 13 TC2 */
- __I uint32_t TC3_:1; /*!< bit: 14 TC3 */
- __I uint32_t :1; /*!< bit: 15 Reserved */
- __I uint32_t RAMECC_:1; /*!< bit: 16 RAMECC */
- __I uint32_t :15; /*!< bit: 17..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PAC_INTFLAGB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_INTFLAGB_OFFSET 0x18 /**< \brief (PAC_INTFLAGB offset) Peripheral interrupt flag status - Bridge B */
-#define PAC_INTFLAGB_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGB reset_value) Peripheral interrupt flag status - Bridge B */
-
-#define PAC_INTFLAGB_USB_Pos 0 /**< \brief (PAC_INTFLAGB) USB */
-#define PAC_INTFLAGB_USB (_U_(0x1) << PAC_INTFLAGB_USB_Pos)
-#define PAC_INTFLAGB_DSU_Pos 1 /**< \brief (PAC_INTFLAGB) DSU */
-#define PAC_INTFLAGB_DSU (_U_(0x1) << PAC_INTFLAGB_DSU_Pos)
-#define PAC_INTFLAGB_NVMCTRL_Pos 2 /**< \brief (PAC_INTFLAGB) NVMCTRL */
-#define PAC_INTFLAGB_NVMCTRL (_U_(0x1) << PAC_INTFLAGB_NVMCTRL_Pos)
-#define PAC_INTFLAGB_CMCC_Pos 3 /**< \brief (PAC_INTFLAGB) CMCC */
-#define PAC_INTFLAGB_CMCC (_U_(0x1) << PAC_INTFLAGB_CMCC_Pos)
-#define PAC_INTFLAGB_PORT_Pos 4 /**< \brief (PAC_INTFLAGB) PORT */
-#define PAC_INTFLAGB_PORT (_U_(0x1) << PAC_INTFLAGB_PORT_Pos)
-#define PAC_INTFLAGB_DMAC_Pos 5 /**< \brief (PAC_INTFLAGB) DMAC */
-#define PAC_INTFLAGB_DMAC (_U_(0x1) << PAC_INTFLAGB_DMAC_Pos)
-#define PAC_INTFLAGB_HMATRIX_Pos 6 /**< \brief (PAC_INTFLAGB) HMATRIX */
-#define PAC_INTFLAGB_HMATRIX (_U_(0x1) << PAC_INTFLAGB_HMATRIX_Pos)
-#define PAC_INTFLAGB_EVSYS_Pos 7 /**< \brief (PAC_INTFLAGB) EVSYS */
-#define PAC_INTFLAGB_EVSYS (_U_(0x1) << PAC_INTFLAGB_EVSYS_Pos)
-#define PAC_INTFLAGB_SERCOM2_Pos 9 /**< \brief (PAC_INTFLAGB) SERCOM2 */
-#define PAC_INTFLAGB_SERCOM2 (_U_(0x1) << PAC_INTFLAGB_SERCOM2_Pos)
-#define PAC_INTFLAGB_SERCOM3_Pos 10 /**< \brief (PAC_INTFLAGB) SERCOM3 */
-#define PAC_INTFLAGB_SERCOM3 (_U_(0x1) << PAC_INTFLAGB_SERCOM3_Pos)
-#define PAC_INTFLAGB_TCC0_Pos 11 /**< \brief (PAC_INTFLAGB) TCC0 */
-#define PAC_INTFLAGB_TCC0 (_U_(0x1) << PAC_INTFLAGB_TCC0_Pos)
-#define PAC_INTFLAGB_TCC1_Pos 12 /**< \brief (PAC_INTFLAGB) TCC1 */
-#define PAC_INTFLAGB_TCC1 (_U_(0x1) << PAC_INTFLAGB_TCC1_Pos)
-#define PAC_INTFLAGB_TC2_Pos 13 /**< \brief (PAC_INTFLAGB) TC2 */
-#define PAC_INTFLAGB_TC2 (_U_(0x1) << PAC_INTFLAGB_TC2_Pos)
-#define PAC_INTFLAGB_TC3_Pos 14 /**< \brief (PAC_INTFLAGB) TC3 */
-#define PAC_INTFLAGB_TC3 (_U_(0x1) << PAC_INTFLAGB_TC3_Pos)
-#define PAC_INTFLAGB_RAMECC_Pos 16 /**< \brief (PAC_INTFLAGB) RAMECC */
-#define PAC_INTFLAGB_RAMECC (_U_(0x1) << PAC_INTFLAGB_RAMECC_Pos)
-#define PAC_INTFLAGB_MASK _U_(0x00017EFF) /**< \brief (PAC_INTFLAGB) MASK Register */
-
-/* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint32_t CAN0_:1; /*!< bit: 0 CAN0 */
- __I uint32_t CAN1_:1; /*!< bit: 1 CAN1 */
- __I uint32_t GMAC_:1; /*!< bit: 2 GMAC */
- __I uint32_t TCC2_:1; /*!< bit: 3 TCC2 */
- __I uint32_t TCC3_:1; /*!< bit: 4 TCC3 */
- __I uint32_t TC4_:1; /*!< bit: 5 TC4 */
- __I uint32_t TC5_:1; /*!< bit: 6 TC5 */
- __I uint32_t PDEC_:1; /*!< bit: 7 PDEC */
- __I uint32_t AC_:1; /*!< bit: 8 AC */
- __I uint32_t AES_:1; /*!< bit: 9 AES */
- __I uint32_t TRNG_:1; /*!< bit: 10 TRNG */
- __I uint32_t ICM_:1; /*!< bit: 11 ICM */
- __I uint32_t PUKCC_:1; /*!< bit: 12 PUKCC */
- __I uint32_t QSPI_:1; /*!< bit: 13 QSPI */
- __I uint32_t CCL_:1; /*!< bit: 14 CCL */
- __I uint32_t :17; /*!< bit: 15..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PAC_INTFLAGC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_INTFLAGC_OFFSET 0x1C /**< \brief (PAC_INTFLAGC offset) Peripheral interrupt flag status - Bridge C */
-#define PAC_INTFLAGC_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGC reset_value) Peripheral interrupt flag status - Bridge C */
-
-#define PAC_INTFLAGC_CAN0_Pos 0 /**< \brief (PAC_INTFLAGC) CAN0 */
-#define PAC_INTFLAGC_CAN0 (_U_(0x1) << PAC_INTFLAGC_CAN0_Pos)
-#define PAC_INTFLAGC_CAN1_Pos 1 /**< \brief (PAC_INTFLAGC) CAN1 */
-#define PAC_INTFLAGC_CAN1 (_U_(0x1) << PAC_INTFLAGC_CAN1_Pos)
-#define PAC_INTFLAGC_GMAC_Pos 2 /**< \brief (PAC_INTFLAGC) GMAC */
-#define PAC_INTFLAGC_GMAC (_U_(0x1) << PAC_INTFLAGC_GMAC_Pos)
-#define PAC_INTFLAGC_TCC2_Pos 3 /**< \brief (PAC_INTFLAGC) TCC2 */
-#define PAC_INTFLAGC_TCC2 (_U_(0x1) << PAC_INTFLAGC_TCC2_Pos)
-#define PAC_INTFLAGC_TCC3_Pos 4 /**< \brief (PAC_INTFLAGC) TCC3 */
-#define PAC_INTFLAGC_TCC3 (_U_(0x1) << PAC_INTFLAGC_TCC3_Pos)
-#define PAC_INTFLAGC_TC4_Pos 5 /**< \brief (PAC_INTFLAGC) TC4 */
-#define PAC_INTFLAGC_TC4 (_U_(0x1) << PAC_INTFLAGC_TC4_Pos)
-#define PAC_INTFLAGC_TC5_Pos 6 /**< \brief (PAC_INTFLAGC) TC5 */
-#define PAC_INTFLAGC_TC5 (_U_(0x1) << PAC_INTFLAGC_TC5_Pos)
-#define PAC_INTFLAGC_PDEC_Pos 7 /**< \brief (PAC_INTFLAGC) PDEC */
-#define PAC_INTFLAGC_PDEC (_U_(0x1) << PAC_INTFLAGC_PDEC_Pos)
-#define PAC_INTFLAGC_AC_Pos 8 /**< \brief (PAC_INTFLAGC) AC */
-#define PAC_INTFLAGC_AC (_U_(0x1) << PAC_INTFLAGC_AC_Pos)
-#define PAC_INTFLAGC_AES_Pos 9 /**< \brief (PAC_INTFLAGC) AES */
-#define PAC_INTFLAGC_AES (_U_(0x1) << PAC_INTFLAGC_AES_Pos)
-#define PAC_INTFLAGC_TRNG_Pos 10 /**< \brief (PAC_INTFLAGC) TRNG */
-#define PAC_INTFLAGC_TRNG (_U_(0x1) << PAC_INTFLAGC_TRNG_Pos)
-#define PAC_INTFLAGC_ICM_Pos 11 /**< \brief (PAC_INTFLAGC) ICM */
-#define PAC_INTFLAGC_ICM (_U_(0x1) << PAC_INTFLAGC_ICM_Pos)
-#define PAC_INTFLAGC_PUKCC_Pos 12 /**< \brief (PAC_INTFLAGC) PUKCC */
-#define PAC_INTFLAGC_PUKCC (_U_(0x1) << PAC_INTFLAGC_PUKCC_Pos)
-#define PAC_INTFLAGC_QSPI_Pos 13 /**< \brief (PAC_INTFLAGC) QSPI */
-#define PAC_INTFLAGC_QSPI (_U_(0x1) << PAC_INTFLAGC_QSPI_Pos)
-#define PAC_INTFLAGC_CCL_Pos 14 /**< \brief (PAC_INTFLAGC) CCL */
-#define PAC_INTFLAGC_CCL (_U_(0x1) << PAC_INTFLAGC_CCL_Pos)
-#define PAC_INTFLAGC_MASK _U_(0x00007FFF) /**< \brief (PAC_INTFLAGC) MASK Register */
-
-/* -------- PAC_INTFLAGD : (PAC Offset: 0x20) (R/W 32) Peripheral interrupt flag status - Bridge D -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 */
- __I uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 */
- __I uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 */
- __I uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 */
- __I uint32_t TCC4_:1; /*!< bit: 4 TCC4 */
- __I uint32_t TC6_:1; /*!< bit: 5 TC6 */
- __I uint32_t TC7_:1; /*!< bit: 6 TC7 */
- __I uint32_t ADC0_:1; /*!< bit: 7 ADC0 */
- __I uint32_t ADC1_:1; /*!< bit: 8 ADC1 */
- __I uint32_t DAC_:1; /*!< bit: 9 DAC */
- __I uint32_t I2S_:1; /*!< bit: 10 I2S */
- __I uint32_t PCC_:1; /*!< bit: 11 PCC */
- __I uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PAC_INTFLAGD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_INTFLAGD_OFFSET 0x20 /**< \brief (PAC_INTFLAGD offset) Peripheral interrupt flag status - Bridge D */
-#define PAC_INTFLAGD_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGD reset_value) Peripheral interrupt flag status - Bridge D */
-
-#define PAC_INTFLAGD_SERCOM4_Pos 0 /**< \brief (PAC_INTFLAGD) SERCOM4 */
-#define PAC_INTFLAGD_SERCOM4 (_U_(0x1) << PAC_INTFLAGD_SERCOM4_Pos)
-#define PAC_INTFLAGD_SERCOM5_Pos 1 /**< \brief (PAC_INTFLAGD) SERCOM5 */
-#define PAC_INTFLAGD_SERCOM5 (_U_(0x1) << PAC_INTFLAGD_SERCOM5_Pos)
-#define PAC_INTFLAGD_SERCOM6_Pos 2 /**< \brief (PAC_INTFLAGD) SERCOM6 */
-#define PAC_INTFLAGD_SERCOM6 (_U_(0x1) << PAC_INTFLAGD_SERCOM6_Pos)
-#define PAC_INTFLAGD_SERCOM7_Pos 3 /**< \brief (PAC_INTFLAGD) SERCOM7 */
-#define PAC_INTFLAGD_SERCOM7 (_U_(0x1) << PAC_INTFLAGD_SERCOM7_Pos)
-#define PAC_INTFLAGD_TCC4_Pos 4 /**< \brief (PAC_INTFLAGD) TCC4 */
-#define PAC_INTFLAGD_TCC4 (_U_(0x1) << PAC_INTFLAGD_TCC4_Pos)
-#define PAC_INTFLAGD_TC6_Pos 5 /**< \brief (PAC_INTFLAGD) TC6 */
-#define PAC_INTFLAGD_TC6 (_U_(0x1) << PAC_INTFLAGD_TC6_Pos)
-#define PAC_INTFLAGD_TC7_Pos 6 /**< \brief (PAC_INTFLAGD) TC7 */
-#define PAC_INTFLAGD_TC7 (_U_(0x1) << PAC_INTFLAGD_TC7_Pos)
-#define PAC_INTFLAGD_ADC0_Pos 7 /**< \brief (PAC_INTFLAGD) ADC0 */
-#define PAC_INTFLAGD_ADC0 (_U_(0x1) << PAC_INTFLAGD_ADC0_Pos)
-#define PAC_INTFLAGD_ADC1_Pos 8 /**< \brief (PAC_INTFLAGD) ADC1 */
-#define PAC_INTFLAGD_ADC1 (_U_(0x1) << PAC_INTFLAGD_ADC1_Pos)
-#define PAC_INTFLAGD_DAC_Pos 9 /**< \brief (PAC_INTFLAGD) DAC */
-#define PAC_INTFLAGD_DAC (_U_(0x1) << PAC_INTFLAGD_DAC_Pos)
-#define PAC_INTFLAGD_I2S_Pos 10 /**< \brief (PAC_INTFLAGD) I2S */
-#define PAC_INTFLAGD_I2S (_U_(0x1) << PAC_INTFLAGD_I2S_Pos)
-#define PAC_INTFLAGD_PCC_Pos 11 /**< \brief (PAC_INTFLAGD) PCC */
-#define PAC_INTFLAGD_PCC (_U_(0x1) << PAC_INTFLAGD_PCC_Pos)
-#define PAC_INTFLAGD_MASK _U_(0x00000FFF) /**< \brief (PAC_INTFLAGD) MASK Register */
-
-/* -------- PAC_STATUSA : (PAC Offset: 0x34) (R/ 32) Peripheral write protection status - Bridge A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t PAC_:1; /*!< bit: 0 PAC APB Protect Enable */
- uint32_t PM_:1; /*!< bit: 1 PM APB Protect Enable */
- uint32_t MCLK_:1; /*!< bit: 2 MCLK APB Protect Enable */
- uint32_t RSTC_:1; /*!< bit: 3 RSTC APB Protect Enable */
- uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL APB Protect Enable */
- uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL APB Protect Enable */
- uint32_t SUPC_:1; /*!< bit: 6 SUPC APB Protect Enable */
- uint32_t GCLK_:1; /*!< bit: 7 GCLK APB Protect Enable */
- uint32_t WDT_:1; /*!< bit: 8 WDT APB Protect Enable */
- uint32_t RTC_:1; /*!< bit: 9 RTC APB Protect Enable */
- uint32_t EIC_:1; /*!< bit: 10 EIC APB Protect Enable */
- uint32_t FREQM_:1; /*!< bit: 11 FREQM APB Protect Enable */
- uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 APB Protect Enable */
- uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 APB Protect Enable */
- uint32_t TC0_:1; /*!< bit: 14 TC0 APB Protect Enable */
- uint32_t TC1_:1; /*!< bit: 15 TC1 APB Protect Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PAC_STATUSA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_STATUSA_OFFSET 0x34 /**< \brief (PAC_STATUSA offset) Peripheral write protection status - Bridge A */
-#define PAC_STATUSA_RESETVALUE _U_(0x00010000) /**< \brief (PAC_STATUSA reset_value) Peripheral write protection status - Bridge A */
-
-#define PAC_STATUSA_PAC_Pos 0 /**< \brief (PAC_STATUSA) PAC APB Protect Enable */
-#define PAC_STATUSA_PAC (_U_(0x1) << PAC_STATUSA_PAC_Pos)
-#define PAC_STATUSA_PM_Pos 1 /**< \brief (PAC_STATUSA) PM APB Protect Enable */
-#define PAC_STATUSA_PM (_U_(0x1) << PAC_STATUSA_PM_Pos)
-#define PAC_STATUSA_MCLK_Pos 2 /**< \brief (PAC_STATUSA) MCLK APB Protect Enable */
-#define PAC_STATUSA_MCLK (_U_(0x1) << PAC_STATUSA_MCLK_Pos)
-#define PAC_STATUSA_RSTC_Pos 3 /**< \brief (PAC_STATUSA) RSTC APB Protect Enable */
-#define PAC_STATUSA_RSTC (_U_(0x1) << PAC_STATUSA_RSTC_Pos)
-#define PAC_STATUSA_OSCCTRL_Pos 4 /**< \brief (PAC_STATUSA) OSCCTRL APB Protect Enable */
-#define PAC_STATUSA_OSCCTRL (_U_(0x1) << PAC_STATUSA_OSCCTRL_Pos)
-#define PAC_STATUSA_OSC32KCTRL_Pos 5 /**< \brief (PAC_STATUSA) OSC32KCTRL APB Protect Enable */
-#define PAC_STATUSA_OSC32KCTRL (_U_(0x1) << PAC_STATUSA_OSC32KCTRL_Pos)
-#define PAC_STATUSA_SUPC_Pos 6 /**< \brief (PAC_STATUSA) SUPC APB Protect Enable */
-#define PAC_STATUSA_SUPC (_U_(0x1) << PAC_STATUSA_SUPC_Pos)
-#define PAC_STATUSA_GCLK_Pos 7 /**< \brief (PAC_STATUSA) GCLK APB Protect Enable */
-#define PAC_STATUSA_GCLK (_U_(0x1) << PAC_STATUSA_GCLK_Pos)
-#define PAC_STATUSA_WDT_Pos 8 /**< \brief (PAC_STATUSA) WDT APB Protect Enable */
-#define PAC_STATUSA_WDT (_U_(0x1) << PAC_STATUSA_WDT_Pos)
-#define PAC_STATUSA_RTC_Pos 9 /**< \brief (PAC_STATUSA) RTC APB Protect Enable */
-#define PAC_STATUSA_RTC (_U_(0x1) << PAC_STATUSA_RTC_Pos)
-#define PAC_STATUSA_EIC_Pos 10 /**< \brief (PAC_STATUSA) EIC APB Protect Enable */
-#define PAC_STATUSA_EIC (_U_(0x1) << PAC_STATUSA_EIC_Pos)
-#define PAC_STATUSA_FREQM_Pos 11 /**< \brief (PAC_STATUSA) FREQM APB Protect Enable */
-#define PAC_STATUSA_FREQM (_U_(0x1) << PAC_STATUSA_FREQM_Pos)
-#define PAC_STATUSA_SERCOM0_Pos 12 /**< \brief (PAC_STATUSA) SERCOM0 APB Protect Enable */
-#define PAC_STATUSA_SERCOM0 (_U_(0x1) << PAC_STATUSA_SERCOM0_Pos)
-#define PAC_STATUSA_SERCOM1_Pos 13 /**< \brief (PAC_STATUSA) SERCOM1 APB Protect Enable */
-#define PAC_STATUSA_SERCOM1 (_U_(0x1) << PAC_STATUSA_SERCOM1_Pos)
-#define PAC_STATUSA_TC0_Pos 14 /**< \brief (PAC_STATUSA) TC0 APB Protect Enable */
-#define PAC_STATUSA_TC0 (_U_(0x1) << PAC_STATUSA_TC0_Pos)
-#define PAC_STATUSA_TC1_Pos 15 /**< \brief (PAC_STATUSA) TC1 APB Protect Enable */
-#define PAC_STATUSA_TC1 (_U_(0x1) << PAC_STATUSA_TC1_Pos)
-#define PAC_STATUSA_MASK _U_(0x0000FFFF) /**< \brief (PAC_STATUSA) MASK Register */
-
-/* -------- PAC_STATUSB : (PAC Offset: 0x38) (R/ 32) Peripheral write protection status - Bridge B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t USB_:1; /*!< bit: 0 USB APB Protect Enable */
- uint32_t DSU_:1; /*!< bit: 1 DSU APB Protect Enable */
- uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Protect Enable */
- uint32_t CMCC_:1; /*!< bit: 3 CMCC APB Protect Enable */
- uint32_t PORT_:1; /*!< bit: 4 PORT APB Protect Enable */
- uint32_t DMAC_:1; /*!< bit: 5 DMAC APB Protect Enable */
- uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Protect Enable */
- uint32_t EVSYS_:1; /*!< bit: 7 EVSYS APB Protect Enable */
- uint32_t :1; /*!< bit: 8 Reserved */
- uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 APB Protect Enable */
- uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 APB Protect Enable */
- uint32_t TCC0_:1; /*!< bit: 11 TCC0 APB Protect Enable */
- uint32_t TCC1_:1; /*!< bit: 12 TCC1 APB Protect Enable */
- uint32_t TC2_:1; /*!< bit: 13 TC2 APB Protect Enable */
- uint32_t TC3_:1; /*!< bit: 14 TC3 APB Protect Enable */
- uint32_t :1; /*!< bit: 15 Reserved */
- uint32_t RAMECC_:1; /*!< bit: 16 RAMECC APB Protect Enable */
- uint32_t :15; /*!< bit: 17..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PAC_STATUSB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_STATUSB_OFFSET 0x38 /**< \brief (PAC_STATUSB offset) Peripheral write protection status - Bridge B */
-#define PAC_STATUSB_RESETVALUE _U_(0x00000002) /**< \brief (PAC_STATUSB reset_value) Peripheral write protection status - Bridge B */
-
-#define PAC_STATUSB_USB_Pos 0 /**< \brief (PAC_STATUSB) USB APB Protect Enable */
-#define PAC_STATUSB_USB (_U_(0x1) << PAC_STATUSB_USB_Pos)
-#define PAC_STATUSB_DSU_Pos 1 /**< \brief (PAC_STATUSB) DSU APB Protect Enable */
-#define PAC_STATUSB_DSU (_U_(0x1) << PAC_STATUSB_DSU_Pos)
-#define PAC_STATUSB_NVMCTRL_Pos 2 /**< \brief (PAC_STATUSB) NVMCTRL APB Protect Enable */
-#define PAC_STATUSB_NVMCTRL (_U_(0x1) << PAC_STATUSB_NVMCTRL_Pos)
-#define PAC_STATUSB_CMCC_Pos 3 /**< \brief (PAC_STATUSB) CMCC APB Protect Enable */
-#define PAC_STATUSB_CMCC (_U_(0x1) << PAC_STATUSB_CMCC_Pos)
-#define PAC_STATUSB_PORT_Pos 4 /**< \brief (PAC_STATUSB) PORT APB Protect Enable */
-#define PAC_STATUSB_PORT (_U_(0x1) << PAC_STATUSB_PORT_Pos)
-#define PAC_STATUSB_DMAC_Pos 5 /**< \brief (PAC_STATUSB) DMAC APB Protect Enable */
-#define PAC_STATUSB_DMAC (_U_(0x1) << PAC_STATUSB_DMAC_Pos)
-#define PAC_STATUSB_HMATRIX_Pos 6 /**< \brief (PAC_STATUSB) HMATRIX APB Protect Enable */
-#define PAC_STATUSB_HMATRIX (_U_(0x1) << PAC_STATUSB_HMATRIX_Pos)
-#define PAC_STATUSB_EVSYS_Pos 7 /**< \brief (PAC_STATUSB) EVSYS APB Protect Enable */
-#define PAC_STATUSB_EVSYS (_U_(0x1) << PAC_STATUSB_EVSYS_Pos)
-#define PAC_STATUSB_SERCOM2_Pos 9 /**< \brief (PAC_STATUSB) SERCOM2 APB Protect Enable */
-#define PAC_STATUSB_SERCOM2 (_U_(0x1) << PAC_STATUSB_SERCOM2_Pos)
-#define PAC_STATUSB_SERCOM3_Pos 10 /**< \brief (PAC_STATUSB) SERCOM3 APB Protect Enable */
-#define PAC_STATUSB_SERCOM3 (_U_(0x1) << PAC_STATUSB_SERCOM3_Pos)
-#define PAC_STATUSB_TCC0_Pos 11 /**< \brief (PAC_STATUSB) TCC0 APB Protect Enable */
-#define PAC_STATUSB_TCC0 (_U_(0x1) << PAC_STATUSB_TCC0_Pos)
-#define PAC_STATUSB_TCC1_Pos 12 /**< \brief (PAC_STATUSB) TCC1 APB Protect Enable */
-#define PAC_STATUSB_TCC1 (_U_(0x1) << PAC_STATUSB_TCC1_Pos)
-#define PAC_STATUSB_TC2_Pos 13 /**< \brief (PAC_STATUSB) TC2 APB Protect Enable */
-#define PAC_STATUSB_TC2 (_U_(0x1) << PAC_STATUSB_TC2_Pos)
-#define PAC_STATUSB_TC3_Pos 14 /**< \brief (PAC_STATUSB) TC3 APB Protect Enable */
-#define PAC_STATUSB_TC3 (_U_(0x1) << PAC_STATUSB_TC3_Pos)
-#define PAC_STATUSB_RAMECC_Pos 16 /**< \brief (PAC_STATUSB) RAMECC APB Protect Enable */
-#define PAC_STATUSB_RAMECC (_U_(0x1) << PAC_STATUSB_RAMECC_Pos)
-#define PAC_STATUSB_MASK _U_(0x00017EFF) /**< \brief (PAC_STATUSB) MASK Register */
-
-/* -------- PAC_STATUSC : (PAC Offset: 0x3C) (R/ 32) Peripheral write protection status - Bridge C -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CAN0_:1; /*!< bit: 0 CAN0 APB Protect Enable */
- uint32_t CAN1_:1; /*!< bit: 1 CAN1 APB Protect Enable */
- uint32_t GMAC_:1; /*!< bit: 2 GMAC APB Protect Enable */
- uint32_t TCC2_:1; /*!< bit: 3 TCC2 APB Protect Enable */
- uint32_t TCC3_:1; /*!< bit: 4 TCC3 APB Protect Enable */
- uint32_t TC4_:1; /*!< bit: 5 TC4 APB Protect Enable */
- uint32_t TC5_:1; /*!< bit: 6 TC5 APB Protect Enable */
- uint32_t PDEC_:1; /*!< bit: 7 PDEC APB Protect Enable */
- uint32_t AC_:1; /*!< bit: 8 AC APB Protect Enable */
- uint32_t AES_:1; /*!< bit: 9 AES APB Protect Enable */
- uint32_t TRNG_:1; /*!< bit: 10 TRNG APB Protect Enable */
- uint32_t ICM_:1; /*!< bit: 11 ICM APB Protect Enable */
- uint32_t PUKCC_:1; /*!< bit: 12 PUKCC APB Protect Enable */
- uint32_t QSPI_:1; /*!< bit: 13 QSPI APB Protect Enable */
- uint32_t CCL_:1; /*!< bit: 14 CCL APB Protect Enable */
- uint32_t :17; /*!< bit: 15..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PAC_STATUSC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_STATUSC_OFFSET 0x3C /**< \brief (PAC_STATUSC offset) Peripheral write protection status - Bridge C */
-#define PAC_STATUSC_RESETVALUE _U_(0x00000000) /**< \brief (PAC_STATUSC reset_value) Peripheral write protection status - Bridge C */
-
-#define PAC_STATUSC_CAN0_Pos 0 /**< \brief (PAC_STATUSC) CAN0 APB Protect Enable */
-#define PAC_STATUSC_CAN0 (_U_(0x1) << PAC_STATUSC_CAN0_Pos)
-#define PAC_STATUSC_CAN1_Pos 1 /**< \brief (PAC_STATUSC) CAN1 APB Protect Enable */
-#define PAC_STATUSC_CAN1 (_U_(0x1) << PAC_STATUSC_CAN1_Pos)
-#define PAC_STATUSC_GMAC_Pos 2 /**< \brief (PAC_STATUSC) GMAC APB Protect Enable */
-#define PAC_STATUSC_GMAC (_U_(0x1) << PAC_STATUSC_GMAC_Pos)
-#define PAC_STATUSC_TCC2_Pos 3 /**< \brief (PAC_STATUSC) TCC2 APB Protect Enable */
-#define PAC_STATUSC_TCC2 (_U_(0x1) << PAC_STATUSC_TCC2_Pos)
-#define PAC_STATUSC_TCC3_Pos 4 /**< \brief (PAC_STATUSC) TCC3 APB Protect Enable */
-#define PAC_STATUSC_TCC3 (_U_(0x1) << PAC_STATUSC_TCC3_Pos)
-#define PAC_STATUSC_TC4_Pos 5 /**< \brief (PAC_STATUSC) TC4 APB Protect Enable */
-#define PAC_STATUSC_TC4 (_U_(0x1) << PAC_STATUSC_TC4_Pos)
-#define PAC_STATUSC_TC5_Pos 6 /**< \brief (PAC_STATUSC) TC5 APB Protect Enable */
-#define PAC_STATUSC_TC5 (_U_(0x1) << PAC_STATUSC_TC5_Pos)
-#define PAC_STATUSC_PDEC_Pos 7 /**< \brief (PAC_STATUSC) PDEC APB Protect Enable */
-#define PAC_STATUSC_PDEC (_U_(0x1) << PAC_STATUSC_PDEC_Pos)
-#define PAC_STATUSC_AC_Pos 8 /**< \brief (PAC_STATUSC) AC APB Protect Enable */
-#define PAC_STATUSC_AC (_U_(0x1) << PAC_STATUSC_AC_Pos)
-#define PAC_STATUSC_AES_Pos 9 /**< \brief (PAC_STATUSC) AES APB Protect Enable */
-#define PAC_STATUSC_AES (_U_(0x1) << PAC_STATUSC_AES_Pos)
-#define PAC_STATUSC_TRNG_Pos 10 /**< \brief (PAC_STATUSC) TRNG APB Protect Enable */
-#define PAC_STATUSC_TRNG (_U_(0x1) << PAC_STATUSC_TRNG_Pos)
-#define PAC_STATUSC_ICM_Pos 11 /**< \brief (PAC_STATUSC) ICM APB Protect Enable */
-#define PAC_STATUSC_ICM (_U_(0x1) << PAC_STATUSC_ICM_Pos)
-#define PAC_STATUSC_PUKCC_Pos 12 /**< \brief (PAC_STATUSC) PUKCC APB Protect Enable */
-#define PAC_STATUSC_PUKCC (_U_(0x1) << PAC_STATUSC_PUKCC_Pos)
-#define PAC_STATUSC_QSPI_Pos 13 /**< \brief (PAC_STATUSC) QSPI APB Protect Enable */
-#define PAC_STATUSC_QSPI (_U_(0x1) << PAC_STATUSC_QSPI_Pos)
-#define PAC_STATUSC_CCL_Pos 14 /**< \brief (PAC_STATUSC) CCL APB Protect Enable */
-#define PAC_STATUSC_CCL (_U_(0x1) << PAC_STATUSC_CCL_Pos)
-#define PAC_STATUSC_MASK _U_(0x00007FFF) /**< \brief (PAC_STATUSC) MASK Register */
-
-/* -------- PAC_STATUSD : (PAC Offset: 0x40) (R/ 32) Peripheral write protection status - Bridge D -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 APB Protect Enable */
- uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Protect Enable */
- uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 APB Protect Enable */
- uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 APB Protect Enable */
- uint32_t TCC4_:1; /*!< bit: 4 TCC4 APB Protect Enable */
- uint32_t TC6_:1; /*!< bit: 5 TC6 APB Protect Enable */
- uint32_t TC7_:1; /*!< bit: 6 TC7 APB Protect Enable */
- uint32_t ADC0_:1; /*!< bit: 7 ADC0 APB Protect Enable */
- uint32_t ADC1_:1; /*!< bit: 8 ADC1 APB Protect Enable */
- uint32_t DAC_:1; /*!< bit: 9 DAC APB Protect Enable */
- uint32_t I2S_:1; /*!< bit: 10 I2S APB Protect Enable */
- uint32_t PCC_:1; /*!< bit: 11 PCC APB Protect Enable */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PAC_STATUSD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_STATUSD_OFFSET 0x40 /**< \brief (PAC_STATUSD offset) Peripheral write protection status - Bridge D */
-#define PAC_STATUSD_RESETVALUE _U_(0x00000000) /**< \brief (PAC_STATUSD reset_value) Peripheral write protection status - Bridge D */
-
-#define PAC_STATUSD_SERCOM4_Pos 0 /**< \brief (PAC_STATUSD) SERCOM4 APB Protect Enable */
-#define PAC_STATUSD_SERCOM4 (_U_(0x1) << PAC_STATUSD_SERCOM4_Pos)
-#define PAC_STATUSD_SERCOM5_Pos 1 /**< \brief (PAC_STATUSD) SERCOM5 APB Protect Enable */
-#define PAC_STATUSD_SERCOM5 (_U_(0x1) << PAC_STATUSD_SERCOM5_Pos)
-#define PAC_STATUSD_SERCOM6_Pos 2 /**< \brief (PAC_STATUSD) SERCOM6 APB Protect Enable */
-#define PAC_STATUSD_SERCOM6 (_U_(0x1) << PAC_STATUSD_SERCOM6_Pos)
-#define PAC_STATUSD_SERCOM7_Pos 3 /**< \brief (PAC_STATUSD) SERCOM7 APB Protect Enable */
-#define PAC_STATUSD_SERCOM7 (_U_(0x1) << PAC_STATUSD_SERCOM7_Pos)
-#define PAC_STATUSD_TCC4_Pos 4 /**< \brief (PAC_STATUSD) TCC4 APB Protect Enable */
-#define PAC_STATUSD_TCC4 (_U_(0x1) << PAC_STATUSD_TCC4_Pos)
-#define PAC_STATUSD_TC6_Pos 5 /**< \brief (PAC_STATUSD) TC6 APB Protect Enable */
-#define PAC_STATUSD_TC6 (_U_(0x1) << PAC_STATUSD_TC6_Pos)
-#define PAC_STATUSD_TC7_Pos 6 /**< \brief (PAC_STATUSD) TC7 APB Protect Enable */
-#define PAC_STATUSD_TC7 (_U_(0x1) << PAC_STATUSD_TC7_Pos)
-#define PAC_STATUSD_ADC0_Pos 7 /**< \brief (PAC_STATUSD) ADC0 APB Protect Enable */
-#define PAC_STATUSD_ADC0 (_U_(0x1) << PAC_STATUSD_ADC0_Pos)
-#define PAC_STATUSD_ADC1_Pos 8 /**< \brief (PAC_STATUSD) ADC1 APB Protect Enable */
-#define PAC_STATUSD_ADC1 (_U_(0x1) << PAC_STATUSD_ADC1_Pos)
-#define PAC_STATUSD_DAC_Pos 9 /**< \brief (PAC_STATUSD) DAC APB Protect Enable */
-#define PAC_STATUSD_DAC (_U_(0x1) << PAC_STATUSD_DAC_Pos)
-#define PAC_STATUSD_I2S_Pos 10 /**< \brief (PAC_STATUSD) I2S APB Protect Enable */
-#define PAC_STATUSD_I2S (_U_(0x1) << PAC_STATUSD_I2S_Pos)
-#define PAC_STATUSD_PCC_Pos 11 /**< \brief (PAC_STATUSD) PCC APB Protect Enable */
-#define PAC_STATUSD_PCC (_U_(0x1) << PAC_STATUSD_PCC_Pos)
-#define PAC_STATUSD_MASK _U_(0x00000FFF) /**< \brief (PAC_STATUSD) MASK Register */
-
-/** \brief PAC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO PAC_WRCTRL_Type WRCTRL; /**< \brief Offset: 0x00 (R/W 32) Write control */
- __IO PAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event control */
- RoReg8 Reserved1[0x3];
- __IO PAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt enable clear */
- __IO PAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt enable set */
- RoReg8 Reserved2[0x6];
- __IO PAC_INTFLAGAHB_Type INTFLAGAHB; /**< \brief Offset: 0x10 (R/W 32) Bridge interrupt flag status */
- __IO PAC_INTFLAGA_Type INTFLAGA; /**< \brief Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */
- __IO PAC_INTFLAGB_Type INTFLAGB; /**< \brief Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */
- __IO PAC_INTFLAGC_Type INTFLAGC; /**< \brief Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */
- __IO PAC_INTFLAGD_Type INTFLAGD; /**< \brief Offset: 0x20 (R/W 32) Peripheral interrupt flag status - Bridge D */
- RoReg8 Reserved3[0x10];
- __I PAC_STATUSA_Type STATUSA; /**< \brief Offset: 0x34 (R/ 32) Peripheral write protection status - Bridge A */
- __I PAC_STATUSB_Type STATUSB; /**< \brief Offset: 0x38 (R/ 32) Peripheral write protection status - Bridge B */
- __I PAC_STATUSC_Type STATUSC; /**< \brief Offset: 0x3C (R/ 32) Peripheral write protection status - Bridge C */
- __I PAC_STATUSD_Type STATUSD; /**< \brief Offset: 0x40 (R/ 32) Peripheral write protection status - Bridge D */
-} Pac;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_PAC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for PAC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_PAC_COMPONENT_
+#define _SAME54_PAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PAC */
+/* ========================================================================== */
+/** \addtogroup SAME54_PAC Peripheral Access Controller */
+/*@{*/
+
+#define PAC_U2120
+#define REV_PAC 0x120
+
+/* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PERID:16; /*!< bit: 0..15 Peripheral identifier */
+ uint32_t KEY:8; /*!< bit: 16..23 Peripheral access control key */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_WRCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_WRCTRL_OFFSET 0x00 /**< \brief (PAC_WRCTRL offset) Write control */
+#define PAC_WRCTRL_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WRCTRL reset_value) Write control */
+
+#define PAC_WRCTRL_PERID_Pos 0 /**< \brief (PAC_WRCTRL) Peripheral identifier */
+#define PAC_WRCTRL_PERID_Msk (_U_(0xFFFF) << PAC_WRCTRL_PERID_Pos)
+#define PAC_WRCTRL_PERID(value) (PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos))
+#define PAC_WRCTRL_KEY_Pos 16 /**< \brief (PAC_WRCTRL) Peripheral access control key */
+#define PAC_WRCTRL_KEY_Msk (_U_(0xFF) << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_KEY(value) (PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos))
+#define PAC_WRCTRL_KEY_OFF_Val _U_(0x0) /**< \brief (PAC_WRCTRL) No action */
+#define PAC_WRCTRL_KEY_CLR_Val _U_(0x1) /**< \brief (PAC_WRCTRL) Clear protection */
+#define PAC_WRCTRL_KEY_SET_Val _U_(0x2) /**< \brief (PAC_WRCTRL) Set protection */
+#define PAC_WRCTRL_KEY_SETLCK_Val _U_(0x3) /**< \brief (PAC_WRCTRL) Set and lock protection */
+#define PAC_WRCTRL_KEY_OFF (PAC_WRCTRL_KEY_OFF_Val << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_KEY_CLR (PAC_WRCTRL_KEY_CLR_Val << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_KEY_SET (PAC_WRCTRL_KEY_SET_Val << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_KEY_SETLCK (PAC_WRCTRL_KEY_SETLCK_Val << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_MASK _U_(0x00FFFFFF) /**< \brief (PAC_WRCTRL) MASK Register */
+
+/* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W 8) Event control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ERREO:1; /*!< bit: 0 Peripheral acess error event output */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PAC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_EVCTRL_OFFSET 0x04 /**< \brief (PAC_EVCTRL offset) Event control */
+#define PAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (PAC_EVCTRL reset_value) Event control */
+
+#define PAC_EVCTRL_ERREO_Pos 0 /**< \brief (PAC_EVCTRL) Peripheral acess error event output */
+#define PAC_EVCTRL_ERREO (_U_(0x1) << PAC_EVCTRL_ERREO_Pos)
+#define PAC_EVCTRL_MASK _U_(0x01) /**< \brief (PAC_EVCTRL) MASK Register */
+
+/* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W 8) Interrupt enable clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt disable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PAC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTENCLR_OFFSET 0x08 /**< \brief (PAC_INTENCLR offset) Interrupt enable clear */
+#define PAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PAC_INTENCLR reset_value) Interrupt enable clear */
+
+#define PAC_INTENCLR_ERR_Pos 0 /**< \brief (PAC_INTENCLR) Peripheral access error interrupt disable */
+#define PAC_INTENCLR_ERR (_U_(0x1) << PAC_INTENCLR_ERR_Pos)
+#define PAC_INTENCLR_MASK _U_(0x01) /**< \brief (PAC_INTENCLR) MASK Register */
+
+/* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W 8) Interrupt enable set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PAC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTENSET_OFFSET 0x09 /**< \brief (PAC_INTENSET offset) Interrupt enable set */
+#define PAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PAC_INTENSET reset_value) Interrupt enable set */
+
+#define PAC_INTENSET_ERR_Pos 0 /**< \brief (PAC_INTENSET) Peripheral access error interrupt enable */
+#define PAC_INTENSET_ERR (_U_(0x1) << PAC_INTENSET_ERR_Pos)
+#define PAC_INTENSET_MASK _U_(0x01) /**< \brief (PAC_INTENSET) MASK Register */
+
+/* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t FLASH_:1; /*!< bit: 0 FLASH */
+ __I uint32_t FLASH_ALT_:1; /*!< bit: 1 FLASH_ALT */
+ __I uint32_t SEEPROM_:1; /*!< bit: 2 SEEPROM */
+ __I uint32_t RAMCM4S_:1; /*!< bit: 3 RAMCM4S */
+ __I uint32_t RAMPPPDSU_:1; /*!< bit: 4 RAMPPPDSU */
+ __I uint32_t RAMDMAWR_:1; /*!< bit: 5 RAMDMAWR */
+ __I uint32_t RAMDMACICM_:1; /*!< bit: 6 RAMDMACICM */
+ __I uint32_t HPB0_:1; /*!< bit: 7 HPB0 */
+ __I uint32_t HPB1_:1; /*!< bit: 8 HPB1 */
+ __I uint32_t HPB2_:1; /*!< bit: 9 HPB2 */
+ __I uint32_t HPB3_:1; /*!< bit: 10 HPB3 */
+ __I uint32_t PUKCC_:1; /*!< bit: 11 PUKCC */
+ __I uint32_t SDHC0_:1; /*!< bit: 12 SDHC0 */
+ __I uint32_t SDHC1_:1; /*!< bit: 13 SDHC1 */
+ __I uint32_t QSPI_:1; /*!< bit: 14 QSPI */
+ __I uint32_t BKUPRAM_:1; /*!< bit: 15 BKUPRAM */
+ __I uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_INTFLAGAHB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGAHB_OFFSET 0x10 /**< \brief (PAC_INTFLAGAHB offset) Bridge interrupt flag status */
+#define PAC_INTFLAGAHB_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGAHB reset_value) Bridge interrupt flag status */
+
+#define PAC_INTFLAGAHB_FLASH_Pos 0 /**< \brief (PAC_INTFLAGAHB) FLASH */
+#define PAC_INTFLAGAHB_FLASH (_U_(0x1) << PAC_INTFLAGAHB_FLASH_Pos)
+#define PAC_INTFLAGAHB_FLASH_ALT_Pos 1 /**< \brief (PAC_INTFLAGAHB) FLASH_ALT */
+#define PAC_INTFLAGAHB_FLASH_ALT (_U_(0x1) << PAC_INTFLAGAHB_FLASH_ALT_Pos)
+#define PAC_INTFLAGAHB_SEEPROM_Pos 2 /**< \brief (PAC_INTFLAGAHB) SEEPROM */
+#define PAC_INTFLAGAHB_SEEPROM (_U_(0x1) << PAC_INTFLAGAHB_SEEPROM_Pos)
+#define PAC_INTFLAGAHB_RAMCM4S_Pos 3 /**< \brief (PAC_INTFLAGAHB) RAMCM4S */
+#define PAC_INTFLAGAHB_RAMCM4S (_U_(0x1) << PAC_INTFLAGAHB_RAMCM4S_Pos)
+#define PAC_INTFLAGAHB_RAMPPPDSU_Pos 4 /**< \brief (PAC_INTFLAGAHB) RAMPPPDSU */
+#define PAC_INTFLAGAHB_RAMPPPDSU (_U_(0x1) << PAC_INTFLAGAHB_RAMPPPDSU_Pos)
+#define PAC_INTFLAGAHB_RAMDMAWR_Pos 5 /**< \brief (PAC_INTFLAGAHB) RAMDMAWR */
+#define PAC_INTFLAGAHB_RAMDMAWR (_U_(0x1) << PAC_INTFLAGAHB_RAMDMAWR_Pos)
+#define PAC_INTFLAGAHB_RAMDMACICM_Pos 6 /**< \brief (PAC_INTFLAGAHB) RAMDMACICM */
+#define PAC_INTFLAGAHB_RAMDMACICM (_U_(0x1) << PAC_INTFLAGAHB_RAMDMACICM_Pos)
+#define PAC_INTFLAGAHB_HPB0_Pos 7 /**< \brief (PAC_INTFLAGAHB) HPB0 */
+#define PAC_INTFLAGAHB_HPB0 (_U_(0x1) << PAC_INTFLAGAHB_HPB0_Pos)
+#define PAC_INTFLAGAHB_HPB1_Pos 8 /**< \brief (PAC_INTFLAGAHB) HPB1 */
+#define PAC_INTFLAGAHB_HPB1 (_U_(0x1) << PAC_INTFLAGAHB_HPB1_Pos)
+#define PAC_INTFLAGAHB_HPB2_Pos 9 /**< \brief (PAC_INTFLAGAHB) HPB2 */
+#define PAC_INTFLAGAHB_HPB2 (_U_(0x1) << PAC_INTFLAGAHB_HPB2_Pos)
+#define PAC_INTFLAGAHB_HPB3_Pos 10 /**< \brief (PAC_INTFLAGAHB) HPB3 */
+#define PAC_INTFLAGAHB_HPB3 (_U_(0x1) << PAC_INTFLAGAHB_HPB3_Pos)
+#define PAC_INTFLAGAHB_PUKCC_Pos 11 /**< \brief (PAC_INTFLAGAHB) PUKCC */
+#define PAC_INTFLAGAHB_PUKCC (_U_(0x1) << PAC_INTFLAGAHB_PUKCC_Pos)
+#define PAC_INTFLAGAHB_SDHC0_Pos 12 /**< \brief (PAC_INTFLAGAHB) SDHC0 */
+#define PAC_INTFLAGAHB_SDHC0 (_U_(0x1) << PAC_INTFLAGAHB_SDHC0_Pos)
+#define PAC_INTFLAGAHB_SDHC1_Pos 13 /**< \brief (PAC_INTFLAGAHB) SDHC1 */
+#define PAC_INTFLAGAHB_SDHC1 (_U_(0x1) << PAC_INTFLAGAHB_SDHC1_Pos)
+#define PAC_INTFLAGAHB_QSPI_Pos 14 /**< \brief (PAC_INTFLAGAHB) QSPI */
+#define PAC_INTFLAGAHB_QSPI (_U_(0x1) << PAC_INTFLAGAHB_QSPI_Pos)
+#define PAC_INTFLAGAHB_BKUPRAM_Pos 15 /**< \brief (PAC_INTFLAGAHB) BKUPRAM */
+#define PAC_INTFLAGAHB_BKUPRAM (_U_(0x1) << PAC_INTFLAGAHB_BKUPRAM_Pos)
+#define PAC_INTFLAGAHB_MASK _U_(0x0000FFFF) /**< \brief (PAC_INTFLAGAHB) MASK Register */
+
+/* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t PAC_:1; /*!< bit: 0 PAC */
+ __I uint32_t PM_:1; /*!< bit: 1 PM */
+ __I uint32_t MCLK_:1; /*!< bit: 2 MCLK */
+ __I uint32_t RSTC_:1; /*!< bit: 3 RSTC */
+ __I uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL */
+ __I uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL */
+ __I uint32_t SUPC_:1; /*!< bit: 6 SUPC */
+ __I uint32_t GCLK_:1; /*!< bit: 7 GCLK */
+ __I uint32_t WDT_:1; /*!< bit: 8 WDT */
+ __I uint32_t RTC_:1; /*!< bit: 9 RTC */
+ __I uint32_t EIC_:1; /*!< bit: 10 EIC */
+ __I uint32_t FREQM_:1; /*!< bit: 11 FREQM */
+ __I uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 */
+ __I uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 */
+ __I uint32_t TC0_:1; /*!< bit: 14 TC0 */
+ __I uint32_t TC1_:1; /*!< bit: 15 TC1 */
+ __I uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_INTFLAGA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGA_OFFSET 0x14 /**< \brief (PAC_INTFLAGA offset) Peripheral interrupt flag status - Bridge A */
+#define PAC_INTFLAGA_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGA reset_value) Peripheral interrupt flag status - Bridge A */
+
+#define PAC_INTFLAGA_PAC_Pos 0 /**< \brief (PAC_INTFLAGA) PAC */
+#define PAC_INTFLAGA_PAC (_U_(0x1) << PAC_INTFLAGA_PAC_Pos)
+#define PAC_INTFLAGA_PM_Pos 1 /**< \brief (PAC_INTFLAGA) PM */
+#define PAC_INTFLAGA_PM (_U_(0x1) << PAC_INTFLAGA_PM_Pos)
+#define PAC_INTFLAGA_MCLK_Pos 2 /**< \brief (PAC_INTFLAGA) MCLK */
+#define PAC_INTFLAGA_MCLK (_U_(0x1) << PAC_INTFLAGA_MCLK_Pos)
+#define PAC_INTFLAGA_RSTC_Pos 3 /**< \brief (PAC_INTFLAGA) RSTC */
+#define PAC_INTFLAGA_RSTC (_U_(0x1) << PAC_INTFLAGA_RSTC_Pos)
+#define PAC_INTFLAGA_OSCCTRL_Pos 4 /**< \brief (PAC_INTFLAGA) OSCCTRL */
+#define PAC_INTFLAGA_OSCCTRL (_U_(0x1) << PAC_INTFLAGA_OSCCTRL_Pos)
+#define PAC_INTFLAGA_OSC32KCTRL_Pos 5 /**< \brief (PAC_INTFLAGA) OSC32KCTRL */
+#define PAC_INTFLAGA_OSC32KCTRL (_U_(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos)
+#define PAC_INTFLAGA_SUPC_Pos 6 /**< \brief (PAC_INTFLAGA) SUPC */
+#define PAC_INTFLAGA_SUPC (_U_(0x1) << PAC_INTFLAGA_SUPC_Pos)
+#define PAC_INTFLAGA_GCLK_Pos 7 /**< \brief (PAC_INTFLAGA) GCLK */
+#define PAC_INTFLAGA_GCLK (_U_(0x1) << PAC_INTFLAGA_GCLK_Pos)
+#define PAC_INTFLAGA_WDT_Pos 8 /**< \brief (PAC_INTFLAGA) WDT */
+#define PAC_INTFLAGA_WDT (_U_(0x1) << PAC_INTFLAGA_WDT_Pos)
+#define PAC_INTFLAGA_RTC_Pos 9 /**< \brief (PAC_INTFLAGA) RTC */
+#define PAC_INTFLAGA_RTC (_U_(0x1) << PAC_INTFLAGA_RTC_Pos)
+#define PAC_INTFLAGA_EIC_Pos 10 /**< \brief (PAC_INTFLAGA) EIC */
+#define PAC_INTFLAGA_EIC (_U_(0x1) << PAC_INTFLAGA_EIC_Pos)
+#define PAC_INTFLAGA_FREQM_Pos 11 /**< \brief (PAC_INTFLAGA) FREQM */
+#define PAC_INTFLAGA_FREQM (_U_(0x1) << PAC_INTFLAGA_FREQM_Pos)
+#define PAC_INTFLAGA_SERCOM0_Pos 12 /**< \brief (PAC_INTFLAGA) SERCOM0 */
+#define PAC_INTFLAGA_SERCOM0 (_U_(0x1) << PAC_INTFLAGA_SERCOM0_Pos)
+#define PAC_INTFLAGA_SERCOM1_Pos 13 /**< \brief (PAC_INTFLAGA) SERCOM1 */
+#define PAC_INTFLAGA_SERCOM1 (_U_(0x1) << PAC_INTFLAGA_SERCOM1_Pos)
+#define PAC_INTFLAGA_TC0_Pos 14 /**< \brief (PAC_INTFLAGA) TC0 */
+#define PAC_INTFLAGA_TC0 (_U_(0x1) << PAC_INTFLAGA_TC0_Pos)
+#define PAC_INTFLAGA_TC1_Pos 15 /**< \brief (PAC_INTFLAGA) TC1 */
+#define PAC_INTFLAGA_TC1 (_U_(0x1) << PAC_INTFLAGA_TC1_Pos)
+#define PAC_INTFLAGA_MASK _U_(0x0000FFFF) /**< \brief (PAC_INTFLAGA) MASK Register */
+
+/* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t USB_:1; /*!< bit: 0 USB */
+ __I uint32_t DSU_:1; /*!< bit: 1 DSU */
+ __I uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL */
+ __I uint32_t CMCC_:1; /*!< bit: 3 CMCC */
+ __I uint32_t PORT_:1; /*!< bit: 4 PORT */
+ __I uint32_t DMAC_:1; /*!< bit: 5 DMAC */
+ __I uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX */
+ __I uint32_t EVSYS_:1; /*!< bit: 7 EVSYS */
+ __I uint32_t :1; /*!< bit: 8 Reserved */
+ __I uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 */
+ __I uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 */
+ __I uint32_t TCC0_:1; /*!< bit: 11 TCC0 */
+ __I uint32_t TCC1_:1; /*!< bit: 12 TCC1 */
+ __I uint32_t TC2_:1; /*!< bit: 13 TC2 */
+ __I uint32_t TC3_:1; /*!< bit: 14 TC3 */
+ __I uint32_t :1; /*!< bit: 15 Reserved */
+ __I uint32_t RAMECC_:1; /*!< bit: 16 RAMECC */
+ __I uint32_t :15; /*!< bit: 17..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_INTFLAGB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGB_OFFSET 0x18 /**< \brief (PAC_INTFLAGB offset) Peripheral interrupt flag status - Bridge B */
+#define PAC_INTFLAGB_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGB reset_value) Peripheral interrupt flag status - Bridge B */
+
+#define PAC_INTFLAGB_USB_Pos 0 /**< \brief (PAC_INTFLAGB) USB */
+#define PAC_INTFLAGB_USB (_U_(0x1) << PAC_INTFLAGB_USB_Pos)
+#define PAC_INTFLAGB_DSU_Pos 1 /**< \brief (PAC_INTFLAGB) DSU */
+#define PAC_INTFLAGB_DSU (_U_(0x1) << PAC_INTFLAGB_DSU_Pos)
+#define PAC_INTFLAGB_NVMCTRL_Pos 2 /**< \brief (PAC_INTFLAGB) NVMCTRL */
+#define PAC_INTFLAGB_NVMCTRL (_U_(0x1) << PAC_INTFLAGB_NVMCTRL_Pos)
+#define PAC_INTFLAGB_CMCC_Pos 3 /**< \brief (PAC_INTFLAGB) CMCC */
+#define PAC_INTFLAGB_CMCC (_U_(0x1) << PAC_INTFLAGB_CMCC_Pos)
+#define PAC_INTFLAGB_PORT_Pos 4 /**< \brief (PAC_INTFLAGB) PORT */
+#define PAC_INTFLAGB_PORT (_U_(0x1) << PAC_INTFLAGB_PORT_Pos)
+#define PAC_INTFLAGB_DMAC_Pos 5 /**< \brief (PAC_INTFLAGB) DMAC */
+#define PAC_INTFLAGB_DMAC (_U_(0x1) << PAC_INTFLAGB_DMAC_Pos)
+#define PAC_INTFLAGB_HMATRIX_Pos 6 /**< \brief (PAC_INTFLAGB) HMATRIX */
+#define PAC_INTFLAGB_HMATRIX (_U_(0x1) << PAC_INTFLAGB_HMATRIX_Pos)
+#define PAC_INTFLAGB_EVSYS_Pos 7 /**< \brief (PAC_INTFLAGB) EVSYS */
+#define PAC_INTFLAGB_EVSYS (_U_(0x1) << PAC_INTFLAGB_EVSYS_Pos)
+#define PAC_INTFLAGB_SERCOM2_Pos 9 /**< \brief (PAC_INTFLAGB) SERCOM2 */
+#define PAC_INTFLAGB_SERCOM2 (_U_(0x1) << PAC_INTFLAGB_SERCOM2_Pos)
+#define PAC_INTFLAGB_SERCOM3_Pos 10 /**< \brief (PAC_INTFLAGB) SERCOM3 */
+#define PAC_INTFLAGB_SERCOM3 (_U_(0x1) << PAC_INTFLAGB_SERCOM3_Pos)
+#define PAC_INTFLAGB_TCC0_Pos 11 /**< \brief (PAC_INTFLAGB) TCC0 */
+#define PAC_INTFLAGB_TCC0 (_U_(0x1) << PAC_INTFLAGB_TCC0_Pos)
+#define PAC_INTFLAGB_TCC1_Pos 12 /**< \brief (PAC_INTFLAGB) TCC1 */
+#define PAC_INTFLAGB_TCC1 (_U_(0x1) << PAC_INTFLAGB_TCC1_Pos)
+#define PAC_INTFLAGB_TC2_Pos 13 /**< \brief (PAC_INTFLAGB) TC2 */
+#define PAC_INTFLAGB_TC2 (_U_(0x1) << PAC_INTFLAGB_TC2_Pos)
+#define PAC_INTFLAGB_TC3_Pos 14 /**< \brief (PAC_INTFLAGB) TC3 */
+#define PAC_INTFLAGB_TC3 (_U_(0x1) << PAC_INTFLAGB_TC3_Pos)
+#define PAC_INTFLAGB_RAMECC_Pos 16 /**< \brief (PAC_INTFLAGB) RAMECC */
+#define PAC_INTFLAGB_RAMECC (_U_(0x1) << PAC_INTFLAGB_RAMECC_Pos)
+#define PAC_INTFLAGB_MASK _U_(0x00017EFF) /**< \brief (PAC_INTFLAGB) MASK Register */
+
+/* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t CAN0_:1; /*!< bit: 0 CAN0 */
+ __I uint32_t CAN1_:1; /*!< bit: 1 CAN1 */
+ __I uint32_t GMAC_:1; /*!< bit: 2 GMAC */
+ __I uint32_t TCC2_:1; /*!< bit: 3 TCC2 */
+ __I uint32_t TCC3_:1; /*!< bit: 4 TCC3 */
+ __I uint32_t TC4_:1; /*!< bit: 5 TC4 */
+ __I uint32_t TC5_:1; /*!< bit: 6 TC5 */
+ __I uint32_t PDEC_:1; /*!< bit: 7 PDEC */
+ __I uint32_t AC_:1; /*!< bit: 8 AC */
+ __I uint32_t AES_:1; /*!< bit: 9 AES */
+ __I uint32_t TRNG_:1; /*!< bit: 10 TRNG */
+ __I uint32_t ICM_:1; /*!< bit: 11 ICM */
+ __I uint32_t PUKCC_:1; /*!< bit: 12 PUKCC */
+ __I uint32_t QSPI_:1; /*!< bit: 13 QSPI */
+ __I uint32_t CCL_:1; /*!< bit: 14 CCL */
+ __I uint32_t :17; /*!< bit: 15..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_INTFLAGC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGC_OFFSET 0x1C /**< \brief (PAC_INTFLAGC offset) Peripheral interrupt flag status - Bridge C */
+#define PAC_INTFLAGC_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGC reset_value) Peripheral interrupt flag status - Bridge C */
+
+#define PAC_INTFLAGC_CAN0_Pos 0 /**< \brief (PAC_INTFLAGC) CAN0 */
+#define PAC_INTFLAGC_CAN0 (_U_(0x1) << PAC_INTFLAGC_CAN0_Pos)
+#define PAC_INTFLAGC_CAN1_Pos 1 /**< \brief (PAC_INTFLAGC) CAN1 */
+#define PAC_INTFLAGC_CAN1 (_U_(0x1) << PAC_INTFLAGC_CAN1_Pos)
+#define PAC_INTFLAGC_GMAC_Pos 2 /**< \brief (PAC_INTFLAGC) GMAC */
+#define PAC_INTFLAGC_GMAC (_U_(0x1) << PAC_INTFLAGC_GMAC_Pos)
+#define PAC_INTFLAGC_TCC2_Pos 3 /**< \brief (PAC_INTFLAGC) TCC2 */
+#define PAC_INTFLAGC_TCC2 (_U_(0x1) << PAC_INTFLAGC_TCC2_Pos)
+#define PAC_INTFLAGC_TCC3_Pos 4 /**< \brief (PAC_INTFLAGC) TCC3 */
+#define PAC_INTFLAGC_TCC3 (_U_(0x1) << PAC_INTFLAGC_TCC3_Pos)
+#define PAC_INTFLAGC_TC4_Pos 5 /**< \brief (PAC_INTFLAGC) TC4 */
+#define PAC_INTFLAGC_TC4 (_U_(0x1) << PAC_INTFLAGC_TC4_Pos)
+#define PAC_INTFLAGC_TC5_Pos 6 /**< \brief (PAC_INTFLAGC) TC5 */
+#define PAC_INTFLAGC_TC5 (_U_(0x1) << PAC_INTFLAGC_TC5_Pos)
+#define PAC_INTFLAGC_PDEC_Pos 7 /**< \brief (PAC_INTFLAGC) PDEC */
+#define PAC_INTFLAGC_PDEC (_U_(0x1) << PAC_INTFLAGC_PDEC_Pos)
+#define PAC_INTFLAGC_AC_Pos 8 /**< \brief (PAC_INTFLAGC) AC */
+#define PAC_INTFLAGC_AC (_U_(0x1) << PAC_INTFLAGC_AC_Pos)
+#define PAC_INTFLAGC_AES_Pos 9 /**< \brief (PAC_INTFLAGC) AES */
+#define PAC_INTFLAGC_AES (_U_(0x1) << PAC_INTFLAGC_AES_Pos)
+#define PAC_INTFLAGC_TRNG_Pos 10 /**< \brief (PAC_INTFLAGC) TRNG */
+#define PAC_INTFLAGC_TRNG (_U_(0x1) << PAC_INTFLAGC_TRNG_Pos)
+#define PAC_INTFLAGC_ICM_Pos 11 /**< \brief (PAC_INTFLAGC) ICM */
+#define PAC_INTFLAGC_ICM (_U_(0x1) << PAC_INTFLAGC_ICM_Pos)
+#define PAC_INTFLAGC_PUKCC_Pos 12 /**< \brief (PAC_INTFLAGC) PUKCC */
+#define PAC_INTFLAGC_PUKCC (_U_(0x1) << PAC_INTFLAGC_PUKCC_Pos)
+#define PAC_INTFLAGC_QSPI_Pos 13 /**< \brief (PAC_INTFLAGC) QSPI */
+#define PAC_INTFLAGC_QSPI (_U_(0x1) << PAC_INTFLAGC_QSPI_Pos)
+#define PAC_INTFLAGC_CCL_Pos 14 /**< \brief (PAC_INTFLAGC) CCL */
+#define PAC_INTFLAGC_CCL (_U_(0x1) << PAC_INTFLAGC_CCL_Pos)
+#define PAC_INTFLAGC_MASK _U_(0x00007FFF) /**< \brief (PAC_INTFLAGC) MASK Register */
+
+/* -------- PAC_INTFLAGD : (PAC Offset: 0x20) (R/W 32) Peripheral interrupt flag status - Bridge D -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 */
+ __I uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 */
+ __I uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 */
+ __I uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 */
+ __I uint32_t TCC4_:1; /*!< bit: 4 TCC4 */
+ __I uint32_t TC6_:1; /*!< bit: 5 TC6 */
+ __I uint32_t TC7_:1; /*!< bit: 6 TC7 */
+ __I uint32_t ADC0_:1; /*!< bit: 7 ADC0 */
+ __I uint32_t ADC1_:1; /*!< bit: 8 ADC1 */
+ __I uint32_t DAC_:1; /*!< bit: 9 DAC */
+ __I uint32_t I2S_:1; /*!< bit: 10 I2S */
+ __I uint32_t PCC_:1; /*!< bit: 11 PCC */
+ __I uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_INTFLAGD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGD_OFFSET 0x20 /**< \brief (PAC_INTFLAGD offset) Peripheral interrupt flag status - Bridge D */
+#define PAC_INTFLAGD_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGD reset_value) Peripheral interrupt flag status - Bridge D */
+
+#define PAC_INTFLAGD_SERCOM4_Pos 0 /**< \brief (PAC_INTFLAGD) SERCOM4 */
+#define PAC_INTFLAGD_SERCOM4 (_U_(0x1) << PAC_INTFLAGD_SERCOM4_Pos)
+#define PAC_INTFLAGD_SERCOM5_Pos 1 /**< \brief (PAC_INTFLAGD) SERCOM5 */
+#define PAC_INTFLAGD_SERCOM5 (_U_(0x1) << PAC_INTFLAGD_SERCOM5_Pos)
+#define PAC_INTFLAGD_SERCOM6_Pos 2 /**< \brief (PAC_INTFLAGD) SERCOM6 */
+#define PAC_INTFLAGD_SERCOM6 (_U_(0x1) << PAC_INTFLAGD_SERCOM6_Pos)
+#define PAC_INTFLAGD_SERCOM7_Pos 3 /**< \brief (PAC_INTFLAGD) SERCOM7 */
+#define PAC_INTFLAGD_SERCOM7 (_U_(0x1) << PAC_INTFLAGD_SERCOM7_Pos)
+#define PAC_INTFLAGD_TCC4_Pos 4 /**< \brief (PAC_INTFLAGD) TCC4 */
+#define PAC_INTFLAGD_TCC4 (_U_(0x1) << PAC_INTFLAGD_TCC4_Pos)
+#define PAC_INTFLAGD_TC6_Pos 5 /**< \brief (PAC_INTFLAGD) TC6 */
+#define PAC_INTFLAGD_TC6 (_U_(0x1) << PAC_INTFLAGD_TC6_Pos)
+#define PAC_INTFLAGD_TC7_Pos 6 /**< \brief (PAC_INTFLAGD) TC7 */
+#define PAC_INTFLAGD_TC7 (_U_(0x1) << PAC_INTFLAGD_TC7_Pos)
+#define PAC_INTFLAGD_ADC0_Pos 7 /**< \brief (PAC_INTFLAGD) ADC0 */
+#define PAC_INTFLAGD_ADC0 (_U_(0x1) << PAC_INTFLAGD_ADC0_Pos)
+#define PAC_INTFLAGD_ADC1_Pos 8 /**< \brief (PAC_INTFLAGD) ADC1 */
+#define PAC_INTFLAGD_ADC1 (_U_(0x1) << PAC_INTFLAGD_ADC1_Pos)
+#define PAC_INTFLAGD_DAC_Pos 9 /**< \brief (PAC_INTFLAGD) DAC */
+#define PAC_INTFLAGD_DAC (_U_(0x1) << PAC_INTFLAGD_DAC_Pos)
+#define PAC_INTFLAGD_I2S_Pos 10 /**< \brief (PAC_INTFLAGD) I2S */
+#define PAC_INTFLAGD_I2S (_U_(0x1) << PAC_INTFLAGD_I2S_Pos)
+#define PAC_INTFLAGD_PCC_Pos 11 /**< \brief (PAC_INTFLAGD) PCC */
+#define PAC_INTFLAGD_PCC (_U_(0x1) << PAC_INTFLAGD_PCC_Pos)
+#define PAC_INTFLAGD_MASK _U_(0x00000FFF) /**< \brief (PAC_INTFLAGD) MASK Register */
+
+/* -------- PAC_STATUSA : (PAC Offset: 0x34) (R/ 32) Peripheral write protection status - Bridge A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PAC_:1; /*!< bit: 0 PAC APB Protect Enable */
+ uint32_t PM_:1; /*!< bit: 1 PM APB Protect Enable */
+ uint32_t MCLK_:1; /*!< bit: 2 MCLK APB Protect Enable */
+ uint32_t RSTC_:1; /*!< bit: 3 RSTC APB Protect Enable */
+ uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL APB Protect Enable */
+ uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL APB Protect Enable */
+ uint32_t SUPC_:1; /*!< bit: 6 SUPC APB Protect Enable */
+ uint32_t GCLK_:1; /*!< bit: 7 GCLK APB Protect Enable */
+ uint32_t WDT_:1; /*!< bit: 8 WDT APB Protect Enable */
+ uint32_t RTC_:1; /*!< bit: 9 RTC APB Protect Enable */
+ uint32_t EIC_:1; /*!< bit: 10 EIC APB Protect Enable */
+ uint32_t FREQM_:1; /*!< bit: 11 FREQM APB Protect Enable */
+ uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 APB Protect Enable */
+ uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 APB Protect Enable */
+ uint32_t TC0_:1; /*!< bit: 14 TC0 APB Protect Enable */
+ uint32_t TC1_:1; /*!< bit: 15 TC1 APB Protect Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_STATUSA_OFFSET 0x34 /**< \brief (PAC_STATUSA offset) Peripheral write protection status - Bridge A */
+#define PAC_STATUSA_RESETVALUE _U_(0x00010000) /**< \brief (PAC_STATUSA reset_value) Peripheral write protection status - Bridge A */
+
+#define PAC_STATUSA_PAC_Pos 0 /**< \brief (PAC_STATUSA) PAC APB Protect Enable */
+#define PAC_STATUSA_PAC (_U_(0x1) << PAC_STATUSA_PAC_Pos)
+#define PAC_STATUSA_PM_Pos 1 /**< \brief (PAC_STATUSA) PM APB Protect Enable */
+#define PAC_STATUSA_PM (_U_(0x1) << PAC_STATUSA_PM_Pos)
+#define PAC_STATUSA_MCLK_Pos 2 /**< \brief (PAC_STATUSA) MCLK APB Protect Enable */
+#define PAC_STATUSA_MCLK (_U_(0x1) << PAC_STATUSA_MCLK_Pos)
+#define PAC_STATUSA_RSTC_Pos 3 /**< \brief (PAC_STATUSA) RSTC APB Protect Enable */
+#define PAC_STATUSA_RSTC (_U_(0x1) << PAC_STATUSA_RSTC_Pos)
+#define PAC_STATUSA_OSCCTRL_Pos 4 /**< \brief (PAC_STATUSA) OSCCTRL APB Protect Enable */
+#define PAC_STATUSA_OSCCTRL (_U_(0x1) << PAC_STATUSA_OSCCTRL_Pos)
+#define PAC_STATUSA_OSC32KCTRL_Pos 5 /**< \brief (PAC_STATUSA) OSC32KCTRL APB Protect Enable */
+#define PAC_STATUSA_OSC32KCTRL (_U_(0x1) << PAC_STATUSA_OSC32KCTRL_Pos)
+#define PAC_STATUSA_SUPC_Pos 6 /**< \brief (PAC_STATUSA) SUPC APB Protect Enable */
+#define PAC_STATUSA_SUPC (_U_(0x1) << PAC_STATUSA_SUPC_Pos)
+#define PAC_STATUSA_GCLK_Pos 7 /**< \brief (PAC_STATUSA) GCLK APB Protect Enable */
+#define PAC_STATUSA_GCLK (_U_(0x1) << PAC_STATUSA_GCLK_Pos)
+#define PAC_STATUSA_WDT_Pos 8 /**< \brief (PAC_STATUSA) WDT APB Protect Enable */
+#define PAC_STATUSA_WDT (_U_(0x1) << PAC_STATUSA_WDT_Pos)
+#define PAC_STATUSA_RTC_Pos 9 /**< \brief (PAC_STATUSA) RTC APB Protect Enable */
+#define PAC_STATUSA_RTC (_U_(0x1) << PAC_STATUSA_RTC_Pos)
+#define PAC_STATUSA_EIC_Pos 10 /**< \brief (PAC_STATUSA) EIC APB Protect Enable */
+#define PAC_STATUSA_EIC (_U_(0x1) << PAC_STATUSA_EIC_Pos)
+#define PAC_STATUSA_FREQM_Pos 11 /**< \brief (PAC_STATUSA) FREQM APB Protect Enable */
+#define PAC_STATUSA_FREQM (_U_(0x1) << PAC_STATUSA_FREQM_Pos)
+#define PAC_STATUSA_SERCOM0_Pos 12 /**< \brief (PAC_STATUSA) SERCOM0 APB Protect Enable */
+#define PAC_STATUSA_SERCOM0 (_U_(0x1) << PAC_STATUSA_SERCOM0_Pos)
+#define PAC_STATUSA_SERCOM1_Pos 13 /**< \brief (PAC_STATUSA) SERCOM1 APB Protect Enable */
+#define PAC_STATUSA_SERCOM1 (_U_(0x1) << PAC_STATUSA_SERCOM1_Pos)
+#define PAC_STATUSA_TC0_Pos 14 /**< \brief (PAC_STATUSA) TC0 APB Protect Enable */
+#define PAC_STATUSA_TC0 (_U_(0x1) << PAC_STATUSA_TC0_Pos)
+#define PAC_STATUSA_TC1_Pos 15 /**< \brief (PAC_STATUSA) TC1 APB Protect Enable */
+#define PAC_STATUSA_TC1 (_U_(0x1) << PAC_STATUSA_TC1_Pos)
+#define PAC_STATUSA_MASK _U_(0x0000FFFF) /**< \brief (PAC_STATUSA) MASK Register */
+
+/* -------- PAC_STATUSB : (PAC Offset: 0x38) (R/ 32) Peripheral write protection status - Bridge B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t USB_:1; /*!< bit: 0 USB APB Protect Enable */
+ uint32_t DSU_:1; /*!< bit: 1 DSU APB Protect Enable */
+ uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Protect Enable */
+ uint32_t CMCC_:1; /*!< bit: 3 CMCC APB Protect Enable */
+ uint32_t PORT_:1; /*!< bit: 4 PORT APB Protect Enable */
+ uint32_t DMAC_:1; /*!< bit: 5 DMAC APB Protect Enable */
+ uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Protect Enable */
+ uint32_t EVSYS_:1; /*!< bit: 7 EVSYS APB Protect Enable */
+ uint32_t :1; /*!< bit: 8 Reserved */
+ uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 APB Protect Enable */
+ uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 APB Protect Enable */
+ uint32_t TCC0_:1; /*!< bit: 11 TCC0 APB Protect Enable */
+ uint32_t TCC1_:1; /*!< bit: 12 TCC1 APB Protect Enable */
+ uint32_t TC2_:1; /*!< bit: 13 TC2 APB Protect Enable */
+ uint32_t TC3_:1; /*!< bit: 14 TC3 APB Protect Enable */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t RAMECC_:1; /*!< bit: 16 RAMECC APB Protect Enable */
+ uint32_t :15; /*!< bit: 17..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_STATUSB_OFFSET 0x38 /**< \brief (PAC_STATUSB offset) Peripheral write protection status - Bridge B */
+#define PAC_STATUSB_RESETVALUE _U_(0x00000002) /**< \brief (PAC_STATUSB reset_value) Peripheral write protection status - Bridge B */
+
+#define PAC_STATUSB_USB_Pos 0 /**< \brief (PAC_STATUSB) USB APB Protect Enable */
+#define PAC_STATUSB_USB (_U_(0x1) << PAC_STATUSB_USB_Pos)
+#define PAC_STATUSB_DSU_Pos 1 /**< \brief (PAC_STATUSB) DSU APB Protect Enable */
+#define PAC_STATUSB_DSU (_U_(0x1) << PAC_STATUSB_DSU_Pos)
+#define PAC_STATUSB_NVMCTRL_Pos 2 /**< \brief (PAC_STATUSB) NVMCTRL APB Protect Enable */
+#define PAC_STATUSB_NVMCTRL (_U_(0x1) << PAC_STATUSB_NVMCTRL_Pos)
+#define PAC_STATUSB_CMCC_Pos 3 /**< \brief (PAC_STATUSB) CMCC APB Protect Enable */
+#define PAC_STATUSB_CMCC (_U_(0x1) << PAC_STATUSB_CMCC_Pos)
+#define PAC_STATUSB_PORT_Pos 4 /**< \brief (PAC_STATUSB) PORT APB Protect Enable */
+#define PAC_STATUSB_PORT (_U_(0x1) << PAC_STATUSB_PORT_Pos)
+#define PAC_STATUSB_DMAC_Pos 5 /**< \brief (PAC_STATUSB) DMAC APB Protect Enable */
+#define PAC_STATUSB_DMAC (_U_(0x1) << PAC_STATUSB_DMAC_Pos)
+#define PAC_STATUSB_HMATRIX_Pos 6 /**< \brief (PAC_STATUSB) HMATRIX APB Protect Enable */
+#define PAC_STATUSB_HMATRIX (_U_(0x1) << PAC_STATUSB_HMATRIX_Pos)
+#define PAC_STATUSB_EVSYS_Pos 7 /**< \brief (PAC_STATUSB) EVSYS APB Protect Enable */
+#define PAC_STATUSB_EVSYS (_U_(0x1) << PAC_STATUSB_EVSYS_Pos)
+#define PAC_STATUSB_SERCOM2_Pos 9 /**< \brief (PAC_STATUSB) SERCOM2 APB Protect Enable */
+#define PAC_STATUSB_SERCOM2 (_U_(0x1) << PAC_STATUSB_SERCOM2_Pos)
+#define PAC_STATUSB_SERCOM3_Pos 10 /**< \brief (PAC_STATUSB) SERCOM3 APB Protect Enable */
+#define PAC_STATUSB_SERCOM3 (_U_(0x1) << PAC_STATUSB_SERCOM3_Pos)
+#define PAC_STATUSB_TCC0_Pos 11 /**< \brief (PAC_STATUSB) TCC0 APB Protect Enable */
+#define PAC_STATUSB_TCC0 (_U_(0x1) << PAC_STATUSB_TCC0_Pos)
+#define PAC_STATUSB_TCC1_Pos 12 /**< \brief (PAC_STATUSB) TCC1 APB Protect Enable */
+#define PAC_STATUSB_TCC1 (_U_(0x1) << PAC_STATUSB_TCC1_Pos)
+#define PAC_STATUSB_TC2_Pos 13 /**< \brief (PAC_STATUSB) TC2 APB Protect Enable */
+#define PAC_STATUSB_TC2 (_U_(0x1) << PAC_STATUSB_TC2_Pos)
+#define PAC_STATUSB_TC3_Pos 14 /**< \brief (PAC_STATUSB) TC3 APB Protect Enable */
+#define PAC_STATUSB_TC3 (_U_(0x1) << PAC_STATUSB_TC3_Pos)
+#define PAC_STATUSB_RAMECC_Pos 16 /**< \brief (PAC_STATUSB) RAMECC APB Protect Enable */
+#define PAC_STATUSB_RAMECC (_U_(0x1) << PAC_STATUSB_RAMECC_Pos)
+#define PAC_STATUSB_MASK _U_(0x00017EFF) /**< \brief (PAC_STATUSB) MASK Register */
+
+/* -------- PAC_STATUSC : (PAC Offset: 0x3C) (R/ 32) Peripheral write protection status - Bridge C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CAN0_:1; /*!< bit: 0 CAN0 APB Protect Enable */
+ uint32_t CAN1_:1; /*!< bit: 1 CAN1 APB Protect Enable */
+ uint32_t GMAC_:1; /*!< bit: 2 GMAC APB Protect Enable */
+ uint32_t TCC2_:1; /*!< bit: 3 TCC2 APB Protect Enable */
+ uint32_t TCC3_:1; /*!< bit: 4 TCC3 APB Protect Enable */
+ uint32_t TC4_:1; /*!< bit: 5 TC4 APB Protect Enable */
+ uint32_t TC5_:1; /*!< bit: 6 TC5 APB Protect Enable */
+ uint32_t PDEC_:1; /*!< bit: 7 PDEC APB Protect Enable */
+ uint32_t AC_:1; /*!< bit: 8 AC APB Protect Enable */
+ uint32_t AES_:1; /*!< bit: 9 AES APB Protect Enable */
+ uint32_t TRNG_:1; /*!< bit: 10 TRNG APB Protect Enable */
+ uint32_t ICM_:1; /*!< bit: 11 ICM APB Protect Enable */
+ uint32_t PUKCC_:1; /*!< bit: 12 PUKCC APB Protect Enable */
+ uint32_t QSPI_:1; /*!< bit: 13 QSPI APB Protect Enable */
+ uint32_t CCL_:1; /*!< bit: 14 CCL APB Protect Enable */
+ uint32_t :17; /*!< bit: 15..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_STATUSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_STATUSC_OFFSET 0x3C /**< \brief (PAC_STATUSC offset) Peripheral write protection status - Bridge C */
+#define PAC_STATUSC_RESETVALUE _U_(0x00000000) /**< \brief (PAC_STATUSC reset_value) Peripheral write protection status - Bridge C */
+
+#define PAC_STATUSC_CAN0_Pos 0 /**< \brief (PAC_STATUSC) CAN0 APB Protect Enable */
+#define PAC_STATUSC_CAN0 (_U_(0x1) << PAC_STATUSC_CAN0_Pos)
+#define PAC_STATUSC_CAN1_Pos 1 /**< \brief (PAC_STATUSC) CAN1 APB Protect Enable */
+#define PAC_STATUSC_CAN1 (_U_(0x1) << PAC_STATUSC_CAN1_Pos)
+#define PAC_STATUSC_GMAC_Pos 2 /**< \brief (PAC_STATUSC) GMAC APB Protect Enable */
+#define PAC_STATUSC_GMAC (_U_(0x1) << PAC_STATUSC_GMAC_Pos)
+#define PAC_STATUSC_TCC2_Pos 3 /**< \brief (PAC_STATUSC) TCC2 APB Protect Enable */
+#define PAC_STATUSC_TCC2 (_U_(0x1) << PAC_STATUSC_TCC2_Pos)
+#define PAC_STATUSC_TCC3_Pos 4 /**< \brief (PAC_STATUSC) TCC3 APB Protect Enable */
+#define PAC_STATUSC_TCC3 (_U_(0x1) << PAC_STATUSC_TCC3_Pos)
+#define PAC_STATUSC_TC4_Pos 5 /**< \brief (PAC_STATUSC) TC4 APB Protect Enable */
+#define PAC_STATUSC_TC4 (_U_(0x1) << PAC_STATUSC_TC4_Pos)
+#define PAC_STATUSC_TC5_Pos 6 /**< \brief (PAC_STATUSC) TC5 APB Protect Enable */
+#define PAC_STATUSC_TC5 (_U_(0x1) << PAC_STATUSC_TC5_Pos)
+#define PAC_STATUSC_PDEC_Pos 7 /**< \brief (PAC_STATUSC) PDEC APB Protect Enable */
+#define PAC_STATUSC_PDEC (_U_(0x1) << PAC_STATUSC_PDEC_Pos)
+#define PAC_STATUSC_AC_Pos 8 /**< \brief (PAC_STATUSC) AC APB Protect Enable */
+#define PAC_STATUSC_AC (_U_(0x1) << PAC_STATUSC_AC_Pos)
+#define PAC_STATUSC_AES_Pos 9 /**< \brief (PAC_STATUSC) AES APB Protect Enable */
+#define PAC_STATUSC_AES (_U_(0x1) << PAC_STATUSC_AES_Pos)
+#define PAC_STATUSC_TRNG_Pos 10 /**< \brief (PAC_STATUSC) TRNG APB Protect Enable */
+#define PAC_STATUSC_TRNG (_U_(0x1) << PAC_STATUSC_TRNG_Pos)
+#define PAC_STATUSC_ICM_Pos 11 /**< \brief (PAC_STATUSC) ICM APB Protect Enable */
+#define PAC_STATUSC_ICM (_U_(0x1) << PAC_STATUSC_ICM_Pos)
+#define PAC_STATUSC_PUKCC_Pos 12 /**< \brief (PAC_STATUSC) PUKCC APB Protect Enable */
+#define PAC_STATUSC_PUKCC (_U_(0x1) << PAC_STATUSC_PUKCC_Pos)
+#define PAC_STATUSC_QSPI_Pos 13 /**< \brief (PAC_STATUSC) QSPI APB Protect Enable */
+#define PAC_STATUSC_QSPI (_U_(0x1) << PAC_STATUSC_QSPI_Pos)
+#define PAC_STATUSC_CCL_Pos 14 /**< \brief (PAC_STATUSC) CCL APB Protect Enable */
+#define PAC_STATUSC_CCL (_U_(0x1) << PAC_STATUSC_CCL_Pos)
+#define PAC_STATUSC_MASK _U_(0x00007FFF) /**< \brief (PAC_STATUSC) MASK Register */
+
+/* -------- PAC_STATUSD : (PAC Offset: 0x40) (R/ 32) Peripheral write protection status - Bridge D -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 APB Protect Enable */
+ uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Protect Enable */
+ uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 APB Protect Enable */
+ uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 APB Protect Enable */
+ uint32_t TCC4_:1; /*!< bit: 4 TCC4 APB Protect Enable */
+ uint32_t TC6_:1; /*!< bit: 5 TC6 APB Protect Enable */
+ uint32_t TC7_:1; /*!< bit: 6 TC7 APB Protect Enable */
+ uint32_t ADC0_:1; /*!< bit: 7 ADC0 APB Protect Enable */
+ uint32_t ADC1_:1; /*!< bit: 8 ADC1 APB Protect Enable */
+ uint32_t DAC_:1; /*!< bit: 9 DAC APB Protect Enable */
+ uint32_t I2S_:1; /*!< bit: 10 I2S APB Protect Enable */
+ uint32_t PCC_:1; /*!< bit: 11 PCC APB Protect Enable */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_STATUSD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_STATUSD_OFFSET 0x40 /**< \brief (PAC_STATUSD offset) Peripheral write protection status - Bridge D */
+#define PAC_STATUSD_RESETVALUE _U_(0x00000000) /**< \brief (PAC_STATUSD reset_value) Peripheral write protection status - Bridge D */
+
+#define PAC_STATUSD_SERCOM4_Pos 0 /**< \brief (PAC_STATUSD) SERCOM4 APB Protect Enable */
+#define PAC_STATUSD_SERCOM4 (_U_(0x1) << PAC_STATUSD_SERCOM4_Pos)
+#define PAC_STATUSD_SERCOM5_Pos 1 /**< \brief (PAC_STATUSD) SERCOM5 APB Protect Enable */
+#define PAC_STATUSD_SERCOM5 (_U_(0x1) << PAC_STATUSD_SERCOM5_Pos)
+#define PAC_STATUSD_SERCOM6_Pos 2 /**< \brief (PAC_STATUSD) SERCOM6 APB Protect Enable */
+#define PAC_STATUSD_SERCOM6 (_U_(0x1) << PAC_STATUSD_SERCOM6_Pos)
+#define PAC_STATUSD_SERCOM7_Pos 3 /**< \brief (PAC_STATUSD) SERCOM7 APB Protect Enable */
+#define PAC_STATUSD_SERCOM7 (_U_(0x1) << PAC_STATUSD_SERCOM7_Pos)
+#define PAC_STATUSD_TCC4_Pos 4 /**< \brief (PAC_STATUSD) TCC4 APB Protect Enable */
+#define PAC_STATUSD_TCC4 (_U_(0x1) << PAC_STATUSD_TCC4_Pos)
+#define PAC_STATUSD_TC6_Pos 5 /**< \brief (PAC_STATUSD) TC6 APB Protect Enable */
+#define PAC_STATUSD_TC6 (_U_(0x1) << PAC_STATUSD_TC6_Pos)
+#define PAC_STATUSD_TC7_Pos 6 /**< \brief (PAC_STATUSD) TC7 APB Protect Enable */
+#define PAC_STATUSD_TC7 (_U_(0x1) << PAC_STATUSD_TC7_Pos)
+#define PAC_STATUSD_ADC0_Pos 7 /**< \brief (PAC_STATUSD) ADC0 APB Protect Enable */
+#define PAC_STATUSD_ADC0 (_U_(0x1) << PAC_STATUSD_ADC0_Pos)
+#define PAC_STATUSD_ADC1_Pos 8 /**< \brief (PAC_STATUSD) ADC1 APB Protect Enable */
+#define PAC_STATUSD_ADC1 (_U_(0x1) << PAC_STATUSD_ADC1_Pos)
+#define PAC_STATUSD_DAC_Pos 9 /**< \brief (PAC_STATUSD) DAC APB Protect Enable */
+#define PAC_STATUSD_DAC (_U_(0x1) << PAC_STATUSD_DAC_Pos)
+#define PAC_STATUSD_I2S_Pos 10 /**< \brief (PAC_STATUSD) I2S APB Protect Enable */
+#define PAC_STATUSD_I2S (_U_(0x1) << PAC_STATUSD_I2S_Pos)
+#define PAC_STATUSD_PCC_Pos 11 /**< \brief (PAC_STATUSD) PCC APB Protect Enable */
+#define PAC_STATUSD_PCC (_U_(0x1) << PAC_STATUSD_PCC_Pos)
+#define PAC_STATUSD_MASK _U_(0x00000FFF) /**< \brief (PAC_STATUSD) MASK Register */
+
+/** \brief PAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PAC_WRCTRL_Type WRCTRL; /**< \brief Offset: 0x00 (R/W 32) Write control */
+ __IO PAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event control */
+ RoReg8 Reserved1[0x3];
+ __IO PAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt enable clear */
+ __IO PAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt enable set */
+ RoReg8 Reserved2[0x6];
+ __IO PAC_INTFLAGAHB_Type INTFLAGAHB; /**< \brief Offset: 0x10 (R/W 32) Bridge interrupt flag status */
+ __IO PAC_INTFLAGA_Type INTFLAGA; /**< \brief Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */
+ __IO PAC_INTFLAGB_Type INTFLAGB; /**< \brief Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */
+ __IO PAC_INTFLAGC_Type INTFLAGC; /**< \brief Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */
+ __IO PAC_INTFLAGD_Type INTFLAGD; /**< \brief Offset: 0x20 (R/W 32) Peripheral interrupt flag status - Bridge D */
+ RoReg8 Reserved3[0x10];
+ __I PAC_STATUSA_Type STATUSA; /**< \brief Offset: 0x34 (R/ 32) Peripheral write protection status - Bridge A */
+ __I PAC_STATUSB_Type STATUSB; /**< \brief Offset: 0x38 (R/ 32) Peripheral write protection status - Bridge B */
+ __I PAC_STATUSC_Type STATUSC; /**< \brief Offset: 0x3C (R/ 32) Peripheral write protection status - Bridge C */
+ __I PAC_STATUSD_Type STATUSD; /**< \brief Offset: 0x40 (R/ 32) Peripheral write protection status - Bridge D */
+} Pac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_PAC_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/pcc.h b/sysmoOCTSIM/include/component/pcc.h
index 0c7e604..c79c3a1 100644
--- a/sysmoOCTSIM/include/component/pcc.h
+++ b/sysmoOCTSIM/include/component/pcc.h
@@ -1,251 +1,251 @@
-/**
- * \file
- *
- * \brief Component description for PCC
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_PCC_COMPONENT_
-#define _SAME54_PCC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR PCC */
-/* ========================================================================== */
-/** \addtogroup SAME54_PCC Parallel Capture Controller */
-/*@{*/
-
-#define PCC_U2017
-#define REV_PCC 0x110
-
-/* -------- PCC_MR : (PCC Offset: 0x00) (R/W 32) Mode Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t PCEN:1; /*!< bit: 0 Parallel Capture Enable */
- uint32_t :3; /*!< bit: 1.. 3 Reserved */
- uint32_t DSIZE:2; /*!< bit: 4.. 5 Data size */
- uint32_t :2; /*!< bit: 6.. 7 Reserved */
- uint32_t SCALE:1; /*!< bit: 8 Scale data */
- uint32_t ALWYS:1; /*!< bit: 9 Always Sampling */
- uint32_t HALFS:1; /*!< bit: 10 Half Sampling */
- uint32_t FRSTS:1; /*!< bit: 11 First sample */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t ISIZE:3; /*!< bit: 16..18 Input Data Size */
- uint32_t :11; /*!< bit: 19..29 Reserved */
- uint32_t CID:2; /*!< bit: 30..31 Clear If Disabled */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PCC_MR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PCC_MR_OFFSET 0x00 /**< \brief (PCC_MR offset) Mode Register */
-#define PCC_MR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_MR reset_value) Mode Register */
-
-#define PCC_MR_PCEN_Pos 0 /**< \brief (PCC_MR) Parallel Capture Enable */
-#define PCC_MR_PCEN (_U_(0x1) << PCC_MR_PCEN_Pos)
-#define PCC_MR_DSIZE_Pos 4 /**< \brief (PCC_MR) Data size */
-#define PCC_MR_DSIZE_Msk (_U_(0x3) << PCC_MR_DSIZE_Pos)
-#define PCC_MR_DSIZE(value) (PCC_MR_DSIZE_Msk & ((value) << PCC_MR_DSIZE_Pos))
-#define PCC_MR_SCALE_Pos 8 /**< \brief (PCC_MR) Scale data */
-#define PCC_MR_SCALE (_U_(0x1) << PCC_MR_SCALE_Pos)
-#define PCC_MR_ALWYS_Pos 9 /**< \brief (PCC_MR) Always Sampling */
-#define PCC_MR_ALWYS (_U_(0x1) << PCC_MR_ALWYS_Pos)
-#define PCC_MR_HALFS_Pos 10 /**< \brief (PCC_MR) Half Sampling */
-#define PCC_MR_HALFS (_U_(0x1) << PCC_MR_HALFS_Pos)
-#define PCC_MR_FRSTS_Pos 11 /**< \brief (PCC_MR) First sample */
-#define PCC_MR_FRSTS (_U_(0x1) << PCC_MR_FRSTS_Pos)
-#define PCC_MR_ISIZE_Pos 16 /**< \brief (PCC_MR) Input Data Size */
-#define PCC_MR_ISIZE_Msk (_U_(0x7) << PCC_MR_ISIZE_Pos)
-#define PCC_MR_ISIZE(value) (PCC_MR_ISIZE_Msk & ((value) << PCC_MR_ISIZE_Pos))
-#define PCC_MR_CID_Pos 30 /**< \brief (PCC_MR) Clear If Disabled */
-#define PCC_MR_CID_Msk (_U_(0x3) << PCC_MR_CID_Pos)
-#define PCC_MR_CID(value) (PCC_MR_CID_Msk & ((value) << PCC_MR_CID_Pos))
-#define PCC_MR_MASK _U_(0xC0070F31) /**< \brief (PCC_MR) MASK Register */
-
-/* -------- PCC_IER : (PCC Offset: 0x04) ( /W 32) Interrupt Enable Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Enable */
- uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Enable */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PCC_IER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PCC_IER_OFFSET 0x04 /**< \brief (PCC_IER offset) Interrupt Enable Register */
-#define PCC_IER_RESETVALUE _U_(0x00000000) /**< \brief (PCC_IER reset_value) Interrupt Enable Register */
-
-#define PCC_IER_DRDY_Pos 0 /**< \brief (PCC_IER) Data Ready Interrupt Enable */
-#define PCC_IER_DRDY (_U_(0x1) << PCC_IER_DRDY_Pos)
-#define PCC_IER_OVRE_Pos 1 /**< \brief (PCC_IER) Overrun Error Interrupt Enable */
-#define PCC_IER_OVRE (_U_(0x1) << PCC_IER_OVRE_Pos)
-#define PCC_IER_MASK _U_(0x00000003) /**< \brief (PCC_IER) MASK Register */
-
-/* -------- PCC_IDR : (PCC Offset: 0x08) ( /W 32) Interrupt Disable Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Disable */
- uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Disable */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PCC_IDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PCC_IDR_OFFSET 0x08 /**< \brief (PCC_IDR offset) Interrupt Disable Register */
-#define PCC_IDR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_IDR reset_value) Interrupt Disable Register */
-
-#define PCC_IDR_DRDY_Pos 0 /**< \brief (PCC_IDR) Data Ready Interrupt Disable */
-#define PCC_IDR_DRDY (_U_(0x1) << PCC_IDR_DRDY_Pos)
-#define PCC_IDR_OVRE_Pos 1 /**< \brief (PCC_IDR) Overrun Error Interrupt Disable */
-#define PCC_IDR_OVRE (_U_(0x1) << PCC_IDR_OVRE_Pos)
-#define PCC_IDR_MASK _U_(0x00000003) /**< \brief (PCC_IDR) MASK Register */
-
-/* -------- PCC_IMR : (PCC Offset: 0x0C) (R/ 32) Interrupt Mask Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Mask */
- uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Mask */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PCC_IMR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PCC_IMR_OFFSET 0x0C /**< \brief (PCC_IMR offset) Interrupt Mask Register */
-#define PCC_IMR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_IMR reset_value) Interrupt Mask Register */
-
-#define PCC_IMR_DRDY_Pos 0 /**< \brief (PCC_IMR) Data Ready Interrupt Mask */
-#define PCC_IMR_DRDY (_U_(0x1) << PCC_IMR_DRDY_Pos)
-#define PCC_IMR_OVRE_Pos 1 /**< \brief (PCC_IMR) Overrun Error Interrupt Mask */
-#define PCC_IMR_OVRE (_U_(0x1) << PCC_IMR_OVRE_Pos)
-#define PCC_IMR_MASK _U_(0x00000003) /**< \brief (PCC_IMR) MASK Register */
-
-/* -------- PCC_ISR : (PCC Offset: 0x10) (R/ 32) Interrupt Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Status */
- uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Status */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PCC_ISR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PCC_ISR_OFFSET 0x10 /**< \brief (PCC_ISR offset) Interrupt Status Register */
-#define PCC_ISR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_ISR reset_value) Interrupt Status Register */
-
-#define PCC_ISR_DRDY_Pos 0 /**< \brief (PCC_ISR) Data Ready Interrupt Status */
-#define PCC_ISR_DRDY (_U_(0x1) << PCC_ISR_DRDY_Pos)
-#define PCC_ISR_OVRE_Pos 1 /**< \brief (PCC_ISR) Overrun Error Interrupt Status */
-#define PCC_ISR_OVRE (_U_(0x1) << PCC_ISR_OVRE_Pos)
-#define PCC_ISR_MASK _U_(0x00000003) /**< \brief (PCC_ISR) MASK Register */
-
-/* -------- PCC_RHR : (PCC Offset: 0x14) (R/ 32) Reception Holding Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RDATA:32; /*!< bit: 0..31 Reception Data */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PCC_RHR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PCC_RHR_OFFSET 0x14 /**< \brief (PCC_RHR offset) Reception Holding Register */
-#define PCC_RHR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_RHR reset_value) Reception Holding Register */
-
-#define PCC_RHR_RDATA_Pos 0 /**< \brief (PCC_RHR) Reception Data */
-#define PCC_RHR_RDATA_Msk (_U_(0xFFFFFFFF) << PCC_RHR_RDATA_Pos)
-#define PCC_RHR_RDATA(value) (PCC_RHR_RDATA_Msk & ((value) << PCC_RHR_RDATA_Pos))
-#define PCC_RHR_MASK _U_(0xFFFFFFFF) /**< \brief (PCC_RHR) MASK Register */
-
-/* -------- PCC_WPMR : (PCC Offset: 0xE0) (R/W 32) Write Protection Mode Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t WPEN:1; /*!< bit: 0 Write Protection Enable */
- uint32_t :7; /*!< bit: 1.. 7 Reserved */
- uint32_t WPKEY:24; /*!< bit: 8..31 Write Protection Key */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PCC_WPMR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PCC_WPMR_OFFSET 0xE0 /**< \brief (PCC_WPMR offset) Write Protection Mode Register */
-#define PCC_WPMR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_WPMR reset_value) Write Protection Mode Register */
-
-#define PCC_WPMR_WPEN_Pos 0 /**< \brief (PCC_WPMR) Write Protection Enable */
-#define PCC_WPMR_WPEN (_U_(0x1) << PCC_WPMR_WPEN_Pos)
-#define PCC_WPMR_WPKEY_Pos 8 /**< \brief (PCC_WPMR) Write Protection Key */
-#define PCC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PCC_WPMR_WPKEY_Pos)
-#define PCC_WPMR_WPKEY(value) (PCC_WPMR_WPKEY_Msk & ((value) << PCC_WPMR_WPKEY_Pos))
-#define PCC_WPMR_MASK _U_(0xFFFFFF01) /**< \brief (PCC_WPMR) MASK Register */
-
-/* -------- PCC_WPSR : (PCC Offset: 0xE4) (R/ 32) Write Protection Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t WPVS:1; /*!< bit: 0 Write Protection Violation Source */
- uint32_t :7; /*!< bit: 1.. 7 Reserved */
- uint32_t WPVSRC:16; /*!< bit: 8..23 Write Protection Violation Status */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PCC_WPSR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PCC_WPSR_OFFSET 0xE4 /**< \brief (PCC_WPSR offset) Write Protection Status Register */
-#define PCC_WPSR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_WPSR reset_value) Write Protection Status Register */
-
-#define PCC_WPSR_WPVS_Pos 0 /**< \brief (PCC_WPSR) Write Protection Violation Source */
-#define PCC_WPSR_WPVS (_U_(0x1) << PCC_WPSR_WPVS_Pos)
-#define PCC_WPSR_WPVSRC_Pos 8 /**< \brief (PCC_WPSR) Write Protection Violation Status */
-#define PCC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PCC_WPSR_WPVSRC_Pos)
-#define PCC_WPSR_WPVSRC(value) (PCC_WPSR_WPVSRC_Msk & ((value) << PCC_WPSR_WPVSRC_Pos))
-#define PCC_WPSR_MASK _U_(0x00FFFF01) /**< \brief (PCC_WPSR) MASK Register */
-
-/** \brief PCC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO PCC_MR_Type MR; /**< \brief Offset: 0x00 (R/W 32) Mode Register */
- __O PCC_IER_Type IER; /**< \brief Offset: 0x04 ( /W 32) Interrupt Enable Register */
- __O PCC_IDR_Type IDR; /**< \brief Offset: 0x08 ( /W 32) Interrupt Disable Register */
- __I PCC_IMR_Type IMR; /**< \brief Offset: 0x0C (R/ 32) Interrupt Mask Register */
- __I PCC_ISR_Type ISR; /**< \brief Offset: 0x10 (R/ 32) Interrupt Status Register */
- __I PCC_RHR_Type RHR; /**< \brief Offset: 0x14 (R/ 32) Reception Holding Register */
- RoReg8 Reserved1[0xC8];
- __IO PCC_WPMR_Type WPMR; /**< \brief Offset: 0xE0 (R/W 32) Write Protection Mode Register */
- __I PCC_WPSR_Type WPSR; /**< \brief Offset: 0xE4 (R/ 32) Write Protection Status Register */
-} Pcc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_PCC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for PCC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_PCC_COMPONENT_
+#define _SAME54_PCC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PCC */
+/* ========================================================================== */
+/** \addtogroup SAME54_PCC Parallel Capture Controller */
+/*@{*/
+
+#define PCC_U2017
+#define REV_PCC 0x110
+
+/* -------- PCC_MR : (PCC Offset: 0x00) (R/W 32) Mode Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PCEN:1; /*!< bit: 0 Parallel Capture Enable */
+ uint32_t :3; /*!< bit: 1.. 3 Reserved */
+ uint32_t DSIZE:2; /*!< bit: 4.. 5 Data size */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t SCALE:1; /*!< bit: 8 Scale data */
+ uint32_t ALWYS:1; /*!< bit: 9 Always Sampling */
+ uint32_t HALFS:1; /*!< bit: 10 Half Sampling */
+ uint32_t FRSTS:1; /*!< bit: 11 First sample */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t ISIZE:3; /*!< bit: 16..18 Input Data Size */
+ uint32_t :11; /*!< bit: 19..29 Reserved */
+ uint32_t CID:2; /*!< bit: 30..31 Clear If Disabled */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PCC_MR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_MR_OFFSET 0x00 /**< \brief (PCC_MR offset) Mode Register */
+#define PCC_MR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_MR reset_value) Mode Register */
+
+#define PCC_MR_PCEN_Pos 0 /**< \brief (PCC_MR) Parallel Capture Enable */
+#define PCC_MR_PCEN (_U_(0x1) << PCC_MR_PCEN_Pos)
+#define PCC_MR_DSIZE_Pos 4 /**< \brief (PCC_MR) Data size */
+#define PCC_MR_DSIZE_Msk (_U_(0x3) << PCC_MR_DSIZE_Pos)
+#define PCC_MR_DSIZE(value) (PCC_MR_DSIZE_Msk & ((value) << PCC_MR_DSIZE_Pos))
+#define PCC_MR_SCALE_Pos 8 /**< \brief (PCC_MR) Scale data */
+#define PCC_MR_SCALE (_U_(0x1) << PCC_MR_SCALE_Pos)
+#define PCC_MR_ALWYS_Pos 9 /**< \brief (PCC_MR) Always Sampling */
+#define PCC_MR_ALWYS (_U_(0x1) << PCC_MR_ALWYS_Pos)
+#define PCC_MR_HALFS_Pos 10 /**< \brief (PCC_MR) Half Sampling */
+#define PCC_MR_HALFS (_U_(0x1) << PCC_MR_HALFS_Pos)
+#define PCC_MR_FRSTS_Pos 11 /**< \brief (PCC_MR) First sample */
+#define PCC_MR_FRSTS (_U_(0x1) << PCC_MR_FRSTS_Pos)
+#define PCC_MR_ISIZE_Pos 16 /**< \brief (PCC_MR) Input Data Size */
+#define PCC_MR_ISIZE_Msk (_U_(0x7) << PCC_MR_ISIZE_Pos)
+#define PCC_MR_ISIZE(value) (PCC_MR_ISIZE_Msk & ((value) << PCC_MR_ISIZE_Pos))
+#define PCC_MR_CID_Pos 30 /**< \brief (PCC_MR) Clear If Disabled */
+#define PCC_MR_CID_Msk (_U_(0x3) << PCC_MR_CID_Pos)
+#define PCC_MR_CID(value) (PCC_MR_CID_Msk & ((value) << PCC_MR_CID_Pos))
+#define PCC_MR_MASK _U_(0xC0070F31) /**< \brief (PCC_MR) MASK Register */
+
+/* -------- PCC_IER : (PCC Offset: 0x04) ( /W 32) Interrupt Enable Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Enable */
+ uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Enable */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PCC_IER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_IER_OFFSET 0x04 /**< \brief (PCC_IER offset) Interrupt Enable Register */
+#define PCC_IER_RESETVALUE _U_(0x00000000) /**< \brief (PCC_IER reset_value) Interrupt Enable Register */
+
+#define PCC_IER_DRDY_Pos 0 /**< \brief (PCC_IER) Data Ready Interrupt Enable */
+#define PCC_IER_DRDY (_U_(0x1) << PCC_IER_DRDY_Pos)
+#define PCC_IER_OVRE_Pos 1 /**< \brief (PCC_IER) Overrun Error Interrupt Enable */
+#define PCC_IER_OVRE (_U_(0x1) << PCC_IER_OVRE_Pos)
+#define PCC_IER_MASK _U_(0x00000003) /**< \brief (PCC_IER) MASK Register */
+
+/* -------- PCC_IDR : (PCC Offset: 0x08) ( /W 32) Interrupt Disable Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Disable */
+ uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Disable */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PCC_IDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_IDR_OFFSET 0x08 /**< \brief (PCC_IDR offset) Interrupt Disable Register */
+#define PCC_IDR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_IDR reset_value) Interrupt Disable Register */
+
+#define PCC_IDR_DRDY_Pos 0 /**< \brief (PCC_IDR) Data Ready Interrupt Disable */
+#define PCC_IDR_DRDY (_U_(0x1) << PCC_IDR_DRDY_Pos)
+#define PCC_IDR_OVRE_Pos 1 /**< \brief (PCC_IDR) Overrun Error Interrupt Disable */
+#define PCC_IDR_OVRE (_U_(0x1) << PCC_IDR_OVRE_Pos)
+#define PCC_IDR_MASK _U_(0x00000003) /**< \brief (PCC_IDR) MASK Register */
+
+/* -------- PCC_IMR : (PCC Offset: 0x0C) (R/ 32) Interrupt Mask Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Mask */
+ uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Mask */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PCC_IMR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_IMR_OFFSET 0x0C /**< \brief (PCC_IMR offset) Interrupt Mask Register */
+#define PCC_IMR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_IMR reset_value) Interrupt Mask Register */
+
+#define PCC_IMR_DRDY_Pos 0 /**< \brief (PCC_IMR) Data Ready Interrupt Mask */
+#define PCC_IMR_DRDY (_U_(0x1) << PCC_IMR_DRDY_Pos)
+#define PCC_IMR_OVRE_Pos 1 /**< \brief (PCC_IMR) Overrun Error Interrupt Mask */
+#define PCC_IMR_OVRE (_U_(0x1) << PCC_IMR_OVRE_Pos)
+#define PCC_IMR_MASK _U_(0x00000003) /**< \brief (PCC_IMR) MASK Register */
+
+/* -------- PCC_ISR : (PCC Offset: 0x10) (R/ 32) Interrupt Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Status */
+ uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Status */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PCC_ISR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_ISR_OFFSET 0x10 /**< \brief (PCC_ISR offset) Interrupt Status Register */
+#define PCC_ISR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_ISR reset_value) Interrupt Status Register */
+
+#define PCC_ISR_DRDY_Pos 0 /**< \brief (PCC_ISR) Data Ready Interrupt Status */
+#define PCC_ISR_DRDY (_U_(0x1) << PCC_ISR_DRDY_Pos)
+#define PCC_ISR_OVRE_Pos 1 /**< \brief (PCC_ISR) Overrun Error Interrupt Status */
+#define PCC_ISR_OVRE (_U_(0x1) << PCC_ISR_OVRE_Pos)
+#define PCC_ISR_MASK _U_(0x00000003) /**< \brief (PCC_ISR) MASK Register */
+
+/* -------- PCC_RHR : (PCC Offset: 0x14) (R/ 32) Reception Holding Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RDATA:32; /*!< bit: 0..31 Reception Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PCC_RHR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_RHR_OFFSET 0x14 /**< \brief (PCC_RHR offset) Reception Holding Register */
+#define PCC_RHR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_RHR reset_value) Reception Holding Register */
+
+#define PCC_RHR_RDATA_Pos 0 /**< \brief (PCC_RHR) Reception Data */
+#define PCC_RHR_RDATA_Msk (_U_(0xFFFFFFFF) << PCC_RHR_RDATA_Pos)
+#define PCC_RHR_RDATA(value) (PCC_RHR_RDATA_Msk & ((value) << PCC_RHR_RDATA_Pos))
+#define PCC_RHR_MASK _U_(0xFFFFFFFF) /**< \brief (PCC_RHR) MASK Register */
+
+/* -------- PCC_WPMR : (PCC Offset: 0xE0) (R/W 32) Write Protection Mode Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WPEN:1; /*!< bit: 0 Write Protection Enable */
+ uint32_t :7; /*!< bit: 1.. 7 Reserved */
+ uint32_t WPKEY:24; /*!< bit: 8..31 Write Protection Key */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PCC_WPMR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_WPMR_OFFSET 0xE0 /**< \brief (PCC_WPMR offset) Write Protection Mode Register */
+#define PCC_WPMR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_WPMR reset_value) Write Protection Mode Register */
+
+#define PCC_WPMR_WPEN_Pos 0 /**< \brief (PCC_WPMR) Write Protection Enable */
+#define PCC_WPMR_WPEN (_U_(0x1) << PCC_WPMR_WPEN_Pos)
+#define PCC_WPMR_WPKEY_Pos 8 /**< \brief (PCC_WPMR) Write Protection Key */
+#define PCC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PCC_WPMR_WPKEY_Pos)
+#define PCC_WPMR_WPKEY(value) (PCC_WPMR_WPKEY_Msk & ((value) << PCC_WPMR_WPKEY_Pos))
+#define PCC_WPMR_MASK _U_(0xFFFFFF01) /**< \brief (PCC_WPMR) MASK Register */
+
+/* -------- PCC_WPSR : (PCC Offset: 0xE4) (R/ 32) Write Protection Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WPVS:1; /*!< bit: 0 Write Protection Violation Source */
+ uint32_t :7; /*!< bit: 1.. 7 Reserved */
+ uint32_t WPVSRC:16; /*!< bit: 8..23 Write Protection Violation Status */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PCC_WPSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_WPSR_OFFSET 0xE4 /**< \brief (PCC_WPSR offset) Write Protection Status Register */
+#define PCC_WPSR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_WPSR reset_value) Write Protection Status Register */
+
+#define PCC_WPSR_WPVS_Pos 0 /**< \brief (PCC_WPSR) Write Protection Violation Source */
+#define PCC_WPSR_WPVS (_U_(0x1) << PCC_WPSR_WPVS_Pos)
+#define PCC_WPSR_WPVSRC_Pos 8 /**< \brief (PCC_WPSR) Write Protection Violation Status */
+#define PCC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PCC_WPSR_WPVSRC_Pos)
+#define PCC_WPSR_WPVSRC(value) (PCC_WPSR_WPVSRC_Msk & ((value) << PCC_WPSR_WPVSRC_Pos))
+#define PCC_WPSR_MASK _U_(0x00FFFF01) /**< \brief (PCC_WPSR) MASK Register */
+
+/** \brief PCC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PCC_MR_Type MR; /**< \brief Offset: 0x00 (R/W 32) Mode Register */
+ __O PCC_IER_Type IER; /**< \brief Offset: 0x04 ( /W 32) Interrupt Enable Register */
+ __O PCC_IDR_Type IDR; /**< \brief Offset: 0x08 ( /W 32) Interrupt Disable Register */
+ __I PCC_IMR_Type IMR; /**< \brief Offset: 0x0C (R/ 32) Interrupt Mask Register */
+ __I PCC_ISR_Type ISR; /**< \brief Offset: 0x10 (R/ 32) Interrupt Status Register */
+ __I PCC_RHR_Type RHR; /**< \brief Offset: 0x14 (R/ 32) Reception Holding Register */
+ RoReg8 Reserved1[0xC8];
+ __IO PCC_WPMR_Type WPMR; /**< \brief Offset: 0xE0 (R/W 32) Write Protection Mode Register */
+ __I PCC_WPSR_Type WPSR; /**< \brief Offset: 0xE4 (R/ 32) Write Protection Status Register */
+} Pcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_PCC_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/pdec.h b/sysmoOCTSIM/include/component/pdec.h
index f47d4f9..9d5651b 100644
--- a/sysmoOCTSIM/include/component/pdec.h
+++ b/sysmoOCTSIM/include/component/pdec.h
@@ -1,726 +1,726 @@
-/**
- * \file
- *
- * \brief Component description for PDEC
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_PDEC_COMPONENT_
-#define _SAME54_PDEC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR PDEC */
-/* ========================================================================== */
-/** \addtogroup SAME54_PDEC Quadrature Decodeur */
-/*@{*/
-
-#define PDEC_U2263
-#define REV_PDEC 0x100
-
-/* -------- PDEC_CTRLA : (PDEC Offset: 0x00) (R/W 32) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:2; /*!< bit: 2.. 3 Operation Mode */
- uint32_t :2; /*!< bit: 4.. 5 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t CONF:3; /*!< bit: 8..10 PDEC Configuration */
- uint32_t ALOCK:1; /*!< bit: 11 Auto Lock */
- uint32_t :2; /*!< bit: 12..13 Reserved */
- uint32_t SWAP:1; /*!< bit: 14 PDEC Phase A and B Swap */
- uint32_t PEREN:1; /*!< bit: 15 Period Enable */
- uint32_t PINEN0:1; /*!< bit: 16 PDEC Input From Pin 0 Enable */
- uint32_t PINEN1:1; /*!< bit: 17 PDEC Input From Pin 1 Enable */
- uint32_t PINEN2:1; /*!< bit: 18 PDEC Input From Pin 2 Enable */
- uint32_t :1; /*!< bit: 19 Reserved */
- uint32_t PINVEN0:1; /*!< bit: 20 IO Pin 0 Invert Enable */
- uint32_t PINVEN1:1; /*!< bit: 21 IO Pin 1 Invert Enable */
- uint32_t PINVEN2:1; /*!< bit: 22 IO Pin 2 Invert Enable */
- uint32_t :1; /*!< bit: 23 Reserved */
- uint32_t ANGULAR:3; /*!< bit: 24..26 Angular Counter Length */
- uint32_t :1; /*!< bit: 27 Reserved */
- uint32_t MAXCMP:4; /*!< bit: 28..31 Maximum Consecutive Missing Pulses */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t PINEN:3; /*!< bit: 16..18 PDEC Input From Pin x Enable */
- uint32_t :1; /*!< bit: 19 Reserved */
- uint32_t PINVEN:3; /*!< bit: 20..22 IO Pin x Invert Enable */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} PDEC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_CTRLA_OFFSET 0x00 /**< \brief (PDEC_CTRLA offset) Control A */
-#define PDEC_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_CTRLA reset_value) Control A */
-
-#define PDEC_CTRLA_SWRST_Pos 0 /**< \brief (PDEC_CTRLA) Software Reset */
-#define PDEC_CTRLA_SWRST (_U_(0x1) << PDEC_CTRLA_SWRST_Pos)
-#define PDEC_CTRLA_ENABLE_Pos 1 /**< \brief (PDEC_CTRLA) Enable */
-#define PDEC_CTRLA_ENABLE (_U_(0x1) << PDEC_CTRLA_ENABLE_Pos)
-#define PDEC_CTRLA_MODE_Pos 2 /**< \brief (PDEC_CTRLA) Operation Mode */
-#define PDEC_CTRLA_MODE_Msk (_U_(0x3) << PDEC_CTRLA_MODE_Pos)
-#define PDEC_CTRLA_MODE(value) (PDEC_CTRLA_MODE_Msk & ((value) << PDEC_CTRLA_MODE_Pos))
-#define PDEC_CTRLA_MODE_QDEC_Val _U_(0x0) /**< \brief (PDEC_CTRLA) QDEC operating mode */
-#define PDEC_CTRLA_MODE_HALL_Val _U_(0x1) /**< \brief (PDEC_CTRLA) HALL operating mode */
-#define PDEC_CTRLA_MODE_COUNTER_Val _U_(0x2) /**< \brief (PDEC_CTRLA) COUNTER operating mode */
-#define PDEC_CTRLA_MODE_QDEC (PDEC_CTRLA_MODE_QDEC_Val << PDEC_CTRLA_MODE_Pos)
-#define PDEC_CTRLA_MODE_HALL (PDEC_CTRLA_MODE_HALL_Val << PDEC_CTRLA_MODE_Pos)
-#define PDEC_CTRLA_MODE_COUNTER (PDEC_CTRLA_MODE_COUNTER_Val << PDEC_CTRLA_MODE_Pos)
-#define PDEC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (PDEC_CTRLA) Run in Standby */
-#define PDEC_CTRLA_RUNSTDBY (_U_(0x1) << PDEC_CTRLA_RUNSTDBY_Pos)
-#define PDEC_CTRLA_CONF_Pos 8 /**< \brief (PDEC_CTRLA) PDEC Configuration */
-#define PDEC_CTRLA_CONF_Msk (_U_(0x7) << PDEC_CTRLA_CONF_Pos)
-#define PDEC_CTRLA_CONF(value) (PDEC_CTRLA_CONF_Msk & ((value) << PDEC_CTRLA_CONF_Pos))
-#define PDEC_CTRLA_CONF_X4_Val _U_(0x0) /**< \brief (PDEC_CTRLA) Quadrature decoder direction */
-#define PDEC_CTRLA_CONF_X4S_Val _U_(0x1) /**< \brief (PDEC_CTRLA) Secure Quadrature decoder direction */
-#define PDEC_CTRLA_CONF_X2_Val _U_(0x2) /**< \brief (PDEC_CTRLA) Decoder direction */
-#define PDEC_CTRLA_CONF_X2S_Val _U_(0x3) /**< \brief (PDEC_CTRLA) Secure decoder direction */
-#define PDEC_CTRLA_CONF_AUTOC_Val _U_(0x4) /**< \brief (PDEC_CTRLA) Auto correction mode */
-#define PDEC_CTRLA_CONF_X4 (PDEC_CTRLA_CONF_X4_Val << PDEC_CTRLA_CONF_Pos)
-#define PDEC_CTRLA_CONF_X4S (PDEC_CTRLA_CONF_X4S_Val << PDEC_CTRLA_CONF_Pos)
-#define PDEC_CTRLA_CONF_X2 (PDEC_CTRLA_CONF_X2_Val << PDEC_CTRLA_CONF_Pos)
-#define PDEC_CTRLA_CONF_X2S (PDEC_CTRLA_CONF_X2S_Val << PDEC_CTRLA_CONF_Pos)
-#define PDEC_CTRLA_CONF_AUTOC (PDEC_CTRLA_CONF_AUTOC_Val << PDEC_CTRLA_CONF_Pos)
-#define PDEC_CTRLA_ALOCK_Pos 11 /**< \brief (PDEC_CTRLA) Auto Lock */
-#define PDEC_CTRLA_ALOCK (_U_(0x1) << PDEC_CTRLA_ALOCK_Pos)
-#define PDEC_CTRLA_SWAP_Pos 14 /**< \brief (PDEC_CTRLA) PDEC Phase A and B Swap */
-#define PDEC_CTRLA_SWAP (_U_(0x1) << PDEC_CTRLA_SWAP_Pos)
-#define PDEC_CTRLA_PEREN_Pos 15 /**< \brief (PDEC_CTRLA) Period Enable */
-#define PDEC_CTRLA_PEREN (_U_(0x1) << PDEC_CTRLA_PEREN_Pos)
-#define PDEC_CTRLA_PINEN0_Pos 16 /**< \brief (PDEC_CTRLA) PDEC Input From Pin 0 Enable */
-#define PDEC_CTRLA_PINEN0 (_U_(1) << PDEC_CTRLA_PINEN0_Pos)
-#define PDEC_CTRLA_PINEN1_Pos 17 /**< \brief (PDEC_CTRLA) PDEC Input From Pin 1 Enable */
-#define PDEC_CTRLA_PINEN1 (_U_(1) << PDEC_CTRLA_PINEN1_Pos)
-#define PDEC_CTRLA_PINEN2_Pos 18 /**< \brief (PDEC_CTRLA) PDEC Input From Pin 2 Enable */
-#define PDEC_CTRLA_PINEN2 (_U_(1) << PDEC_CTRLA_PINEN2_Pos)
-#define PDEC_CTRLA_PINEN_Pos 16 /**< \brief (PDEC_CTRLA) PDEC Input From Pin x Enable */
-#define PDEC_CTRLA_PINEN_Msk (_U_(0x7) << PDEC_CTRLA_PINEN_Pos)
-#define PDEC_CTRLA_PINEN(value) (PDEC_CTRLA_PINEN_Msk & ((value) << PDEC_CTRLA_PINEN_Pos))
-#define PDEC_CTRLA_PINVEN0_Pos 20 /**< \brief (PDEC_CTRLA) IO Pin 0 Invert Enable */
-#define PDEC_CTRLA_PINVEN0 (_U_(1) << PDEC_CTRLA_PINVEN0_Pos)
-#define PDEC_CTRLA_PINVEN1_Pos 21 /**< \brief (PDEC_CTRLA) IO Pin 1 Invert Enable */
-#define PDEC_CTRLA_PINVEN1 (_U_(1) << PDEC_CTRLA_PINVEN1_Pos)
-#define PDEC_CTRLA_PINVEN2_Pos 22 /**< \brief (PDEC_CTRLA) IO Pin 2 Invert Enable */
-#define PDEC_CTRLA_PINVEN2 (_U_(1) << PDEC_CTRLA_PINVEN2_Pos)
-#define PDEC_CTRLA_PINVEN_Pos 20 /**< \brief (PDEC_CTRLA) IO Pin x Invert Enable */
-#define PDEC_CTRLA_PINVEN_Msk (_U_(0x7) << PDEC_CTRLA_PINVEN_Pos)
-#define PDEC_CTRLA_PINVEN(value) (PDEC_CTRLA_PINVEN_Msk & ((value) << PDEC_CTRLA_PINVEN_Pos))
-#define PDEC_CTRLA_ANGULAR_Pos 24 /**< \brief (PDEC_CTRLA) Angular Counter Length */
-#define PDEC_CTRLA_ANGULAR_Msk (_U_(0x7) << PDEC_CTRLA_ANGULAR_Pos)
-#define PDEC_CTRLA_ANGULAR(value) (PDEC_CTRLA_ANGULAR_Msk & ((value) << PDEC_CTRLA_ANGULAR_Pos))
-#define PDEC_CTRLA_MAXCMP_Pos 28 /**< \brief (PDEC_CTRLA) Maximum Consecutive Missing Pulses */
-#define PDEC_CTRLA_MAXCMP_Msk (_U_(0xF) << PDEC_CTRLA_MAXCMP_Pos)
-#define PDEC_CTRLA_MAXCMP(value) (PDEC_CTRLA_MAXCMP_Msk & ((value) << PDEC_CTRLA_MAXCMP_Pos))
-#define PDEC_CTRLA_MASK _U_(0xF777CF4F) /**< \brief (PDEC_CTRLA) MASK Register */
-
-/* -------- PDEC_CTRLBCLR : (PDEC Offset: 0x04) (R/W 8) Control B Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t :1; /*!< bit: 0 Reserved */
- uint8_t LUPD:1; /*!< bit: 1 Lock Update */
- uint8_t :3; /*!< bit: 2.. 4 Reserved */
- uint8_t CMD:3; /*!< bit: 5.. 7 Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PDEC_CTRLBCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_CTRLBCLR_OFFSET 0x04 /**< \brief (PDEC_CTRLBCLR offset) Control B Clear */
-#define PDEC_CTRLBCLR_RESETVALUE _U_(0x00) /**< \brief (PDEC_CTRLBCLR reset_value) Control B Clear */
-
-#define PDEC_CTRLBCLR_LUPD_Pos 1 /**< \brief (PDEC_CTRLBCLR) Lock Update */
-#define PDEC_CTRLBCLR_LUPD (_U_(0x1) << PDEC_CTRLBCLR_LUPD_Pos)
-#define PDEC_CTRLBCLR_CMD_Pos 5 /**< \brief (PDEC_CTRLBCLR) Command */
-#define PDEC_CTRLBCLR_CMD_Msk (_U_(0x7) << PDEC_CTRLBCLR_CMD_Pos)
-#define PDEC_CTRLBCLR_CMD(value) (PDEC_CTRLBCLR_CMD_Msk & ((value) << PDEC_CTRLBCLR_CMD_Pos))
-#define PDEC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< \brief (PDEC_CTRLBCLR) No action */
-#define PDEC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (PDEC_CTRLBCLR) Force a counter restart or retrigger */
-#define PDEC_CTRLBCLR_CMD_UPDATE_Val _U_(0x2) /**< \brief (PDEC_CTRLBCLR) Force update of double buffered registers */
-#define PDEC_CTRLBCLR_CMD_READSYNC_Val _U_(0x3) /**< \brief (PDEC_CTRLBCLR) Force a read synchronization of COUNT */
-#define PDEC_CTRLBCLR_CMD_START_Val _U_(0x4) /**< \brief (PDEC_CTRLBCLR) Start QDEC/HALL */
-#define PDEC_CTRLBCLR_CMD_STOP_Val _U_(0x5) /**< \brief (PDEC_CTRLBCLR) Stop QDEC/HALL */
-#define PDEC_CTRLBCLR_CMD_NONE (PDEC_CTRLBCLR_CMD_NONE_Val << PDEC_CTRLBCLR_CMD_Pos)
-#define PDEC_CTRLBCLR_CMD_RETRIGGER (PDEC_CTRLBCLR_CMD_RETRIGGER_Val << PDEC_CTRLBCLR_CMD_Pos)
-#define PDEC_CTRLBCLR_CMD_UPDATE (PDEC_CTRLBCLR_CMD_UPDATE_Val << PDEC_CTRLBCLR_CMD_Pos)
-#define PDEC_CTRLBCLR_CMD_READSYNC (PDEC_CTRLBCLR_CMD_READSYNC_Val << PDEC_CTRLBCLR_CMD_Pos)
-#define PDEC_CTRLBCLR_CMD_START (PDEC_CTRLBCLR_CMD_START_Val << PDEC_CTRLBCLR_CMD_Pos)
-#define PDEC_CTRLBCLR_CMD_STOP (PDEC_CTRLBCLR_CMD_STOP_Val << PDEC_CTRLBCLR_CMD_Pos)
-#define PDEC_CTRLBCLR_MASK _U_(0xE2) /**< \brief (PDEC_CTRLBCLR) MASK Register */
-
-/* -------- PDEC_CTRLBSET : (PDEC Offset: 0x05) (R/W 8) Control B Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t :1; /*!< bit: 0 Reserved */
- uint8_t LUPD:1; /*!< bit: 1 Lock Update */
- uint8_t :3; /*!< bit: 2.. 4 Reserved */
- uint8_t CMD:3; /*!< bit: 5.. 7 Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PDEC_CTRLBSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_CTRLBSET_OFFSET 0x05 /**< \brief (PDEC_CTRLBSET offset) Control B Set */
-#define PDEC_CTRLBSET_RESETVALUE _U_(0x00) /**< \brief (PDEC_CTRLBSET reset_value) Control B Set */
-
-#define PDEC_CTRLBSET_LUPD_Pos 1 /**< \brief (PDEC_CTRLBSET) Lock Update */
-#define PDEC_CTRLBSET_LUPD (_U_(0x1) << PDEC_CTRLBSET_LUPD_Pos)
-#define PDEC_CTRLBSET_CMD_Pos 5 /**< \brief (PDEC_CTRLBSET) Command */
-#define PDEC_CTRLBSET_CMD_Msk (_U_(0x7) << PDEC_CTRLBSET_CMD_Pos)
-#define PDEC_CTRLBSET_CMD(value) (PDEC_CTRLBSET_CMD_Msk & ((value) << PDEC_CTRLBSET_CMD_Pos))
-#define PDEC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< \brief (PDEC_CTRLBSET) No action */
-#define PDEC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (PDEC_CTRLBSET) Force a counter restart or retrigger */
-#define PDEC_CTRLBSET_CMD_UPDATE_Val _U_(0x2) /**< \brief (PDEC_CTRLBSET) Force update of double buffered registers */
-#define PDEC_CTRLBSET_CMD_READSYNC_Val _U_(0x3) /**< \brief (PDEC_CTRLBSET) Force a read synchronization of COUNT */
-#define PDEC_CTRLBSET_CMD_START_Val _U_(0x4) /**< \brief (PDEC_CTRLBSET) Start QDEC/HALL */
-#define PDEC_CTRLBSET_CMD_STOP_Val _U_(0x5) /**< \brief (PDEC_CTRLBSET) Stop QDEC/HALL */
-#define PDEC_CTRLBSET_CMD_NONE (PDEC_CTRLBSET_CMD_NONE_Val << PDEC_CTRLBSET_CMD_Pos)
-#define PDEC_CTRLBSET_CMD_RETRIGGER (PDEC_CTRLBSET_CMD_RETRIGGER_Val << PDEC_CTRLBSET_CMD_Pos)
-#define PDEC_CTRLBSET_CMD_UPDATE (PDEC_CTRLBSET_CMD_UPDATE_Val << PDEC_CTRLBSET_CMD_Pos)
-#define PDEC_CTRLBSET_CMD_READSYNC (PDEC_CTRLBSET_CMD_READSYNC_Val << PDEC_CTRLBSET_CMD_Pos)
-#define PDEC_CTRLBSET_CMD_START (PDEC_CTRLBSET_CMD_START_Val << PDEC_CTRLBSET_CMD_Pos)
-#define PDEC_CTRLBSET_CMD_STOP (PDEC_CTRLBSET_CMD_STOP_Val << PDEC_CTRLBSET_CMD_Pos)
-#define PDEC_CTRLBSET_MASK _U_(0xE2) /**< \brief (PDEC_CTRLBSET) MASK Register */
-
-/* -------- PDEC_EVCTRL : (PDEC Offset: 0x06) (R/W 16) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t EVACT:2; /*!< bit: 0.. 1 Event Action */
- uint16_t EVINV:3; /*!< bit: 2.. 4 Inverted Event Input Enable */
- uint16_t EVEI:3; /*!< bit: 5.. 7 Event Input Enable */
- uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
- uint16_t ERREO:1; /*!< bit: 9 Error Output Event Enable */
- uint16_t DIREO:1; /*!< bit: 10 Direction Output Event Enable */
- uint16_t VLCEO:1; /*!< bit: 11 Velocity Output Event Enable */
- uint16_t MCEO0:1; /*!< bit: 12 Match Channel 0 Event Output Enable */
- uint16_t MCEO1:1; /*!< bit: 13 Match Channel 1 Event Output Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t :12; /*!< bit: 0..11 Reserved */
- uint16_t MCEO:2; /*!< bit: 12..13 Match Channel x Event Output Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} PDEC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_EVCTRL_OFFSET 0x06 /**< \brief (PDEC_EVCTRL offset) Event Control */
-#define PDEC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (PDEC_EVCTRL reset_value) Event Control */
-
-#define PDEC_EVCTRL_EVACT_Pos 0 /**< \brief (PDEC_EVCTRL) Event Action */
-#define PDEC_EVCTRL_EVACT_Msk (_U_(0x3) << PDEC_EVCTRL_EVACT_Pos)
-#define PDEC_EVCTRL_EVACT(value) (PDEC_EVCTRL_EVACT_Msk & ((value) << PDEC_EVCTRL_EVACT_Pos))
-#define PDEC_EVCTRL_EVACT_OFF_Val _U_(0x0) /**< \brief (PDEC_EVCTRL) Event action disabled */
-#define PDEC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1) /**< \brief (PDEC_EVCTRL) Start, restart or retrigger on event */
-#define PDEC_EVCTRL_EVACT_COUNT_Val _U_(0x2) /**< \brief (PDEC_EVCTRL) Count on event */
-#define PDEC_EVCTRL_EVACT_OFF (PDEC_EVCTRL_EVACT_OFF_Val << PDEC_EVCTRL_EVACT_Pos)
-#define PDEC_EVCTRL_EVACT_RETRIGGER (PDEC_EVCTRL_EVACT_RETRIGGER_Val << PDEC_EVCTRL_EVACT_Pos)
-#define PDEC_EVCTRL_EVACT_COUNT (PDEC_EVCTRL_EVACT_COUNT_Val << PDEC_EVCTRL_EVACT_Pos)
-#define PDEC_EVCTRL_EVINV_Pos 2 /**< \brief (PDEC_EVCTRL) Inverted Event Input Enable */
-#define PDEC_EVCTRL_EVINV_Msk (_U_(0x7) << PDEC_EVCTRL_EVINV_Pos)
-#define PDEC_EVCTRL_EVINV(value) (PDEC_EVCTRL_EVINV_Msk & ((value) << PDEC_EVCTRL_EVINV_Pos))
-#define PDEC_EVCTRL_EVEI_Pos 5 /**< \brief (PDEC_EVCTRL) Event Input Enable */
-#define PDEC_EVCTRL_EVEI_Msk (_U_(0x7) << PDEC_EVCTRL_EVEI_Pos)
-#define PDEC_EVCTRL_EVEI(value) (PDEC_EVCTRL_EVEI_Msk & ((value) << PDEC_EVCTRL_EVEI_Pos))
-#define PDEC_EVCTRL_OVFEO_Pos 8 /**< \brief (PDEC_EVCTRL) Overflow/Underflow Output Event Enable */
-#define PDEC_EVCTRL_OVFEO (_U_(0x1) << PDEC_EVCTRL_OVFEO_Pos)
-#define PDEC_EVCTRL_ERREO_Pos 9 /**< \brief (PDEC_EVCTRL) Error Output Event Enable */
-#define PDEC_EVCTRL_ERREO (_U_(0x1) << PDEC_EVCTRL_ERREO_Pos)
-#define PDEC_EVCTRL_DIREO_Pos 10 /**< \brief (PDEC_EVCTRL) Direction Output Event Enable */
-#define PDEC_EVCTRL_DIREO (_U_(0x1) << PDEC_EVCTRL_DIREO_Pos)
-#define PDEC_EVCTRL_VLCEO_Pos 11 /**< \brief (PDEC_EVCTRL) Velocity Output Event Enable */
-#define PDEC_EVCTRL_VLCEO (_U_(0x1) << PDEC_EVCTRL_VLCEO_Pos)
-#define PDEC_EVCTRL_MCEO0_Pos 12 /**< \brief (PDEC_EVCTRL) Match Channel 0 Event Output Enable */
-#define PDEC_EVCTRL_MCEO0 (_U_(1) << PDEC_EVCTRL_MCEO0_Pos)
-#define PDEC_EVCTRL_MCEO1_Pos 13 /**< \brief (PDEC_EVCTRL) Match Channel 1 Event Output Enable */
-#define PDEC_EVCTRL_MCEO1 (_U_(1) << PDEC_EVCTRL_MCEO1_Pos)
-#define PDEC_EVCTRL_MCEO_Pos 12 /**< \brief (PDEC_EVCTRL) Match Channel x Event Output Enable */
-#define PDEC_EVCTRL_MCEO_Msk (_U_(0x3) << PDEC_EVCTRL_MCEO_Pos)
-#define PDEC_EVCTRL_MCEO(value) (PDEC_EVCTRL_MCEO_Msk & ((value) << PDEC_EVCTRL_MCEO_Pos))
-#define PDEC_EVCTRL_MASK _U_(0x3FFF) /**< \brief (PDEC_EVCTRL) MASK Register */
-
-/* -------- PDEC_INTENCLR : (PDEC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow Interrupt Disable */
- uint8_t ERR:1; /*!< bit: 1 Error Interrupt Disable */
- uint8_t DIR:1; /*!< bit: 2 Direction Interrupt Disable */
- uint8_t VLC:1; /*!< bit: 3 Velocity Interrupt Disable */
- uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match Disable */
- uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match Disable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match Disable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} PDEC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_INTENCLR_OFFSET 0x08 /**< \brief (PDEC_INTENCLR offset) Interrupt Enable Clear */
-#define PDEC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PDEC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define PDEC_INTENCLR_OVF_Pos 0 /**< \brief (PDEC_INTENCLR) Overflow/Underflow Interrupt Disable */
-#define PDEC_INTENCLR_OVF (_U_(0x1) << PDEC_INTENCLR_OVF_Pos)
-#define PDEC_INTENCLR_ERR_Pos 1 /**< \brief (PDEC_INTENCLR) Error Interrupt Disable */
-#define PDEC_INTENCLR_ERR (_U_(0x1) << PDEC_INTENCLR_ERR_Pos)
-#define PDEC_INTENCLR_DIR_Pos 2 /**< \brief (PDEC_INTENCLR) Direction Interrupt Disable */
-#define PDEC_INTENCLR_DIR (_U_(0x1) << PDEC_INTENCLR_DIR_Pos)
-#define PDEC_INTENCLR_VLC_Pos 3 /**< \brief (PDEC_INTENCLR) Velocity Interrupt Disable */
-#define PDEC_INTENCLR_VLC (_U_(0x1) << PDEC_INTENCLR_VLC_Pos)
-#define PDEC_INTENCLR_MC0_Pos 4 /**< \brief (PDEC_INTENCLR) Channel 0 Compare Match Disable */
-#define PDEC_INTENCLR_MC0 (_U_(1) << PDEC_INTENCLR_MC0_Pos)
-#define PDEC_INTENCLR_MC1_Pos 5 /**< \brief (PDEC_INTENCLR) Channel 1 Compare Match Disable */
-#define PDEC_INTENCLR_MC1 (_U_(1) << PDEC_INTENCLR_MC1_Pos)
-#define PDEC_INTENCLR_MC_Pos 4 /**< \brief (PDEC_INTENCLR) Channel x Compare Match Disable */
-#define PDEC_INTENCLR_MC_Msk (_U_(0x3) << PDEC_INTENCLR_MC_Pos)
-#define PDEC_INTENCLR_MC(value) (PDEC_INTENCLR_MC_Msk & ((value) << PDEC_INTENCLR_MC_Pos))
-#define PDEC_INTENCLR_MASK _U_(0x3F) /**< \brief (PDEC_INTENCLR) MASK Register */
-
-/* -------- PDEC_INTENSET : (PDEC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow Interrupt Enable */
- uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
- uint8_t DIR:1; /*!< bit: 2 Direction Interrupt Enable */
- uint8_t VLC:1; /*!< bit: 3 Velocity Interrupt Enable */
- uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match Enable */
- uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} PDEC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_INTENSET_OFFSET 0x09 /**< \brief (PDEC_INTENSET offset) Interrupt Enable Set */
-#define PDEC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PDEC_INTENSET reset_value) Interrupt Enable Set */
-
-#define PDEC_INTENSET_OVF_Pos 0 /**< \brief (PDEC_INTENSET) Overflow/Underflow Interrupt Enable */
-#define PDEC_INTENSET_OVF (_U_(0x1) << PDEC_INTENSET_OVF_Pos)
-#define PDEC_INTENSET_ERR_Pos 1 /**< \brief (PDEC_INTENSET) Error Interrupt Enable */
-#define PDEC_INTENSET_ERR (_U_(0x1) << PDEC_INTENSET_ERR_Pos)
-#define PDEC_INTENSET_DIR_Pos 2 /**< \brief (PDEC_INTENSET) Direction Interrupt Enable */
-#define PDEC_INTENSET_DIR (_U_(0x1) << PDEC_INTENSET_DIR_Pos)
-#define PDEC_INTENSET_VLC_Pos 3 /**< \brief (PDEC_INTENSET) Velocity Interrupt Enable */
-#define PDEC_INTENSET_VLC (_U_(0x1) << PDEC_INTENSET_VLC_Pos)
-#define PDEC_INTENSET_MC0_Pos 4 /**< \brief (PDEC_INTENSET) Channel 0 Compare Match Enable */
-#define PDEC_INTENSET_MC0 (_U_(1) << PDEC_INTENSET_MC0_Pos)
-#define PDEC_INTENSET_MC1_Pos 5 /**< \brief (PDEC_INTENSET) Channel 1 Compare Match Enable */
-#define PDEC_INTENSET_MC1 (_U_(1) << PDEC_INTENSET_MC1_Pos)
-#define PDEC_INTENSET_MC_Pos 4 /**< \brief (PDEC_INTENSET) Channel x Compare Match Enable */
-#define PDEC_INTENSET_MC_Msk (_U_(0x3) << PDEC_INTENSET_MC_Pos)
-#define PDEC_INTENSET_MC(value) (PDEC_INTENSET_MC_Msk & ((value) << PDEC_INTENSET_MC_Pos))
-#define PDEC_INTENSET_MASK _U_(0x3F) /**< \brief (PDEC_INTENSET) MASK Register */
-
-/* -------- PDEC_INTFLAG : (PDEC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow */
- __I uint8_t ERR:1; /*!< bit: 1 Error */
- __I uint8_t DIR:1; /*!< bit: 2 Direction Change */
- __I uint8_t VLC:1; /*!< bit: 3 Velocity */
- __I uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match */
- __I uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match */
- __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t :4; /*!< bit: 0.. 3 Reserved */
- __I uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match */
- __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} PDEC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_INTFLAG_OFFSET 0x0A /**< \brief (PDEC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define PDEC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (PDEC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define PDEC_INTFLAG_OVF_Pos 0 /**< \brief (PDEC_INTFLAG) Overflow/Underflow */
-#define PDEC_INTFLAG_OVF (_U_(0x1) << PDEC_INTFLAG_OVF_Pos)
-#define PDEC_INTFLAG_ERR_Pos 1 /**< \brief (PDEC_INTFLAG) Error */
-#define PDEC_INTFLAG_ERR (_U_(0x1) << PDEC_INTFLAG_ERR_Pos)
-#define PDEC_INTFLAG_DIR_Pos 2 /**< \brief (PDEC_INTFLAG) Direction Change */
-#define PDEC_INTFLAG_DIR (_U_(0x1) << PDEC_INTFLAG_DIR_Pos)
-#define PDEC_INTFLAG_VLC_Pos 3 /**< \brief (PDEC_INTFLAG) Velocity */
-#define PDEC_INTFLAG_VLC (_U_(0x1) << PDEC_INTFLAG_VLC_Pos)
-#define PDEC_INTFLAG_MC0_Pos 4 /**< \brief (PDEC_INTFLAG) Channel 0 Compare Match */
-#define PDEC_INTFLAG_MC0 (_U_(1) << PDEC_INTFLAG_MC0_Pos)
-#define PDEC_INTFLAG_MC1_Pos 5 /**< \brief (PDEC_INTFLAG) Channel 1 Compare Match */
-#define PDEC_INTFLAG_MC1 (_U_(1) << PDEC_INTFLAG_MC1_Pos)
-#define PDEC_INTFLAG_MC_Pos 4 /**< \brief (PDEC_INTFLAG) Channel x Compare Match */
-#define PDEC_INTFLAG_MC_Msk (_U_(0x3) << PDEC_INTFLAG_MC_Pos)
-#define PDEC_INTFLAG_MC(value) (PDEC_INTFLAG_MC_Msk & ((value) << PDEC_INTFLAG_MC_Pos))
-#define PDEC_INTFLAG_MASK _U_(0x3F) /**< \brief (PDEC_INTFLAG) MASK Register */
-
-/* -------- PDEC_STATUS : (PDEC Offset: 0x0C) (R/W 16) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t QERR:1; /*!< bit: 0 Quadrature Error Flag */
- uint16_t IDXERR:1; /*!< bit: 1 Index Error Flag */
- uint16_t MPERR:1; /*!< bit: 2 Missing Pulse Error flag */
- uint16_t :1; /*!< bit: 3 Reserved */
- uint16_t WINERR:1; /*!< bit: 4 Window Error Flag */
- uint16_t HERR:1; /*!< bit: 5 Hall Error Flag */
- uint16_t STOP:1; /*!< bit: 6 Stop */
- uint16_t DIR:1; /*!< bit: 7 Direction Status Flag */
- uint16_t PRESCBUFV:1; /*!< bit: 8 Prescaler Buffer Valid */
- uint16_t FILTERBUFV:1; /*!< bit: 9 Filter Buffer Valid */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t CCBUFV0:1; /*!< bit: 12 Compare Channel 0 Buffer Valid */
- uint16_t CCBUFV1:1; /*!< bit: 13 Compare Channel 1 Buffer Valid */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t :12; /*!< bit: 0..11 Reserved */
- uint16_t CCBUFV:2; /*!< bit: 12..13 Compare Channel x Buffer Valid */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} PDEC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_STATUS_OFFSET 0x0C /**< \brief (PDEC_STATUS offset) Status */
-#define PDEC_STATUS_RESETVALUE _U_(0x0040) /**< \brief (PDEC_STATUS reset_value) Status */
-
-#define PDEC_STATUS_QERR_Pos 0 /**< \brief (PDEC_STATUS) Quadrature Error Flag */
-#define PDEC_STATUS_QERR (_U_(0x1) << PDEC_STATUS_QERR_Pos)
-#define PDEC_STATUS_IDXERR_Pos 1 /**< \brief (PDEC_STATUS) Index Error Flag */
-#define PDEC_STATUS_IDXERR (_U_(0x1) << PDEC_STATUS_IDXERR_Pos)
-#define PDEC_STATUS_MPERR_Pos 2 /**< \brief (PDEC_STATUS) Missing Pulse Error flag */
-#define PDEC_STATUS_MPERR (_U_(0x1) << PDEC_STATUS_MPERR_Pos)
-#define PDEC_STATUS_WINERR_Pos 4 /**< \brief (PDEC_STATUS) Window Error Flag */
-#define PDEC_STATUS_WINERR (_U_(0x1) << PDEC_STATUS_WINERR_Pos)
-#define PDEC_STATUS_HERR_Pos 5 /**< \brief (PDEC_STATUS) Hall Error Flag */
-#define PDEC_STATUS_HERR (_U_(0x1) << PDEC_STATUS_HERR_Pos)
-#define PDEC_STATUS_STOP_Pos 6 /**< \brief (PDEC_STATUS) Stop */
-#define PDEC_STATUS_STOP (_U_(0x1) << PDEC_STATUS_STOP_Pos)
-#define PDEC_STATUS_DIR_Pos 7 /**< \brief (PDEC_STATUS) Direction Status Flag */
-#define PDEC_STATUS_DIR (_U_(0x1) << PDEC_STATUS_DIR_Pos)
-#define PDEC_STATUS_PRESCBUFV_Pos 8 /**< \brief (PDEC_STATUS) Prescaler Buffer Valid */
-#define PDEC_STATUS_PRESCBUFV (_U_(0x1) << PDEC_STATUS_PRESCBUFV_Pos)
-#define PDEC_STATUS_FILTERBUFV_Pos 9 /**< \brief (PDEC_STATUS) Filter Buffer Valid */
-#define PDEC_STATUS_FILTERBUFV (_U_(0x1) << PDEC_STATUS_FILTERBUFV_Pos)
-#define PDEC_STATUS_CCBUFV0_Pos 12 /**< \brief (PDEC_STATUS) Compare Channel 0 Buffer Valid */
-#define PDEC_STATUS_CCBUFV0 (_U_(1) << PDEC_STATUS_CCBUFV0_Pos)
-#define PDEC_STATUS_CCBUFV1_Pos 13 /**< \brief (PDEC_STATUS) Compare Channel 1 Buffer Valid */
-#define PDEC_STATUS_CCBUFV1 (_U_(1) << PDEC_STATUS_CCBUFV1_Pos)
-#define PDEC_STATUS_CCBUFV_Pos 12 /**< \brief (PDEC_STATUS) Compare Channel x Buffer Valid */
-#define PDEC_STATUS_CCBUFV_Msk (_U_(0x3) << PDEC_STATUS_CCBUFV_Pos)
-#define PDEC_STATUS_CCBUFV(value) (PDEC_STATUS_CCBUFV_Msk & ((value) << PDEC_STATUS_CCBUFV_Pos))
-#define PDEC_STATUS_MASK _U_(0x33F7) /**< \brief (PDEC_STATUS) MASK Register */
-
-/* -------- PDEC_DBGCTRL : (PDEC Offset: 0x0F) (R/W 8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PDEC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_DBGCTRL_OFFSET 0x0F /**< \brief (PDEC_DBGCTRL offset) Debug Control */
-#define PDEC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (PDEC_DBGCTRL reset_value) Debug Control */
-
-#define PDEC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (PDEC_DBGCTRL) Debug Run Mode */
-#define PDEC_DBGCTRL_DBGRUN (_U_(0x1) << PDEC_DBGCTRL_DBGRUN_Pos)
-#define PDEC_DBGCTRL_MASK _U_(0x01) /**< \brief (PDEC_DBGCTRL) MASK Register */
-
-/* -------- PDEC_SYNCBUSY : (PDEC Offset: 0x10) (R/ 32) Synchronization Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
- uint32_t CTRLB:1; /*!< bit: 2 Control B Synchronization Busy */
- uint32_t STATUS:1; /*!< bit: 3 Status Synchronization Busy */
- uint32_t PRESC:1; /*!< bit: 4 Prescaler Synchronization Busy */
- uint32_t FILTER:1; /*!< bit: 5 Filter Synchronization Busy */
- uint32_t COUNT:1; /*!< bit: 6 Count Synchronization Busy */
- uint32_t CC0:1; /*!< bit: 7 Compare Channel 0 Synchronization Busy */
- uint32_t CC1:1; /*!< bit: 8 Compare Channel 1 Synchronization Busy */
- uint32_t :23; /*!< bit: 9..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :7; /*!< bit: 0.. 6 Reserved */
- uint32_t CC:2; /*!< bit: 7.. 8 Compare Channel x Synchronization Busy */
- uint32_t :23; /*!< bit: 9..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} PDEC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_SYNCBUSY_OFFSET 0x10 /**< \brief (PDEC_SYNCBUSY offset) Synchronization Status */
-#define PDEC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_SYNCBUSY reset_value) Synchronization Status */
-
-#define PDEC_SYNCBUSY_SWRST_Pos 0 /**< \brief (PDEC_SYNCBUSY) Software Reset Synchronization Busy */
-#define PDEC_SYNCBUSY_SWRST (_U_(0x1) << PDEC_SYNCBUSY_SWRST_Pos)
-#define PDEC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (PDEC_SYNCBUSY) Enable Synchronization Busy */
-#define PDEC_SYNCBUSY_ENABLE (_U_(0x1) << PDEC_SYNCBUSY_ENABLE_Pos)
-#define PDEC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (PDEC_SYNCBUSY) Control B Synchronization Busy */
-#define PDEC_SYNCBUSY_CTRLB (_U_(0x1) << PDEC_SYNCBUSY_CTRLB_Pos)
-#define PDEC_SYNCBUSY_STATUS_Pos 3 /**< \brief (PDEC_SYNCBUSY) Status Synchronization Busy */
-#define PDEC_SYNCBUSY_STATUS (_U_(0x1) << PDEC_SYNCBUSY_STATUS_Pos)
-#define PDEC_SYNCBUSY_PRESC_Pos 4 /**< \brief (PDEC_SYNCBUSY) Prescaler Synchronization Busy */
-#define PDEC_SYNCBUSY_PRESC (_U_(0x1) << PDEC_SYNCBUSY_PRESC_Pos)
-#define PDEC_SYNCBUSY_FILTER_Pos 5 /**< \brief (PDEC_SYNCBUSY) Filter Synchronization Busy */
-#define PDEC_SYNCBUSY_FILTER (_U_(0x1) << PDEC_SYNCBUSY_FILTER_Pos)
-#define PDEC_SYNCBUSY_COUNT_Pos 6 /**< \brief (PDEC_SYNCBUSY) Count Synchronization Busy */
-#define PDEC_SYNCBUSY_COUNT (_U_(0x1) << PDEC_SYNCBUSY_COUNT_Pos)
-#define PDEC_SYNCBUSY_CC0_Pos 7 /**< \brief (PDEC_SYNCBUSY) Compare Channel 0 Synchronization Busy */
-#define PDEC_SYNCBUSY_CC0 (_U_(1) << PDEC_SYNCBUSY_CC0_Pos)
-#define PDEC_SYNCBUSY_CC1_Pos 8 /**< \brief (PDEC_SYNCBUSY) Compare Channel 1 Synchronization Busy */
-#define PDEC_SYNCBUSY_CC1 (_U_(1) << PDEC_SYNCBUSY_CC1_Pos)
-#define PDEC_SYNCBUSY_CC_Pos 7 /**< \brief (PDEC_SYNCBUSY) Compare Channel x Synchronization Busy */
-#define PDEC_SYNCBUSY_CC_Msk (_U_(0x3) << PDEC_SYNCBUSY_CC_Pos)
-#define PDEC_SYNCBUSY_CC(value) (PDEC_SYNCBUSY_CC_Msk & ((value) << PDEC_SYNCBUSY_CC_Pos))
-#define PDEC_SYNCBUSY_MASK _U_(0x000001FF) /**< \brief (PDEC_SYNCBUSY) MASK Register */
-
-/* -------- PDEC_PRESC : (PDEC Offset: 0x14) (R/W 8) Prescaler Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t PRESC:4; /*!< bit: 0.. 3 Prescaler Value */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PDEC_PRESC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_PRESC_OFFSET 0x14 /**< \brief (PDEC_PRESC offset) Prescaler Value */
-#define PDEC_PRESC_RESETVALUE _U_(0x00) /**< \brief (PDEC_PRESC reset_value) Prescaler Value */
-
-#define PDEC_PRESC_PRESC_Pos 0 /**< \brief (PDEC_PRESC) Prescaler Value */
-#define PDEC_PRESC_PRESC_Msk (_U_(0xF) << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC(value) (PDEC_PRESC_PRESC_Msk & ((value) << PDEC_PRESC_PRESC_Pos))
-#define PDEC_PRESC_PRESC_DIV1_Val _U_(0x0) /**< \brief (PDEC_PRESC) No division */
-#define PDEC_PRESC_PRESC_DIV2_Val _U_(0x1) /**< \brief (PDEC_PRESC) Divide by 2 */
-#define PDEC_PRESC_PRESC_DIV4_Val _U_(0x2) /**< \brief (PDEC_PRESC) Divide by 4 */
-#define PDEC_PRESC_PRESC_DIV8_Val _U_(0x3) /**< \brief (PDEC_PRESC) Divide by 8 */
-#define PDEC_PRESC_PRESC_DIV16_Val _U_(0x4) /**< \brief (PDEC_PRESC) Divide by 16 */
-#define PDEC_PRESC_PRESC_DIV32_Val _U_(0x5) /**< \brief (PDEC_PRESC) Divide by 32 */
-#define PDEC_PRESC_PRESC_DIV64_Val _U_(0x6) /**< \brief (PDEC_PRESC) Divide by 64 */
-#define PDEC_PRESC_PRESC_DIV128_Val _U_(0x7) /**< \brief (PDEC_PRESC) Divide by 128 */
-#define PDEC_PRESC_PRESC_DIV256_Val _U_(0x8) /**< \brief (PDEC_PRESC) Divide by 256 */
-#define PDEC_PRESC_PRESC_DIV512_Val _U_(0x9) /**< \brief (PDEC_PRESC) Divide by 512 */
-#define PDEC_PRESC_PRESC_DIV1024_Val _U_(0xA) /**< \brief (PDEC_PRESC) Divide by 1024 */
-#define PDEC_PRESC_PRESC_DIV1 (PDEC_PRESC_PRESC_DIV1_Val << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV2 (PDEC_PRESC_PRESC_DIV2_Val << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV4 (PDEC_PRESC_PRESC_DIV4_Val << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV8 (PDEC_PRESC_PRESC_DIV8_Val << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV16 (PDEC_PRESC_PRESC_DIV16_Val << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV32 (PDEC_PRESC_PRESC_DIV32_Val << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV64 (PDEC_PRESC_PRESC_DIV64_Val << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV128 (PDEC_PRESC_PRESC_DIV128_Val << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV256 (PDEC_PRESC_PRESC_DIV256_Val << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV512 (PDEC_PRESC_PRESC_DIV512_Val << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV1024 (PDEC_PRESC_PRESC_DIV1024_Val << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_MASK _U_(0x0F) /**< \brief (PDEC_PRESC) MASK Register */
-
-/* -------- PDEC_FILTER : (PDEC Offset: 0x15) (R/W 8) Filter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t FILTER:8; /*!< bit: 0.. 7 Filter Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PDEC_FILTER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_FILTER_OFFSET 0x15 /**< \brief (PDEC_FILTER offset) Filter Value */
-#define PDEC_FILTER_RESETVALUE _U_(0x00) /**< \brief (PDEC_FILTER reset_value) Filter Value */
-
-#define PDEC_FILTER_FILTER_Pos 0 /**< \brief (PDEC_FILTER) Filter Value */
-#define PDEC_FILTER_FILTER_Msk (_U_(0xFF) << PDEC_FILTER_FILTER_Pos)
-#define PDEC_FILTER_FILTER(value) (PDEC_FILTER_FILTER_Msk & ((value) << PDEC_FILTER_FILTER_Pos))
-#define PDEC_FILTER_MASK _U_(0xFF) /**< \brief (PDEC_FILTER) MASK Register */
-
-/* -------- PDEC_PRESCBUF : (PDEC Offset: 0x18) (R/W 8) Prescaler Buffer Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t PRESCBUF:4; /*!< bit: 0.. 3 Prescaler Buffer Value */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PDEC_PRESCBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_PRESCBUF_OFFSET 0x18 /**< \brief (PDEC_PRESCBUF offset) Prescaler Buffer Value */
-#define PDEC_PRESCBUF_RESETVALUE _U_(0x00) /**< \brief (PDEC_PRESCBUF reset_value) Prescaler Buffer Value */
-
-#define PDEC_PRESCBUF_PRESCBUF_Pos 0 /**< \brief (PDEC_PRESCBUF) Prescaler Buffer Value */
-#define PDEC_PRESCBUF_PRESCBUF_Msk (_U_(0xF) << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF(value) (PDEC_PRESCBUF_PRESCBUF_Msk & ((value) << PDEC_PRESCBUF_PRESCBUF_Pos))
-#define PDEC_PRESCBUF_PRESCBUF_DIV1_Val _U_(0x0) /**< \brief (PDEC_PRESCBUF) No division */
-#define PDEC_PRESCBUF_PRESCBUF_DIV2_Val _U_(0x1) /**< \brief (PDEC_PRESCBUF) Divide by 2 */
-#define PDEC_PRESCBUF_PRESCBUF_DIV4_Val _U_(0x2) /**< \brief (PDEC_PRESCBUF) Divide by 4 */
-#define PDEC_PRESCBUF_PRESCBUF_DIV8_Val _U_(0x3) /**< \brief (PDEC_PRESCBUF) Divide by 8 */
-#define PDEC_PRESCBUF_PRESCBUF_DIV16_Val _U_(0x4) /**< \brief (PDEC_PRESCBUF) Divide by 16 */
-#define PDEC_PRESCBUF_PRESCBUF_DIV32_Val _U_(0x5) /**< \brief (PDEC_PRESCBUF) Divide by 32 */
-#define PDEC_PRESCBUF_PRESCBUF_DIV64_Val _U_(0x6) /**< \brief (PDEC_PRESCBUF) Divide by 64 */
-#define PDEC_PRESCBUF_PRESCBUF_DIV128_Val _U_(0x7) /**< \brief (PDEC_PRESCBUF) Divide by 128 */
-#define PDEC_PRESCBUF_PRESCBUF_DIV256_Val _U_(0x8) /**< \brief (PDEC_PRESCBUF) Divide by 256 */
-#define PDEC_PRESCBUF_PRESCBUF_DIV512_Val _U_(0x9) /**< \brief (PDEC_PRESCBUF) Divide by 512 */
-#define PDEC_PRESCBUF_PRESCBUF_DIV1024_Val _U_(0xA) /**< \brief (PDEC_PRESCBUF) Divide by 1024 */
-#define PDEC_PRESCBUF_PRESCBUF_DIV1 (PDEC_PRESCBUF_PRESCBUF_DIV1_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV2 (PDEC_PRESCBUF_PRESCBUF_DIV2_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV4 (PDEC_PRESCBUF_PRESCBUF_DIV4_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV8 (PDEC_PRESCBUF_PRESCBUF_DIV8_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV16 (PDEC_PRESCBUF_PRESCBUF_DIV16_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV32 (PDEC_PRESCBUF_PRESCBUF_DIV32_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV64 (PDEC_PRESCBUF_PRESCBUF_DIV64_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV128 (PDEC_PRESCBUF_PRESCBUF_DIV128_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV256 (PDEC_PRESCBUF_PRESCBUF_DIV256_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV512 (PDEC_PRESCBUF_PRESCBUF_DIV512_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV1024 (PDEC_PRESCBUF_PRESCBUF_DIV1024_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_MASK _U_(0x0F) /**< \brief (PDEC_PRESCBUF) MASK Register */
-
-/* -------- PDEC_FILTERBUF : (PDEC Offset: 0x19) (R/W 8) Filter Buffer Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t FILTERBUF:8; /*!< bit: 0.. 7 Filter Buffer Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PDEC_FILTERBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_FILTERBUF_OFFSET 0x19 /**< \brief (PDEC_FILTERBUF offset) Filter Buffer Value */
-#define PDEC_FILTERBUF_RESETVALUE _U_(0x00) /**< \brief (PDEC_FILTERBUF reset_value) Filter Buffer Value */
-
-#define PDEC_FILTERBUF_FILTERBUF_Pos 0 /**< \brief (PDEC_FILTERBUF) Filter Buffer Value */
-#define PDEC_FILTERBUF_FILTERBUF_Msk (_U_(0xFF) << PDEC_FILTERBUF_FILTERBUF_Pos)
-#define PDEC_FILTERBUF_FILTERBUF(value) (PDEC_FILTERBUF_FILTERBUF_Msk & ((value) << PDEC_FILTERBUF_FILTERBUF_Pos))
-#define PDEC_FILTERBUF_MASK _U_(0xFF) /**< \brief (PDEC_FILTERBUF) MASK Register */
-
-/* -------- PDEC_COUNT : (PDEC Offset: 0x1C) (R/W 32) Counter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t COUNT:16; /*!< bit: 0..15 Counter Value */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PDEC_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_COUNT_OFFSET 0x1C /**< \brief (PDEC_COUNT offset) Counter Value */
-#define PDEC_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_COUNT reset_value) Counter Value */
-
-#define PDEC_COUNT_COUNT_Pos 0 /**< \brief (PDEC_COUNT) Counter Value */
-#define PDEC_COUNT_COUNT_Msk (_U_(0xFFFF) << PDEC_COUNT_COUNT_Pos)
-#define PDEC_COUNT_COUNT(value) (PDEC_COUNT_COUNT_Msk & ((value) << PDEC_COUNT_COUNT_Pos))
-#define PDEC_COUNT_MASK _U_(0x0000FFFF) /**< \brief (PDEC_COUNT) MASK Register */
-
-/* -------- PDEC_CC : (PDEC Offset: 0x20) (R/W 32) Channel n Compare Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CC:16; /*!< bit: 0..15 Channel Compare Value */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PDEC_CC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_CC_OFFSET 0x20 /**< \brief (PDEC_CC offset) Channel n Compare Value */
-#define PDEC_CC_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_CC reset_value) Channel n Compare Value */
-
-#define PDEC_CC_CC_Pos 0 /**< \brief (PDEC_CC) Channel Compare Value */
-#define PDEC_CC_CC_Msk (_U_(0xFFFF) << PDEC_CC_CC_Pos)
-#define PDEC_CC_CC(value) (PDEC_CC_CC_Msk & ((value) << PDEC_CC_CC_Pos))
-#define PDEC_CC_MASK _U_(0x0000FFFF) /**< \brief (PDEC_CC) MASK Register */
-
-/* -------- PDEC_CCBUF : (PDEC Offset: 0x30) (R/W 32) Channel Compare Buffer Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CCBUF:16; /*!< bit: 0..15 Channel Compare Buffer Value */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PDEC_CCBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_CCBUF_OFFSET 0x30 /**< \brief (PDEC_CCBUF offset) Channel Compare Buffer Value */
-#define PDEC_CCBUF_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_CCBUF reset_value) Channel Compare Buffer Value */
-
-#define PDEC_CCBUF_CCBUF_Pos 0 /**< \brief (PDEC_CCBUF) Channel Compare Buffer Value */
-#define PDEC_CCBUF_CCBUF_Msk (_U_(0xFFFF) << PDEC_CCBUF_CCBUF_Pos)
-#define PDEC_CCBUF_CCBUF(value) (PDEC_CCBUF_CCBUF_Msk & ((value) << PDEC_CCBUF_CCBUF_Pos))
-#define PDEC_CCBUF_MASK _U_(0x0000FFFF) /**< \brief (PDEC_CCBUF) MASK Register */
-
-/** \brief PDEC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO PDEC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
- __IO PDEC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO PDEC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- __IO PDEC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
- __IO PDEC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
- __IO PDEC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
- __IO PDEC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
- RoReg8 Reserved1[0x1];
- __IO PDEC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/W 16) Status */
- RoReg8 Reserved2[0x1];
- __IO PDEC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
- __I PDEC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
- __IO PDEC_PRESC_Type PRESC; /**< \brief Offset: 0x14 (R/W 8) Prescaler Value */
- __IO PDEC_FILTER_Type FILTER; /**< \brief Offset: 0x15 (R/W 8) Filter Value */
- RoReg8 Reserved3[0x2];
- __IO PDEC_PRESCBUF_Type PRESCBUF; /**< \brief Offset: 0x18 (R/W 8) Prescaler Buffer Value */
- __IO PDEC_FILTERBUF_Type FILTERBUF; /**< \brief Offset: 0x19 (R/W 8) Filter Buffer Value */
- RoReg8 Reserved4[0x2];
- __IO PDEC_COUNT_Type COUNT; /**< \brief Offset: 0x1C (R/W 32) Counter Value */
- __IO PDEC_CC_Type CC[2]; /**< \brief Offset: 0x20 (R/W 32) Channel n Compare Value */
- RoReg8 Reserved5[0x8];
- __IO PDEC_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 32) Channel Compare Buffer Value */
-} Pdec;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_PDEC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for PDEC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_PDEC_COMPONENT_
+#define _SAME54_PDEC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PDEC */
+/* ========================================================================== */
+/** \addtogroup SAME54_PDEC Quadrature Decodeur */
+/*@{*/
+
+#define PDEC_U2263
+#define REV_PDEC 0x100
+
+/* -------- PDEC_CTRLA : (PDEC Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:2; /*!< bit: 2.. 3 Operation Mode */
+ uint32_t :2; /*!< bit: 4.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t CONF:3; /*!< bit: 8..10 PDEC Configuration */
+ uint32_t ALOCK:1; /*!< bit: 11 Auto Lock */
+ uint32_t :2; /*!< bit: 12..13 Reserved */
+ uint32_t SWAP:1; /*!< bit: 14 PDEC Phase A and B Swap */
+ uint32_t PEREN:1; /*!< bit: 15 Period Enable */
+ uint32_t PINEN0:1; /*!< bit: 16 PDEC Input From Pin 0 Enable */
+ uint32_t PINEN1:1; /*!< bit: 17 PDEC Input From Pin 1 Enable */
+ uint32_t PINEN2:1; /*!< bit: 18 PDEC Input From Pin 2 Enable */
+ uint32_t :1; /*!< bit: 19 Reserved */
+ uint32_t PINVEN0:1; /*!< bit: 20 IO Pin 0 Invert Enable */
+ uint32_t PINVEN1:1; /*!< bit: 21 IO Pin 1 Invert Enable */
+ uint32_t PINVEN2:1; /*!< bit: 22 IO Pin 2 Invert Enable */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t ANGULAR:3; /*!< bit: 24..26 Angular Counter Length */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t MAXCMP:4; /*!< bit: 28..31 Maximum Consecutive Missing Pulses */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t PINEN:3; /*!< bit: 16..18 PDEC Input From Pin x Enable */
+ uint32_t :1; /*!< bit: 19 Reserved */
+ uint32_t PINVEN:3; /*!< bit: 20..22 IO Pin x Invert Enable */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} PDEC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_CTRLA_OFFSET 0x00 /**< \brief (PDEC_CTRLA offset) Control A */
+#define PDEC_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_CTRLA reset_value) Control A */
+
+#define PDEC_CTRLA_SWRST_Pos 0 /**< \brief (PDEC_CTRLA) Software Reset */
+#define PDEC_CTRLA_SWRST (_U_(0x1) << PDEC_CTRLA_SWRST_Pos)
+#define PDEC_CTRLA_ENABLE_Pos 1 /**< \brief (PDEC_CTRLA) Enable */
+#define PDEC_CTRLA_ENABLE (_U_(0x1) << PDEC_CTRLA_ENABLE_Pos)
+#define PDEC_CTRLA_MODE_Pos 2 /**< \brief (PDEC_CTRLA) Operation Mode */
+#define PDEC_CTRLA_MODE_Msk (_U_(0x3) << PDEC_CTRLA_MODE_Pos)
+#define PDEC_CTRLA_MODE(value) (PDEC_CTRLA_MODE_Msk & ((value) << PDEC_CTRLA_MODE_Pos))
+#define PDEC_CTRLA_MODE_QDEC_Val _U_(0x0) /**< \brief (PDEC_CTRLA) QDEC operating mode */
+#define PDEC_CTRLA_MODE_HALL_Val _U_(0x1) /**< \brief (PDEC_CTRLA) HALL operating mode */
+#define PDEC_CTRLA_MODE_COUNTER_Val _U_(0x2) /**< \brief (PDEC_CTRLA) COUNTER operating mode */
+#define PDEC_CTRLA_MODE_QDEC (PDEC_CTRLA_MODE_QDEC_Val << PDEC_CTRLA_MODE_Pos)
+#define PDEC_CTRLA_MODE_HALL (PDEC_CTRLA_MODE_HALL_Val << PDEC_CTRLA_MODE_Pos)
+#define PDEC_CTRLA_MODE_COUNTER (PDEC_CTRLA_MODE_COUNTER_Val << PDEC_CTRLA_MODE_Pos)
+#define PDEC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (PDEC_CTRLA) Run in Standby */
+#define PDEC_CTRLA_RUNSTDBY (_U_(0x1) << PDEC_CTRLA_RUNSTDBY_Pos)
+#define PDEC_CTRLA_CONF_Pos 8 /**< \brief (PDEC_CTRLA) PDEC Configuration */
+#define PDEC_CTRLA_CONF_Msk (_U_(0x7) << PDEC_CTRLA_CONF_Pos)
+#define PDEC_CTRLA_CONF(value) (PDEC_CTRLA_CONF_Msk & ((value) << PDEC_CTRLA_CONF_Pos))
+#define PDEC_CTRLA_CONF_X4_Val _U_(0x0) /**< \brief (PDEC_CTRLA) Quadrature decoder direction */
+#define PDEC_CTRLA_CONF_X4S_Val _U_(0x1) /**< \brief (PDEC_CTRLA) Secure Quadrature decoder direction */
+#define PDEC_CTRLA_CONF_X2_Val _U_(0x2) /**< \brief (PDEC_CTRLA) Decoder direction */
+#define PDEC_CTRLA_CONF_X2S_Val _U_(0x3) /**< \brief (PDEC_CTRLA) Secure decoder direction */
+#define PDEC_CTRLA_CONF_AUTOC_Val _U_(0x4) /**< \brief (PDEC_CTRLA) Auto correction mode */
+#define PDEC_CTRLA_CONF_X4 (PDEC_CTRLA_CONF_X4_Val << PDEC_CTRLA_CONF_Pos)
+#define PDEC_CTRLA_CONF_X4S (PDEC_CTRLA_CONF_X4S_Val << PDEC_CTRLA_CONF_Pos)
+#define PDEC_CTRLA_CONF_X2 (PDEC_CTRLA_CONF_X2_Val << PDEC_CTRLA_CONF_Pos)
+#define PDEC_CTRLA_CONF_X2S (PDEC_CTRLA_CONF_X2S_Val << PDEC_CTRLA_CONF_Pos)
+#define PDEC_CTRLA_CONF_AUTOC (PDEC_CTRLA_CONF_AUTOC_Val << PDEC_CTRLA_CONF_Pos)
+#define PDEC_CTRLA_ALOCK_Pos 11 /**< \brief (PDEC_CTRLA) Auto Lock */
+#define PDEC_CTRLA_ALOCK (_U_(0x1) << PDEC_CTRLA_ALOCK_Pos)
+#define PDEC_CTRLA_SWAP_Pos 14 /**< \brief (PDEC_CTRLA) PDEC Phase A and B Swap */
+#define PDEC_CTRLA_SWAP (_U_(0x1) << PDEC_CTRLA_SWAP_Pos)
+#define PDEC_CTRLA_PEREN_Pos 15 /**< \brief (PDEC_CTRLA) Period Enable */
+#define PDEC_CTRLA_PEREN (_U_(0x1) << PDEC_CTRLA_PEREN_Pos)
+#define PDEC_CTRLA_PINEN0_Pos 16 /**< \brief (PDEC_CTRLA) PDEC Input From Pin 0 Enable */
+#define PDEC_CTRLA_PINEN0 (_U_(1) << PDEC_CTRLA_PINEN0_Pos)
+#define PDEC_CTRLA_PINEN1_Pos 17 /**< \brief (PDEC_CTRLA) PDEC Input From Pin 1 Enable */
+#define PDEC_CTRLA_PINEN1 (_U_(1) << PDEC_CTRLA_PINEN1_Pos)
+#define PDEC_CTRLA_PINEN2_Pos 18 /**< \brief (PDEC_CTRLA) PDEC Input From Pin 2 Enable */
+#define PDEC_CTRLA_PINEN2 (_U_(1) << PDEC_CTRLA_PINEN2_Pos)
+#define PDEC_CTRLA_PINEN_Pos 16 /**< \brief (PDEC_CTRLA) PDEC Input From Pin x Enable */
+#define PDEC_CTRLA_PINEN_Msk (_U_(0x7) << PDEC_CTRLA_PINEN_Pos)
+#define PDEC_CTRLA_PINEN(value) (PDEC_CTRLA_PINEN_Msk & ((value) << PDEC_CTRLA_PINEN_Pos))
+#define PDEC_CTRLA_PINVEN0_Pos 20 /**< \brief (PDEC_CTRLA) IO Pin 0 Invert Enable */
+#define PDEC_CTRLA_PINVEN0 (_U_(1) << PDEC_CTRLA_PINVEN0_Pos)
+#define PDEC_CTRLA_PINVEN1_Pos 21 /**< \brief (PDEC_CTRLA) IO Pin 1 Invert Enable */
+#define PDEC_CTRLA_PINVEN1 (_U_(1) << PDEC_CTRLA_PINVEN1_Pos)
+#define PDEC_CTRLA_PINVEN2_Pos 22 /**< \brief (PDEC_CTRLA) IO Pin 2 Invert Enable */
+#define PDEC_CTRLA_PINVEN2 (_U_(1) << PDEC_CTRLA_PINVEN2_Pos)
+#define PDEC_CTRLA_PINVEN_Pos 20 /**< \brief (PDEC_CTRLA) IO Pin x Invert Enable */
+#define PDEC_CTRLA_PINVEN_Msk (_U_(0x7) << PDEC_CTRLA_PINVEN_Pos)
+#define PDEC_CTRLA_PINVEN(value) (PDEC_CTRLA_PINVEN_Msk & ((value) << PDEC_CTRLA_PINVEN_Pos))
+#define PDEC_CTRLA_ANGULAR_Pos 24 /**< \brief (PDEC_CTRLA) Angular Counter Length */
+#define PDEC_CTRLA_ANGULAR_Msk (_U_(0x7) << PDEC_CTRLA_ANGULAR_Pos)
+#define PDEC_CTRLA_ANGULAR(value) (PDEC_CTRLA_ANGULAR_Msk & ((value) << PDEC_CTRLA_ANGULAR_Pos))
+#define PDEC_CTRLA_MAXCMP_Pos 28 /**< \brief (PDEC_CTRLA) Maximum Consecutive Missing Pulses */
+#define PDEC_CTRLA_MAXCMP_Msk (_U_(0xF) << PDEC_CTRLA_MAXCMP_Pos)
+#define PDEC_CTRLA_MAXCMP(value) (PDEC_CTRLA_MAXCMP_Msk & ((value) << PDEC_CTRLA_MAXCMP_Pos))
+#define PDEC_CTRLA_MASK _U_(0xF777CF4F) /**< \brief (PDEC_CTRLA) MASK Register */
+
+/* -------- PDEC_CTRLBCLR : (PDEC Offset: 0x04) (R/W 8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t :3; /*!< bit: 2.. 4 Reserved */
+ uint8_t CMD:3; /*!< bit: 5.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_CTRLBCLR_OFFSET 0x04 /**< \brief (PDEC_CTRLBCLR offset) Control B Clear */
+#define PDEC_CTRLBCLR_RESETVALUE _U_(0x00) /**< \brief (PDEC_CTRLBCLR reset_value) Control B Clear */
+
+#define PDEC_CTRLBCLR_LUPD_Pos 1 /**< \brief (PDEC_CTRLBCLR) Lock Update */
+#define PDEC_CTRLBCLR_LUPD (_U_(0x1) << PDEC_CTRLBCLR_LUPD_Pos)
+#define PDEC_CTRLBCLR_CMD_Pos 5 /**< \brief (PDEC_CTRLBCLR) Command */
+#define PDEC_CTRLBCLR_CMD_Msk (_U_(0x7) << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_CMD(value) (PDEC_CTRLBCLR_CMD_Msk & ((value) << PDEC_CTRLBCLR_CMD_Pos))
+#define PDEC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< \brief (PDEC_CTRLBCLR) No action */
+#define PDEC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (PDEC_CTRLBCLR) Force a counter restart or retrigger */
+#define PDEC_CTRLBCLR_CMD_UPDATE_Val _U_(0x2) /**< \brief (PDEC_CTRLBCLR) Force update of double buffered registers */
+#define PDEC_CTRLBCLR_CMD_READSYNC_Val _U_(0x3) /**< \brief (PDEC_CTRLBCLR) Force a read synchronization of COUNT */
+#define PDEC_CTRLBCLR_CMD_START_Val _U_(0x4) /**< \brief (PDEC_CTRLBCLR) Start QDEC/HALL */
+#define PDEC_CTRLBCLR_CMD_STOP_Val _U_(0x5) /**< \brief (PDEC_CTRLBCLR) Stop QDEC/HALL */
+#define PDEC_CTRLBCLR_CMD_NONE (PDEC_CTRLBCLR_CMD_NONE_Val << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_CMD_RETRIGGER (PDEC_CTRLBCLR_CMD_RETRIGGER_Val << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_CMD_UPDATE (PDEC_CTRLBCLR_CMD_UPDATE_Val << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_CMD_READSYNC (PDEC_CTRLBCLR_CMD_READSYNC_Val << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_CMD_START (PDEC_CTRLBCLR_CMD_START_Val << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_CMD_STOP (PDEC_CTRLBCLR_CMD_STOP_Val << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_MASK _U_(0xE2) /**< \brief (PDEC_CTRLBCLR) MASK Register */
+
+/* -------- PDEC_CTRLBSET : (PDEC Offset: 0x05) (R/W 8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t :3; /*!< bit: 2.. 4 Reserved */
+ uint8_t CMD:3; /*!< bit: 5.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_CTRLBSET_OFFSET 0x05 /**< \brief (PDEC_CTRLBSET offset) Control B Set */
+#define PDEC_CTRLBSET_RESETVALUE _U_(0x00) /**< \brief (PDEC_CTRLBSET reset_value) Control B Set */
+
+#define PDEC_CTRLBSET_LUPD_Pos 1 /**< \brief (PDEC_CTRLBSET) Lock Update */
+#define PDEC_CTRLBSET_LUPD (_U_(0x1) << PDEC_CTRLBSET_LUPD_Pos)
+#define PDEC_CTRLBSET_CMD_Pos 5 /**< \brief (PDEC_CTRLBSET) Command */
+#define PDEC_CTRLBSET_CMD_Msk (_U_(0x7) << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_CMD(value) (PDEC_CTRLBSET_CMD_Msk & ((value) << PDEC_CTRLBSET_CMD_Pos))
+#define PDEC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< \brief (PDEC_CTRLBSET) No action */
+#define PDEC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (PDEC_CTRLBSET) Force a counter restart or retrigger */
+#define PDEC_CTRLBSET_CMD_UPDATE_Val _U_(0x2) /**< \brief (PDEC_CTRLBSET) Force update of double buffered registers */
+#define PDEC_CTRLBSET_CMD_READSYNC_Val _U_(0x3) /**< \brief (PDEC_CTRLBSET) Force a read synchronization of COUNT */
+#define PDEC_CTRLBSET_CMD_START_Val _U_(0x4) /**< \brief (PDEC_CTRLBSET) Start QDEC/HALL */
+#define PDEC_CTRLBSET_CMD_STOP_Val _U_(0x5) /**< \brief (PDEC_CTRLBSET) Stop QDEC/HALL */
+#define PDEC_CTRLBSET_CMD_NONE (PDEC_CTRLBSET_CMD_NONE_Val << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_CMD_RETRIGGER (PDEC_CTRLBSET_CMD_RETRIGGER_Val << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_CMD_UPDATE (PDEC_CTRLBSET_CMD_UPDATE_Val << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_CMD_READSYNC (PDEC_CTRLBSET_CMD_READSYNC_Val << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_CMD_START (PDEC_CTRLBSET_CMD_START_Val << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_CMD_STOP (PDEC_CTRLBSET_CMD_STOP_Val << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_MASK _U_(0xE2) /**< \brief (PDEC_CTRLBSET) MASK Register */
+
+/* -------- PDEC_EVCTRL : (PDEC Offset: 0x06) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t EVACT:2; /*!< bit: 0.. 1 Event Action */
+ uint16_t EVINV:3; /*!< bit: 2.. 4 Inverted Event Input Enable */
+ uint16_t EVEI:3; /*!< bit: 5.. 7 Event Input Enable */
+ uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
+ uint16_t ERREO:1; /*!< bit: 9 Error Output Event Enable */
+ uint16_t DIREO:1; /*!< bit: 10 Direction Output Event Enable */
+ uint16_t VLCEO:1; /*!< bit: 11 Velocity Output Event Enable */
+ uint16_t MCEO0:1; /*!< bit: 12 Match Channel 0 Event Output Enable */
+ uint16_t MCEO1:1; /*!< bit: 13 Match Channel 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :12; /*!< bit: 0..11 Reserved */
+ uint16_t MCEO:2; /*!< bit: 12..13 Match Channel x Event Output Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} PDEC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_EVCTRL_OFFSET 0x06 /**< \brief (PDEC_EVCTRL offset) Event Control */
+#define PDEC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (PDEC_EVCTRL reset_value) Event Control */
+
+#define PDEC_EVCTRL_EVACT_Pos 0 /**< \brief (PDEC_EVCTRL) Event Action */
+#define PDEC_EVCTRL_EVACT_Msk (_U_(0x3) << PDEC_EVCTRL_EVACT_Pos)
+#define PDEC_EVCTRL_EVACT(value) (PDEC_EVCTRL_EVACT_Msk & ((value) << PDEC_EVCTRL_EVACT_Pos))
+#define PDEC_EVCTRL_EVACT_OFF_Val _U_(0x0) /**< \brief (PDEC_EVCTRL) Event action disabled */
+#define PDEC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1) /**< \brief (PDEC_EVCTRL) Start, restart or retrigger on event */
+#define PDEC_EVCTRL_EVACT_COUNT_Val _U_(0x2) /**< \brief (PDEC_EVCTRL) Count on event */
+#define PDEC_EVCTRL_EVACT_OFF (PDEC_EVCTRL_EVACT_OFF_Val << PDEC_EVCTRL_EVACT_Pos)
+#define PDEC_EVCTRL_EVACT_RETRIGGER (PDEC_EVCTRL_EVACT_RETRIGGER_Val << PDEC_EVCTRL_EVACT_Pos)
+#define PDEC_EVCTRL_EVACT_COUNT (PDEC_EVCTRL_EVACT_COUNT_Val << PDEC_EVCTRL_EVACT_Pos)
+#define PDEC_EVCTRL_EVINV_Pos 2 /**< \brief (PDEC_EVCTRL) Inverted Event Input Enable */
+#define PDEC_EVCTRL_EVINV_Msk (_U_(0x7) << PDEC_EVCTRL_EVINV_Pos)
+#define PDEC_EVCTRL_EVINV(value) (PDEC_EVCTRL_EVINV_Msk & ((value) << PDEC_EVCTRL_EVINV_Pos))
+#define PDEC_EVCTRL_EVEI_Pos 5 /**< \brief (PDEC_EVCTRL) Event Input Enable */
+#define PDEC_EVCTRL_EVEI_Msk (_U_(0x7) << PDEC_EVCTRL_EVEI_Pos)
+#define PDEC_EVCTRL_EVEI(value) (PDEC_EVCTRL_EVEI_Msk & ((value) << PDEC_EVCTRL_EVEI_Pos))
+#define PDEC_EVCTRL_OVFEO_Pos 8 /**< \brief (PDEC_EVCTRL) Overflow/Underflow Output Event Enable */
+#define PDEC_EVCTRL_OVFEO (_U_(0x1) << PDEC_EVCTRL_OVFEO_Pos)
+#define PDEC_EVCTRL_ERREO_Pos 9 /**< \brief (PDEC_EVCTRL) Error Output Event Enable */
+#define PDEC_EVCTRL_ERREO (_U_(0x1) << PDEC_EVCTRL_ERREO_Pos)
+#define PDEC_EVCTRL_DIREO_Pos 10 /**< \brief (PDEC_EVCTRL) Direction Output Event Enable */
+#define PDEC_EVCTRL_DIREO (_U_(0x1) << PDEC_EVCTRL_DIREO_Pos)
+#define PDEC_EVCTRL_VLCEO_Pos 11 /**< \brief (PDEC_EVCTRL) Velocity Output Event Enable */
+#define PDEC_EVCTRL_VLCEO (_U_(0x1) << PDEC_EVCTRL_VLCEO_Pos)
+#define PDEC_EVCTRL_MCEO0_Pos 12 /**< \brief (PDEC_EVCTRL) Match Channel 0 Event Output Enable */
+#define PDEC_EVCTRL_MCEO0 (_U_(1) << PDEC_EVCTRL_MCEO0_Pos)
+#define PDEC_EVCTRL_MCEO1_Pos 13 /**< \brief (PDEC_EVCTRL) Match Channel 1 Event Output Enable */
+#define PDEC_EVCTRL_MCEO1 (_U_(1) << PDEC_EVCTRL_MCEO1_Pos)
+#define PDEC_EVCTRL_MCEO_Pos 12 /**< \brief (PDEC_EVCTRL) Match Channel x Event Output Enable */
+#define PDEC_EVCTRL_MCEO_Msk (_U_(0x3) << PDEC_EVCTRL_MCEO_Pos)
+#define PDEC_EVCTRL_MCEO(value) (PDEC_EVCTRL_MCEO_Msk & ((value) << PDEC_EVCTRL_MCEO_Pos))
+#define PDEC_EVCTRL_MASK _U_(0x3FFF) /**< \brief (PDEC_EVCTRL) MASK Register */
+
+/* -------- PDEC_INTENCLR : (PDEC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow Interrupt Disable */
+ uint8_t ERR:1; /*!< bit: 1 Error Interrupt Disable */
+ uint8_t DIR:1; /*!< bit: 2 Direction Interrupt Disable */
+ uint8_t VLC:1; /*!< bit: 3 Velocity Interrupt Disable */
+ uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match Disable */
+ uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match Disable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match Disable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_INTENCLR_OFFSET 0x08 /**< \brief (PDEC_INTENCLR offset) Interrupt Enable Clear */
+#define PDEC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PDEC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define PDEC_INTENCLR_OVF_Pos 0 /**< \brief (PDEC_INTENCLR) Overflow/Underflow Interrupt Disable */
+#define PDEC_INTENCLR_OVF (_U_(0x1) << PDEC_INTENCLR_OVF_Pos)
+#define PDEC_INTENCLR_ERR_Pos 1 /**< \brief (PDEC_INTENCLR) Error Interrupt Disable */
+#define PDEC_INTENCLR_ERR (_U_(0x1) << PDEC_INTENCLR_ERR_Pos)
+#define PDEC_INTENCLR_DIR_Pos 2 /**< \brief (PDEC_INTENCLR) Direction Interrupt Disable */
+#define PDEC_INTENCLR_DIR (_U_(0x1) << PDEC_INTENCLR_DIR_Pos)
+#define PDEC_INTENCLR_VLC_Pos 3 /**< \brief (PDEC_INTENCLR) Velocity Interrupt Disable */
+#define PDEC_INTENCLR_VLC (_U_(0x1) << PDEC_INTENCLR_VLC_Pos)
+#define PDEC_INTENCLR_MC0_Pos 4 /**< \brief (PDEC_INTENCLR) Channel 0 Compare Match Disable */
+#define PDEC_INTENCLR_MC0 (_U_(1) << PDEC_INTENCLR_MC0_Pos)
+#define PDEC_INTENCLR_MC1_Pos 5 /**< \brief (PDEC_INTENCLR) Channel 1 Compare Match Disable */
+#define PDEC_INTENCLR_MC1 (_U_(1) << PDEC_INTENCLR_MC1_Pos)
+#define PDEC_INTENCLR_MC_Pos 4 /**< \brief (PDEC_INTENCLR) Channel x Compare Match Disable */
+#define PDEC_INTENCLR_MC_Msk (_U_(0x3) << PDEC_INTENCLR_MC_Pos)
+#define PDEC_INTENCLR_MC(value) (PDEC_INTENCLR_MC_Msk & ((value) << PDEC_INTENCLR_MC_Pos))
+#define PDEC_INTENCLR_MASK _U_(0x3F) /**< \brief (PDEC_INTENCLR) MASK Register */
+
+/* -------- PDEC_INTENSET : (PDEC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow Interrupt Enable */
+ uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t DIR:1; /*!< bit: 2 Direction Interrupt Enable */
+ uint8_t VLC:1; /*!< bit: 3 Velocity Interrupt Enable */
+ uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match Enable */
+ uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_INTENSET_OFFSET 0x09 /**< \brief (PDEC_INTENSET offset) Interrupt Enable Set */
+#define PDEC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PDEC_INTENSET reset_value) Interrupt Enable Set */
+
+#define PDEC_INTENSET_OVF_Pos 0 /**< \brief (PDEC_INTENSET) Overflow/Underflow Interrupt Enable */
+#define PDEC_INTENSET_OVF (_U_(0x1) << PDEC_INTENSET_OVF_Pos)
+#define PDEC_INTENSET_ERR_Pos 1 /**< \brief (PDEC_INTENSET) Error Interrupt Enable */
+#define PDEC_INTENSET_ERR (_U_(0x1) << PDEC_INTENSET_ERR_Pos)
+#define PDEC_INTENSET_DIR_Pos 2 /**< \brief (PDEC_INTENSET) Direction Interrupt Enable */
+#define PDEC_INTENSET_DIR (_U_(0x1) << PDEC_INTENSET_DIR_Pos)
+#define PDEC_INTENSET_VLC_Pos 3 /**< \brief (PDEC_INTENSET) Velocity Interrupt Enable */
+#define PDEC_INTENSET_VLC (_U_(0x1) << PDEC_INTENSET_VLC_Pos)
+#define PDEC_INTENSET_MC0_Pos 4 /**< \brief (PDEC_INTENSET) Channel 0 Compare Match Enable */
+#define PDEC_INTENSET_MC0 (_U_(1) << PDEC_INTENSET_MC0_Pos)
+#define PDEC_INTENSET_MC1_Pos 5 /**< \brief (PDEC_INTENSET) Channel 1 Compare Match Enable */
+#define PDEC_INTENSET_MC1 (_U_(1) << PDEC_INTENSET_MC1_Pos)
+#define PDEC_INTENSET_MC_Pos 4 /**< \brief (PDEC_INTENSET) Channel x Compare Match Enable */
+#define PDEC_INTENSET_MC_Msk (_U_(0x3) << PDEC_INTENSET_MC_Pos)
+#define PDEC_INTENSET_MC(value) (PDEC_INTENSET_MC_Msk & ((value) << PDEC_INTENSET_MC_Pos))
+#define PDEC_INTENSET_MASK _U_(0x3F) /**< \brief (PDEC_INTENSET) MASK Register */
+
+/* -------- PDEC_INTFLAG : (PDEC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow */
+ __I uint8_t ERR:1; /*!< bit: 1 Error */
+ __I uint8_t DIR:1; /*!< bit: 2 Direction Change */
+ __I uint8_t VLC:1; /*!< bit: 3 Velocity */
+ __I uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match */
+ __I uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ __I uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_INTFLAG_OFFSET 0x0A /**< \brief (PDEC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define PDEC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (PDEC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define PDEC_INTFLAG_OVF_Pos 0 /**< \brief (PDEC_INTFLAG) Overflow/Underflow */
+#define PDEC_INTFLAG_OVF (_U_(0x1) << PDEC_INTFLAG_OVF_Pos)
+#define PDEC_INTFLAG_ERR_Pos 1 /**< \brief (PDEC_INTFLAG) Error */
+#define PDEC_INTFLAG_ERR (_U_(0x1) << PDEC_INTFLAG_ERR_Pos)
+#define PDEC_INTFLAG_DIR_Pos 2 /**< \brief (PDEC_INTFLAG) Direction Change */
+#define PDEC_INTFLAG_DIR (_U_(0x1) << PDEC_INTFLAG_DIR_Pos)
+#define PDEC_INTFLAG_VLC_Pos 3 /**< \brief (PDEC_INTFLAG) Velocity */
+#define PDEC_INTFLAG_VLC (_U_(0x1) << PDEC_INTFLAG_VLC_Pos)
+#define PDEC_INTFLAG_MC0_Pos 4 /**< \brief (PDEC_INTFLAG) Channel 0 Compare Match */
+#define PDEC_INTFLAG_MC0 (_U_(1) << PDEC_INTFLAG_MC0_Pos)
+#define PDEC_INTFLAG_MC1_Pos 5 /**< \brief (PDEC_INTFLAG) Channel 1 Compare Match */
+#define PDEC_INTFLAG_MC1 (_U_(1) << PDEC_INTFLAG_MC1_Pos)
+#define PDEC_INTFLAG_MC_Pos 4 /**< \brief (PDEC_INTFLAG) Channel x Compare Match */
+#define PDEC_INTFLAG_MC_Msk (_U_(0x3) << PDEC_INTFLAG_MC_Pos)
+#define PDEC_INTFLAG_MC(value) (PDEC_INTFLAG_MC_Msk & ((value) << PDEC_INTFLAG_MC_Pos))
+#define PDEC_INTFLAG_MASK _U_(0x3F) /**< \brief (PDEC_INTFLAG) MASK Register */
+
+/* -------- PDEC_STATUS : (PDEC Offset: 0x0C) (R/W 16) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t QERR:1; /*!< bit: 0 Quadrature Error Flag */
+ uint16_t IDXERR:1; /*!< bit: 1 Index Error Flag */
+ uint16_t MPERR:1; /*!< bit: 2 Missing Pulse Error flag */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t WINERR:1; /*!< bit: 4 Window Error Flag */
+ uint16_t HERR:1; /*!< bit: 5 Hall Error Flag */
+ uint16_t STOP:1; /*!< bit: 6 Stop */
+ uint16_t DIR:1; /*!< bit: 7 Direction Status Flag */
+ uint16_t PRESCBUFV:1; /*!< bit: 8 Prescaler Buffer Valid */
+ uint16_t FILTERBUFV:1; /*!< bit: 9 Filter Buffer Valid */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t CCBUFV0:1; /*!< bit: 12 Compare Channel 0 Buffer Valid */
+ uint16_t CCBUFV1:1; /*!< bit: 13 Compare Channel 1 Buffer Valid */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :12; /*!< bit: 0..11 Reserved */
+ uint16_t CCBUFV:2; /*!< bit: 12..13 Compare Channel x Buffer Valid */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} PDEC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_STATUS_OFFSET 0x0C /**< \brief (PDEC_STATUS offset) Status */
+#define PDEC_STATUS_RESETVALUE _U_(0x0040) /**< \brief (PDEC_STATUS reset_value) Status */
+
+#define PDEC_STATUS_QERR_Pos 0 /**< \brief (PDEC_STATUS) Quadrature Error Flag */
+#define PDEC_STATUS_QERR (_U_(0x1) << PDEC_STATUS_QERR_Pos)
+#define PDEC_STATUS_IDXERR_Pos 1 /**< \brief (PDEC_STATUS) Index Error Flag */
+#define PDEC_STATUS_IDXERR (_U_(0x1) << PDEC_STATUS_IDXERR_Pos)
+#define PDEC_STATUS_MPERR_Pos 2 /**< \brief (PDEC_STATUS) Missing Pulse Error flag */
+#define PDEC_STATUS_MPERR (_U_(0x1) << PDEC_STATUS_MPERR_Pos)
+#define PDEC_STATUS_WINERR_Pos 4 /**< \brief (PDEC_STATUS) Window Error Flag */
+#define PDEC_STATUS_WINERR (_U_(0x1) << PDEC_STATUS_WINERR_Pos)
+#define PDEC_STATUS_HERR_Pos 5 /**< \brief (PDEC_STATUS) Hall Error Flag */
+#define PDEC_STATUS_HERR (_U_(0x1) << PDEC_STATUS_HERR_Pos)
+#define PDEC_STATUS_STOP_Pos 6 /**< \brief (PDEC_STATUS) Stop */
+#define PDEC_STATUS_STOP (_U_(0x1) << PDEC_STATUS_STOP_Pos)
+#define PDEC_STATUS_DIR_Pos 7 /**< \brief (PDEC_STATUS) Direction Status Flag */
+#define PDEC_STATUS_DIR (_U_(0x1) << PDEC_STATUS_DIR_Pos)
+#define PDEC_STATUS_PRESCBUFV_Pos 8 /**< \brief (PDEC_STATUS) Prescaler Buffer Valid */
+#define PDEC_STATUS_PRESCBUFV (_U_(0x1) << PDEC_STATUS_PRESCBUFV_Pos)
+#define PDEC_STATUS_FILTERBUFV_Pos 9 /**< \brief (PDEC_STATUS) Filter Buffer Valid */
+#define PDEC_STATUS_FILTERBUFV (_U_(0x1) << PDEC_STATUS_FILTERBUFV_Pos)
+#define PDEC_STATUS_CCBUFV0_Pos 12 /**< \brief (PDEC_STATUS) Compare Channel 0 Buffer Valid */
+#define PDEC_STATUS_CCBUFV0 (_U_(1) << PDEC_STATUS_CCBUFV0_Pos)
+#define PDEC_STATUS_CCBUFV1_Pos 13 /**< \brief (PDEC_STATUS) Compare Channel 1 Buffer Valid */
+#define PDEC_STATUS_CCBUFV1 (_U_(1) << PDEC_STATUS_CCBUFV1_Pos)
+#define PDEC_STATUS_CCBUFV_Pos 12 /**< \brief (PDEC_STATUS) Compare Channel x Buffer Valid */
+#define PDEC_STATUS_CCBUFV_Msk (_U_(0x3) << PDEC_STATUS_CCBUFV_Pos)
+#define PDEC_STATUS_CCBUFV(value) (PDEC_STATUS_CCBUFV_Msk & ((value) << PDEC_STATUS_CCBUFV_Pos))
+#define PDEC_STATUS_MASK _U_(0x33F7) /**< \brief (PDEC_STATUS) MASK Register */
+
+/* -------- PDEC_DBGCTRL : (PDEC Offset: 0x0F) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_DBGCTRL_OFFSET 0x0F /**< \brief (PDEC_DBGCTRL offset) Debug Control */
+#define PDEC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (PDEC_DBGCTRL reset_value) Debug Control */
+
+#define PDEC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (PDEC_DBGCTRL) Debug Run Mode */
+#define PDEC_DBGCTRL_DBGRUN (_U_(0x1) << PDEC_DBGCTRL_DBGRUN_Pos)
+#define PDEC_DBGCTRL_MASK _U_(0x01) /**< \brief (PDEC_DBGCTRL) MASK Register */
+
+/* -------- PDEC_SYNCBUSY : (PDEC Offset: 0x10) (R/ 32) Synchronization Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 Control B Synchronization Busy */
+ uint32_t STATUS:1; /*!< bit: 3 Status Synchronization Busy */
+ uint32_t PRESC:1; /*!< bit: 4 Prescaler Synchronization Busy */
+ uint32_t FILTER:1; /*!< bit: 5 Filter Synchronization Busy */
+ uint32_t COUNT:1; /*!< bit: 6 Count Synchronization Busy */
+ uint32_t CC0:1; /*!< bit: 7 Compare Channel 0 Synchronization Busy */
+ uint32_t CC1:1; /*!< bit: 8 Compare Channel 1 Synchronization Busy */
+ uint32_t :23; /*!< bit: 9..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :7; /*!< bit: 0.. 6 Reserved */
+ uint32_t CC:2; /*!< bit: 7.. 8 Compare Channel x Synchronization Busy */
+ uint32_t :23; /*!< bit: 9..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} PDEC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_SYNCBUSY_OFFSET 0x10 /**< \brief (PDEC_SYNCBUSY offset) Synchronization Status */
+#define PDEC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_SYNCBUSY reset_value) Synchronization Status */
+
+#define PDEC_SYNCBUSY_SWRST_Pos 0 /**< \brief (PDEC_SYNCBUSY) Software Reset Synchronization Busy */
+#define PDEC_SYNCBUSY_SWRST (_U_(0x1) << PDEC_SYNCBUSY_SWRST_Pos)
+#define PDEC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (PDEC_SYNCBUSY) Enable Synchronization Busy */
+#define PDEC_SYNCBUSY_ENABLE (_U_(0x1) << PDEC_SYNCBUSY_ENABLE_Pos)
+#define PDEC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (PDEC_SYNCBUSY) Control B Synchronization Busy */
+#define PDEC_SYNCBUSY_CTRLB (_U_(0x1) << PDEC_SYNCBUSY_CTRLB_Pos)
+#define PDEC_SYNCBUSY_STATUS_Pos 3 /**< \brief (PDEC_SYNCBUSY) Status Synchronization Busy */
+#define PDEC_SYNCBUSY_STATUS (_U_(0x1) << PDEC_SYNCBUSY_STATUS_Pos)
+#define PDEC_SYNCBUSY_PRESC_Pos 4 /**< \brief (PDEC_SYNCBUSY) Prescaler Synchronization Busy */
+#define PDEC_SYNCBUSY_PRESC (_U_(0x1) << PDEC_SYNCBUSY_PRESC_Pos)
+#define PDEC_SYNCBUSY_FILTER_Pos 5 /**< \brief (PDEC_SYNCBUSY) Filter Synchronization Busy */
+#define PDEC_SYNCBUSY_FILTER (_U_(0x1) << PDEC_SYNCBUSY_FILTER_Pos)
+#define PDEC_SYNCBUSY_COUNT_Pos 6 /**< \brief (PDEC_SYNCBUSY) Count Synchronization Busy */
+#define PDEC_SYNCBUSY_COUNT (_U_(0x1) << PDEC_SYNCBUSY_COUNT_Pos)
+#define PDEC_SYNCBUSY_CC0_Pos 7 /**< \brief (PDEC_SYNCBUSY) Compare Channel 0 Synchronization Busy */
+#define PDEC_SYNCBUSY_CC0 (_U_(1) << PDEC_SYNCBUSY_CC0_Pos)
+#define PDEC_SYNCBUSY_CC1_Pos 8 /**< \brief (PDEC_SYNCBUSY) Compare Channel 1 Synchronization Busy */
+#define PDEC_SYNCBUSY_CC1 (_U_(1) << PDEC_SYNCBUSY_CC1_Pos)
+#define PDEC_SYNCBUSY_CC_Pos 7 /**< \brief (PDEC_SYNCBUSY) Compare Channel x Synchronization Busy */
+#define PDEC_SYNCBUSY_CC_Msk (_U_(0x3) << PDEC_SYNCBUSY_CC_Pos)
+#define PDEC_SYNCBUSY_CC(value) (PDEC_SYNCBUSY_CC_Msk & ((value) << PDEC_SYNCBUSY_CC_Pos))
+#define PDEC_SYNCBUSY_MASK _U_(0x000001FF) /**< \brief (PDEC_SYNCBUSY) MASK Register */
+
+/* -------- PDEC_PRESC : (PDEC Offset: 0x14) (R/W 8) Prescaler Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PRESC:4; /*!< bit: 0.. 3 Prescaler Value */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_PRESC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_PRESC_OFFSET 0x14 /**< \brief (PDEC_PRESC offset) Prescaler Value */
+#define PDEC_PRESC_RESETVALUE _U_(0x00) /**< \brief (PDEC_PRESC reset_value) Prescaler Value */
+
+#define PDEC_PRESC_PRESC_Pos 0 /**< \brief (PDEC_PRESC) Prescaler Value */
+#define PDEC_PRESC_PRESC_Msk (_U_(0xF) << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC(value) (PDEC_PRESC_PRESC_Msk & ((value) << PDEC_PRESC_PRESC_Pos))
+#define PDEC_PRESC_PRESC_DIV1_Val _U_(0x0) /**< \brief (PDEC_PRESC) No division */
+#define PDEC_PRESC_PRESC_DIV2_Val _U_(0x1) /**< \brief (PDEC_PRESC) Divide by 2 */
+#define PDEC_PRESC_PRESC_DIV4_Val _U_(0x2) /**< \brief (PDEC_PRESC) Divide by 4 */
+#define PDEC_PRESC_PRESC_DIV8_Val _U_(0x3) /**< \brief (PDEC_PRESC) Divide by 8 */
+#define PDEC_PRESC_PRESC_DIV16_Val _U_(0x4) /**< \brief (PDEC_PRESC) Divide by 16 */
+#define PDEC_PRESC_PRESC_DIV32_Val _U_(0x5) /**< \brief (PDEC_PRESC) Divide by 32 */
+#define PDEC_PRESC_PRESC_DIV64_Val _U_(0x6) /**< \brief (PDEC_PRESC) Divide by 64 */
+#define PDEC_PRESC_PRESC_DIV128_Val _U_(0x7) /**< \brief (PDEC_PRESC) Divide by 128 */
+#define PDEC_PRESC_PRESC_DIV256_Val _U_(0x8) /**< \brief (PDEC_PRESC) Divide by 256 */
+#define PDEC_PRESC_PRESC_DIV512_Val _U_(0x9) /**< \brief (PDEC_PRESC) Divide by 512 */
+#define PDEC_PRESC_PRESC_DIV1024_Val _U_(0xA) /**< \brief (PDEC_PRESC) Divide by 1024 */
+#define PDEC_PRESC_PRESC_DIV1 (PDEC_PRESC_PRESC_DIV1_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV2 (PDEC_PRESC_PRESC_DIV2_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV4 (PDEC_PRESC_PRESC_DIV4_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV8 (PDEC_PRESC_PRESC_DIV8_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV16 (PDEC_PRESC_PRESC_DIV16_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV32 (PDEC_PRESC_PRESC_DIV32_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV64 (PDEC_PRESC_PRESC_DIV64_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV128 (PDEC_PRESC_PRESC_DIV128_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV256 (PDEC_PRESC_PRESC_DIV256_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV512 (PDEC_PRESC_PRESC_DIV512_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV1024 (PDEC_PRESC_PRESC_DIV1024_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_MASK _U_(0x0F) /**< \brief (PDEC_PRESC) MASK Register */
+
+/* -------- PDEC_FILTER : (PDEC Offset: 0x15) (R/W 8) Filter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FILTER:8; /*!< bit: 0.. 7 Filter Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_FILTER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_FILTER_OFFSET 0x15 /**< \brief (PDEC_FILTER offset) Filter Value */
+#define PDEC_FILTER_RESETVALUE _U_(0x00) /**< \brief (PDEC_FILTER reset_value) Filter Value */
+
+#define PDEC_FILTER_FILTER_Pos 0 /**< \brief (PDEC_FILTER) Filter Value */
+#define PDEC_FILTER_FILTER_Msk (_U_(0xFF) << PDEC_FILTER_FILTER_Pos)
+#define PDEC_FILTER_FILTER(value) (PDEC_FILTER_FILTER_Msk & ((value) << PDEC_FILTER_FILTER_Pos))
+#define PDEC_FILTER_MASK _U_(0xFF) /**< \brief (PDEC_FILTER) MASK Register */
+
+/* -------- PDEC_PRESCBUF : (PDEC Offset: 0x18) (R/W 8) Prescaler Buffer Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PRESCBUF:4; /*!< bit: 0.. 3 Prescaler Buffer Value */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_PRESCBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_PRESCBUF_OFFSET 0x18 /**< \brief (PDEC_PRESCBUF offset) Prescaler Buffer Value */
+#define PDEC_PRESCBUF_RESETVALUE _U_(0x00) /**< \brief (PDEC_PRESCBUF reset_value) Prescaler Buffer Value */
+
+#define PDEC_PRESCBUF_PRESCBUF_Pos 0 /**< \brief (PDEC_PRESCBUF) Prescaler Buffer Value */
+#define PDEC_PRESCBUF_PRESCBUF_Msk (_U_(0xF) << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF(value) (PDEC_PRESCBUF_PRESCBUF_Msk & ((value) << PDEC_PRESCBUF_PRESCBUF_Pos))
+#define PDEC_PRESCBUF_PRESCBUF_DIV1_Val _U_(0x0) /**< \brief (PDEC_PRESCBUF) No division */
+#define PDEC_PRESCBUF_PRESCBUF_DIV2_Val _U_(0x1) /**< \brief (PDEC_PRESCBUF) Divide by 2 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV4_Val _U_(0x2) /**< \brief (PDEC_PRESCBUF) Divide by 4 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV8_Val _U_(0x3) /**< \brief (PDEC_PRESCBUF) Divide by 8 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV16_Val _U_(0x4) /**< \brief (PDEC_PRESCBUF) Divide by 16 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV32_Val _U_(0x5) /**< \brief (PDEC_PRESCBUF) Divide by 32 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV64_Val _U_(0x6) /**< \brief (PDEC_PRESCBUF) Divide by 64 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV128_Val _U_(0x7) /**< \brief (PDEC_PRESCBUF) Divide by 128 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV256_Val _U_(0x8) /**< \brief (PDEC_PRESCBUF) Divide by 256 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV512_Val _U_(0x9) /**< \brief (PDEC_PRESCBUF) Divide by 512 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV1024_Val _U_(0xA) /**< \brief (PDEC_PRESCBUF) Divide by 1024 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV1 (PDEC_PRESCBUF_PRESCBUF_DIV1_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV2 (PDEC_PRESCBUF_PRESCBUF_DIV2_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV4 (PDEC_PRESCBUF_PRESCBUF_DIV4_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV8 (PDEC_PRESCBUF_PRESCBUF_DIV8_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV16 (PDEC_PRESCBUF_PRESCBUF_DIV16_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV32 (PDEC_PRESCBUF_PRESCBUF_DIV32_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV64 (PDEC_PRESCBUF_PRESCBUF_DIV64_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV128 (PDEC_PRESCBUF_PRESCBUF_DIV128_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV256 (PDEC_PRESCBUF_PRESCBUF_DIV256_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV512 (PDEC_PRESCBUF_PRESCBUF_DIV512_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV1024 (PDEC_PRESCBUF_PRESCBUF_DIV1024_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_MASK _U_(0x0F) /**< \brief (PDEC_PRESCBUF) MASK Register */
+
+/* -------- PDEC_FILTERBUF : (PDEC Offset: 0x19) (R/W 8) Filter Buffer Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FILTERBUF:8; /*!< bit: 0.. 7 Filter Buffer Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_FILTERBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_FILTERBUF_OFFSET 0x19 /**< \brief (PDEC_FILTERBUF offset) Filter Buffer Value */
+#define PDEC_FILTERBUF_RESETVALUE _U_(0x00) /**< \brief (PDEC_FILTERBUF reset_value) Filter Buffer Value */
+
+#define PDEC_FILTERBUF_FILTERBUF_Pos 0 /**< \brief (PDEC_FILTERBUF) Filter Buffer Value */
+#define PDEC_FILTERBUF_FILTERBUF_Msk (_U_(0xFF) << PDEC_FILTERBUF_FILTERBUF_Pos)
+#define PDEC_FILTERBUF_FILTERBUF(value) (PDEC_FILTERBUF_FILTERBUF_Msk & ((value) << PDEC_FILTERBUF_FILTERBUF_Pos))
+#define PDEC_FILTERBUF_MASK _U_(0xFF) /**< \brief (PDEC_FILTERBUF) MASK Register */
+
+/* -------- PDEC_COUNT : (PDEC Offset: 0x1C) (R/W 32) Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COUNT:16; /*!< bit: 0..15 Counter Value */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PDEC_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_COUNT_OFFSET 0x1C /**< \brief (PDEC_COUNT offset) Counter Value */
+#define PDEC_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_COUNT reset_value) Counter Value */
+
+#define PDEC_COUNT_COUNT_Pos 0 /**< \brief (PDEC_COUNT) Counter Value */
+#define PDEC_COUNT_COUNT_Msk (_U_(0xFFFF) << PDEC_COUNT_COUNT_Pos)
+#define PDEC_COUNT_COUNT(value) (PDEC_COUNT_COUNT_Msk & ((value) << PDEC_COUNT_COUNT_Pos))
+#define PDEC_COUNT_MASK _U_(0x0000FFFF) /**< \brief (PDEC_COUNT) MASK Register */
+
+/* -------- PDEC_CC : (PDEC Offset: 0x20) (R/W 32) Channel n Compare Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CC:16; /*!< bit: 0..15 Channel Compare Value */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PDEC_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_CC_OFFSET 0x20 /**< \brief (PDEC_CC offset) Channel n Compare Value */
+#define PDEC_CC_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_CC reset_value) Channel n Compare Value */
+
+#define PDEC_CC_CC_Pos 0 /**< \brief (PDEC_CC) Channel Compare Value */
+#define PDEC_CC_CC_Msk (_U_(0xFFFF) << PDEC_CC_CC_Pos)
+#define PDEC_CC_CC(value) (PDEC_CC_CC_Msk & ((value) << PDEC_CC_CC_Pos))
+#define PDEC_CC_MASK _U_(0x0000FFFF) /**< \brief (PDEC_CC) MASK Register */
+
+/* -------- PDEC_CCBUF : (PDEC Offset: 0x30) (R/W 32) Channel Compare Buffer Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CCBUF:16; /*!< bit: 0..15 Channel Compare Buffer Value */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PDEC_CCBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_CCBUF_OFFSET 0x30 /**< \brief (PDEC_CCBUF offset) Channel Compare Buffer Value */
+#define PDEC_CCBUF_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_CCBUF reset_value) Channel Compare Buffer Value */
+
+#define PDEC_CCBUF_CCBUF_Pos 0 /**< \brief (PDEC_CCBUF) Channel Compare Buffer Value */
+#define PDEC_CCBUF_CCBUF_Msk (_U_(0xFFFF) << PDEC_CCBUF_CCBUF_Pos)
+#define PDEC_CCBUF_CCBUF(value) (PDEC_CCBUF_CCBUF_Msk & ((value) << PDEC_CCBUF_CCBUF_Pos))
+#define PDEC_CCBUF_MASK _U_(0x0000FFFF) /**< \brief (PDEC_CCBUF) MASK Register */
+
+/** \brief PDEC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PDEC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO PDEC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO PDEC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO PDEC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
+ __IO PDEC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
+ __IO PDEC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
+ __IO PDEC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO PDEC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/W 16) Status */
+ RoReg8 Reserved2[0x1];
+ __IO PDEC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
+ __I PDEC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
+ __IO PDEC_PRESC_Type PRESC; /**< \brief Offset: 0x14 (R/W 8) Prescaler Value */
+ __IO PDEC_FILTER_Type FILTER; /**< \brief Offset: 0x15 (R/W 8) Filter Value */
+ RoReg8 Reserved3[0x2];
+ __IO PDEC_PRESCBUF_Type PRESCBUF; /**< \brief Offset: 0x18 (R/W 8) Prescaler Buffer Value */
+ __IO PDEC_FILTERBUF_Type FILTERBUF; /**< \brief Offset: 0x19 (R/W 8) Filter Buffer Value */
+ RoReg8 Reserved4[0x2];
+ __IO PDEC_COUNT_Type COUNT; /**< \brief Offset: 0x1C (R/W 32) Counter Value */
+ __IO PDEC_CC_Type CC[2]; /**< \brief Offset: 0x20 (R/W 32) Channel n Compare Value */
+ RoReg8 Reserved5[0x8];
+ __IO PDEC_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 32) Channel Compare Buffer Value */
+} Pdec;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_PDEC_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/pm.h b/sysmoOCTSIM/include/component/pm.h
index 08b1cf6..b2f14d4 100644
--- a/sysmoOCTSIM/include/component/pm.h
+++ b/sysmoOCTSIM/include/component/pm.h
@@ -1,261 +1,261 @@
-/**
- * \file
- *
- * \brief Component description for PM
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_PM_COMPONENT_
-#define _SAME54_PM_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR PM */
-/* ========================================================================== */
-/** \addtogroup SAME54_PM Power Manager */
-/*@{*/
-
-#define PM_U2406
-#define REV_PM 0x100
-
-/* -------- PM_CTRLA : (PM Offset: 0x00) (R/W 8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t :2; /*!< bit: 0.. 1 Reserved */
- uint8_t IORET:1; /*!< bit: 2 I/O Retention */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PM_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_CTRLA_OFFSET 0x00 /**< \brief (PM_CTRLA offset) Control A */
-#define PM_CTRLA_RESETVALUE _U_(0x00) /**< \brief (PM_CTRLA reset_value) Control A */
-
-#define PM_CTRLA_IORET_Pos 2 /**< \brief (PM_CTRLA) I/O Retention */
-#define PM_CTRLA_IORET (_U_(0x1) << PM_CTRLA_IORET_Pos)
-#define PM_CTRLA_MASK _U_(0x04) /**< \brief (PM_CTRLA) MASK Register */
-
-/* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W 8) Sleep Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SLEEPMODE:3; /*!< bit: 0.. 2 Sleep Mode */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PM_SLEEPCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_SLEEPCFG_OFFSET 0x01 /**< \brief (PM_SLEEPCFG offset) Sleep Configuration */
-#define PM_SLEEPCFG_RESETVALUE _U_(0x02) /**< \brief (PM_SLEEPCFG reset_value) Sleep Configuration */
-
-#define PM_SLEEPCFG_SLEEPMODE_Pos 0 /**< \brief (PM_SLEEPCFG) Sleep Mode */
-#define PM_SLEEPCFG_SLEEPMODE_Msk (_U_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos)
-#define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos))
-#define PM_SLEEPCFG_SLEEPMODE_IDLE0_Val _U_(0x0) /**< \brief (PM_SLEEPCFG) CPU clock is OFF */
-#define PM_SLEEPCFG_SLEEPMODE_IDLE1_Val _U_(0x1) /**< \brief (PM_SLEEPCFG) AHB clock is OFF */
-#define PM_SLEEPCFG_SLEEPMODE_IDLE2_Val _U_(0x2) /**< \brief (PM_SLEEPCFG) APB clock are OFF */
-#define PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _U_(0x4) /**< \brief (PM_SLEEPCFG) All Clocks are OFF */
-#define PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val _U_(0x5) /**< \brief (PM_SLEEPCFG) Backup domain is ON as well as some PDRAMs */
-#define PM_SLEEPCFG_SLEEPMODE_BACKUP_Val _U_(0x6) /**< \brief (PM_SLEEPCFG) Only Backup domain is powered ON */
-#define PM_SLEEPCFG_SLEEPMODE_OFF_Val _U_(0x7) /**< \brief (PM_SLEEPCFG) All power domains are powered OFF */
-#define PM_SLEEPCFG_SLEEPMODE_IDLE0 (PM_SLEEPCFG_SLEEPMODE_IDLE0_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
-#define PM_SLEEPCFG_SLEEPMODE_IDLE1 (PM_SLEEPCFG_SLEEPMODE_IDLE1_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
-#define PM_SLEEPCFG_SLEEPMODE_IDLE2 (PM_SLEEPCFG_SLEEPMODE_IDLE2_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
-#define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
-#define PM_SLEEPCFG_SLEEPMODE_HIBERNATE (PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
-#define PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
-#define PM_SLEEPCFG_SLEEPMODE_OFF (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
-#define PM_SLEEPCFG_MASK _U_(0x07) /**< \brief (PM_SLEEPCFG) MASK Register */
-
-/* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PM_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_INTENCLR_OFFSET 0x04 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
-#define PM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define PM_INTENCLR_SLEEPRDY_Pos 0 /**< \brief (PM_INTENCLR) Sleep Mode Entry Ready Enable */
-#define PM_INTENCLR_SLEEPRDY (_U_(0x1) << PM_INTENCLR_SLEEPRDY_Pos)
-#define PM_INTENCLR_MASK _U_(0x01) /**< \brief (PM_INTENCLR) MASK Register */
-
-/* -------- PM_INTENSET : (PM Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PM_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_INTENSET_OFFSET 0x05 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
-#define PM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
-
-#define PM_INTENSET_SLEEPRDY_Pos 0 /**< \brief (PM_INTENSET) Sleep Mode Entry Ready Enable */
-#define PM_INTENSET_SLEEPRDY (_U_(0x1) << PM_INTENSET_SLEEPRDY_Pos)
-#define PM_INTENSET_MASK _U_(0x01) /**< \brief (PM_INTENSET) MASK Register */
-
-/* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready */
- __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PM_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_INTFLAG_OFFSET 0x06 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
-#define PM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define PM_INTFLAG_SLEEPRDY_Pos 0 /**< \brief (PM_INTFLAG) Sleep Mode Entry Ready */
-#define PM_INTFLAG_SLEEPRDY (_U_(0x1) << PM_INTFLAG_SLEEPRDY_Pos)
-#define PM_INTFLAG_MASK _U_(0x01) /**< \brief (PM_INTFLAG) MASK Register */
-
-/* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 8) Standby Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t RAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t FASTWKUP:2; /*!< bit: 4.. 5 Fast Wakeup */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PM_STDBYCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_STDBYCFG_OFFSET 0x08 /**< \brief (PM_STDBYCFG offset) Standby Configuration */
-#define PM_STDBYCFG_RESETVALUE _U_(0x00) /**< \brief (PM_STDBYCFG reset_value) Standby Configuration */
-
-#define PM_STDBYCFG_RAMCFG_Pos 0 /**< \brief (PM_STDBYCFG) Ram Configuration */
-#define PM_STDBYCFG_RAMCFG_Msk (_U_(0x3) << PM_STDBYCFG_RAMCFG_Pos)
-#define PM_STDBYCFG_RAMCFG(value) (PM_STDBYCFG_RAMCFG_Msk & ((value) << PM_STDBYCFG_RAMCFG_Pos))
-#define PM_STDBYCFG_RAMCFG_RET_Val _U_(0x0) /**< \brief (PM_STDBYCFG) All the RAMs are retained */
-#define PM_STDBYCFG_RAMCFG_PARTIAL_Val _U_(0x1) /**< \brief (PM_STDBYCFG) Only the first 32K bytes are retained */
-#define PM_STDBYCFG_RAMCFG_OFF_Val _U_(0x2) /**< \brief (PM_STDBYCFG) All the RAMs are OFF */
-#define PM_STDBYCFG_RAMCFG_RET (PM_STDBYCFG_RAMCFG_RET_Val << PM_STDBYCFG_RAMCFG_Pos)
-#define PM_STDBYCFG_RAMCFG_PARTIAL (PM_STDBYCFG_RAMCFG_PARTIAL_Val << PM_STDBYCFG_RAMCFG_Pos)
-#define PM_STDBYCFG_RAMCFG_OFF (PM_STDBYCFG_RAMCFG_OFF_Val << PM_STDBYCFG_RAMCFG_Pos)
-#define PM_STDBYCFG_FASTWKUP_Pos 4 /**< \brief (PM_STDBYCFG) Fast Wakeup */
-#define PM_STDBYCFG_FASTWKUP_Msk (_U_(0x3) << PM_STDBYCFG_FASTWKUP_Pos)
-#define PM_STDBYCFG_FASTWKUP(value) (PM_STDBYCFG_FASTWKUP_Msk & ((value) << PM_STDBYCFG_FASTWKUP_Pos))
-#define PM_STDBYCFG_MASK _U_(0x33) /**< \brief (PM_STDBYCFG) MASK Register */
-
-/* -------- PM_HIBCFG : (PM Offset: 0x09) (R/W 8) Hibernate Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t RAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */
- uint8_t BRAMCFG:2; /*!< bit: 2.. 3 Backup Ram Configuration */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PM_HIBCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_HIBCFG_OFFSET 0x09 /**< \brief (PM_HIBCFG offset) Hibernate Configuration */
-#define PM_HIBCFG_RESETVALUE _U_(0x00) /**< \brief (PM_HIBCFG reset_value) Hibernate Configuration */
-
-#define PM_HIBCFG_RAMCFG_Pos 0 /**< \brief (PM_HIBCFG) Ram Configuration */
-#define PM_HIBCFG_RAMCFG_Msk (_U_(0x3) << PM_HIBCFG_RAMCFG_Pos)
-#define PM_HIBCFG_RAMCFG(value) (PM_HIBCFG_RAMCFG_Msk & ((value) << PM_HIBCFG_RAMCFG_Pos))
-#define PM_HIBCFG_BRAMCFG_Pos 2 /**< \brief (PM_HIBCFG) Backup Ram Configuration */
-#define PM_HIBCFG_BRAMCFG_Msk (_U_(0x3) << PM_HIBCFG_BRAMCFG_Pos)
-#define PM_HIBCFG_BRAMCFG(value) (PM_HIBCFG_BRAMCFG_Msk & ((value) << PM_HIBCFG_BRAMCFG_Pos))
-#define PM_HIBCFG_MASK _U_(0x0F) /**< \brief (PM_HIBCFG) MASK Register */
-
-/* -------- PM_BKUPCFG : (PM Offset: 0x0A) (R/W 8) Backup Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t BRAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PM_BKUPCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_BKUPCFG_OFFSET 0x0A /**< \brief (PM_BKUPCFG offset) Backup Configuration */
-#define PM_BKUPCFG_RESETVALUE _U_(0x00) /**< \brief (PM_BKUPCFG reset_value) Backup Configuration */
-
-#define PM_BKUPCFG_BRAMCFG_Pos 0 /**< \brief (PM_BKUPCFG) Ram Configuration */
-#define PM_BKUPCFG_BRAMCFG_Msk (_U_(0x3) << PM_BKUPCFG_BRAMCFG_Pos)
-#define PM_BKUPCFG_BRAMCFG(value) (PM_BKUPCFG_BRAMCFG_Msk & ((value) << PM_BKUPCFG_BRAMCFG_Pos))
-#define PM_BKUPCFG_MASK _U_(0x03) /**< \brief (PM_BKUPCFG) MASK Register */
-
-/* -------- PM_PWSAKDLY : (PM Offset: 0x12) (R/W 8) Power Switch Acknowledge Delay -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DLYVAL:7; /*!< bit: 0.. 6 Delay Value */
- uint8_t IGNACK:1; /*!< bit: 7 Ignore Acknowledge */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PM_PWSAKDLY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_PWSAKDLY_OFFSET 0x12 /**< \brief (PM_PWSAKDLY offset) Power Switch Acknowledge Delay */
-#define PM_PWSAKDLY_RESETVALUE _U_(0x00) /**< \brief (PM_PWSAKDLY reset_value) Power Switch Acknowledge Delay */
-
-#define PM_PWSAKDLY_DLYVAL_Pos 0 /**< \brief (PM_PWSAKDLY) Delay Value */
-#define PM_PWSAKDLY_DLYVAL_Msk (_U_(0x7F) << PM_PWSAKDLY_DLYVAL_Pos)
-#define PM_PWSAKDLY_DLYVAL(value) (PM_PWSAKDLY_DLYVAL_Msk & ((value) << PM_PWSAKDLY_DLYVAL_Pos))
-#define PM_PWSAKDLY_IGNACK_Pos 7 /**< \brief (PM_PWSAKDLY) Ignore Acknowledge */
-#define PM_PWSAKDLY_IGNACK (_U_(0x1) << PM_PWSAKDLY_IGNACK_Pos)
-#define PM_PWSAKDLY_MASK _U_(0xFF) /**< \brief (PM_PWSAKDLY) MASK Register */
-
-/** \brief PM hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO PM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
- __IO PM_SLEEPCFG_Type SLEEPCFG; /**< \brief Offset: 0x01 (R/W 8) Sleep Configuration */
- RoReg8 Reserved1[0x2];
- __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
- __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
- __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
- RoReg8 Reserved2[0x1];
- __IO PM_STDBYCFG_Type STDBYCFG; /**< \brief Offset: 0x08 (R/W 8) Standby Configuration */
- __IO PM_HIBCFG_Type HIBCFG; /**< \brief Offset: 0x09 (R/W 8) Hibernate Configuration */
- __IO PM_BKUPCFG_Type BKUPCFG; /**< \brief Offset: 0x0A (R/W 8) Backup Configuration */
- RoReg8 Reserved3[0x7];
- __IO PM_PWSAKDLY_Type PWSAKDLY; /**< \brief Offset: 0x12 (R/W 8) Power Switch Acknowledge Delay */
-} Pm;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_PM_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for PM
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_PM_COMPONENT_
+#define _SAME54_PM_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PM */
+/* ========================================================================== */
+/** \addtogroup SAME54_PM Power Manager */
+/*@{*/
+
+#define PM_U2406
+#define REV_PM 0x100
+
+/* -------- PM_CTRLA : (PM Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t IORET:1; /*!< bit: 2 I/O Retention */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CTRLA_OFFSET 0x00 /**< \brief (PM_CTRLA offset) Control A */
+#define PM_CTRLA_RESETVALUE _U_(0x00) /**< \brief (PM_CTRLA reset_value) Control A */
+
+#define PM_CTRLA_IORET_Pos 2 /**< \brief (PM_CTRLA) I/O Retention */
+#define PM_CTRLA_IORET (_U_(0x1) << PM_CTRLA_IORET_Pos)
+#define PM_CTRLA_MASK _U_(0x04) /**< \brief (PM_CTRLA) MASK Register */
+
+/* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W 8) Sleep Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SLEEPMODE:3; /*!< bit: 0.. 2 Sleep Mode */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_SLEEPCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_SLEEPCFG_OFFSET 0x01 /**< \brief (PM_SLEEPCFG offset) Sleep Configuration */
+#define PM_SLEEPCFG_RESETVALUE _U_(0x02) /**< \brief (PM_SLEEPCFG reset_value) Sleep Configuration */
+
+#define PM_SLEEPCFG_SLEEPMODE_Pos 0 /**< \brief (PM_SLEEPCFG) Sleep Mode */
+#define PM_SLEEPCFG_SLEEPMODE_Msk (_U_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos))
+#define PM_SLEEPCFG_SLEEPMODE_IDLE0_Val _U_(0x0) /**< \brief (PM_SLEEPCFG) CPU clock is OFF */
+#define PM_SLEEPCFG_SLEEPMODE_IDLE1_Val _U_(0x1) /**< \brief (PM_SLEEPCFG) AHB clock is OFF */
+#define PM_SLEEPCFG_SLEEPMODE_IDLE2_Val _U_(0x2) /**< \brief (PM_SLEEPCFG) APB clock are OFF */
+#define PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _U_(0x4) /**< \brief (PM_SLEEPCFG) All Clocks are OFF */
+#define PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val _U_(0x5) /**< \brief (PM_SLEEPCFG) Backup domain is ON as well as some PDRAMs */
+#define PM_SLEEPCFG_SLEEPMODE_BACKUP_Val _U_(0x6) /**< \brief (PM_SLEEPCFG) Only Backup domain is powered ON */
+#define PM_SLEEPCFG_SLEEPMODE_OFF_Val _U_(0x7) /**< \brief (PM_SLEEPCFG) All power domains are powered OFF */
+#define PM_SLEEPCFG_SLEEPMODE_IDLE0 (PM_SLEEPCFG_SLEEPMODE_IDLE0_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_IDLE1 (PM_SLEEPCFG_SLEEPMODE_IDLE1_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_IDLE2 (PM_SLEEPCFG_SLEEPMODE_IDLE2_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_HIBERNATE (PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_OFF (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_MASK _U_(0x07) /**< \brief (PM_SLEEPCFG) MASK Register */
+
+/* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENCLR_OFFSET 0x04 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
+#define PM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define PM_INTENCLR_SLEEPRDY_Pos 0 /**< \brief (PM_INTENCLR) Sleep Mode Entry Ready Enable */
+#define PM_INTENCLR_SLEEPRDY (_U_(0x1) << PM_INTENCLR_SLEEPRDY_Pos)
+#define PM_INTENCLR_MASK _U_(0x01) /**< \brief (PM_INTENCLR) MASK Register */
+
+/* -------- PM_INTENSET : (PM Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENSET_OFFSET 0x05 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
+#define PM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
+
+#define PM_INTENSET_SLEEPRDY_Pos 0 /**< \brief (PM_INTENSET) Sleep Mode Entry Ready Enable */
+#define PM_INTENSET_SLEEPRDY (_U_(0x1) << PM_INTENSET_SLEEPRDY_Pos)
+#define PM_INTENSET_MASK _U_(0x01) /**< \brief (PM_INTENSET) MASK Register */
+
+/* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTFLAG_OFFSET 0x06 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
+#define PM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define PM_INTFLAG_SLEEPRDY_Pos 0 /**< \brief (PM_INTFLAG) Sleep Mode Entry Ready */
+#define PM_INTFLAG_SLEEPRDY (_U_(0x1) << PM_INTFLAG_SLEEPRDY_Pos)
+#define PM_INTFLAG_MASK _U_(0x01) /**< \brief (PM_INTFLAG) MASK Register */
+
+/* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 8) Standby Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t FASTWKUP:2; /*!< bit: 4.. 5 Fast Wakeup */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_STDBYCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_STDBYCFG_OFFSET 0x08 /**< \brief (PM_STDBYCFG offset) Standby Configuration */
+#define PM_STDBYCFG_RESETVALUE _U_(0x00) /**< \brief (PM_STDBYCFG reset_value) Standby Configuration */
+
+#define PM_STDBYCFG_RAMCFG_Pos 0 /**< \brief (PM_STDBYCFG) Ram Configuration */
+#define PM_STDBYCFG_RAMCFG_Msk (_U_(0x3) << PM_STDBYCFG_RAMCFG_Pos)
+#define PM_STDBYCFG_RAMCFG(value) (PM_STDBYCFG_RAMCFG_Msk & ((value) << PM_STDBYCFG_RAMCFG_Pos))
+#define PM_STDBYCFG_RAMCFG_RET_Val _U_(0x0) /**< \brief (PM_STDBYCFG) All the RAMs are retained */
+#define PM_STDBYCFG_RAMCFG_PARTIAL_Val _U_(0x1) /**< \brief (PM_STDBYCFG) Only the first 32K bytes are retained */
+#define PM_STDBYCFG_RAMCFG_OFF_Val _U_(0x2) /**< \brief (PM_STDBYCFG) All the RAMs are OFF */
+#define PM_STDBYCFG_RAMCFG_RET (PM_STDBYCFG_RAMCFG_RET_Val << PM_STDBYCFG_RAMCFG_Pos)
+#define PM_STDBYCFG_RAMCFG_PARTIAL (PM_STDBYCFG_RAMCFG_PARTIAL_Val << PM_STDBYCFG_RAMCFG_Pos)
+#define PM_STDBYCFG_RAMCFG_OFF (PM_STDBYCFG_RAMCFG_OFF_Val << PM_STDBYCFG_RAMCFG_Pos)
+#define PM_STDBYCFG_FASTWKUP_Pos 4 /**< \brief (PM_STDBYCFG) Fast Wakeup */
+#define PM_STDBYCFG_FASTWKUP_Msk (_U_(0x3) << PM_STDBYCFG_FASTWKUP_Pos)
+#define PM_STDBYCFG_FASTWKUP(value) (PM_STDBYCFG_FASTWKUP_Msk & ((value) << PM_STDBYCFG_FASTWKUP_Pos))
+#define PM_STDBYCFG_MASK _U_(0x33) /**< \brief (PM_STDBYCFG) MASK Register */
+
+/* -------- PM_HIBCFG : (PM Offset: 0x09) (R/W 8) Hibernate Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */
+ uint8_t BRAMCFG:2; /*!< bit: 2.. 3 Backup Ram Configuration */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_HIBCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_HIBCFG_OFFSET 0x09 /**< \brief (PM_HIBCFG offset) Hibernate Configuration */
+#define PM_HIBCFG_RESETVALUE _U_(0x00) /**< \brief (PM_HIBCFG reset_value) Hibernate Configuration */
+
+#define PM_HIBCFG_RAMCFG_Pos 0 /**< \brief (PM_HIBCFG) Ram Configuration */
+#define PM_HIBCFG_RAMCFG_Msk (_U_(0x3) << PM_HIBCFG_RAMCFG_Pos)
+#define PM_HIBCFG_RAMCFG(value) (PM_HIBCFG_RAMCFG_Msk & ((value) << PM_HIBCFG_RAMCFG_Pos))
+#define PM_HIBCFG_BRAMCFG_Pos 2 /**< \brief (PM_HIBCFG) Backup Ram Configuration */
+#define PM_HIBCFG_BRAMCFG_Msk (_U_(0x3) << PM_HIBCFG_BRAMCFG_Pos)
+#define PM_HIBCFG_BRAMCFG(value) (PM_HIBCFG_BRAMCFG_Msk & ((value) << PM_HIBCFG_BRAMCFG_Pos))
+#define PM_HIBCFG_MASK _U_(0x0F) /**< \brief (PM_HIBCFG) MASK Register */
+
+/* -------- PM_BKUPCFG : (PM Offset: 0x0A) (R/W 8) Backup Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t BRAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_BKUPCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_BKUPCFG_OFFSET 0x0A /**< \brief (PM_BKUPCFG offset) Backup Configuration */
+#define PM_BKUPCFG_RESETVALUE _U_(0x00) /**< \brief (PM_BKUPCFG reset_value) Backup Configuration */
+
+#define PM_BKUPCFG_BRAMCFG_Pos 0 /**< \brief (PM_BKUPCFG) Ram Configuration */
+#define PM_BKUPCFG_BRAMCFG_Msk (_U_(0x3) << PM_BKUPCFG_BRAMCFG_Pos)
+#define PM_BKUPCFG_BRAMCFG(value) (PM_BKUPCFG_BRAMCFG_Msk & ((value) << PM_BKUPCFG_BRAMCFG_Pos))
+#define PM_BKUPCFG_MASK _U_(0x03) /**< \brief (PM_BKUPCFG) MASK Register */
+
+/* -------- PM_PWSAKDLY : (PM Offset: 0x12) (R/W 8) Power Switch Acknowledge Delay -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DLYVAL:7; /*!< bit: 0.. 6 Delay Value */
+ uint8_t IGNACK:1; /*!< bit: 7 Ignore Acknowledge */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_PWSAKDLY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_PWSAKDLY_OFFSET 0x12 /**< \brief (PM_PWSAKDLY offset) Power Switch Acknowledge Delay */
+#define PM_PWSAKDLY_RESETVALUE _U_(0x00) /**< \brief (PM_PWSAKDLY reset_value) Power Switch Acknowledge Delay */
+
+#define PM_PWSAKDLY_DLYVAL_Pos 0 /**< \brief (PM_PWSAKDLY) Delay Value */
+#define PM_PWSAKDLY_DLYVAL_Msk (_U_(0x7F) << PM_PWSAKDLY_DLYVAL_Pos)
+#define PM_PWSAKDLY_DLYVAL(value) (PM_PWSAKDLY_DLYVAL_Msk & ((value) << PM_PWSAKDLY_DLYVAL_Pos))
+#define PM_PWSAKDLY_IGNACK_Pos 7 /**< \brief (PM_PWSAKDLY) Ignore Acknowledge */
+#define PM_PWSAKDLY_IGNACK (_U_(0x1) << PM_PWSAKDLY_IGNACK_Pos)
+#define PM_PWSAKDLY_MASK _U_(0xFF) /**< \brief (PM_PWSAKDLY) MASK Register */
+
+/** \brief PM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __IO PM_SLEEPCFG_Type SLEEPCFG; /**< \brief Offset: 0x01 (R/W 8) Sleep Configuration */
+ RoReg8 Reserved1[0x2];
+ __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
+ __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
+ __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved2[0x1];
+ __IO PM_STDBYCFG_Type STDBYCFG; /**< \brief Offset: 0x08 (R/W 8) Standby Configuration */
+ __IO PM_HIBCFG_Type HIBCFG; /**< \brief Offset: 0x09 (R/W 8) Hibernate Configuration */
+ __IO PM_BKUPCFG_Type BKUPCFG; /**< \brief Offset: 0x0A (R/W 8) Backup Configuration */
+ RoReg8 Reserved3[0x7];
+ __IO PM_PWSAKDLY_Type PWSAKDLY; /**< \brief Offset: 0x12 (R/W 8) Power Switch Acknowledge Delay */
+} Pm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_PM_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/port.h b/sysmoOCTSIM/include/component/port.h
index 233ca56..829353a 100644
--- a/sysmoOCTSIM/include/component/port.h
+++ b/sysmoOCTSIM/include/component/port.h
@@ -1,414 +1,414 @@
-/**
- * \file
- *
- * \brief Component description for PORT
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_PORT_COMPONENT_
-#define _SAME54_PORT_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR PORT */
-/* ========================================================================== */
-/** \addtogroup SAME54_PORT Port Module */
-/*@{*/
-
-#define PORT_U2210
-#define REV_PORT 0x220
-
-/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PORT_DIR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */
-#define PORT_DIR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIR reset_value) Data Direction */
-
-#define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */
-#define PORT_DIR_DIR_Msk (_U_(0xFFFFFFFF) << PORT_DIR_DIR_Pos)
-#define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
-#define PORT_DIR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIR) MASK Register */
-
-/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PORT_DIRCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
-#define PORT_DIRCLR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
-
-#define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
-#define PORT_DIRCLR_DIRCLR_Msk (_U_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos)
-#define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
-#define PORT_DIRCLR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRCLR) MASK Register */
-
-/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PORT_DIRSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */
-#define PORT_DIRSET_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
-
-#define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */
-#define PORT_DIRSET_DIRSET_Msk (_U_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos)
-#define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
-#define PORT_DIRSET_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRSET) MASK Register */
-
-/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PORT_DIRTGL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
-#define PORT_DIRTGL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
-
-#define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
-#define PORT_DIRTGL_DIRTGL_Msk (_U_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos)
-#define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
-#define PORT_DIRTGL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRTGL) MASK Register */
-
-/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t OUT:32; /*!< bit: 0..31 PORT Data Output Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PORT_OUT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */
-#define PORT_OUT_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUT reset_value) Data Output Value */
-
-#define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) PORT Data Output Value */
-#define PORT_OUT_OUT_Msk (_U_(0xFFFFFFFF) << PORT_OUT_OUT_Pos)
-#define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
-#define PORT_OUT_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUT) MASK Register */
-
-/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t OUTCLR:32; /*!< bit: 0..31 PORT Data Output Value Clear */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PORT_OUTCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
-#define PORT_OUTCLR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
-
-#define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) PORT Data Output Value Clear */
-#define PORT_OUTCLR_OUTCLR_Msk (_U_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos)
-#define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
-#define PORT_OUTCLR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTCLR) MASK Register */
-
-/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t OUTSET:32; /*!< bit: 0..31 PORT Data Output Value Set */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PORT_OUTSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */
-#define PORT_OUTSET_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
-
-#define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) PORT Data Output Value Set */
-#define PORT_OUTSET_OUTSET_Msk (_U_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos)
-#define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
-#define PORT_OUTSET_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTSET) MASK Register */
-
-/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t OUTTGL:32; /*!< bit: 0..31 PORT Data Output Value Toggle */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PORT_OUTTGL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
-#define PORT_OUTTGL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
-
-#define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) PORT Data Output Value Toggle */
-#define PORT_OUTTGL_OUTTGL_Msk (_U_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos)
-#define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
-#define PORT_OUTTGL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTTGL) MASK Register */
-
-/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t IN:32; /*!< bit: 0..31 PORT Data Input Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PORT_IN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */
-#define PORT_IN_RESETVALUE _U_(0x00000000) /**< \brief (PORT_IN reset_value) Data Input Value */
-
-#define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) PORT Data Input Value */
-#define PORT_IN_IN_Msk (_U_(0xFFFFFFFF) << PORT_IN_IN_Pos)
-#define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
-#define PORT_IN_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_IN) MASK Register */
-
-/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PORT_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */
-#define PORT_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_CTRL reset_value) Control */
-
-#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */
-#define PORT_CTRL_SAMPLING_Msk (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos)
-#define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
-#define PORT_CTRL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_CTRL) MASK Register */
-
-/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
- uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
- uint32_t INEN:1; /*!< bit: 17 Input Enable */
- uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
- uint32_t :3; /*!< bit: 19..21 Reserved */
- uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
- uint32_t :1; /*!< bit: 23 Reserved */
- uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
- uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
- uint32_t :1; /*!< bit: 29 Reserved */
- uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
- uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PORT_WRCONFIG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */
-#define PORT_WRCONFIG_RESETVALUE _U_(0x00000000) /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
-
-#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
-#define PORT_WRCONFIG_PINMASK_Msk (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos)
-#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
-#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
-#define PORT_WRCONFIG_PMUXEN (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos)
-#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */
-#define PORT_WRCONFIG_INEN (_U_(0x1) << PORT_WRCONFIG_INEN_Pos)
-#define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */
-#define PORT_WRCONFIG_PULLEN (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos)
-#define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
-#define PORT_WRCONFIG_DRVSTR (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos)
-#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
-#define PORT_WRCONFIG_PMUX_Msk (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos)
-#define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
-#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */
-#define PORT_WRCONFIG_WRPMUX (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos)
-#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */
-#define PORT_WRCONFIG_WRPINCFG (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos)
-#define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */
-#define PORT_WRCONFIG_HWSEL (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos)
-#define PORT_WRCONFIG_MASK _U_(0xDF47FFFF) /**< \brief (PORT_WRCONFIG) MASK Register */
-
-/* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) GROUP Event Input Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t PID0:5; /*!< bit: 0.. 4 PORT Event Pin Identifier 0 */
- uint32_t EVACT0:2; /*!< bit: 5.. 6 PORT Event Action 0 */
- uint32_t PORTEI0:1; /*!< bit: 7 PORT Event Input Enable 0 */
- uint32_t PID1:5; /*!< bit: 8..12 PORT Event Pin Identifier 1 */
- uint32_t EVACT1:2; /*!< bit: 13..14 PORT Event Action 1 */
- uint32_t PORTEI1:1; /*!< bit: 15 PORT Event Input Enable 1 */
- uint32_t PID2:5; /*!< bit: 16..20 PORT Event Pin Identifier 2 */
- uint32_t EVACT2:2; /*!< bit: 21..22 PORT Event Action 2 */
- uint32_t PORTEI2:1; /*!< bit: 23 PORT Event Input Enable 2 */
- uint32_t PID3:5; /*!< bit: 24..28 PORT Event Pin Identifier 3 */
- uint32_t EVACT3:2; /*!< bit: 29..30 PORT Event Action 3 */
- uint32_t PORTEI3:1; /*!< bit: 31 PORT Event Input Enable 3 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} PORT_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_EVCTRL_OFFSET 0x2C /**< \brief (PORT_EVCTRL offset) Event Input Control */
-#define PORT_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_EVCTRL reset_value) Event Input Control */
-
-#define PORT_EVCTRL_PID0_Pos 0 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 0 */
-#define PORT_EVCTRL_PID0_Msk (_U_(0x1F) << PORT_EVCTRL_PID0_Pos)
-#define PORT_EVCTRL_PID0(value) (PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos))
-#define PORT_EVCTRL_EVACT0_Pos 5 /**< \brief (PORT_EVCTRL) PORT Event Action 0 */
-#define PORT_EVCTRL_EVACT0_Msk (_U_(0x3) << PORT_EVCTRL_EVACT0_Pos)
-#define PORT_EVCTRL_EVACT0(value) (PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos))
-#define PORT_EVCTRL_EVACT0_OUT_Val _U_(0x0) /**< \brief (PORT_EVCTRL) Event output to pin */
-#define PORT_EVCTRL_EVACT0_SET_Val _U_(0x1) /**< \brief (PORT_EVCTRL) Set output register of pin on event */
-#define PORT_EVCTRL_EVACT0_CLR_Val _U_(0x2) /**< \brief (PORT_EVCTRL) Clear output register of pin on event */
-#define PORT_EVCTRL_EVACT0_TGL_Val _U_(0x3) /**< \brief (PORT_EVCTRL) Toggle output register of pin on event */
-#define PORT_EVCTRL_EVACT0_OUT (PORT_EVCTRL_EVACT0_OUT_Val << PORT_EVCTRL_EVACT0_Pos)
-#define PORT_EVCTRL_EVACT0_SET (PORT_EVCTRL_EVACT0_SET_Val << PORT_EVCTRL_EVACT0_Pos)
-#define PORT_EVCTRL_EVACT0_CLR (PORT_EVCTRL_EVACT0_CLR_Val << PORT_EVCTRL_EVACT0_Pos)
-#define PORT_EVCTRL_EVACT0_TGL (PORT_EVCTRL_EVACT0_TGL_Val << PORT_EVCTRL_EVACT0_Pos)
-#define PORT_EVCTRL_PORTEI0_Pos 7 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 0 */
-#define PORT_EVCTRL_PORTEI0 (_U_(0x1) << PORT_EVCTRL_PORTEI0_Pos)
-#define PORT_EVCTRL_PID1_Pos 8 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 1 */
-#define PORT_EVCTRL_PID1_Msk (_U_(0x1F) << PORT_EVCTRL_PID1_Pos)
-#define PORT_EVCTRL_PID1(value) (PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos))
-#define PORT_EVCTRL_EVACT1_Pos 13 /**< \brief (PORT_EVCTRL) PORT Event Action 1 */
-#define PORT_EVCTRL_EVACT1_Msk (_U_(0x3) << PORT_EVCTRL_EVACT1_Pos)
-#define PORT_EVCTRL_EVACT1(value) (PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos))
-#define PORT_EVCTRL_PORTEI1_Pos 15 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 1 */
-#define PORT_EVCTRL_PORTEI1 (_U_(0x1) << PORT_EVCTRL_PORTEI1_Pos)
-#define PORT_EVCTRL_PID2_Pos 16 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 2 */
-#define PORT_EVCTRL_PID2_Msk (_U_(0x1F) << PORT_EVCTRL_PID2_Pos)
-#define PORT_EVCTRL_PID2(value) (PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos))
-#define PORT_EVCTRL_EVACT2_Pos 21 /**< \brief (PORT_EVCTRL) PORT Event Action 2 */
-#define PORT_EVCTRL_EVACT2_Msk (_U_(0x3) << PORT_EVCTRL_EVACT2_Pos)
-#define PORT_EVCTRL_EVACT2(value) (PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos))
-#define PORT_EVCTRL_PORTEI2_Pos 23 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 2 */
-#define PORT_EVCTRL_PORTEI2 (_U_(0x1) << PORT_EVCTRL_PORTEI2_Pos)
-#define PORT_EVCTRL_PID3_Pos 24 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 3 */
-#define PORT_EVCTRL_PID3_Msk (_U_(0x1F) << PORT_EVCTRL_PID3_Pos)
-#define PORT_EVCTRL_PID3(value) (PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos))
-#define PORT_EVCTRL_EVACT3_Pos 29 /**< \brief (PORT_EVCTRL) PORT Event Action 3 */
-#define PORT_EVCTRL_EVACT3_Msk (_U_(0x3) << PORT_EVCTRL_EVACT3_Pos)
-#define PORT_EVCTRL_EVACT3(value) (PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos))
-#define PORT_EVCTRL_PORTEI3_Pos 31 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 3 */
-#define PORT_EVCTRL_PORTEI3 (_U_(0x1) << PORT_EVCTRL_PORTEI3_Pos)
-#define PORT_EVCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_EVCTRL) MASK Register */
-
-/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing for Even-Numbered Pin */
- uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing for Odd-Numbered Pin */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PORT_PMUX_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing */
-#define PORT_PMUX_RESETVALUE _U_(0x00) /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing */
-
-#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin */
-#define PORT_PMUX_PMUXE_Msk (_U_(0xF) << PORT_PMUX_PMUXE_Pos)
-#define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
-#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin */
-#define PORT_PMUX_PMUXO_Msk (_U_(0xF) << PORT_PMUX_PMUXO_Pos)
-#define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
-#define PORT_PMUX_MASK _U_(0xFF) /**< \brief (PORT_PMUX) MASK Register */
-
-/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
- uint8_t INEN:1; /*!< bit: 1 Input Enable */
- uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
- uint8_t :3; /*!< bit: 3.. 5 Reserved */
- uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} PORT_PINCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration */
-#define PORT_PINCFG_RESETVALUE _U_(0x00) /**< \brief (PORT_PINCFG reset_value) Pin Configuration */
-
-#define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
-#define PORT_PINCFG_PMUXEN (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos)
-#define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */
-#define PORT_PINCFG_INEN (_U_(0x1) << PORT_PINCFG_INEN_Pos)
-#define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */
-#define PORT_PINCFG_PULLEN (_U_(0x1) << PORT_PINCFG_PULLEN_Pos)
-#define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
-#define PORT_PINCFG_DRVSTR (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos)
-#define PORT_PINCFG_MASK _U_(0x47) /**< \brief (PORT_PINCFG) MASK Register */
-
-/** \brief PortGroup hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
- __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
- __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
- __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
- __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
- __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
- __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
- __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
- __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
- __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
- __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
- __IO PORT_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2C (R/W 32) Event Input Control */
- __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing */
- __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration */
- RoReg8 Reserved1[0x20];
-} PortGroup;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief PORT hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- PortGroup Group[4]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
-} Port;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_PORT_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for PORT
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_PORT_COMPONENT_
+#define _SAME54_PORT_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PORT */
+/* ========================================================================== */
+/** \addtogroup SAME54_PORT Port Module */
+/*@{*/
+
+#define PORT_U2210
+#define REV_PORT 0x220
+
+/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */
+#define PORT_DIR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIR reset_value) Data Direction */
+
+#define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */
+#define PORT_DIR_DIR_Msk (_U_(0xFFFFFFFF) << PORT_DIR_DIR_Pos)
+#define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
+#define PORT_DIR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIR) MASK Register */
+
+/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIRCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
+#define PORT_DIRCLR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
+
+#define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
+#define PORT_DIRCLR_DIRCLR_Msk (_U_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos)
+#define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
+#define PORT_DIRCLR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRCLR) MASK Register */
+
+/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIRSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */
+#define PORT_DIRSET_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
+
+#define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */
+#define PORT_DIRSET_DIRSET_Msk (_U_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos)
+#define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
+#define PORT_DIRSET_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRSET) MASK Register */
+
+/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIRTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
+#define PORT_DIRTGL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
+
+#define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
+#define PORT_DIRTGL_DIRTGL_Msk (_U_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos)
+#define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
+#define PORT_DIRTGL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRTGL) MASK Register */
+
+/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUT:32; /*!< bit: 0..31 PORT Data Output Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */
+#define PORT_OUT_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUT reset_value) Data Output Value */
+
+#define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) PORT Data Output Value */
+#define PORT_OUT_OUT_Msk (_U_(0xFFFFFFFF) << PORT_OUT_OUT_Pos)
+#define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
+#define PORT_OUT_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUT) MASK Register */
+
+/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUTCLR:32; /*!< bit: 0..31 PORT Data Output Value Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUTCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
+#define PORT_OUTCLR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
+
+#define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) PORT Data Output Value Clear */
+#define PORT_OUTCLR_OUTCLR_Msk (_U_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos)
+#define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
+#define PORT_OUTCLR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTCLR) MASK Register */
+
+/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUTSET:32; /*!< bit: 0..31 PORT Data Output Value Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUTSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */
+#define PORT_OUTSET_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
+
+#define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) PORT Data Output Value Set */
+#define PORT_OUTSET_OUTSET_Msk (_U_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos)
+#define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
+#define PORT_OUTSET_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTSET) MASK Register */
+
+/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUTTGL:32; /*!< bit: 0..31 PORT Data Output Value Toggle */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUTTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
+#define PORT_OUTTGL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
+
+#define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) PORT Data Output Value Toggle */
+#define PORT_OUTTGL_OUTTGL_Msk (_U_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos)
+#define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
+#define PORT_OUTTGL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTTGL) MASK Register */
+
+/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t IN:32; /*!< bit: 0..31 PORT Data Input Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_IN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */
+#define PORT_IN_RESETVALUE _U_(0x00000000) /**< \brief (PORT_IN reset_value) Data Input Value */
+
+#define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) PORT Data Input Value */
+#define PORT_IN_IN_Msk (_U_(0xFFFFFFFF) << PORT_IN_IN_Pos)
+#define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
+#define PORT_IN_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_IN) MASK Register */
+
+/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */
+#define PORT_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_CTRL reset_value) Control */
+
+#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */
+#define PORT_CTRL_SAMPLING_Msk (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos)
+#define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
+#define PORT_CTRL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_CTRL) MASK Register */
+
+/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
+ uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
+ uint32_t INEN:1; /*!< bit: 17 Input Enable */
+ uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
+ uint32_t :3; /*!< bit: 19..21 Reserved */
+ uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
+ uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
+ uint32_t :1; /*!< bit: 29 Reserved */
+ uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
+ uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_WRCONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */
+#define PORT_WRCONFIG_RESETVALUE _U_(0x00000000) /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
+
+#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
+#define PORT_WRCONFIG_PINMASK_Msk (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos)
+#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
+#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
+#define PORT_WRCONFIG_PMUXEN (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos)
+#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */
+#define PORT_WRCONFIG_INEN (_U_(0x1) << PORT_WRCONFIG_INEN_Pos)
+#define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */
+#define PORT_WRCONFIG_PULLEN (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos)
+#define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
+#define PORT_WRCONFIG_DRVSTR (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos)
+#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
+#define PORT_WRCONFIG_PMUX_Msk (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos)
+#define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
+#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */
+#define PORT_WRCONFIG_WRPMUX (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos)
+#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */
+#define PORT_WRCONFIG_WRPINCFG (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos)
+#define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */
+#define PORT_WRCONFIG_HWSEL (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos)
+#define PORT_WRCONFIG_MASK _U_(0xDF47FFFF) /**< \brief (PORT_WRCONFIG) MASK Register */
+
+/* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) GROUP Event Input Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PID0:5; /*!< bit: 0.. 4 PORT Event Pin Identifier 0 */
+ uint32_t EVACT0:2; /*!< bit: 5.. 6 PORT Event Action 0 */
+ uint32_t PORTEI0:1; /*!< bit: 7 PORT Event Input Enable 0 */
+ uint32_t PID1:5; /*!< bit: 8..12 PORT Event Pin Identifier 1 */
+ uint32_t EVACT1:2; /*!< bit: 13..14 PORT Event Action 1 */
+ uint32_t PORTEI1:1; /*!< bit: 15 PORT Event Input Enable 1 */
+ uint32_t PID2:5; /*!< bit: 16..20 PORT Event Pin Identifier 2 */
+ uint32_t EVACT2:2; /*!< bit: 21..22 PORT Event Action 2 */
+ uint32_t PORTEI2:1; /*!< bit: 23 PORT Event Input Enable 2 */
+ uint32_t PID3:5; /*!< bit: 24..28 PORT Event Pin Identifier 3 */
+ uint32_t EVACT3:2; /*!< bit: 29..30 PORT Event Action 3 */
+ uint32_t PORTEI3:1; /*!< bit: 31 PORT Event Input Enable 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_EVCTRL_OFFSET 0x2C /**< \brief (PORT_EVCTRL offset) Event Input Control */
+#define PORT_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_EVCTRL reset_value) Event Input Control */
+
+#define PORT_EVCTRL_PID0_Pos 0 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 0 */
+#define PORT_EVCTRL_PID0_Msk (_U_(0x1F) << PORT_EVCTRL_PID0_Pos)
+#define PORT_EVCTRL_PID0(value) (PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos))
+#define PORT_EVCTRL_EVACT0_Pos 5 /**< \brief (PORT_EVCTRL) PORT Event Action 0 */
+#define PORT_EVCTRL_EVACT0_Msk (_U_(0x3) << PORT_EVCTRL_EVACT0_Pos)
+#define PORT_EVCTRL_EVACT0(value) (PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos))
+#define PORT_EVCTRL_EVACT0_OUT_Val _U_(0x0) /**< \brief (PORT_EVCTRL) Event output to pin */
+#define PORT_EVCTRL_EVACT0_SET_Val _U_(0x1) /**< \brief (PORT_EVCTRL) Set output register of pin on event */
+#define PORT_EVCTRL_EVACT0_CLR_Val _U_(0x2) /**< \brief (PORT_EVCTRL) Clear output register of pin on event */
+#define PORT_EVCTRL_EVACT0_TGL_Val _U_(0x3) /**< \brief (PORT_EVCTRL) Toggle output register of pin on event */
+#define PORT_EVCTRL_EVACT0_OUT (PORT_EVCTRL_EVACT0_OUT_Val << PORT_EVCTRL_EVACT0_Pos)
+#define PORT_EVCTRL_EVACT0_SET (PORT_EVCTRL_EVACT0_SET_Val << PORT_EVCTRL_EVACT0_Pos)
+#define PORT_EVCTRL_EVACT0_CLR (PORT_EVCTRL_EVACT0_CLR_Val << PORT_EVCTRL_EVACT0_Pos)
+#define PORT_EVCTRL_EVACT0_TGL (PORT_EVCTRL_EVACT0_TGL_Val << PORT_EVCTRL_EVACT0_Pos)
+#define PORT_EVCTRL_PORTEI0_Pos 7 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 0 */
+#define PORT_EVCTRL_PORTEI0 (_U_(0x1) << PORT_EVCTRL_PORTEI0_Pos)
+#define PORT_EVCTRL_PID1_Pos 8 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 1 */
+#define PORT_EVCTRL_PID1_Msk (_U_(0x1F) << PORT_EVCTRL_PID1_Pos)
+#define PORT_EVCTRL_PID1(value) (PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos))
+#define PORT_EVCTRL_EVACT1_Pos 13 /**< \brief (PORT_EVCTRL) PORT Event Action 1 */
+#define PORT_EVCTRL_EVACT1_Msk (_U_(0x3) << PORT_EVCTRL_EVACT1_Pos)
+#define PORT_EVCTRL_EVACT1(value) (PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos))
+#define PORT_EVCTRL_PORTEI1_Pos 15 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 1 */
+#define PORT_EVCTRL_PORTEI1 (_U_(0x1) << PORT_EVCTRL_PORTEI1_Pos)
+#define PORT_EVCTRL_PID2_Pos 16 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 2 */
+#define PORT_EVCTRL_PID2_Msk (_U_(0x1F) << PORT_EVCTRL_PID2_Pos)
+#define PORT_EVCTRL_PID2(value) (PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos))
+#define PORT_EVCTRL_EVACT2_Pos 21 /**< \brief (PORT_EVCTRL) PORT Event Action 2 */
+#define PORT_EVCTRL_EVACT2_Msk (_U_(0x3) << PORT_EVCTRL_EVACT2_Pos)
+#define PORT_EVCTRL_EVACT2(value) (PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos))
+#define PORT_EVCTRL_PORTEI2_Pos 23 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 2 */
+#define PORT_EVCTRL_PORTEI2 (_U_(0x1) << PORT_EVCTRL_PORTEI2_Pos)
+#define PORT_EVCTRL_PID3_Pos 24 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 3 */
+#define PORT_EVCTRL_PID3_Msk (_U_(0x1F) << PORT_EVCTRL_PID3_Pos)
+#define PORT_EVCTRL_PID3(value) (PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos))
+#define PORT_EVCTRL_EVACT3_Pos 29 /**< \brief (PORT_EVCTRL) PORT Event Action 3 */
+#define PORT_EVCTRL_EVACT3_Msk (_U_(0x3) << PORT_EVCTRL_EVACT3_Pos)
+#define PORT_EVCTRL_EVACT3(value) (PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos))
+#define PORT_EVCTRL_PORTEI3_Pos 31 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 3 */
+#define PORT_EVCTRL_PORTEI3 (_U_(0x1) << PORT_EVCTRL_PORTEI3_Pos)
+#define PORT_EVCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_EVCTRL) MASK Register */
+
+/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing for Even-Numbered Pin */
+ uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing for Odd-Numbered Pin */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PORT_PMUX_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing */
+#define PORT_PMUX_RESETVALUE _U_(0x00) /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing */
+
+#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin */
+#define PORT_PMUX_PMUXE_Msk (_U_(0xF) << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
+#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin */
+#define PORT_PMUX_PMUXO_Msk (_U_(0xF) << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
+#define PORT_PMUX_MASK _U_(0xFF) /**< \brief (PORT_PMUX) MASK Register */
+
+/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
+ uint8_t INEN:1; /*!< bit: 1 Input Enable */
+ uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PORT_PINCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration */
+#define PORT_PINCFG_RESETVALUE _U_(0x00) /**< \brief (PORT_PINCFG reset_value) Pin Configuration */
+
+#define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
+#define PORT_PINCFG_PMUXEN (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos)
+#define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */
+#define PORT_PINCFG_INEN (_U_(0x1) << PORT_PINCFG_INEN_Pos)
+#define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */
+#define PORT_PINCFG_PULLEN (_U_(0x1) << PORT_PINCFG_PULLEN_Pos)
+#define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
+#define PORT_PINCFG_DRVSTR (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos)
+#define PORT_PINCFG_MASK _U_(0x47) /**< \brief (PORT_PINCFG) MASK Register */
+
+/** \brief PortGroup hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
+ __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
+ __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
+ __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
+ __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
+ __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
+ __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
+ __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
+ __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
+ __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
+ __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
+ __IO PORT_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2C (R/W 32) Event Input Control */
+ __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing */
+ __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration */
+ RoReg8 Reserved1[0x20];
+} PortGroup;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief PORT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ PortGroup Group[4]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
+} Port;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_PORT_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/qspi.h b/sysmoOCTSIM/include/component/qspi.h
index 2ee0af4..6fe4789 100644
--- a/sysmoOCTSIM/include/component/qspi.h
+++ b/sysmoOCTSIM/include/component/qspi.h
@@ -1,528 +1,528 @@
-/**
- * \file
- *
- * \brief Component description for QSPI
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_QSPI_COMPONENT_
-#define _SAME54_QSPI_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR QSPI */
-/* ========================================================================== */
-/** \addtogroup SAME54_QSPI Quad SPI interface */
-/*@{*/
-
-#define QSPI_U2008
-#define REV_QSPI 0x163
-
-/* -------- QSPI_CTRLA : (QSPI Offset: 0x00) (R/W 32) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t :22; /*!< bit: 2..23 Reserved */
- uint32_t LASTXFER:1; /*!< bit: 24 Last Transfer */
- uint32_t :7; /*!< bit: 25..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} QSPI_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_CTRLA_OFFSET 0x00 /**< \brief (QSPI_CTRLA offset) Control A */
-#define QSPI_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_CTRLA reset_value) Control A */
-
-#define QSPI_CTRLA_SWRST_Pos 0 /**< \brief (QSPI_CTRLA) Software Reset */
-#define QSPI_CTRLA_SWRST (_U_(0x1) << QSPI_CTRLA_SWRST_Pos)
-#define QSPI_CTRLA_ENABLE_Pos 1 /**< \brief (QSPI_CTRLA) Enable */
-#define QSPI_CTRLA_ENABLE (_U_(0x1) << QSPI_CTRLA_ENABLE_Pos)
-#define QSPI_CTRLA_LASTXFER_Pos 24 /**< \brief (QSPI_CTRLA) Last Transfer */
-#define QSPI_CTRLA_LASTXFER (_U_(0x1) << QSPI_CTRLA_LASTXFER_Pos)
-#define QSPI_CTRLA_MASK _U_(0x01000003) /**< \brief (QSPI_CTRLA) MASK Register */
-
-/* -------- QSPI_CTRLB : (QSPI Offset: 0x04) (R/W 32) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t MODE:1; /*!< bit: 0 Serial Memory Mode */
- uint32_t LOOPEN:1; /*!< bit: 1 Local Loopback Enable */
- uint32_t WDRBT:1; /*!< bit: 2 Wait Data Read Before Transfer */
- uint32_t SMEMREG:1; /*!< bit: 3 Serial Memory reg */
- uint32_t CSMODE:2; /*!< bit: 4.. 5 Chip Select Mode */
- uint32_t :2; /*!< bit: 6.. 7 Reserved */
- uint32_t DATALEN:4; /*!< bit: 8..11 Data Length */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t DLYBCT:8; /*!< bit: 16..23 Delay Between Consecutive Transfers */
- uint32_t DLYCS:8; /*!< bit: 24..31 Minimum Inactive CS Delay */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} QSPI_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_CTRLB_OFFSET 0x04 /**< \brief (QSPI_CTRLB offset) Control B */
-#define QSPI_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_CTRLB reset_value) Control B */
-
-#define QSPI_CTRLB_MODE_Pos 0 /**< \brief (QSPI_CTRLB) Serial Memory Mode */
-#define QSPI_CTRLB_MODE (_U_(0x1) << QSPI_CTRLB_MODE_Pos)
-#define QSPI_CTRLB_MODE_SPI_Val _U_(0x0) /**< \brief (QSPI_CTRLB) SPI operating mode */
-#define QSPI_CTRLB_MODE_MEMORY_Val _U_(0x1) /**< \brief (QSPI_CTRLB) Serial Memory operating mode */
-#define QSPI_CTRLB_MODE_SPI (QSPI_CTRLB_MODE_SPI_Val << QSPI_CTRLB_MODE_Pos)
-#define QSPI_CTRLB_MODE_MEMORY (QSPI_CTRLB_MODE_MEMORY_Val << QSPI_CTRLB_MODE_Pos)
-#define QSPI_CTRLB_LOOPEN_Pos 1 /**< \brief (QSPI_CTRLB) Local Loopback Enable */
-#define QSPI_CTRLB_LOOPEN (_U_(0x1) << QSPI_CTRLB_LOOPEN_Pos)
-#define QSPI_CTRLB_WDRBT_Pos 2 /**< \brief (QSPI_CTRLB) Wait Data Read Before Transfer */
-#define QSPI_CTRLB_WDRBT (_U_(0x1) << QSPI_CTRLB_WDRBT_Pos)
-#define QSPI_CTRLB_SMEMREG_Pos 3 /**< \brief (QSPI_CTRLB) Serial Memory reg */
-#define QSPI_CTRLB_SMEMREG (_U_(0x1) << QSPI_CTRLB_SMEMREG_Pos)
-#define QSPI_CTRLB_CSMODE_Pos 4 /**< \brief (QSPI_CTRLB) Chip Select Mode */
-#define QSPI_CTRLB_CSMODE_Msk (_U_(0x3) << QSPI_CTRLB_CSMODE_Pos)
-#define QSPI_CTRLB_CSMODE(value) (QSPI_CTRLB_CSMODE_Msk & ((value) << QSPI_CTRLB_CSMODE_Pos))
-#define QSPI_CTRLB_CSMODE_NORELOAD_Val _U_(0x0) /**< \brief (QSPI_CTRLB) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. */
-#define QSPI_CTRLB_CSMODE_LASTXFER_Val _U_(0x1) /**< \brief (QSPI_CTRLB) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. */
-#define QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val _U_(0x2) /**< \brief (QSPI_CTRLB) The chip select is deasserted systematically after each transfer. */
-#define QSPI_CTRLB_CSMODE_NORELOAD (QSPI_CTRLB_CSMODE_NORELOAD_Val << QSPI_CTRLB_CSMODE_Pos)
-#define QSPI_CTRLB_CSMODE_LASTXFER (QSPI_CTRLB_CSMODE_LASTXFER_Val << QSPI_CTRLB_CSMODE_Pos)
-#define QSPI_CTRLB_CSMODE_SYSTEMATICALLY (QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val << QSPI_CTRLB_CSMODE_Pos)
-#define QSPI_CTRLB_DATALEN_Pos 8 /**< \brief (QSPI_CTRLB) Data Length */
-#define QSPI_CTRLB_DATALEN_Msk (_U_(0xF) << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DATALEN(value) (QSPI_CTRLB_DATALEN_Msk & ((value) << QSPI_CTRLB_DATALEN_Pos))
-#define QSPI_CTRLB_DATALEN_8BITS_Val _U_(0x0) /**< \brief (QSPI_CTRLB) 8-bits transfer */
-#define QSPI_CTRLB_DATALEN_9BITS_Val _U_(0x1) /**< \brief (QSPI_CTRLB) 9 bits transfer */
-#define QSPI_CTRLB_DATALEN_10BITS_Val _U_(0x2) /**< \brief (QSPI_CTRLB) 10-bits transfer */
-#define QSPI_CTRLB_DATALEN_11BITS_Val _U_(0x3) /**< \brief (QSPI_CTRLB) 11-bits transfer */
-#define QSPI_CTRLB_DATALEN_12BITS_Val _U_(0x4) /**< \brief (QSPI_CTRLB) 12-bits transfer */
-#define QSPI_CTRLB_DATALEN_13BITS_Val _U_(0x5) /**< \brief (QSPI_CTRLB) 13-bits transfer */
-#define QSPI_CTRLB_DATALEN_14BITS_Val _U_(0x6) /**< \brief (QSPI_CTRLB) 14-bits transfer */
-#define QSPI_CTRLB_DATALEN_15BITS_Val _U_(0x7) /**< \brief (QSPI_CTRLB) 15-bits transfer */
-#define QSPI_CTRLB_DATALEN_16BITS_Val _U_(0x8) /**< \brief (QSPI_CTRLB) 16-bits transfer */
-#define QSPI_CTRLB_DATALEN_8BITS (QSPI_CTRLB_DATALEN_8BITS_Val << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DATALEN_9BITS (QSPI_CTRLB_DATALEN_9BITS_Val << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DATALEN_10BITS (QSPI_CTRLB_DATALEN_10BITS_Val << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DATALEN_11BITS (QSPI_CTRLB_DATALEN_11BITS_Val << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DATALEN_12BITS (QSPI_CTRLB_DATALEN_12BITS_Val << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DATALEN_13BITS (QSPI_CTRLB_DATALEN_13BITS_Val << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DATALEN_14BITS (QSPI_CTRLB_DATALEN_14BITS_Val << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DATALEN_15BITS (QSPI_CTRLB_DATALEN_15BITS_Val << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DATALEN_16BITS (QSPI_CTRLB_DATALEN_16BITS_Val << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DLYBCT_Pos 16 /**< \brief (QSPI_CTRLB) Delay Between Consecutive Transfers */
-#define QSPI_CTRLB_DLYBCT_Msk (_U_(0xFF) << QSPI_CTRLB_DLYBCT_Pos)
-#define QSPI_CTRLB_DLYBCT(value) (QSPI_CTRLB_DLYBCT_Msk & ((value) << QSPI_CTRLB_DLYBCT_Pos))
-#define QSPI_CTRLB_DLYCS_Pos 24 /**< \brief (QSPI_CTRLB) Minimum Inactive CS Delay */
-#define QSPI_CTRLB_DLYCS_Msk (_U_(0xFF) << QSPI_CTRLB_DLYCS_Pos)
-#define QSPI_CTRLB_DLYCS(value) (QSPI_CTRLB_DLYCS_Msk & ((value) << QSPI_CTRLB_DLYCS_Pos))
-#define QSPI_CTRLB_MASK _U_(0xFFFF0F3F) /**< \brief (QSPI_CTRLB) MASK Register */
-
-/* -------- QSPI_BAUD : (QSPI Offset: 0x08) (R/W 32) Baud Rate -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CPOL:1; /*!< bit: 0 Clock Polarity */
- uint32_t CPHA:1; /*!< bit: 1 Clock Phase */
- uint32_t :6; /*!< bit: 2.. 7 Reserved */
- uint32_t BAUD:8; /*!< bit: 8..15 Serial Clock Baud Rate */
- uint32_t DLYBS:8; /*!< bit: 16..23 Delay Before SCK */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} QSPI_BAUD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_BAUD_OFFSET 0x08 /**< \brief (QSPI_BAUD offset) Baud Rate */
-#define QSPI_BAUD_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_BAUD reset_value) Baud Rate */
-
-#define QSPI_BAUD_CPOL_Pos 0 /**< \brief (QSPI_BAUD) Clock Polarity */
-#define QSPI_BAUD_CPOL (_U_(0x1) << QSPI_BAUD_CPOL_Pos)
-#define QSPI_BAUD_CPHA_Pos 1 /**< \brief (QSPI_BAUD) Clock Phase */
-#define QSPI_BAUD_CPHA (_U_(0x1) << QSPI_BAUD_CPHA_Pos)
-#define QSPI_BAUD_BAUD_Pos 8 /**< \brief (QSPI_BAUD) Serial Clock Baud Rate */
-#define QSPI_BAUD_BAUD_Msk (_U_(0xFF) << QSPI_BAUD_BAUD_Pos)
-#define QSPI_BAUD_BAUD(value) (QSPI_BAUD_BAUD_Msk & ((value) << QSPI_BAUD_BAUD_Pos))
-#define QSPI_BAUD_DLYBS_Pos 16 /**< \brief (QSPI_BAUD) Delay Before SCK */
-#define QSPI_BAUD_DLYBS_Msk (_U_(0xFF) << QSPI_BAUD_DLYBS_Pos)
-#define QSPI_BAUD_DLYBS(value) (QSPI_BAUD_DLYBS_Msk & ((value) << QSPI_BAUD_DLYBS_Pos))
-#define QSPI_BAUD_MASK _U_(0x00FFFF03) /**< \brief (QSPI_BAUD) MASK Register */
-
-/* -------- QSPI_RXDATA : (QSPI Offset: 0x0C) (R/ 32) Receive Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DATA:16; /*!< bit: 0..15 Receive Data */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} QSPI_RXDATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_RXDATA_OFFSET 0x0C /**< \brief (QSPI_RXDATA offset) Receive Data */
-#define QSPI_RXDATA_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_RXDATA reset_value) Receive Data */
-
-#define QSPI_RXDATA_DATA_Pos 0 /**< \brief (QSPI_RXDATA) Receive Data */
-#define QSPI_RXDATA_DATA_Msk (_U_(0xFFFF) << QSPI_RXDATA_DATA_Pos)
-#define QSPI_RXDATA_DATA(value) (QSPI_RXDATA_DATA_Msk & ((value) << QSPI_RXDATA_DATA_Pos))
-#define QSPI_RXDATA_MASK _U_(0x0000FFFF) /**< \brief (QSPI_RXDATA) MASK Register */
-
-/* -------- QSPI_TXDATA : (QSPI Offset: 0x10) ( /W 32) Transmit Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DATA:16; /*!< bit: 0..15 Transmit Data */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} QSPI_TXDATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_TXDATA_OFFSET 0x10 /**< \brief (QSPI_TXDATA offset) Transmit Data */
-#define QSPI_TXDATA_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_TXDATA reset_value) Transmit Data */
-
-#define QSPI_TXDATA_DATA_Pos 0 /**< \brief (QSPI_TXDATA) Transmit Data */
-#define QSPI_TXDATA_DATA_Msk (_U_(0xFFFF) << QSPI_TXDATA_DATA_Pos)
-#define QSPI_TXDATA_DATA(value) (QSPI_TXDATA_DATA_Msk & ((value) << QSPI_TXDATA_DATA_Pos))
-#define QSPI_TXDATA_MASK _U_(0x0000FFFF) /**< \brief (QSPI_TXDATA) MASK Register */
-
-/* -------- QSPI_INTENCLR : (QSPI Offset: 0x14) (R/W 32) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full Interrupt Disable */
- uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty Interrupt Disable */
- uint32_t TXC:1; /*!< bit: 2 Transmission Complete Interrupt Disable */
- uint32_t ERROR:1; /*!< bit: 3 Overrun Error Interrupt Disable */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise Interrupt Disable */
- uint32_t :1; /*!< bit: 9 Reserved */
- uint32_t INSTREND:1; /*!< bit: 10 Instruction End Interrupt Disable */
- uint32_t :21; /*!< bit: 11..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} QSPI_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_INTENCLR_OFFSET 0x14 /**< \brief (QSPI_INTENCLR offset) Interrupt Enable Clear */
-#define QSPI_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define QSPI_INTENCLR_RXC_Pos 0 /**< \brief (QSPI_INTENCLR) Receive Data Register Full Interrupt Disable */
-#define QSPI_INTENCLR_RXC (_U_(0x1) << QSPI_INTENCLR_RXC_Pos)
-#define QSPI_INTENCLR_DRE_Pos 1 /**< \brief (QSPI_INTENCLR) Transmit Data Register Empty Interrupt Disable */
-#define QSPI_INTENCLR_DRE (_U_(0x1) << QSPI_INTENCLR_DRE_Pos)
-#define QSPI_INTENCLR_TXC_Pos 2 /**< \brief (QSPI_INTENCLR) Transmission Complete Interrupt Disable */
-#define QSPI_INTENCLR_TXC (_U_(0x1) << QSPI_INTENCLR_TXC_Pos)
-#define QSPI_INTENCLR_ERROR_Pos 3 /**< \brief (QSPI_INTENCLR) Overrun Error Interrupt Disable */
-#define QSPI_INTENCLR_ERROR (_U_(0x1) << QSPI_INTENCLR_ERROR_Pos)
-#define QSPI_INTENCLR_CSRISE_Pos 8 /**< \brief (QSPI_INTENCLR) Chip Select Rise Interrupt Disable */
-#define QSPI_INTENCLR_CSRISE (_U_(0x1) << QSPI_INTENCLR_CSRISE_Pos)
-#define QSPI_INTENCLR_INSTREND_Pos 10 /**< \brief (QSPI_INTENCLR) Instruction End Interrupt Disable */
-#define QSPI_INTENCLR_INSTREND (_U_(0x1) << QSPI_INTENCLR_INSTREND_Pos)
-#define QSPI_INTENCLR_MASK _U_(0x0000050F) /**< \brief (QSPI_INTENCLR) MASK Register */
-
-/* -------- QSPI_INTENSET : (QSPI Offset: 0x18) (R/W 32) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full Interrupt Enable */
- uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty Interrupt Enable */
- uint32_t TXC:1; /*!< bit: 2 Transmission Complete Interrupt Enable */
- uint32_t ERROR:1; /*!< bit: 3 Overrun Error Interrupt Enable */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise Interrupt Enable */
- uint32_t :1; /*!< bit: 9 Reserved */
- uint32_t INSTREND:1; /*!< bit: 10 Instruction End Interrupt Enable */
- uint32_t :21; /*!< bit: 11..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} QSPI_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_INTENSET_OFFSET 0x18 /**< \brief (QSPI_INTENSET offset) Interrupt Enable Set */
-#define QSPI_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INTENSET reset_value) Interrupt Enable Set */
-
-#define QSPI_INTENSET_RXC_Pos 0 /**< \brief (QSPI_INTENSET) Receive Data Register Full Interrupt Enable */
-#define QSPI_INTENSET_RXC (_U_(0x1) << QSPI_INTENSET_RXC_Pos)
-#define QSPI_INTENSET_DRE_Pos 1 /**< \brief (QSPI_INTENSET) Transmit Data Register Empty Interrupt Enable */
-#define QSPI_INTENSET_DRE (_U_(0x1) << QSPI_INTENSET_DRE_Pos)
-#define QSPI_INTENSET_TXC_Pos 2 /**< \brief (QSPI_INTENSET) Transmission Complete Interrupt Enable */
-#define QSPI_INTENSET_TXC (_U_(0x1) << QSPI_INTENSET_TXC_Pos)
-#define QSPI_INTENSET_ERROR_Pos 3 /**< \brief (QSPI_INTENSET) Overrun Error Interrupt Enable */
-#define QSPI_INTENSET_ERROR (_U_(0x1) << QSPI_INTENSET_ERROR_Pos)
-#define QSPI_INTENSET_CSRISE_Pos 8 /**< \brief (QSPI_INTENSET) Chip Select Rise Interrupt Enable */
-#define QSPI_INTENSET_CSRISE (_U_(0x1) << QSPI_INTENSET_CSRISE_Pos)
-#define QSPI_INTENSET_INSTREND_Pos 10 /**< \brief (QSPI_INTENSET) Instruction End Interrupt Enable */
-#define QSPI_INTENSET_INSTREND (_U_(0x1) << QSPI_INTENSET_INSTREND_Pos)
-#define QSPI_INTENSET_MASK _U_(0x0000050F) /**< \brief (QSPI_INTENSET) MASK Register */
-
-/* -------- QSPI_INTFLAG : (QSPI Offset: 0x1C) (R/W 32) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full */
- __I uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty */
- __I uint32_t TXC:1; /*!< bit: 2 Transmission Complete */
- __I uint32_t ERROR:1; /*!< bit: 3 Overrun Error */
- __I uint32_t :4; /*!< bit: 4.. 7 Reserved */
- __I uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise */
- __I uint32_t :1; /*!< bit: 9 Reserved */
- __I uint32_t INSTREND:1; /*!< bit: 10 Instruction End */
- __I uint32_t :21; /*!< bit: 11..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} QSPI_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_INTFLAG_OFFSET 0x1C /**< \brief (QSPI_INTFLAG offset) Interrupt Flag Status and Clear */
-#define QSPI_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define QSPI_INTFLAG_RXC_Pos 0 /**< \brief (QSPI_INTFLAG) Receive Data Register Full */
-#define QSPI_INTFLAG_RXC (_U_(0x1) << QSPI_INTFLAG_RXC_Pos)
-#define QSPI_INTFLAG_DRE_Pos 1 /**< \brief (QSPI_INTFLAG) Transmit Data Register Empty */
-#define QSPI_INTFLAG_DRE (_U_(0x1) << QSPI_INTFLAG_DRE_Pos)
-#define QSPI_INTFLAG_TXC_Pos 2 /**< \brief (QSPI_INTFLAG) Transmission Complete */
-#define QSPI_INTFLAG_TXC (_U_(0x1) << QSPI_INTFLAG_TXC_Pos)
-#define QSPI_INTFLAG_ERROR_Pos 3 /**< \brief (QSPI_INTFLAG) Overrun Error */
-#define QSPI_INTFLAG_ERROR (_U_(0x1) << QSPI_INTFLAG_ERROR_Pos)
-#define QSPI_INTFLAG_CSRISE_Pos 8 /**< \brief (QSPI_INTFLAG) Chip Select Rise */
-#define QSPI_INTFLAG_CSRISE (_U_(0x1) << QSPI_INTFLAG_CSRISE_Pos)
-#define QSPI_INTFLAG_INSTREND_Pos 10 /**< \brief (QSPI_INTFLAG) Instruction End */
-#define QSPI_INTFLAG_INSTREND (_U_(0x1) << QSPI_INTFLAG_INSTREND_Pos)
-#define QSPI_INTFLAG_MASK _U_(0x0000050F) /**< \brief (QSPI_INTFLAG) MASK Register */
-
-/* -------- QSPI_STATUS : (QSPI Offset: 0x20) (R/ 32) Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t :7; /*!< bit: 2.. 8 Reserved */
- uint32_t CSSTATUS:1; /*!< bit: 9 Chip Select */
- uint32_t :22; /*!< bit: 10..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} QSPI_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_STATUS_OFFSET 0x20 /**< \brief (QSPI_STATUS offset) Status Register */
-#define QSPI_STATUS_RESETVALUE _U_(0x00000200) /**< \brief (QSPI_STATUS reset_value) Status Register */
-
-#define QSPI_STATUS_ENABLE_Pos 1 /**< \brief (QSPI_STATUS) Enable */
-#define QSPI_STATUS_ENABLE (_U_(0x1) << QSPI_STATUS_ENABLE_Pos)
-#define QSPI_STATUS_CSSTATUS_Pos 9 /**< \brief (QSPI_STATUS) Chip Select */
-#define QSPI_STATUS_CSSTATUS (_U_(0x1) << QSPI_STATUS_CSSTATUS_Pos)
-#define QSPI_STATUS_MASK _U_(0x00000202) /**< \brief (QSPI_STATUS) MASK Register */
-
-/* -------- QSPI_INSTRADDR : (QSPI Offset: 0x30) (R/W 32) Instruction Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ADDR:32; /*!< bit: 0..31 Instruction Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} QSPI_INSTRADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_INSTRADDR_OFFSET 0x30 /**< \brief (QSPI_INSTRADDR offset) Instruction Address */
-#define QSPI_INSTRADDR_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INSTRADDR reset_value) Instruction Address */
-
-#define QSPI_INSTRADDR_ADDR_Pos 0 /**< \brief (QSPI_INSTRADDR) Instruction Address */
-#define QSPI_INSTRADDR_ADDR_Msk (_U_(0xFFFFFFFF) << QSPI_INSTRADDR_ADDR_Pos)
-#define QSPI_INSTRADDR_ADDR(value) (QSPI_INSTRADDR_ADDR_Msk & ((value) << QSPI_INSTRADDR_ADDR_Pos))
-#define QSPI_INSTRADDR_MASK _U_(0xFFFFFFFF) /**< \brief (QSPI_INSTRADDR) MASK Register */
-
-/* -------- QSPI_INSTRCTRL : (QSPI Offset: 0x34) (R/W 32) Instruction Code -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t INSTR:8; /*!< bit: 0.. 7 Instruction Code */
- uint32_t :8; /*!< bit: 8..15 Reserved */
- uint32_t OPTCODE:8; /*!< bit: 16..23 Option Code */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} QSPI_INSTRCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_INSTRCTRL_OFFSET 0x34 /**< \brief (QSPI_INSTRCTRL offset) Instruction Code */
-#define QSPI_INSTRCTRL_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INSTRCTRL reset_value) Instruction Code */
-
-#define QSPI_INSTRCTRL_INSTR_Pos 0 /**< \brief (QSPI_INSTRCTRL) Instruction Code */
-#define QSPI_INSTRCTRL_INSTR_Msk (_U_(0xFF) << QSPI_INSTRCTRL_INSTR_Pos)
-#define QSPI_INSTRCTRL_INSTR(value) (QSPI_INSTRCTRL_INSTR_Msk & ((value) << QSPI_INSTRCTRL_INSTR_Pos))
-#define QSPI_INSTRCTRL_OPTCODE_Pos 16 /**< \brief (QSPI_INSTRCTRL) Option Code */
-#define QSPI_INSTRCTRL_OPTCODE_Msk (_U_(0xFF) << QSPI_INSTRCTRL_OPTCODE_Pos)
-#define QSPI_INSTRCTRL_OPTCODE(value) (QSPI_INSTRCTRL_OPTCODE_Msk & ((value) << QSPI_INSTRCTRL_OPTCODE_Pos))
-#define QSPI_INSTRCTRL_MASK _U_(0x00FF00FF) /**< \brief (QSPI_INSTRCTRL) MASK Register */
-
-/* -------- QSPI_INSTRFRAME : (QSPI Offset: 0x38) (R/W 32) Instruction Frame -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t WIDTH:3; /*!< bit: 0.. 2 Instruction Code, Address, Option Code and Data Width */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t INSTREN:1; /*!< bit: 4 Instruction Enable */
- uint32_t ADDREN:1; /*!< bit: 5 Address Enable */
- uint32_t OPTCODEEN:1; /*!< bit: 6 Option Enable */
- uint32_t DATAEN:1; /*!< bit: 7 Data Enable */
- uint32_t OPTCODELEN:2; /*!< bit: 8.. 9 Option Code Length */
- uint32_t ADDRLEN:1; /*!< bit: 10 Address Length */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t TFRTYPE:2; /*!< bit: 12..13 Data Transfer Type */
- uint32_t CRMODE:1; /*!< bit: 14 Continuous Read Mode */
- uint32_t DDREN:1; /*!< bit: 15 Double Data Rate Enable */
- uint32_t DUMMYLEN:5; /*!< bit: 16..20 Dummy Cycles Length */
- uint32_t :11; /*!< bit: 21..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} QSPI_INSTRFRAME_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_INSTRFRAME_OFFSET 0x38 /**< \brief (QSPI_INSTRFRAME offset) Instruction Frame */
-#define QSPI_INSTRFRAME_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INSTRFRAME reset_value) Instruction Frame */
-
-#define QSPI_INSTRFRAME_WIDTH_Pos 0 /**< \brief (QSPI_INSTRFRAME) Instruction Code, Address, Option Code and Data Width */
-#define QSPI_INSTRFRAME_WIDTH_Msk (_U_(0x7) << QSPI_INSTRFRAME_WIDTH_Pos)
-#define QSPI_INSTRFRAME_WIDTH(value) (QSPI_INSTRFRAME_WIDTH_Msk & ((value) << QSPI_INSTRFRAME_WIDTH_Pos))
-#define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */
-#define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */
-#define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val _U_(0x2) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */
-#define QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val _U_(0x3) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */
-#define QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val _U_(0x4) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */
-#define QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val _U_(0x5) /**< \brief (QSPI_INSTRFRAME) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */
-#define QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val _U_(0x6) /**< \brief (QSPI_INSTRFRAME) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */
-#define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI (QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val << QSPI_INSTRFRAME_WIDTH_Pos)
-#define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT (QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
-#define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT (QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
-#define QSPI_INSTRFRAME_WIDTH_DUAL_IO (QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
-#define QSPI_INSTRFRAME_WIDTH_QUAD_IO (QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
-#define QSPI_INSTRFRAME_WIDTH_DUAL_CMD (QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
-#define QSPI_INSTRFRAME_WIDTH_QUAD_CMD (QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
-#define QSPI_INSTRFRAME_INSTREN_Pos 4 /**< \brief (QSPI_INSTRFRAME) Instruction Enable */
-#define QSPI_INSTRFRAME_INSTREN (_U_(0x1) << QSPI_INSTRFRAME_INSTREN_Pos)
-#define QSPI_INSTRFRAME_ADDREN_Pos 5 /**< \brief (QSPI_INSTRFRAME) Address Enable */
-#define QSPI_INSTRFRAME_ADDREN (_U_(0x1) << QSPI_INSTRFRAME_ADDREN_Pos)
-#define QSPI_INSTRFRAME_OPTCODEEN_Pos 6 /**< \brief (QSPI_INSTRFRAME) Option Enable */
-#define QSPI_INSTRFRAME_OPTCODEEN (_U_(0x1) << QSPI_INSTRFRAME_OPTCODEEN_Pos)
-#define QSPI_INSTRFRAME_DATAEN_Pos 7 /**< \brief (QSPI_INSTRFRAME) Data Enable */
-#define QSPI_INSTRFRAME_DATAEN (_U_(0x1) << QSPI_INSTRFRAME_DATAEN_Pos)
-#define QSPI_INSTRFRAME_OPTCODELEN_Pos 8 /**< \brief (QSPI_INSTRFRAME) Option Code Length */
-#define QSPI_INSTRFRAME_OPTCODELEN_Msk (_U_(0x3) << QSPI_INSTRFRAME_OPTCODELEN_Pos)
-#define QSPI_INSTRFRAME_OPTCODELEN(value) (QSPI_INSTRFRAME_OPTCODELEN_Msk & ((value) << QSPI_INSTRFRAME_OPTCODELEN_Pos))
-#define QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) 1-bit length option code */
-#define QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) 2-bits length option code */
-#define QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val _U_(0x2) /**< \brief (QSPI_INSTRFRAME) 4-bits length option code */
-#define QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val _U_(0x3) /**< \brief (QSPI_INSTRFRAME) 8-bits length option code */
-#define QSPI_INSTRFRAME_OPTCODELEN_1BIT (QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
-#define QSPI_INSTRFRAME_OPTCODELEN_2BITS (QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
-#define QSPI_INSTRFRAME_OPTCODELEN_4BITS (QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
-#define QSPI_INSTRFRAME_OPTCODELEN_8BITS (QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
-#define QSPI_INSTRFRAME_ADDRLEN_Pos 10 /**< \brief (QSPI_INSTRFRAME) Address Length */
-#define QSPI_INSTRFRAME_ADDRLEN (_U_(0x1) << QSPI_INSTRFRAME_ADDRLEN_Pos)
-#define QSPI_INSTRFRAME_ADDRLEN_24BITS_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) 24-bits address length */
-#define QSPI_INSTRFRAME_ADDRLEN_32BITS_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) 32-bits address length */
-#define QSPI_INSTRFRAME_ADDRLEN_24BITS (QSPI_INSTRFRAME_ADDRLEN_24BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
-#define QSPI_INSTRFRAME_ADDRLEN_32BITS (QSPI_INSTRFRAME_ADDRLEN_32BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
-#define QSPI_INSTRFRAME_TFRTYPE_Pos 12 /**< \brief (QSPI_INSTRFRAME) Data Transfer Type */
-#define QSPI_INSTRFRAME_TFRTYPE_Msk (_U_(0x3) << QSPI_INSTRFRAME_TFRTYPE_Pos)
-#define QSPI_INSTRFRAME_TFRTYPE(value) (QSPI_INSTRFRAME_TFRTYPE_Msk & ((value) << QSPI_INSTRFRAME_TFRTYPE_Pos))
-#define QSPI_INSTRFRAME_TFRTYPE_READ_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. */
-#define QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. */
-#define QSPI_INSTRFRAME_TFRTYPE_WRITE_Val _U_(0x2) /**< \brief (QSPI_INSTRFRAME) Write transfer into the serial memory.Scrambling is not performed. */
-#define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val _U_(0x3) /**< \brief (QSPI_INSTRFRAME) Write data transfer into the serial memory.If enabled, scrambling is performed. */
-#define QSPI_INSTRFRAME_TFRTYPE_READ (QSPI_INSTRFRAME_TFRTYPE_READ_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
-#define QSPI_INSTRFRAME_TFRTYPE_READMEMORY (QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
-#define QSPI_INSTRFRAME_TFRTYPE_WRITE (QSPI_INSTRFRAME_TFRTYPE_WRITE_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
-#define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY (QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
-#define QSPI_INSTRFRAME_CRMODE_Pos 14 /**< \brief (QSPI_INSTRFRAME) Continuous Read Mode */
-#define QSPI_INSTRFRAME_CRMODE (_U_(0x1) << QSPI_INSTRFRAME_CRMODE_Pos)
-#define QSPI_INSTRFRAME_DDREN_Pos 15 /**< \brief (QSPI_INSTRFRAME) Double Data Rate Enable */
-#define QSPI_INSTRFRAME_DDREN (_U_(0x1) << QSPI_INSTRFRAME_DDREN_Pos)
-#define QSPI_INSTRFRAME_DUMMYLEN_Pos 16 /**< \brief (QSPI_INSTRFRAME) Dummy Cycles Length */
-#define QSPI_INSTRFRAME_DUMMYLEN_Msk (_U_(0x1F) << QSPI_INSTRFRAME_DUMMYLEN_Pos)
-#define QSPI_INSTRFRAME_DUMMYLEN(value) (QSPI_INSTRFRAME_DUMMYLEN_Msk & ((value) << QSPI_INSTRFRAME_DUMMYLEN_Pos))
-#define QSPI_INSTRFRAME_MASK _U_(0x001FF7F7) /**< \brief (QSPI_INSTRFRAME) MASK Register */
-
-/* -------- QSPI_SCRAMBCTRL : (QSPI Offset: 0x40) (R/W 32) Scrambling Mode -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ENABLE:1; /*!< bit: 0 Scrambling/Unscrambling Enable */
- uint32_t RANDOMDIS:1; /*!< bit: 1 Scrambling/Unscrambling Random Value Disable */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} QSPI_SCRAMBCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_SCRAMBCTRL_OFFSET 0x40 /**< \brief (QSPI_SCRAMBCTRL offset) Scrambling Mode */
-#define QSPI_SCRAMBCTRL_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_SCRAMBCTRL reset_value) Scrambling Mode */
-
-#define QSPI_SCRAMBCTRL_ENABLE_Pos 0 /**< \brief (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Enable */
-#define QSPI_SCRAMBCTRL_ENABLE (_U_(0x1) << QSPI_SCRAMBCTRL_ENABLE_Pos)
-#define QSPI_SCRAMBCTRL_RANDOMDIS_Pos 1 /**< \brief (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Random Value Disable */
-#define QSPI_SCRAMBCTRL_RANDOMDIS (_U_(0x1) << QSPI_SCRAMBCTRL_RANDOMDIS_Pos)
-#define QSPI_SCRAMBCTRL_MASK _U_(0x00000003) /**< \brief (QSPI_SCRAMBCTRL) MASK Register */
-
-/* -------- QSPI_SCRAMBKEY : (QSPI Offset: 0x44) ( /W 32) Scrambling Key -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t KEY:32; /*!< bit: 0..31 Scrambling User Key */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} QSPI_SCRAMBKEY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_SCRAMBKEY_OFFSET 0x44 /**< \brief (QSPI_SCRAMBKEY offset) Scrambling Key */
-#define QSPI_SCRAMBKEY_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_SCRAMBKEY reset_value) Scrambling Key */
-
-#define QSPI_SCRAMBKEY_KEY_Pos 0 /**< \brief (QSPI_SCRAMBKEY) Scrambling User Key */
-#define QSPI_SCRAMBKEY_KEY_Msk (_U_(0xFFFFFFFF) << QSPI_SCRAMBKEY_KEY_Pos)
-#define QSPI_SCRAMBKEY_KEY(value) (QSPI_SCRAMBKEY_KEY_Msk & ((value) << QSPI_SCRAMBKEY_KEY_Pos))
-#define QSPI_SCRAMBKEY_MASK _U_(0xFFFFFFFF) /**< \brief (QSPI_SCRAMBKEY) MASK Register */
-
-/** \brief QSPI APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO QSPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
- __IO QSPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
- __IO QSPI_BAUD_Type BAUD; /**< \brief Offset: 0x08 (R/W 32) Baud Rate */
- __I QSPI_RXDATA_Type RXDATA; /**< \brief Offset: 0x0C (R/ 32) Receive Data */
- __O QSPI_TXDATA_Type TXDATA; /**< \brief Offset: 0x10 ( /W 32) Transmit Data */
- __IO QSPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Clear */
- __IO QSPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x18 (R/W 32) Interrupt Enable Set */
- __IO QSPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x1C (R/W 32) Interrupt Flag Status and Clear */
- __I QSPI_STATUS_Type STATUS; /**< \brief Offset: 0x20 (R/ 32) Status Register */
- RoReg8 Reserved1[0xC];
- __IO QSPI_INSTRADDR_Type INSTRADDR; /**< \brief Offset: 0x30 (R/W 32) Instruction Address */
- __IO QSPI_INSTRCTRL_Type INSTRCTRL; /**< \brief Offset: 0x34 (R/W 32) Instruction Code */
- __IO QSPI_INSTRFRAME_Type INSTRFRAME; /**< \brief Offset: 0x38 (R/W 32) Instruction Frame */
- RoReg8 Reserved2[0x4];
- __IO QSPI_SCRAMBCTRL_Type SCRAMBCTRL; /**< \brief Offset: 0x40 (R/W 32) Scrambling Mode */
- __O QSPI_SCRAMBKEY_Type SCRAMBKEY; /**< \brief Offset: 0x44 ( /W 32) Scrambling Key */
-} Qspi;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_QSPI_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for QSPI
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_QSPI_COMPONENT_
+#define _SAME54_QSPI_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR QSPI */
+/* ========================================================================== */
+/** \addtogroup SAME54_QSPI Quad SPI interface */
+/*@{*/
+
+#define QSPI_U2008
+#define REV_QSPI 0x163
+
+/* -------- QSPI_CTRLA : (QSPI Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t :22; /*!< bit: 2..23 Reserved */
+ uint32_t LASTXFER:1; /*!< bit: 24 Last Transfer */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_CTRLA_OFFSET 0x00 /**< \brief (QSPI_CTRLA offset) Control A */
+#define QSPI_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_CTRLA reset_value) Control A */
+
+#define QSPI_CTRLA_SWRST_Pos 0 /**< \brief (QSPI_CTRLA) Software Reset */
+#define QSPI_CTRLA_SWRST (_U_(0x1) << QSPI_CTRLA_SWRST_Pos)
+#define QSPI_CTRLA_ENABLE_Pos 1 /**< \brief (QSPI_CTRLA) Enable */
+#define QSPI_CTRLA_ENABLE (_U_(0x1) << QSPI_CTRLA_ENABLE_Pos)
+#define QSPI_CTRLA_LASTXFER_Pos 24 /**< \brief (QSPI_CTRLA) Last Transfer */
+#define QSPI_CTRLA_LASTXFER (_U_(0x1) << QSPI_CTRLA_LASTXFER_Pos)
+#define QSPI_CTRLA_MASK _U_(0x01000003) /**< \brief (QSPI_CTRLA) MASK Register */
+
+/* -------- QSPI_CTRLB : (QSPI Offset: 0x04) (R/W 32) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MODE:1; /*!< bit: 0 Serial Memory Mode */
+ uint32_t LOOPEN:1; /*!< bit: 1 Local Loopback Enable */
+ uint32_t WDRBT:1; /*!< bit: 2 Wait Data Read Before Transfer */
+ uint32_t SMEMREG:1; /*!< bit: 3 Serial Memory reg */
+ uint32_t CSMODE:2; /*!< bit: 4.. 5 Chip Select Mode */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t DATALEN:4; /*!< bit: 8..11 Data Length */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t DLYBCT:8; /*!< bit: 16..23 Delay Between Consecutive Transfers */
+ uint32_t DLYCS:8; /*!< bit: 24..31 Minimum Inactive CS Delay */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_CTRLB_OFFSET 0x04 /**< \brief (QSPI_CTRLB offset) Control B */
+#define QSPI_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_CTRLB reset_value) Control B */
+
+#define QSPI_CTRLB_MODE_Pos 0 /**< \brief (QSPI_CTRLB) Serial Memory Mode */
+#define QSPI_CTRLB_MODE (_U_(0x1) << QSPI_CTRLB_MODE_Pos)
+#define QSPI_CTRLB_MODE_SPI_Val _U_(0x0) /**< \brief (QSPI_CTRLB) SPI operating mode */
+#define QSPI_CTRLB_MODE_MEMORY_Val _U_(0x1) /**< \brief (QSPI_CTRLB) Serial Memory operating mode */
+#define QSPI_CTRLB_MODE_SPI (QSPI_CTRLB_MODE_SPI_Val << QSPI_CTRLB_MODE_Pos)
+#define QSPI_CTRLB_MODE_MEMORY (QSPI_CTRLB_MODE_MEMORY_Val << QSPI_CTRLB_MODE_Pos)
+#define QSPI_CTRLB_LOOPEN_Pos 1 /**< \brief (QSPI_CTRLB) Local Loopback Enable */
+#define QSPI_CTRLB_LOOPEN (_U_(0x1) << QSPI_CTRLB_LOOPEN_Pos)
+#define QSPI_CTRLB_WDRBT_Pos 2 /**< \brief (QSPI_CTRLB) Wait Data Read Before Transfer */
+#define QSPI_CTRLB_WDRBT (_U_(0x1) << QSPI_CTRLB_WDRBT_Pos)
+#define QSPI_CTRLB_SMEMREG_Pos 3 /**< \brief (QSPI_CTRLB) Serial Memory reg */
+#define QSPI_CTRLB_SMEMREG (_U_(0x1) << QSPI_CTRLB_SMEMREG_Pos)
+#define QSPI_CTRLB_CSMODE_Pos 4 /**< \brief (QSPI_CTRLB) Chip Select Mode */
+#define QSPI_CTRLB_CSMODE_Msk (_U_(0x3) << QSPI_CTRLB_CSMODE_Pos)
+#define QSPI_CTRLB_CSMODE(value) (QSPI_CTRLB_CSMODE_Msk & ((value) << QSPI_CTRLB_CSMODE_Pos))
+#define QSPI_CTRLB_CSMODE_NORELOAD_Val _U_(0x0) /**< \brief (QSPI_CTRLB) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. */
+#define QSPI_CTRLB_CSMODE_LASTXFER_Val _U_(0x1) /**< \brief (QSPI_CTRLB) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. */
+#define QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val _U_(0x2) /**< \brief (QSPI_CTRLB) The chip select is deasserted systematically after each transfer. */
+#define QSPI_CTRLB_CSMODE_NORELOAD (QSPI_CTRLB_CSMODE_NORELOAD_Val << QSPI_CTRLB_CSMODE_Pos)
+#define QSPI_CTRLB_CSMODE_LASTXFER (QSPI_CTRLB_CSMODE_LASTXFER_Val << QSPI_CTRLB_CSMODE_Pos)
+#define QSPI_CTRLB_CSMODE_SYSTEMATICALLY (QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val << QSPI_CTRLB_CSMODE_Pos)
+#define QSPI_CTRLB_DATALEN_Pos 8 /**< \brief (QSPI_CTRLB) Data Length */
+#define QSPI_CTRLB_DATALEN_Msk (_U_(0xF) << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN(value) (QSPI_CTRLB_DATALEN_Msk & ((value) << QSPI_CTRLB_DATALEN_Pos))
+#define QSPI_CTRLB_DATALEN_8BITS_Val _U_(0x0) /**< \brief (QSPI_CTRLB) 8-bits transfer */
+#define QSPI_CTRLB_DATALEN_9BITS_Val _U_(0x1) /**< \brief (QSPI_CTRLB) 9 bits transfer */
+#define QSPI_CTRLB_DATALEN_10BITS_Val _U_(0x2) /**< \brief (QSPI_CTRLB) 10-bits transfer */
+#define QSPI_CTRLB_DATALEN_11BITS_Val _U_(0x3) /**< \brief (QSPI_CTRLB) 11-bits transfer */
+#define QSPI_CTRLB_DATALEN_12BITS_Val _U_(0x4) /**< \brief (QSPI_CTRLB) 12-bits transfer */
+#define QSPI_CTRLB_DATALEN_13BITS_Val _U_(0x5) /**< \brief (QSPI_CTRLB) 13-bits transfer */
+#define QSPI_CTRLB_DATALEN_14BITS_Val _U_(0x6) /**< \brief (QSPI_CTRLB) 14-bits transfer */
+#define QSPI_CTRLB_DATALEN_15BITS_Val _U_(0x7) /**< \brief (QSPI_CTRLB) 15-bits transfer */
+#define QSPI_CTRLB_DATALEN_16BITS_Val _U_(0x8) /**< \brief (QSPI_CTRLB) 16-bits transfer */
+#define QSPI_CTRLB_DATALEN_8BITS (QSPI_CTRLB_DATALEN_8BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_9BITS (QSPI_CTRLB_DATALEN_9BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_10BITS (QSPI_CTRLB_DATALEN_10BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_11BITS (QSPI_CTRLB_DATALEN_11BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_12BITS (QSPI_CTRLB_DATALEN_12BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_13BITS (QSPI_CTRLB_DATALEN_13BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_14BITS (QSPI_CTRLB_DATALEN_14BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_15BITS (QSPI_CTRLB_DATALEN_15BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_16BITS (QSPI_CTRLB_DATALEN_16BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DLYBCT_Pos 16 /**< \brief (QSPI_CTRLB) Delay Between Consecutive Transfers */
+#define QSPI_CTRLB_DLYBCT_Msk (_U_(0xFF) << QSPI_CTRLB_DLYBCT_Pos)
+#define QSPI_CTRLB_DLYBCT(value) (QSPI_CTRLB_DLYBCT_Msk & ((value) << QSPI_CTRLB_DLYBCT_Pos))
+#define QSPI_CTRLB_DLYCS_Pos 24 /**< \brief (QSPI_CTRLB) Minimum Inactive CS Delay */
+#define QSPI_CTRLB_DLYCS_Msk (_U_(0xFF) << QSPI_CTRLB_DLYCS_Pos)
+#define QSPI_CTRLB_DLYCS(value) (QSPI_CTRLB_DLYCS_Msk & ((value) << QSPI_CTRLB_DLYCS_Pos))
+#define QSPI_CTRLB_MASK _U_(0xFFFF0F3F) /**< \brief (QSPI_CTRLB) MASK Register */
+
+/* -------- QSPI_BAUD : (QSPI Offset: 0x08) (R/W 32) Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CPOL:1; /*!< bit: 0 Clock Polarity */
+ uint32_t CPHA:1; /*!< bit: 1 Clock Phase */
+ uint32_t :6; /*!< bit: 2.. 7 Reserved */
+ uint32_t BAUD:8; /*!< bit: 8..15 Serial Clock Baud Rate */
+ uint32_t DLYBS:8; /*!< bit: 16..23 Delay Before SCK */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_BAUD_OFFSET 0x08 /**< \brief (QSPI_BAUD offset) Baud Rate */
+#define QSPI_BAUD_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_BAUD reset_value) Baud Rate */
+
+#define QSPI_BAUD_CPOL_Pos 0 /**< \brief (QSPI_BAUD) Clock Polarity */
+#define QSPI_BAUD_CPOL (_U_(0x1) << QSPI_BAUD_CPOL_Pos)
+#define QSPI_BAUD_CPHA_Pos 1 /**< \brief (QSPI_BAUD) Clock Phase */
+#define QSPI_BAUD_CPHA (_U_(0x1) << QSPI_BAUD_CPHA_Pos)
+#define QSPI_BAUD_BAUD_Pos 8 /**< \brief (QSPI_BAUD) Serial Clock Baud Rate */
+#define QSPI_BAUD_BAUD_Msk (_U_(0xFF) << QSPI_BAUD_BAUD_Pos)
+#define QSPI_BAUD_BAUD(value) (QSPI_BAUD_BAUD_Msk & ((value) << QSPI_BAUD_BAUD_Pos))
+#define QSPI_BAUD_DLYBS_Pos 16 /**< \brief (QSPI_BAUD) Delay Before SCK */
+#define QSPI_BAUD_DLYBS_Msk (_U_(0xFF) << QSPI_BAUD_DLYBS_Pos)
+#define QSPI_BAUD_DLYBS(value) (QSPI_BAUD_DLYBS_Msk & ((value) << QSPI_BAUD_DLYBS_Pos))
+#define QSPI_BAUD_MASK _U_(0x00FFFF03) /**< \brief (QSPI_BAUD) MASK Register */
+
+/* -------- QSPI_RXDATA : (QSPI Offset: 0x0C) (R/ 32) Receive Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:16; /*!< bit: 0..15 Receive Data */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_RXDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_RXDATA_OFFSET 0x0C /**< \brief (QSPI_RXDATA offset) Receive Data */
+#define QSPI_RXDATA_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_RXDATA reset_value) Receive Data */
+
+#define QSPI_RXDATA_DATA_Pos 0 /**< \brief (QSPI_RXDATA) Receive Data */
+#define QSPI_RXDATA_DATA_Msk (_U_(0xFFFF) << QSPI_RXDATA_DATA_Pos)
+#define QSPI_RXDATA_DATA(value) (QSPI_RXDATA_DATA_Msk & ((value) << QSPI_RXDATA_DATA_Pos))
+#define QSPI_RXDATA_MASK _U_(0x0000FFFF) /**< \brief (QSPI_RXDATA) MASK Register */
+
+/* -------- QSPI_TXDATA : (QSPI Offset: 0x10) ( /W 32) Transmit Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:16; /*!< bit: 0..15 Transmit Data */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_TXDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_TXDATA_OFFSET 0x10 /**< \brief (QSPI_TXDATA offset) Transmit Data */
+#define QSPI_TXDATA_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_TXDATA reset_value) Transmit Data */
+
+#define QSPI_TXDATA_DATA_Pos 0 /**< \brief (QSPI_TXDATA) Transmit Data */
+#define QSPI_TXDATA_DATA_Msk (_U_(0xFFFF) << QSPI_TXDATA_DATA_Pos)
+#define QSPI_TXDATA_DATA(value) (QSPI_TXDATA_DATA_Msk & ((value) << QSPI_TXDATA_DATA_Pos))
+#define QSPI_TXDATA_MASK _U_(0x0000FFFF) /**< \brief (QSPI_TXDATA) MASK Register */
+
+/* -------- QSPI_INTENCLR : (QSPI Offset: 0x14) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full Interrupt Disable */
+ uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty Interrupt Disable */
+ uint32_t TXC:1; /*!< bit: 2 Transmission Complete Interrupt Disable */
+ uint32_t ERROR:1; /*!< bit: 3 Overrun Error Interrupt Disable */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise Interrupt Disable */
+ uint32_t :1; /*!< bit: 9 Reserved */
+ uint32_t INSTREND:1; /*!< bit: 10 Instruction End Interrupt Disable */
+ uint32_t :21; /*!< bit: 11..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_INTENCLR_OFFSET 0x14 /**< \brief (QSPI_INTENCLR offset) Interrupt Enable Clear */
+#define QSPI_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define QSPI_INTENCLR_RXC_Pos 0 /**< \brief (QSPI_INTENCLR) Receive Data Register Full Interrupt Disable */
+#define QSPI_INTENCLR_RXC (_U_(0x1) << QSPI_INTENCLR_RXC_Pos)
+#define QSPI_INTENCLR_DRE_Pos 1 /**< \brief (QSPI_INTENCLR) Transmit Data Register Empty Interrupt Disable */
+#define QSPI_INTENCLR_DRE (_U_(0x1) << QSPI_INTENCLR_DRE_Pos)
+#define QSPI_INTENCLR_TXC_Pos 2 /**< \brief (QSPI_INTENCLR) Transmission Complete Interrupt Disable */
+#define QSPI_INTENCLR_TXC (_U_(0x1) << QSPI_INTENCLR_TXC_Pos)
+#define QSPI_INTENCLR_ERROR_Pos 3 /**< \brief (QSPI_INTENCLR) Overrun Error Interrupt Disable */
+#define QSPI_INTENCLR_ERROR (_U_(0x1) << QSPI_INTENCLR_ERROR_Pos)
+#define QSPI_INTENCLR_CSRISE_Pos 8 /**< \brief (QSPI_INTENCLR) Chip Select Rise Interrupt Disable */
+#define QSPI_INTENCLR_CSRISE (_U_(0x1) << QSPI_INTENCLR_CSRISE_Pos)
+#define QSPI_INTENCLR_INSTREND_Pos 10 /**< \brief (QSPI_INTENCLR) Instruction End Interrupt Disable */
+#define QSPI_INTENCLR_INSTREND (_U_(0x1) << QSPI_INTENCLR_INSTREND_Pos)
+#define QSPI_INTENCLR_MASK _U_(0x0000050F) /**< \brief (QSPI_INTENCLR) MASK Register */
+
+/* -------- QSPI_INTENSET : (QSPI Offset: 0x18) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full Interrupt Enable */
+ uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty Interrupt Enable */
+ uint32_t TXC:1; /*!< bit: 2 Transmission Complete Interrupt Enable */
+ uint32_t ERROR:1; /*!< bit: 3 Overrun Error Interrupt Enable */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise Interrupt Enable */
+ uint32_t :1; /*!< bit: 9 Reserved */
+ uint32_t INSTREND:1; /*!< bit: 10 Instruction End Interrupt Enable */
+ uint32_t :21; /*!< bit: 11..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_INTENSET_OFFSET 0x18 /**< \brief (QSPI_INTENSET offset) Interrupt Enable Set */
+#define QSPI_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INTENSET reset_value) Interrupt Enable Set */
+
+#define QSPI_INTENSET_RXC_Pos 0 /**< \brief (QSPI_INTENSET) Receive Data Register Full Interrupt Enable */
+#define QSPI_INTENSET_RXC (_U_(0x1) << QSPI_INTENSET_RXC_Pos)
+#define QSPI_INTENSET_DRE_Pos 1 /**< \brief (QSPI_INTENSET) Transmit Data Register Empty Interrupt Enable */
+#define QSPI_INTENSET_DRE (_U_(0x1) << QSPI_INTENSET_DRE_Pos)
+#define QSPI_INTENSET_TXC_Pos 2 /**< \brief (QSPI_INTENSET) Transmission Complete Interrupt Enable */
+#define QSPI_INTENSET_TXC (_U_(0x1) << QSPI_INTENSET_TXC_Pos)
+#define QSPI_INTENSET_ERROR_Pos 3 /**< \brief (QSPI_INTENSET) Overrun Error Interrupt Enable */
+#define QSPI_INTENSET_ERROR (_U_(0x1) << QSPI_INTENSET_ERROR_Pos)
+#define QSPI_INTENSET_CSRISE_Pos 8 /**< \brief (QSPI_INTENSET) Chip Select Rise Interrupt Enable */
+#define QSPI_INTENSET_CSRISE (_U_(0x1) << QSPI_INTENSET_CSRISE_Pos)
+#define QSPI_INTENSET_INSTREND_Pos 10 /**< \brief (QSPI_INTENSET) Instruction End Interrupt Enable */
+#define QSPI_INTENSET_INSTREND (_U_(0x1) << QSPI_INTENSET_INSTREND_Pos)
+#define QSPI_INTENSET_MASK _U_(0x0000050F) /**< \brief (QSPI_INTENSET) MASK Register */
+
+/* -------- QSPI_INTFLAG : (QSPI Offset: 0x1C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full */
+ __I uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty */
+ __I uint32_t TXC:1; /*!< bit: 2 Transmission Complete */
+ __I uint32_t ERROR:1; /*!< bit: 3 Overrun Error */
+ __I uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ __I uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise */
+ __I uint32_t :1; /*!< bit: 9 Reserved */
+ __I uint32_t INSTREND:1; /*!< bit: 10 Instruction End */
+ __I uint32_t :21; /*!< bit: 11..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_INTFLAG_OFFSET 0x1C /**< \brief (QSPI_INTFLAG offset) Interrupt Flag Status and Clear */
+#define QSPI_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define QSPI_INTFLAG_RXC_Pos 0 /**< \brief (QSPI_INTFLAG) Receive Data Register Full */
+#define QSPI_INTFLAG_RXC (_U_(0x1) << QSPI_INTFLAG_RXC_Pos)
+#define QSPI_INTFLAG_DRE_Pos 1 /**< \brief (QSPI_INTFLAG) Transmit Data Register Empty */
+#define QSPI_INTFLAG_DRE (_U_(0x1) << QSPI_INTFLAG_DRE_Pos)
+#define QSPI_INTFLAG_TXC_Pos 2 /**< \brief (QSPI_INTFLAG) Transmission Complete */
+#define QSPI_INTFLAG_TXC (_U_(0x1) << QSPI_INTFLAG_TXC_Pos)
+#define QSPI_INTFLAG_ERROR_Pos 3 /**< \brief (QSPI_INTFLAG) Overrun Error */
+#define QSPI_INTFLAG_ERROR (_U_(0x1) << QSPI_INTFLAG_ERROR_Pos)
+#define QSPI_INTFLAG_CSRISE_Pos 8 /**< \brief (QSPI_INTFLAG) Chip Select Rise */
+#define QSPI_INTFLAG_CSRISE (_U_(0x1) << QSPI_INTFLAG_CSRISE_Pos)
+#define QSPI_INTFLAG_INSTREND_Pos 10 /**< \brief (QSPI_INTFLAG) Instruction End */
+#define QSPI_INTFLAG_INSTREND (_U_(0x1) << QSPI_INTFLAG_INSTREND_Pos)
+#define QSPI_INTFLAG_MASK _U_(0x0000050F) /**< \brief (QSPI_INTFLAG) MASK Register */
+
+/* -------- QSPI_STATUS : (QSPI Offset: 0x20) (R/ 32) Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t :7; /*!< bit: 2.. 8 Reserved */
+ uint32_t CSSTATUS:1; /*!< bit: 9 Chip Select */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_STATUS_OFFSET 0x20 /**< \brief (QSPI_STATUS offset) Status Register */
+#define QSPI_STATUS_RESETVALUE _U_(0x00000200) /**< \brief (QSPI_STATUS reset_value) Status Register */
+
+#define QSPI_STATUS_ENABLE_Pos 1 /**< \brief (QSPI_STATUS) Enable */
+#define QSPI_STATUS_ENABLE (_U_(0x1) << QSPI_STATUS_ENABLE_Pos)
+#define QSPI_STATUS_CSSTATUS_Pos 9 /**< \brief (QSPI_STATUS) Chip Select */
+#define QSPI_STATUS_CSSTATUS (_U_(0x1) << QSPI_STATUS_CSSTATUS_Pos)
+#define QSPI_STATUS_MASK _U_(0x00000202) /**< \brief (QSPI_STATUS) MASK Register */
+
+/* -------- QSPI_INSTRADDR : (QSPI Offset: 0x30) (R/W 32) Instruction Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Instruction Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_INSTRADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_INSTRADDR_OFFSET 0x30 /**< \brief (QSPI_INSTRADDR offset) Instruction Address */
+#define QSPI_INSTRADDR_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INSTRADDR reset_value) Instruction Address */
+
+#define QSPI_INSTRADDR_ADDR_Pos 0 /**< \brief (QSPI_INSTRADDR) Instruction Address */
+#define QSPI_INSTRADDR_ADDR_Msk (_U_(0xFFFFFFFF) << QSPI_INSTRADDR_ADDR_Pos)
+#define QSPI_INSTRADDR_ADDR(value) (QSPI_INSTRADDR_ADDR_Msk & ((value) << QSPI_INSTRADDR_ADDR_Pos))
+#define QSPI_INSTRADDR_MASK _U_(0xFFFFFFFF) /**< \brief (QSPI_INSTRADDR) MASK Register */
+
+/* -------- QSPI_INSTRCTRL : (QSPI Offset: 0x34) (R/W 32) Instruction Code -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t INSTR:8; /*!< bit: 0.. 7 Instruction Code */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t OPTCODE:8; /*!< bit: 16..23 Option Code */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_INSTRCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_INSTRCTRL_OFFSET 0x34 /**< \brief (QSPI_INSTRCTRL offset) Instruction Code */
+#define QSPI_INSTRCTRL_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INSTRCTRL reset_value) Instruction Code */
+
+#define QSPI_INSTRCTRL_INSTR_Pos 0 /**< \brief (QSPI_INSTRCTRL) Instruction Code */
+#define QSPI_INSTRCTRL_INSTR_Msk (_U_(0xFF) << QSPI_INSTRCTRL_INSTR_Pos)
+#define QSPI_INSTRCTRL_INSTR(value) (QSPI_INSTRCTRL_INSTR_Msk & ((value) << QSPI_INSTRCTRL_INSTR_Pos))
+#define QSPI_INSTRCTRL_OPTCODE_Pos 16 /**< \brief (QSPI_INSTRCTRL) Option Code */
+#define QSPI_INSTRCTRL_OPTCODE_Msk (_U_(0xFF) << QSPI_INSTRCTRL_OPTCODE_Pos)
+#define QSPI_INSTRCTRL_OPTCODE(value) (QSPI_INSTRCTRL_OPTCODE_Msk & ((value) << QSPI_INSTRCTRL_OPTCODE_Pos))
+#define QSPI_INSTRCTRL_MASK _U_(0x00FF00FF) /**< \brief (QSPI_INSTRCTRL) MASK Register */
+
+/* -------- QSPI_INSTRFRAME : (QSPI Offset: 0x38) (R/W 32) Instruction Frame -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WIDTH:3; /*!< bit: 0.. 2 Instruction Code, Address, Option Code and Data Width */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t INSTREN:1; /*!< bit: 4 Instruction Enable */
+ uint32_t ADDREN:1; /*!< bit: 5 Address Enable */
+ uint32_t OPTCODEEN:1; /*!< bit: 6 Option Enable */
+ uint32_t DATAEN:1; /*!< bit: 7 Data Enable */
+ uint32_t OPTCODELEN:2; /*!< bit: 8.. 9 Option Code Length */
+ uint32_t ADDRLEN:1; /*!< bit: 10 Address Length */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t TFRTYPE:2; /*!< bit: 12..13 Data Transfer Type */
+ uint32_t CRMODE:1; /*!< bit: 14 Continuous Read Mode */
+ uint32_t DDREN:1; /*!< bit: 15 Double Data Rate Enable */
+ uint32_t DUMMYLEN:5; /*!< bit: 16..20 Dummy Cycles Length */
+ uint32_t :11; /*!< bit: 21..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_INSTRFRAME_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_INSTRFRAME_OFFSET 0x38 /**< \brief (QSPI_INSTRFRAME offset) Instruction Frame */
+#define QSPI_INSTRFRAME_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INSTRFRAME reset_value) Instruction Frame */
+
+#define QSPI_INSTRFRAME_WIDTH_Pos 0 /**< \brief (QSPI_INSTRFRAME) Instruction Code, Address, Option Code and Data Width */
+#define QSPI_INSTRFRAME_WIDTH_Msk (_U_(0x7) << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH(value) (QSPI_INSTRFRAME_WIDTH_Msk & ((value) << QSPI_INSTRFRAME_WIDTH_Pos))
+#define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */
+#define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */
+#define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val _U_(0x2) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */
+#define QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val _U_(0x3) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */
+#define QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val _U_(0x4) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */
+#define QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val _U_(0x5) /**< \brief (QSPI_INSTRFRAME) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */
+#define QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val _U_(0x6) /**< \brief (QSPI_INSTRFRAME) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */
+#define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI (QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT (QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT (QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH_DUAL_IO (QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH_QUAD_IO (QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH_DUAL_CMD (QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH_QUAD_CMD (QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_INSTREN_Pos 4 /**< \brief (QSPI_INSTRFRAME) Instruction Enable */
+#define QSPI_INSTRFRAME_INSTREN (_U_(0x1) << QSPI_INSTRFRAME_INSTREN_Pos)
+#define QSPI_INSTRFRAME_ADDREN_Pos 5 /**< \brief (QSPI_INSTRFRAME) Address Enable */
+#define QSPI_INSTRFRAME_ADDREN (_U_(0x1) << QSPI_INSTRFRAME_ADDREN_Pos)
+#define QSPI_INSTRFRAME_OPTCODEEN_Pos 6 /**< \brief (QSPI_INSTRFRAME) Option Enable */
+#define QSPI_INSTRFRAME_OPTCODEEN (_U_(0x1) << QSPI_INSTRFRAME_OPTCODEEN_Pos)
+#define QSPI_INSTRFRAME_DATAEN_Pos 7 /**< \brief (QSPI_INSTRFRAME) Data Enable */
+#define QSPI_INSTRFRAME_DATAEN (_U_(0x1) << QSPI_INSTRFRAME_DATAEN_Pos)
+#define QSPI_INSTRFRAME_OPTCODELEN_Pos 8 /**< \brief (QSPI_INSTRFRAME) Option Code Length */
+#define QSPI_INSTRFRAME_OPTCODELEN_Msk (_U_(0x3) << QSPI_INSTRFRAME_OPTCODELEN_Pos)
+#define QSPI_INSTRFRAME_OPTCODELEN(value) (QSPI_INSTRFRAME_OPTCODELEN_Msk & ((value) << QSPI_INSTRFRAME_OPTCODELEN_Pos))
+#define QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) 1-bit length option code */
+#define QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) 2-bits length option code */
+#define QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val _U_(0x2) /**< \brief (QSPI_INSTRFRAME) 4-bits length option code */
+#define QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val _U_(0x3) /**< \brief (QSPI_INSTRFRAME) 8-bits length option code */
+#define QSPI_INSTRFRAME_OPTCODELEN_1BIT (QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
+#define QSPI_INSTRFRAME_OPTCODELEN_2BITS (QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
+#define QSPI_INSTRFRAME_OPTCODELEN_4BITS (QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
+#define QSPI_INSTRFRAME_OPTCODELEN_8BITS (QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
+#define QSPI_INSTRFRAME_ADDRLEN_Pos 10 /**< \brief (QSPI_INSTRFRAME) Address Length */
+#define QSPI_INSTRFRAME_ADDRLEN (_U_(0x1) << QSPI_INSTRFRAME_ADDRLEN_Pos)
+#define QSPI_INSTRFRAME_ADDRLEN_24BITS_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) 24-bits address length */
+#define QSPI_INSTRFRAME_ADDRLEN_32BITS_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) 32-bits address length */
+#define QSPI_INSTRFRAME_ADDRLEN_24BITS (QSPI_INSTRFRAME_ADDRLEN_24BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
+#define QSPI_INSTRFRAME_ADDRLEN_32BITS (QSPI_INSTRFRAME_ADDRLEN_32BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
+#define QSPI_INSTRFRAME_TFRTYPE_Pos 12 /**< \brief (QSPI_INSTRFRAME) Data Transfer Type */
+#define QSPI_INSTRFRAME_TFRTYPE_Msk (_U_(0x3) << QSPI_INSTRFRAME_TFRTYPE_Pos)
+#define QSPI_INSTRFRAME_TFRTYPE(value) (QSPI_INSTRFRAME_TFRTYPE_Msk & ((value) << QSPI_INSTRFRAME_TFRTYPE_Pos))
+#define QSPI_INSTRFRAME_TFRTYPE_READ_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. */
+#define QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. */
+#define QSPI_INSTRFRAME_TFRTYPE_WRITE_Val _U_(0x2) /**< \brief (QSPI_INSTRFRAME) Write transfer into the serial memory.Scrambling is not performed. */
+#define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val _U_(0x3) /**< \brief (QSPI_INSTRFRAME) Write data transfer into the serial memory.If enabled, scrambling is performed. */
+#define QSPI_INSTRFRAME_TFRTYPE_READ (QSPI_INSTRFRAME_TFRTYPE_READ_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
+#define QSPI_INSTRFRAME_TFRTYPE_READMEMORY (QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
+#define QSPI_INSTRFRAME_TFRTYPE_WRITE (QSPI_INSTRFRAME_TFRTYPE_WRITE_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
+#define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY (QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
+#define QSPI_INSTRFRAME_CRMODE_Pos 14 /**< \brief (QSPI_INSTRFRAME) Continuous Read Mode */
+#define QSPI_INSTRFRAME_CRMODE (_U_(0x1) << QSPI_INSTRFRAME_CRMODE_Pos)
+#define QSPI_INSTRFRAME_DDREN_Pos 15 /**< \brief (QSPI_INSTRFRAME) Double Data Rate Enable */
+#define QSPI_INSTRFRAME_DDREN (_U_(0x1) << QSPI_INSTRFRAME_DDREN_Pos)
+#define QSPI_INSTRFRAME_DUMMYLEN_Pos 16 /**< \brief (QSPI_INSTRFRAME) Dummy Cycles Length */
+#define QSPI_INSTRFRAME_DUMMYLEN_Msk (_U_(0x1F) << QSPI_INSTRFRAME_DUMMYLEN_Pos)
+#define QSPI_INSTRFRAME_DUMMYLEN(value) (QSPI_INSTRFRAME_DUMMYLEN_Msk & ((value) << QSPI_INSTRFRAME_DUMMYLEN_Pos))
+#define QSPI_INSTRFRAME_MASK _U_(0x001FF7F7) /**< \brief (QSPI_INSTRFRAME) MASK Register */
+
+/* -------- QSPI_SCRAMBCTRL : (QSPI Offset: 0x40) (R/W 32) Scrambling Mode -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ENABLE:1; /*!< bit: 0 Scrambling/Unscrambling Enable */
+ uint32_t RANDOMDIS:1; /*!< bit: 1 Scrambling/Unscrambling Random Value Disable */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_SCRAMBCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_SCRAMBCTRL_OFFSET 0x40 /**< \brief (QSPI_SCRAMBCTRL offset) Scrambling Mode */
+#define QSPI_SCRAMBCTRL_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_SCRAMBCTRL reset_value) Scrambling Mode */
+
+#define QSPI_SCRAMBCTRL_ENABLE_Pos 0 /**< \brief (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Enable */
+#define QSPI_SCRAMBCTRL_ENABLE (_U_(0x1) << QSPI_SCRAMBCTRL_ENABLE_Pos)
+#define QSPI_SCRAMBCTRL_RANDOMDIS_Pos 1 /**< \brief (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Random Value Disable */
+#define QSPI_SCRAMBCTRL_RANDOMDIS (_U_(0x1) << QSPI_SCRAMBCTRL_RANDOMDIS_Pos)
+#define QSPI_SCRAMBCTRL_MASK _U_(0x00000003) /**< \brief (QSPI_SCRAMBCTRL) MASK Register */
+
+/* -------- QSPI_SCRAMBKEY : (QSPI Offset: 0x44) ( /W 32) Scrambling Key -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t KEY:32; /*!< bit: 0..31 Scrambling User Key */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_SCRAMBKEY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_SCRAMBKEY_OFFSET 0x44 /**< \brief (QSPI_SCRAMBKEY offset) Scrambling Key */
+#define QSPI_SCRAMBKEY_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_SCRAMBKEY reset_value) Scrambling Key */
+
+#define QSPI_SCRAMBKEY_KEY_Pos 0 /**< \brief (QSPI_SCRAMBKEY) Scrambling User Key */
+#define QSPI_SCRAMBKEY_KEY_Msk (_U_(0xFFFFFFFF) << QSPI_SCRAMBKEY_KEY_Pos)
+#define QSPI_SCRAMBKEY_KEY(value) (QSPI_SCRAMBKEY_KEY_Msk & ((value) << QSPI_SCRAMBKEY_KEY_Pos))
+#define QSPI_SCRAMBKEY_MASK _U_(0xFFFFFFFF) /**< \brief (QSPI_SCRAMBKEY) MASK Register */
+
+/** \brief QSPI APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO QSPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO QSPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
+ __IO QSPI_BAUD_Type BAUD; /**< \brief Offset: 0x08 (R/W 32) Baud Rate */
+ __I QSPI_RXDATA_Type RXDATA; /**< \brief Offset: 0x0C (R/ 32) Receive Data */
+ __O QSPI_TXDATA_Type TXDATA; /**< \brief Offset: 0x10 ( /W 32) Transmit Data */
+ __IO QSPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Clear */
+ __IO QSPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x18 (R/W 32) Interrupt Enable Set */
+ __IO QSPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x1C (R/W 32) Interrupt Flag Status and Clear */
+ __I QSPI_STATUS_Type STATUS; /**< \brief Offset: 0x20 (R/ 32) Status Register */
+ RoReg8 Reserved1[0xC];
+ __IO QSPI_INSTRADDR_Type INSTRADDR; /**< \brief Offset: 0x30 (R/W 32) Instruction Address */
+ __IO QSPI_INSTRCTRL_Type INSTRCTRL; /**< \brief Offset: 0x34 (R/W 32) Instruction Code */
+ __IO QSPI_INSTRFRAME_Type INSTRFRAME; /**< \brief Offset: 0x38 (R/W 32) Instruction Frame */
+ RoReg8 Reserved2[0x4];
+ __IO QSPI_SCRAMBCTRL_Type SCRAMBCTRL; /**< \brief Offset: 0x40 (R/W 32) Scrambling Mode */
+ __O QSPI_SCRAMBKEY_Type SCRAMBKEY; /**< \brief Offset: 0x44 ( /W 32) Scrambling Key */
+} Qspi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_QSPI_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/ramecc.h b/sysmoOCTSIM/include/component/ramecc.h
index 0f8acea..40def66 100644
--- a/sysmoOCTSIM/include/component/ramecc.h
+++ b/sysmoOCTSIM/include/component/ramecc.h
@@ -1,178 +1,178 @@
-/**
- * \file
- *
- * \brief Component description for RAMECC
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_RAMECC_COMPONENT_
-#define _SAME54_RAMECC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR RAMECC */
-/* ========================================================================== */
-/** \addtogroup SAME54_RAMECC RAM ECC */
-/*@{*/
-
-#define RAMECC_U2268
-#define REV_RAMECC 0x100
-
-/* -------- RAMECC_INTENCLR : (RAMECC Offset: 0x0) (R/W 8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt Enable Clear */
- uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt Enable Clear */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} RAMECC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RAMECC_INTENCLR_OFFSET 0x0 /**< \brief (RAMECC_INTENCLR offset) Interrupt Enable Clear */
-#define RAMECC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define RAMECC_INTENCLR_SINGLEE_Pos 0 /**< \brief (RAMECC_INTENCLR) Single Bit ECC Error Interrupt Enable Clear */
-#define RAMECC_INTENCLR_SINGLEE (_U_(0x1) << RAMECC_INTENCLR_SINGLEE_Pos)
-#define RAMECC_INTENCLR_DUALE_Pos 1 /**< \brief (RAMECC_INTENCLR) Dual Bit ECC Error Interrupt Enable Clear */
-#define RAMECC_INTENCLR_DUALE (_U_(0x1) << RAMECC_INTENCLR_DUALE_Pos)
-#define RAMECC_INTENCLR_MASK _U_(0x03) /**< \brief (RAMECC_INTENCLR) MASK Register */
-
-/* -------- RAMECC_INTENSET : (RAMECC Offset: 0x1) (R/W 8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt Enable Set */
- uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt Enable Set */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} RAMECC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RAMECC_INTENSET_OFFSET 0x1 /**< \brief (RAMECC_INTENSET offset) Interrupt Enable Set */
-#define RAMECC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTENSET reset_value) Interrupt Enable Set */
-
-#define RAMECC_INTENSET_SINGLEE_Pos 0 /**< \brief (RAMECC_INTENSET) Single Bit ECC Error Interrupt Enable Set */
-#define RAMECC_INTENSET_SINGLEE (_U_(0x1) << RAMECC_INTENSET_SINGLEE_Pos)
-#define RAMECC_INTENSET_DUALE_Pos 1 /**< \brief (RAMECC_INTENSET) Dual Bit ECC Error Interrupt Enable Set */
-#define RAMECC_INTENSET_DUALE (_U_(0x1) << RAMECC_INTENSET_DUALE_Pos)
-#define RAMECC_INTENSET_MASK _U_(0x03) /**< \brief (RAMECC_INTENSET) MASK Register */
-
-/* -------- RAMECC_INTFLAG : (RAMECC Offset: 0x2) (R/W 8) Interrupt Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt */
- __I uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt */
- __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} RAMECC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RAMECC_INTFLAG_OFFSET 0x2 /**< \brief (RAMECC_INTFLAG offset) Interrupt Flag */
-#define RAMECC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTFLAG reset_value) Interrupt Flag */
-
-#define RAMECC_INTFLAG_SINGLEE_Pos 0 /**< \brief (RAMECC_INTFLAG) Single Bit ECC Error Interrupt */
-#define RAMECC_INTFLAG_SINGLEE (_U_(0x1) << RAMECC_INTFLAG_SINGLEE_Pos)
-#define RAMECC_INTFLAG_DUALE_Pos 1 /**< \brief (RAMECC_INTFLAG) Dual Bit ECC Error Interrupt */
-#define RAMECC_INTFLAG_DUALE (_U_(0x1) << RAMECC_INTFLAG_DUALE_Pos)
-#define RAMECC_INTFLAG_MASK _U_(0x03) /**< \brief (RAMECC_INTFLAG) MASK Register */
-
-/* -------- RAMECC_STATUS : (RAMECC Offset: 0x3) (R/ 8) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t ECCDIS:1; /*!< bit: 0 ECC Disable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} RAMECC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RAMECC_STATUS_OFFSET 0x3 /**< \brief (RAMECC_STATUS offset) Status */
-#define RAMECC_STATUS_RESETVALUE _U_(0x00) /**< \brief (RAMECC_STATUS reset_value) Status */
-
-#define RAMECC_STATUS_ECCDIS_Pos 0 /**< \brief (RAMECC_STATUS) ECC Disable */
-#define RAMECC_STATUS_ECCDIS (_U_(0x1) << RAMECC_STATUS_ECCDIS_Pos)
-#define RAMECC_STATUS_MASK _U_(0x01) /**< \brief (RAMECC_STATUS) MASK Register */
-
-/* -------- RAMECC_ERRADDR : (RAMECC Offset: 0x4) (R/ 32) Error Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ERRADDR:17; /*!< bit: 0..16 Error Address */
- uint32_t :15; /*!< bit: 17..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} RAMECC_ERRADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RAMECC_ERRADDR_OFFSET 0x4 /**< \brief (RAMECC_ERRADDR offset) Error Address */
-#define RAMECC_ERRADDR_RESETVALUE _U_(0x00000000) /**< \brief (RAMECC_ERRADDR reset_value) Error Address */
-
-#define RAMECC_ERRADDR_ERRADDR_Pos 0 /**< \brief (RAMECC_ERRADDR) Error Address */
-#define RAMECC_ERRADDR_ERRADDR_Msk (_U_(0x1FFFF) << RAMECC_ERRADDR_ERRADDR_Pos)
-#define RAMECC_ERRADDR_ERRADDR(value) (RAMECC_ERRADDR_ERRADDR_Msk & ((value) << RAMECC_ERRADDR_ERRADDR_Pos))
-#define RAMECC_ERRADDR_MASK _U_(0x0001FFFF) /**< \brief (RAMECC_ERRADDR) MASK Register */
-
-/* -------- RAMECC_DBGCTRL : (RAMECC Offset: 0xF) (R/W 8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t ECCDIS:1; /*!< bit: 0 ECC Disable */
- uint8_t ECCELOG:1; /*!< bit: 1 ECC Error Log */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} RAMECC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RAMECC_DBGCTRL_OFFSET 0xF /**< \brief (RAMECC_DBGCTRL offset) Debug Control */
-#define RAMECC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (RAMECC_DBGCTRL reset_value) Debug Control */
-
-#define RAMECC_DBGCTRL_ECCDIS_Pos 0 /**< \brief (RAMECC_DBGCTRL) ECC Disable */
-#define RAMECC_DBGCTRL_ECCDIS (_U_(0x1) << RAMECC_DBGCTRL_ECCDIS_Pos)
-#define RAMECC_DBGCTRL_ECCELOG_Pos 1 /**< \brief (RAMECC_DBGCTRL) ECC Error Log */
-#define RAMECC_DBGCTRL_ECCELOG (_U_(0x1) << RAMECC_DBGCTRL_ECCELOG_Pos)
-#define RAMECC_DBGCTRL_MASK _U_(0x03) /**< \brief (RAMECC_DBGCTRL) MASK Register */
-
-/** \brief RAMECC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO RAMECC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0 (R/W 8) Interrupt Enable Clear */
- __IO RAMECC_INTENSET_Type INTENSET; /**< \brief Offset: 0x1 (R/W 8) Interrupt Enable Set */
- __IO RAMECC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2 (R/W 8) Interrupt Flag */
- __I RAMECC_STATUS_Type STATUS; /**< \brief Offset: 0x3 (R/ 8) Status */
- __I RAMECC_ERRADDR_Type ERRADDR; /**< \brief Offset: 0x4 (R/ 32) Error Address */
- RoReg8 Reserved1[0x7];
- __IO RAMECC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0xF (R/W 8) Debug Control */
-} Ramecc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_RAMECC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for RAMECC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_RAMECC_COMPONENT_
+#define _SAME54_RAMECC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR RAMECC */
+/* ========================================================================== */
+/** \addtogroup SAME54_RAMECC RAM ECC */
+/*@{*/
+
+#define RAMECC_U2268
+#define REV_RAMECC 0x100
+
+/* -------- RAMECC_INTENCLR : (RAMECC Offset: 0x0) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt Enable Clear */
+ uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt Enable Clear */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RAMECC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RAMECC_INTENCLR_OFFSET 0x0 /**< \brief (RAMECC_INTENCLR offset) Interrupt Enable Clear */
+#define RAMECC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define RAMECC_INTENCLR_SINGLEE_Pos 0 /**< \brief (RAMECC_INTENCLR) Single Bit ECC Error Interrupt Enable Clear */
+#define RAMECC_INTENCLR_SINGLEE (_U_(0x1) << RAMECC_INTENCLR_SINGLEE_Pos)
+#define RAMECC_INTENCLR_DUALE_Pos 1 /**< \brief (RAMECC_INTENCLR) Dual Bit ECC Error Interrupt Enable Clear */
+#define RAMECC_INTENCLR_DUALE (_U_(0x1) << RAMECC_INTENCLR_DUALE_Pos)
+#define RAMECC_INTENCLR_MASK _U_(0x03) /**< \brief (RAMECC_INTENCLR) MASK Register */
+
+/* -------- RAMECC_INTENSET : (RAMECC Offset: 0x1) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt Enable Set */
+ uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt Enable Set */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RAMECC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RAMECC_INTENSET_OFFSET 0x1 /**< \brief (RAMECC_INTENSET offset) Interrupt Enable Set */
+#define RAMECC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTENSET reset_value) Interrupt Enable Set */
+
+#define RAMECC_INTENSET_SINGLEE_Pos 0 /**< \brief (RAMECC_INTENSET) Single Bit ECC Error Interrupt Enable Set */
+#define RAMECC_INTENSET_SINGLEE (_U_(0x1) << RAMECC_INTENSET_SINGLEE_Pos)
+#define RAMECC_INTENSET_DUALE_Pos 1 /**< \brief (RAMECC_INTENSET) Dual Bit ECC Error Interrupt Enable Set */
+#define RAMECC_INTENSET_DUALE (_U_(0x1) << RAMECC_INTENSET_DUALE_Pos)
+#define RAMECC_INTENSET_MASK _U_(0x03) /**< \brief (RAMECC_INTENSET) MASK Register */
+
+/* -------- RAMECC_INTFLAG : (RAMECC Offset: 0x2) (R/W 8) Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt */
+ __I uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt */
+ __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RAMECC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RAMECC_INTFLAG_OFFSET 0x2 /**< \brief (RAMECC_INTFLAG offset) Interrupt Flag */
+#define RAMECC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTFLAG reset_value) Interrupt Flag */
+
+#define RAMECC_INTFLAG_SINGLEE_Pos 0 /**< \brief (RAMECC_INTFLAG) Single Bit ECC Error Interrupt */
+#define RAMECC_INTFLAG_SINGLEE (_U_(0x1) << RAMECC_INTFLAG_SINGLEE_Pos)
+#define RAMECC_INTFLAG_DUALE_Pos 1 /**< \brief (RAMECC_INTFLAG) Dual Bit ECC Error Interrupt */
+#define RAMECC_INTFLAG_DUALE (_U_(0x1) << RAMECC_INTFLAG_DUALE_Pos)
+#define RAMECC_INTFLAG_MASK _U_(0x03) /**< \brief (RAMECC_INTFLAG) MASK Register */
+
+/* -------- RAMECC_STATUS : (RAMECC Offset: 0x3) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ECCDIS:1; /*!< bit: 0 ECC Disable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RAMECC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RAMECC_STATUS_OFFSET 0x3 /**< \brief (RAMECC_STATUS offset) Status */
+#define RAMECC_STATUS_RESETVALUE _U_(0x00) /**< \brief (RAMECC_STATUS reset_value) Status */
+
+#define RAMECC_STATUS_ECCDIS_Pos 0 /**< \brief (RAMECC_STATUS) ECC Disable */
+#define RAMECC_STATUS_ECCDIS (_U_(0x1) << RAMECC_STATUS_ECCDIS_Pos)
+#define RAMECC_STATUS_MASK _U_(0x01) /**< \brief (RAMECC_STATUS) MASK Register */
+
+/* -------- RAMECC_ERRADDR : (RAMECC Offset: 0x4) (R/ 32) Error Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ERRADDR:17; /*!< bit: 0..16 Error Address */
+ uint32_t :15; /*!< bit: 17..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RAMECC_ERRADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RAMECC_ERRADDR_OFFSET 0x4 /**< \brief (RAMECC_ERRADDR offset) Error Address */
+#define RAMECC_ERRADDR_RESETVALUE _U_(0x00000000) /**< \brief (RAMECC_ERRADDR reset_value) Error Address */
+
+#define RAMECC_ERRADDR_ERRADDR_Pos 0 /**< \brief (RAMECC_ERRADDR) Error Address */
+#define RAMECC_ERRADDR_ERRADDR_Msk (_U_(0x1FFFF) << RAMECC_ERRADDR_ERRADDR_Pos)
+#define RAMECC_ERRADDR_ERRADDR(value) (RAMECC_ERRADDR_ERRADDR_Msk & ((value) << RAMECC_ERRADDR_ERRADDR_Pos))
+#define RAMECC_ERRADDR_MASK _U_(0x0001FFFF) /**< \brief (RAMECC_ERRADDR) MASK Register */
+
+/* -------- RAMECC_DBGCTRL : (RAMECC Offset: 0xF) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ECCDIS:1; /*!< bit: 0 ECC Disable */
+ uint8_t ECCELOG:1; /*!< bit: 1 ECC Error Log */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RAMECC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RAMECC_DBGCTRL_OFFSET 0xF /**< \brief (RAMECC_DBGCTRL offset) Debug Control */
+#define RAMECC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (RAMECC_DBGCTRL reset_value) Debug Control */
+
+#define RAMECC_DBGCTRL_ECCDIS_Pos 0 /**< \brief (RAMECC_DBGCTRL) ECC Disable */
+#define RAMECC_DBGCTRL_ECCDIS (_U_(0x1) << RAMECC_DBGCTRL_ECCDIS_Pos)
+#define RAMECC_DBGCTRL_ECCELOG_Pos 1 /**< \brief (RAMECC_DBGCTRL) ECC Error Log */
+#define RAMECC_DBGCTRL_ECCELOG (_U_(0x1) << RAMECC_DBGCTRL_ECCELOG_Pos)
+#define RAMECC_DBGCTRL_MASK _U_(0x03) /**< \brief (RAMECC_DBGCTRL) MASK Register */
+
+/** \brief RAMECC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO RAMECC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0 (R/W 8) Interrupt Enable Clear */
+ __IO RAMECC_INTENSET_Type INTENSET; /**< \brief Offset: 0x1 (R/W 8) Interrupt Enable Set */
+ __IO RAMECC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2 (R/W 8) Interrupt Flag */
+ __I RAMECC_STATUS_Type STATUS; /**< \brief Offset: 0x3 (R/ 8) Status */
+ __I RAMECC_ERRADDR_Type ERRADDR; /**< \brief Offset: 0x4 (R/ 32) Error Address */
+ RoReg8 Reserved1[0x7];
+ __IO RAMECC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0xF (R/W 8) Debug Control */
+} Ramecc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_RAMECC_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/rstc.h b/sysmoOCTSIM/include/component/rstc.h
index 1ec35da..d1f793d 100644
--- a/sysmoOCTSIM/include/component/rstc.h
+++ b/sysmoOCTSIM/include/component/rstc.h
@@ -1,115 +1,115 @@
-/**
- * \file
- *
- * \brief Component description for RSTC
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_RSTC_COMPONENT_
-#define _SAME54_RSTC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR RSTC */
-/* ========================================================================== */
-/** \addtogroup SAME54_RSTC Reset Controller */
-/*@{*/
-
-#define RSTC_U2239
-#define REV_RSTC 0x400
-
-/* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) (R/ 8) Reset Cause -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t POR:1; /*!< bit: 0 Power On Reset */
- uint8_t BODCORE:1; /*!< bit: 1 Brown Out CORE Detector Reset */
- uint8_t BODVDD:1; /*!< bit: 2 Brown Out VDD Detector Reset */
- uint8_t NVM:1; /*!< bit: 3 NVM Reset */
- uint8_t EXT:1; /*!< bit: 4 External Reset */
- uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
- uint8_t SYST:1; /*!< bit: 6 System Reset Request */
- uint8_t BACKUP:1; /*!< bit: 7 Backup Reset */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} RSTC_RCAUSE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RSTC_RCAUSE_OFFSET 0x00 /**< \brief (RSTC_RCAUSE offset) Reset Cause */
-
-#define RSTC_RCAUSE_POR_Pos 0 /**< \brief (RSTC_RCAUSE) Power On Reset */
-#define RSTC_RCAUSE_POR (_U_(0x1) << RSTC_RCAUSE_POR_Pos)
-#define RSTC_RCAUSE_BODCORE_Pos 1 /**< \brief (RSTC_RCAUSE) Brown Out CORE Detector Reset */
-#define RSTC_RCAUSE_BODCORE (_U_(0x1) << RSTC_RCAUSE_BODCORE_Pos)
-#define RSTC_RCAUSE_BODVDD_Pos 2 /**< \brief (RSTC_RCAUSE) Brown Out VDD Detector Reset */
-#define RSTC_RCAUSE_BODVDD (_U_(0x1) << RSTC_RCAUSE_BODVDD_Pos)
-#define RSTC_RCAUSE_NVM_Pos 3 /**< \brief (RSTC_RCAUSE) NVM Reset */
-#define RSTC_RCAUSE_NVM (_U_(0x1) << RSTC_RCAUSE_NVM_Pos)
-#define RSTC_RCAUSE_EXT_Pos 4 /**< \brief (RSTC_RCAUSE) External Reset */
-#define RSTC_RCAUSE_EXT (_U_(0x1) << RSTC_RCAUSE_EXT_Pos)
-#define RSTC_RCAUSE_WDT_Pos 5 /**< \brief (RSTC_RCAUSE) Watchdog Reset */
-#define RSTC_RCAUSE_WDT (_U_(0x1) << RSTC_RCAUSE_WDT_Pos)
-#define RSTC_RCAUSE_SYST_Pos 6 /**< \brief (RSTC_RCAUSE) System Reset Request */
-#define RSTC_RCAUSE_SYST (_U_(0x1) << RSTC_RCAUSE_SYST_Pos)
-#define RSTC_RCAUSE_BACKUP_Pos 7 /**< \brief (RSTC_RCAUSE) Backup Reset */
-#define RSTC_RCAUSE_BACKUP (_U_(0x1) << RSTC_RCAUSE_BACKUP_Pos)
-#define RSTC_RCAUSE_MASK _U_(0xFF) /**< \brief (RSTC_RCAUSE) MASK Register */
-
-/* -------- RSTC_BKUPEXIT : (RSTC Offset: 0x02) (R/ 8) Backup Exit Source -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t :1; /*!< bit: 0 Reserved */
- uint8_t RTC:1; /*!< bit: 1 Real Timer Counter Interrupt */
- uint8_t BBPS:1; /*!< bit: 2 Battery Backup Power Switch */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t HIB:1; /*!< bit: 7 Hibernate */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} RSTC_BKUPEXIT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RSTC_BKUPEXIT_OFFSET 0x02 /**< \brief (RSTC_BKUPEXIT offset) Backup Exit Source */
-#define RSTC_BKUPEXIT_RESETVALUE _U_(0x00) /**< \brief (RSTC_BKUPEXIT reset_value) Backup Exit Source */
-
-#define RSTC_BKUPEXIT_RTC_Pos 1 /**< \brief (RSTC_BKUPEXIT) Real Timer Counter Interrupt */
-#define RSTC_BKUPEXIT_RTC (_U_(0x1) << RSTC_BKUPEXIT_RTC_Pos)
-#define RSTC_BKUPEXIT_BBPS_Pos 2 /**< \brief (RSTC_BKUPEXIT) Battery Backup Power Switch */
-#define RSTC_BKUPEXIT_BBPS (_U_(0x1) << RSTC_BKUPEXIT_BBPS_Pos)
-#define RSTC_BKUPEXIT_HIB_Pos 7 /**< \brief (RSTC_BKUPEXIT) Hibernate */
-#define RSTC_BKUPEXIT_HIB (_U_(0x1) << RSTC_BKUPEXIT_HIB_Pos)
-#define RSTC_BKUPEXIT_MASK _U_(0x86) /**< \brief (RSTC_BKUPEXIT) MASK Register */
-
-/** \brief RSTC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __I RSTC_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x00 (R/ 8) Reset Cause */
- RoReg8 Reserved1[0x1];
- __I RSTC_BKUPEXIT_Type BKUPEXIT; /**< \brief Offset: 0x02 (R/ 8) Backup Exit Source */
-} Rstc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_RSTC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for RSTC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_RSTC_COMPONENT_
+#define _SAME54_RSTC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR RSTC */
+/* ========================================================================== */
+/** \addtogroup SAME54_RSTC Reset Controller */
+/*@{*/
+
+#define RSTC_U2239
+#define REV_RSTC 0x400
+
+/* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) (R/ 8) Reset Cause -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t POR:1; /*!< bit: 0 Power On Reset */
+ uint8_t BODCORE:1; /*!< bit: 1 Brown Out CORE Detector Reset */
+ uint8_t BODVDD:1; /*!< bit: 2 Brown Out VDD Detector Reset */
+ uint8_t NVM:1; /*!< bit: 3 NVM Reset */
+ uint8_t EXT:1; /*!< bit: 4 External Reset */
+ uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
+ uint8_t SYST:1; /*!< bit: 6 System Reset Request */
+ uint8_t BACKUP:1; /*!< bit: 7 Backup Reset */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RSTC_RCAUSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RSTC_RCAUSE_OFFSET 0x00 /**< \brief (RSTC_RCAUSE offset) Reset Cause */
+
+#define RSTC_RCAUSE_POR_Pos 0 /**< \brief (RSTC_RCAUSE) Power On Reset */
+#define RSTC_RCAUSE_POR (_U_(0x1) << RSTC_RCAUSE_POR_Pos)
+#define RSTC_RCAUSE_BODCORE_Pos 1 /**< \brief (RSTC_RCAUSE) Brown Out CORE Detector Reset */
+#define RSTC_RCAUSE_BODCORE (_U_(0x1) << RSTC_RCAUSE_BODCORE_Pos)
+#define RSTC_RCAUSE_BODVDD_Pos 2 /**< \brief (RSTC_RCAUSE) Brown Out VDD Detector Reset */
+#define RSTC_RCAUSE_BODVDD (_U_(0x1) << RSTC_RCAUSE_BODVDD_Pos)
+#define RSTC_RCAUSE_NVM_Pos 3 /**< \brief (RSTC_RCAUSE) NVM Reset */
+#define RSTC_RCAUSE_NVM (_U_(0x1) << RSTC_RCAUSE_NVM_Pos)
+#define RSTC_RCAUSE_EXT_Pos 4 /**< \brief (RSTC_RCAUSE) External Reset */
+#define RSTC_RCAUSE_EXT (_U_(0x1) << RSTC_RCAUSE_EXT_Pos)
+#define RSTC_RCAUSE_WDT_Pos 5 /**< \brief (RSTC_RCAUSE) Watchdog Reset */
+#define RSTC_RCAUSE_WDT (_U_(0x1) << RSTC_RCAUSE_WDT_Pos)
+#define RSTC_RCAUSE_SYST_Pos 6 /**< \brief (RSTC_RCAUSE) System Reset Request */
+#define RSTC_RCAUSE_SYST (_U_(0x1) << RSTC_RCAUSE_SYST_Pos)
+#define RSTC_RCAUSE_BACKUP_Pos 7 /**< \brief (RSTC_RCAUSE) Backup Reset */
+#define RSTC_RCAUSE_BACKUP (_U_(0x1) << RSTC_RCAUSE_BACKUP_Pos)
+#define RSTC_RCAUSE_MASK _U_(0xFF) /**< \brief (RSTC_RCAUSE) MASK Register */
+
+/* -------- RSTC_BKUPEXIT : (RSTC Offset: 0x02) (R/ 8) Backup Exit Source -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t RTC:1; /*!< bit: 1 Real Timer Counter Interrupt */
+ uint8_t BBPS:1; /*!< bit: 2 Battery Backup Power Switch */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t HIB:1; /*!< bit: 7 Hibernate */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RSTC_BKUPEXIT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RSTC_BKUPEXIT_OFFSET 0x02 /**< \brief (RSTC_BKUPEXIT offset) Backup Exit Source */
+#define RSTC_BKUPEXIT_RESETVALUE _U_(0x00) /**< \brief (RSTC_BKUPEXIT reset_value) Backup Exit Source */
+
+#define RSTC_BKUPEXIT_RTC_Pos 1 /**< \brief (RSTC_BKUPEXIT) Real Timer Counter Interrupt */
+#define RSTC_BKUPEXIT_RTC (_U_(0x1) << RSTC_BKUPEXIT_RTC_Pos)
+#define RSTC_BKUPEXIT_BBPS_Pos 2 /**< \brief (RSTC_BKUPEXIT) Battery Backup Power Switch */
+#define RSTC_BKUPEXIT_BBPS (_U_(0x1) << RSTC_BKUPEXIT_BBPS_Pos)
+#define RSTC_BKUPEXIT_HIB_Pos 7 /**< \brief (RSTC_BKUPEXIT) Hibernate */
+#define RSTC_BKUPEXIT_HIB (_U_(0x1) << RSTC_BKUPEXIT_HIB_Pos)
+#define RSTC_BKUPEXIT_MASK _U_(0x86) /**< \brief (RSTC_BKUPEXIT) MASK Register */
+
+/** \brief RSTC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __I RSTC_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x00 (R/ 8) Reset Cause */
+ RoReg8 Reserved1[0x1];
+ __I RSTC_BKUPEXIT_Type BKUPEXIT; /**< \brief Offset: 0x02 (R/ 8) Backup Exit Source */
+} Rstc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_RSTC_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/rtc.h b/sysmoOCTSIM/include/component/rtc.h
index 4e7a043..d2822a3 100644
--- a/sysmoOCTSIM/include/component/rtc.h
+++ b/sysmoOCTSIM/include/component/rtc.h
@@ -1,2098 +1,2098 @@
-/**
- * \file
- *
- * \brief Component description for RTC
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_RTC_COMPONENT_
-#define _SAME54_RTC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR RTC */
-/* ========================================================================== */
-/** \addtogroup SAME54_RTC Real-Time Counter */
-/*@{*/
-
-#define RTC_U2250
-#define REV_RTC 0x210
-
-/* -------- RTC_MODE0_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
- uint16_t :3; /*!< bit: 4.. 6 Reserved */
- uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
- uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
- uint16_t :1; /*!< bit: 12 Reserved */
- uint16_t BKTRST:1; /*!< bit: 13 BKUP Registers Reset On Tamper Enable */
- uint16_t GPTRST:1; /*!< bit: 14 GP Registers Reset On Tamper Enable */
- uint16_t COUNTSYNC:1; /*!< bit: 15 Count Read Synchronization Enable */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} RTC_MODE0_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRLA offset) MODE0 Control A */
-#define RTC_MODE0_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_CTRLA reset_value) MODE0 Control A */
-
-#define RTC_MODE0_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRLA) Software Reset */
-#define RTC_MODE0_CTRLA_SWRST (_U_(0x1) << RTC_MODE0_CTRLA_SWRST_Pos)
-#define RTC_MODE0_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRLA) Enable */
-#define RTC_MODE0_CTRLA_ENABLE (_U_(0x1) << RTC_MODE0_CTRLA_ENABLE_Pos)
-#define RTC_MODE0_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRLA) Operating Mode */
-#define RTC_MODE0_CTRLA_MODE_Msk (_U_(0x3) << RTC_MODE0_CTRLA_MODE_Pos)
-#define RTC_MODE0_CTRLA_MODE(value) (RTC_MODE0_CTRLA_MODE_Msk & ((value) << RTC_MODE0_CTRLA_MODE_Pos))
-#define RTC_MODE0_CTRLA_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRLA) Mode 0: 32-bit Counter */
-#define RTC_MODE0_CTRLA_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRLA) Mode 1: 16-bit Counter */
-#define RTC_MODE0_CTRLA_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRLA) Mode 2: Clock/Calendar */
-#define RTC_MODE0_CTRLA_MODE_COUNT32 (RTC_MODE0_CTRLA_MODE_COUNT32_Val << RTC_MODE0_CTRLA_MODE_Pos)
-#define RTC_MODE0_CTRLA_MODE_COUNT16 (RTC_MODE0_CTRLA_MODE_COUNT16_Val << RTC_MODE0_CTRLA_MODE_Pos)
-#define RTC_MODE0_CTRLA_MODE_CLOCK (RTC_MODE0_CTRLA_MODE_CLOCK_Val << RTC_MODE0_CTRLA_MODE_Pos)
-#define RTC_MODE0_CTRLA_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRLA) Clear on Match */
-#define RTC_MODE0_CTRLA_MATCHCLR (_U_(0x1) << RTC_MODE0_CTRLA_MATCHCLR_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRLA) Prescaler */
-#define RTC_MODE0_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER(value) (RTC_MODE0_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE0_CTRLA_PRESCALER_Pos))
-#define RTC_MODE0_CTRLA_PRESCALER_OFF_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
-#define RTC_MODE0_CTRLA_PRESCALER_DIV1_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
-#define RTC_MODE0_CTRLA_PRESCALER_DIV2_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */
-#define RTC_MODE0_CTRLA_PRESCALER_DIV4_Val _U_(0x3) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */
-#define RTC_MODE0_CTRLA_PRESCALER_DIV8_Val _U_(0x4) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */
-#define RTC_MODE0_CTRLA_PRESCALER_DIV16_Val _U_(0x5) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */
-#define RTC_MODE0_CTRLA_PRESCALER_DIV32_Val _U_(0x6) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */
-#define RTC_MODE0_CTRLA_PRESCALER_DIV64_Val _U_(0x7) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */
-#define RTC_MODE0_CTRLA_PRESCALER_DIV128_Val _U_(0x8) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */
-#define RTC_MODE0_CTRLA_PRESCALER_DIV256_Val _U_(0x9) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */
-#define RTC_MODE0_CTRLA_PRESCALER_DIV512_Val _U_(0xA) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */
-#define RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val _U_(0xB) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */
-#define RTC_MODE0_CTRLA_PRESCALER_OFF (RTC_MODE0_CTRLA_PRESCALER_OFF_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV1 (RTC_MODE0_CTRLA_PRESCALER_DIV1_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV2 (RTC_MODE0_CTRLA_PRESCALER_DIV2_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV4 (RTC_MODE0_CTRLA_PRESCALER_DIV4_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV8 (RTC_MODE0_CTRLA_PRESCALER_DIV8_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV16 (RTC_MODE0_CTRLA_PRESCALER_DIV16_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV32 (RTC_MODE0_CTRLA_PRESCALER_DIV32_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV64 (RTC_MODE0_CTRLA_PRESCALER_DIV64_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV128 (RTC_MODE0_CTRLA_PRESCALER_DIV128_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV256 (RTC_MODE0_CTRLA_PRESCALER_DIV256_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV512 (RTC_MODE0_CTRLA_PRESCALER_DIV512_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV1024 (RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_BKTRST_Pos 13 /**< \brief (RTC_MODE0_CTRLA) BKUP Registers Reset On Tamper Enable */
-#define RTC_MODE0_CTRLA_BKTRST (_U_(0x1) << RTC_MODE0_CTRLA_BKTRST_Pos)
-#define RTC_MODE0_CTRLA_GPTRST_Pos 14 /**< \brief (RTC_MODE0_CTRLA) GP Registers Reset On Tamper Enable */
-#define RTC_MODE0_CTRLA_GPTRST (_U_(0x1) << RTC_MODE0_CTRLA_GPTRST_Pos)
-#define RTC_MODE0_CTRLA_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE0_CTRLA) Count Read Synchronization Enable */
-#define RTC_MODE0_CTRLA_COUNTSYNC (_U_(0x1) << RTC_MODE0_CTRLA_COUNTSYNC_Pos)
-#define RTC_MODE0_CTRLA_MASK _U_(0xEF8F) /**< \brief (RTC_MODE0_CTRLA) MASK Register */
-
-/* -------- RTC_MODE1_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
- uint16_t :4; /*!< bit: 4.. 7 Reserved */
- uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
- uint16_t :1; /*!< bit: 12 Reserved */
- uint16_t BKTRST:1; /*!< bit: 13 BKUP Registers Reset On Tamper Enable */
- uint16_t GPTRST:1; /*!< bit: 14 GP Registers Reset On Tamper Enable */
- uint16_t COUNTSYNC:1; /*!< bit: 15 Count Read Synchronization Enable */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} RTC_MODE1_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRLA offset) MODE1 Control A */
-#define RTC_MODE1_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_CTRLA reset_value) MODE1 Control A */
-
-#define RTC_MODE1_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRLA) Software Reset */
-#define RTC_MODE1_CTRLA_SWRST (_U_(0x1) << RTC_MODE1_CTRLA_SWRST_Pos)
-#define RTC_MODE1_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRLA) Enable */
-#define RTC_MODE1_CTRLA_ENABLE (_U_(0x1) << RTC_MODE1_CTRLA_ENABLE_Pos)
-#define RTC_MODE1_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRLA) Operating Mode */
-#define RTC_MODE1_CTRLA_MODE_Msk (_U_(0x3) << RTC_MODE1_CTRLA_MODE_Pos)
-#define RTC_MODE1_CTRLA_MODE(value) (RTC_MODE1_CTRLA_MODE_Msk & ((value) << RTC_MODE1_CTRLA_MODE_Pos))
-#define RTC_MODE1_CTRLA_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRLA) Mode 0: 32-bit Counter */
-#define RTC_MODE1_CTRLA_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRLA) Mode 1: 16-bit Counter */
-#define RTC_MODE1_CTRLA_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRLA) Mode 2: Clock/Calendar */
-#define RTC_MODE1_CTRLA_MODE_COUNT32 (RTC_MODE1_CTRLA_MODE_COUNT32_Val << RTC_MODE1_CTRLA_MODE_Pos)
-#define RTC_MODE1_CTRLA_MODE_COUNT16 (RTC_MODE1_CTRLA_MODE_COUNT16_Val << RTC_MODE1_CTRLA_MODE_Pos)
-#define RTC_MODE1_CTRLA_MODE_CLOCK (RTC_MODE1_CTRLA_MODE_CLOCK_Val << RTC_MODE1_CTRLA_MODE_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRLA) Prescaler */
-#define RTC_MODE1_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER(value) (RTC_MODE1_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE1_CTRLA_PRESCALER_Pos))
-#define RTC_MODE1_CTRLA_PRESCALER_OFF_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
-#define RTC_MODE1_CTRLA_PRESCALER_DIV1_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
-#define RTC_MODE1_CTRLA_PRESCALER_DIV2_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */
-#define RTC_MODE1_CTRLA_PRESCALER_DIV4_Val _U_(0x3) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */
-#define RTC_MODE1_CTRLA_PRESCALER_DIV8_Val _U_(0x4) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */
-#define RTC_MODE1_CTRLA_PRESCALER_DIV16_Val _U_(0x5) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */
-#define RTC_MODE1_CTRLA_PRESCALER_DIV32_Val _U_(0x6) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */
-#define RTC_MODE1_CTRLA_PRESCALER_DIV64_Val _U_(0x7) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */
-#define RTC_MODE1_CTRLA_PRESCALER_DIV128_Val _U_(0x8) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */
-#define RTC_MODE1_CTRLA_PRESCALER_DIV256_Val _U_(0x9) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */
-#define RTC_MODE1_CTRLA_PRESCALER_DIV512_Val _U_(0xA) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */
-#define RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val _U_(0xB) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */
-#define RTC_MODE1_CTRLA_PRESCALER_OFF (RTC_MODE1_CTRLA_PRESCALER_OFF_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV1 (RTC_MODE1_CTRLA_PRESCALER_DIV1_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV2 (RTC_MODE1_CTRLA_PRESCALER_DIV2_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV4 (RTC_MODE1_CTRLA_PRESCALER_DIV4_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV8 (RTC_MODE1_CTRLA_PRESCALER_DIV8_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV16 (RTC_MODE1_CTRLA_PRESCALER_DIV16_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV32 (RTC_MODE1_CTRLA_PRESCALER_DIV32_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV64 (RTC_MODE1_CTRLA_PRESCALER_DIV64_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV128 (RTC_MODE1_CTRLA_PRESCALER_DIV128_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV256 (RTC_MODE1_CTRLA_PRESCALER_DIV256_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV512 (RTC_MODE1_CTRLA_PRESCALER_DIV512_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV1024 (RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_BKTRST_Pos 13 /**< \brief (RTC_MODE1_CTRLA) BKUP Registers Reset On Tamper Enable */
-#define RTC_MODE1_CTRLA_BKTRST (_U_(0x1) << RTC_MODE1_CTRLA_BKTRST_Pos)
-#define RTC_MODE1_CTRLA_GPTRST_Pos 14 /**< \brief (RTC_MODE1_CTRLA) GP Registers Reset On Tamper Enable */
-#define RTC_MODE1_CTRLA_GPTRST (_U_(0x1) << RTC_MODE1_CTRLA_GPTRST_Pos)
-#define RTC_MODE1_CTRLA_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE1_CTRLA) Count Read Synchronization Enable */
-#define RTC_MODE1_CTRLA_COUNTSYNC (_U_(0x1) << RTC_MODE1_CTRLA_COUNTSYNC_Pos)
-#define RTC_MODE1_CTRLA_MASK _U_(0xEF0F) /**< \brief (RTC_MODE1_CTRLA) MASK Register */
-
-/* -------- RTC_MODE2_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
- uint16_t :2; /*!< bit: 4.. 5 Reserved */
- uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
- uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
- uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
- uint16_t :1; /*!< bit: 12 Reserved */
- uint16_t BKTRST:1; /*!< bit: 13 BKUP Registers Reset On Tamper Enable */
- uint16_t GPTRST:1; /*!< bit: 14 GP Registers Reset On Tamper Enable */
- uint16_t CLOCKSYNC:1; /*!< bit: 15 Clock Read Synchronization Enable */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} RTC_MODE2_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRLA offset) MODE2 Control A */
-#define RTC_MODE2_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_CTRLA reset_value) MODE2 Control A */
-
-#define RTC_MODE2_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRLA) Software Reset */
-#define RTC_MODE2_CTRLA_SWRST (_U_(0x1) << RTC_MODE2_CTRLA_SWRST_Pos)
-#define RTC_MODE2_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRLA) Enable */
-#define RTC_MODE2_CTRLA_ENABLE (_U_(0x1) << RTC_MODE2_CTRLA_ENABLE_Pos)
-#define RTC_MODE2_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRLA) Operating Mode */
-#define RTC_MODE2_CTRLA_MODE_Msk (_U_(0x3) << RTC_MODE2_CTRLA_MODE_Pos)
-#define RTC_MODE2_CTRLA_MODE(value) (RTC_MODE2_CTRLA_MODE_Msk & ((value) << RTC_MODE2_CTRLA_MODE_Pos))
-#define RTC_MODE2_CTRLA_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRLA) Mode 0: 32-bit Counter */
-#define RTC_MODE2_CTRLA_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRLA) Mode 1: 16-bit Counter */
-#define RTC_MODE2_CTRLA_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRLA) Mode 2: Clock/Calendar */
-#define RTC_MODE2_CTRLA_MODE_COUNT32 (RTC_MODE2_CTRLA_MODE_COUNT32_Val << RTC_MODE2_CTRLA_MODE_Pos)
-#define RTC_MODE2_CTRLA_MODE_COUNT16 (RTC_MODE2_CTRLA_MODE_COUNT16_Val << RTC_MODE2_CTRLA_MODE_Pos)
-#define RTC_MODE2_CTRLA_MODE_CLOCK (RTC_MODE2_CTRLA_MODE_CLOCK_Val << RTC_MODE2_CTRLA_MODE_Pos)
-#define RTC_MODE2_CTRLA_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRLA) Clock Representation */
-#define RTC_MODE2_CTRLA_CLKREP (_U_(0x1) << RTC_MODE2_CTRLA_CLKREP_Pos)
-#define RTC_MODE2_CTRLA_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRLA) Clear on Match */
-#define RTC_MODE2_CTRLA_MATCHCLR (_U_(0x1) << RTC_MODE2_CTRLA_MATCHCLR_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRLA) Prescaler */
-#define RTC_MODE2_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER(value) (RTC_MODE2_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE2_CTRLA_PRESCALER_Pos))
-#define RTC_MODE2_CTRLA_PRESCALER_OFF_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
-#define RTC_MODE2_CTRLA_PRESCALER_DIV1_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
-#define RTC_MODE2_CTRLA_PRESCALER_DIV2_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */
-#define RTC_MODE2_CTRLA_PRESCALER_DIV4_Val _U_(0x3) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */
-#define RTC_MODE2_CTRLA_PRESCALER_DIV8_Val _U_(0x4) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */
-#define RTC_MODE2_CTRLA_PRESCALER_DIV16_Val _U_(0x5) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */
-#define RTC_MODE2_CTRLA_PRESCALER_DIV32_Val _U_(0x6) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */
-#define RTC_MODE2_CTRLA_PRESCALER_DIV64_Val _U_(0x7) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */
-#define RTC_MODE2_CTRLA_PRESCALER_DIV128_Val _U_(0x8) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */
-#define RTC_MODE2_CTRLA_PRESCALER_DIV256_Val _U_(0x9) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */
-#define RTC_MODE2_CTRLA_PRESCALER_DIV512_Val _U_(0xA) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */
-#define RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val _U_(0xB) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */
-#define RTC_MODE2_CTRLA_PRESCALER_OFF (RTC_MODE2_CTRLA_PRESCALER_OFF_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV1 (RTC_MODE2_CTRLA_PRESCALER_DIV1_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV2 (RTC_MODE2_CTRLA_PRESCALER_DIV2_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV4 (RTC_MODE2_CTRLA_PRESCALER_DIV4_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV8 (RTC_MODE2_CTRLA_PRESCALER_DIV8_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV16 (RTC_MODE2_CTRLA_PRESCALER_DIV16_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV32 (RTC_MODE2_CTRLA_PRESCALER_DIV32_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV64 (RTC_MODE2_CTRLA_PRESCALER_DIV64_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV128 (RTC_MODE2_CTRLA_PRESCALER_DIV128_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV256 (RTC_MODE2_CTRLA_PRESCALER_DIV256_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV512 (RTC_MODE2_CTRLA_PRESCALER_DIV512_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV1024 (RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_BKTRST_Pos 13 /**< \brief (RTC_MODE2_CTRLA) BKUP Registers Reset On Tamper Enable */
-#define RTC_MODE2_CTRLA_BKTRST (_U_(0x1) << RTC_MODE2_CTRLA_BKTRST_Pos)
-#define RTC_MODE2_CTRLA_GPTRST_Pos 14 /**< \brief (RTC_MODE2_CTRLA) GP Registers Reset On Tamper Enable */
-#define RTC_MODE2_CTRLA_GPTRST (_U_(0x1) << RTC_MODE2_CTRLA_GPTRST_Pos)
-#define RTC_MODE2_CTRLA_CLOCKSYNC_Pos 15 /**< \brief (RTC_MODE2_CTRLA) Clock Read Synchronization Enable */
-#define RTC_MODE2_CTRLA_CLOCKSYNC (_U_(0x1) << RTC_MODE2_CTRLA_CLOCKSYNC_Pos)
-#define RTC_MODE2_CTRLA_MASK _U_(0xEFCF) /**< \brief (RTC_MODE2_CTRLA) MASK Register */
-
-/* -------- RTC_MODE0_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE0 MODE0 Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t GP0EN:1; /*!< bit: 0 General Purpose 0 Enable */
- uint16_t GP2EN:1; /*!< bit: 1 General Purpose 2 Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t DEBMAJ:1; /*!< bit: 4 Debouncer Majority Enable */
- uint16_t DEBASYNC:1; /*!< bit: 5 Debouncer Asynchronous Enable */
- uint16_t RTCOUT:1; /*!< bit: 6 RTC Output Enable */
- uint16_t DMAEN:1; /*!< bit: 7 DMA Enable */
- uint16_t DEBF:3; /*!< bit: 8..10 Debounce Freqnuency */
- uint16_t :1; /*!< bit: 11 Reserved */
- uint16_t ACTF:3; /*!< bit: 12..14 Active Layer Freqnuency */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} RTC_MODE0_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_CTRLB_OFFSET 0x02 /**< \brief (RTC_MODE0_CTRLB offset) MODE0 Control B */
-#define RTC_MODE0_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_CTRLB reset_value) MODE0 Control B */
-
-#define RTC_MODE0_CTRLB_GP0EN_Pos 0 /**< \brief (RTC_MODE0_CTRLB) General Purpose 0 Enable */
-#define RTC_MODE0_CTRLB_GP0EN (_U_(0x1) << RTC_MODE0_CTRLB_GP0EN_Pos)
-#define RTC_MODE0_CTRLB_GP2EN_Pos 1 /**< \brief (RTC_MODE0_CTRLB) General Purpose 2 Enable */
-#define RTC_MODE0_CTRLB_GP2EN (_U_(0x1) << RTC_MODE0_CTRLB_GP2EN_Pos)
-#define RTC_MODE0_CTRLB_DEBMAJ_Pos 4 /**< \brief (RTC_MODE0_CTRLB) Debouncer Majority Enable */
-#define RTC_MODE0_CTRLB_DEBMAJ (_U_(0x1) << RTC_MODE0_CTRLB_DEBMAJ_Pos)
-#define RTC_MODE0_CTRLB_DEBASYNC_Pos 5 /**< \brief (RTC_MODE0_CTRLB) Debouncer Asynchronous Enable */
-#define RTC_MODE0_CTRLB_DEBASYNC (_U_(0x1) << RTC_MODE0_CTRLB_DEBASYNC_Pos)
-#define RTC_MODE0_CTRLB_RTCOUT_Pos 6 /**< \brief (RTC_MODE0_CTRLB) RTC Output Enable */
-#define RTC_MODE0_CTRLB_RTCOUT (_U_(0x1) << RTC_MODE0_CTRLB_RTCOUT_Pos)
-#define RTC_MODE0_CTRLB_DMAEN_Pos 7 /**< \brief (RTC_MODE0_CTRLB) DMA Enable */
-#define RTC_MODE0_CTRLB_DMAEN (_U_(0x1) << RTC_MODE0_CTRLB_DMAEN_Pos)
-#define RTC_MODE0_CTRLB_DEBF_Pos 8 /**< \brief (RTC_MODE0_CTRLB) Debounce Freqnuency */
-#define RTC_MODE0_CTRLB_DEBF_Msk (_U_(0x7) << RTC_MODE0_CTRLB_DEBF_Pos)
-#define RTC_MODE0_CTRLB_DEBF(value) (RTC_MODE0_CTRLB_DEBF_Msk & ((value) << RTC_MODE0_CTRLB_DEBF_Pos))
-#define RTC_MODE0_CTRLB_DEBF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */
-#define RTC_MODE0_CTRLB_DEBF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */
-#define RTC_MODE0_CTRLB_DEBF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */
-#define RTC_MODE0_CTRLB_DEBF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */
-#define RTC_MODE0_CTRLB_DEBF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */
-#define RTC_MODE0_CTRLB_DEBF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */
-#define RTC_MODE0_CTRLB_DEBF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */
-#define RTC_MODE0_CTRLB_DEBF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */
-#define RTC_MODE0_CTRLB_DEBF_DIV2 (RTC_MODE0_CTRLB_DEBF_DIV2_Val << RTC_MODE0_CTRLB_DEBF_Pos)
-#define RTC_MODE0_CTRLB_DEBF_DIV4 (RTC_MODE0_CTRLB_DEBF_DIV4_Val << RTC_MODE0_CTRLB_DEBF_Pos)
-#define RTC_MODE0_CTRLB_DEBF_DIV8 (RTC_MODE0_CTRLB_DEBF_DIV8_Val << RTC_MODE0_CTRLB_DEBF_Pos)
-#define RTC_MODE0_CTRLB_DEBF_DIV16 (RTC_MODE0_CTRLB_DEBF_DIV16_Val << RTC_MODE0_CTRLB_DEBF_Pos)
-#define RTC_MODE0_CTRLB_DEBF_DIV32 (RTC_MODE0_CTRLB_DEBF_DIV32_Val << RTC_MODE0_CTRLB_DEBF_Pos)
-#define RTC_MODE0_CTRLB_DEBF_DIV64 (RTC_MODE0_CTRLB_DEBF_DIV64_Val << RTC_MODE0_CTRLB_DEBF_Pos)
-#define RTC_MODE0_CTRLB_DEBF_DIV128 (RTC_MODE0_CTRLB_DEBF_DIV128_Val << RTC_MODE0_CTRLB_DEBF_Pos)
-#define RTC_MODE0_CTRLB_DEBF_DIV256 (RTC_MODE0_CTRLB_DEBF_DIV256_Val << RTC_MODE0_CTRLB_DEBF_Pos)
-#define RTC_MODE0_CTRLB_ACTF_Pos 12 /**< \brief (RTC_MODE0_CTRLB) Active Layer Freqnuency */
-#define RTC_MODE0_CTRLB_ACTF_Msk (_U_(0x7) << RTC_MODE0_CTRLB_ACTF_Pos)
-#define RTC_MODE0_CTRLB_ACTF(value) (RTC_MODE0_CTRLB_ACTF_Msk & ((value) << RTC_MODE0_CTRLB_ACTF_Pos))
-#define RTC_MODE0_CTRLB_ACTF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */
-#define RTC_MODE0_CTRLB_ACTF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */
-#define RTC_MODE0_CTRLB_ACTF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */
-#define RTC_MODE0_CTRLB_ACTF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */
-#define RTC_MODE0_CTRLB_ACTF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */
-#define RTC_MODE0_CTRLB_ACTF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */
-#define RTC_MODE0_CTRLB_ACTF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */
-#define RTC_MODE0_CTRLB_ACTF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */
-#define RTC_MODE0_CTRLB_ACTF_DIV2 (RTC_MODE0_CTRLB_ACTF_DIV2_Val << RTC_MODE0_CTRLB_ACTF_Pos)
-#define RTC_MODE0_CTRLB_ACTF_DIV4 (RTC_MODE0_CTRLB_ACTF_DIV4_Val << RTC_MODE0_CTRLB_ACTF_Pos)
-#define RTC_MODE0_CTRLB_ACTF_DIV8 (RTC_MODE0_CTRLB_ACTF_DIV8_Val << RTC_MODE0_CTRLB_ACTF_Pos)
-#define RTC_MODE0_CTRLB_ACTF_DIV16 (RTC_MODE0_CTRLB_ACTF_DIV16_Val << RTC_MODE0_CTRLB_ACTF_Pos)
-#define RTC_MODE0_CTRLB_ACTF_DIV32 (RTC_MODE0_CTRLB_ACTF_DIV32_Val << RTC_MODE0_CTRLB_ACTF_Pos)
-#define RTC_MODE0_CTRLB_ACTF_DIV64 (RTC_MODE0_CTRLB_ACTF_DIV64_Val << RTC_MODE0_CTRLB_ACTF_Pos)
-#define RTC_MODE0_CTRLB_ACTF_DIV128 (RTC_MODE0_CTRLB_ACTF_DIV128_Val << RTC_MODE0_CTRLB_ACTF_Pos)
-#define RTC_MODE0_CTRLB_ACTF_DIV256 (RTC_MODE0_CTRLB_ACTF_DIV256_Val << RTC_MODE0_CTRLB_ACTF_Pos)
-#define RTC_MODE0_CTRLB_MASK _U_(0x77F3) /**< \brief (RTC_MODE0_CTRLB) MASK Register */
-
-/* -------- RTC_MODE1_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE1 MODE1 Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t GP0EN:1; /*!< bit: 0 General Purpose 0 Enable */
- uint16_t GP2EN:1; /*!< bit: 1 General Purpose 2 Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t DEBMAJ:1; /*!< bit: 4 Debouncer Majority Enable */
- uint16_t DEBASYNC:1; /*!< bit: 5 Debouncer Asynchronous Enable */
- uint16_t RTCOUT:1; /*!< bit: 6 RTC Output Enable */
- uint16_t DMAEN:1; /*!< bit: 7 DMA Enable */
- uint16_t DEBF:3; /*!< bit: 8..10 Debounce Freqnuency */
- uint16_t :1; /*!< bit: 11 Reserved */
- uint16_t ACTF:3; /*!< bit: 12..14 Active Layer Freqnuency */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} RTC_MODE1_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_CTRLB_OFFSET 0x02 /**< \brief (RTC_MODE1_CTRLB offset) MODE1 Control B */
-#define RTC_MODE1_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_CTRLB reset_value) MODE1 Control B */
-
-#define RTC_MODE1_CTRLB_GP0EN_Pos 0 /**< \brief (RTC_MODE1_CTRLB) General Purpose 0 Enable */
-#define RTC_MODE1_CTRLB_GP0EN (_U_(0x1) << RTC_MODE1_CTRLB_GP0EN_Pos)
-#define RTC_MODE1_CTRLB_GP2EN_Pos 1 /**< \brief (RTC_MODE1_CTRLB) General Purpose 2 Enable */
-#define RTC_MODE1_CTRLB_GP2EN (_U_(0x1) << RTC_MODE1_CTRLB_GP2EN_Pos)
-#define RTC_MODE1_CTRLB_DEBMAJ_Pos 4 /**< \brief (RTC_MODE1_CTRLB) Debouncer Majority Enable */
-#define RTC_MODE1_CTRLB_DEBMAJ (_U_(0x1) << RTC_MODE1_CTRLB_DEBMAJ_Pos)
-#define RTC_MODE1_CTRLB_DEBASYNC_Pos 5 /**< \brief (RTC_MODE1_CTRLB) Debouncer Asynchronous Enable */
-#define RTC_MODE1_CTRLB_DEBASYNC (_U_(0x1) << RTC_MODE1_CTRLB_DEBASYNC_Pos)
-#define RTC_MODE1_CTRLB_RTCOUT_Pos 6 /**< \brief (RTC_MODE1_CTRLB) RTC Output Enable */
-#define RTC_MODE1_CTRLB_RTCOUT (_U_(0x1) << RTC_MODE1_CTRLB_RTCOUT_Pos)
-#define RTC_MODE1_CTRLB_DMAEN_Pos 7 /**< \brief (RTC_MODE1_CTRLB) DMA Enable */
-#define RTC_MODE1_CTRLB_DMAEN (_U_(0x1) << RTC_MODE1_CTRLB_DMAEN_Pos)
-#define RTC_MODE1_CTRLB_DEBF_Pos 8 /**< \brief (RTC_MODE1_CTRLB) Debounce Freqnuency */
-#define RTC_MODE1_CTRLB_DEBF_Msk (_U_(0x7) << RTC_MODE1_CTRLB_DEBF_Pos)
-#define RTC_MODE1_CTRLB_DEBF(value) (RTC_MODE1_CTRLB_DEBF_Msk & ((value) << RTC_MODE1_CTRLB_DEBF_Pos))
-#define RTC_MODE1_CTRLB_DEBF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */
-#define RTC_MODE1_CTRLB_DEBF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */
-#define RTC_MODE1_CTRLB_DEBF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */
-#define RTC_MODE1_CTRLB_DEBF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */
-#define RTC_MODE1_CTRLB_DEBF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */
-#define RTC_MODE1_CTRLB_DEBF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */
-#define RTC_MODE1_CTRLB_DEBF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */
-#define RTC_MODE1_CTRLB_DEBF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */
-#define RTC_MODE1_CTRLB_DEBF_DIV2 (RTC_MODE1_CTRLB_DEBF_DIV2_Val << RTC_MODE1_CTRLB_DEBF_Pos)
-#define RTC_MODE1_CTRLB_DEBF_DIV4 (RTC_MODE1_CTRLB_DEBF_DIV4_Val << RTC_MODE1_CTRLB_DEBF_Pos)
-#define RTC_MODE1_CTRLB_DEBF_DIV8 (RTC_MODE1_CTRLB_DEBF_DIV8_Val << RTC_MODE1_CTRLB_DEBF_Pos)
-#define RTC_MODE1_CTRLB_DEBF_DIV16 (RTC_MODE1_CTRLB_DEBF_DIV16_Val << RTC_MODE1_CTRLB_DEBF_Pos)
-#define RTC_MODE1_CTRLB_DEBF_DIV32 (RTC_MODE1_CTRLB_DEBF_DIV32_Val << RTC_MODE1_CTRLB_DEBF_Pos)
-#define RTC_MODE1_CTRLB_DEBF_DIV64 (RTC_MODE1_CTRLB_DEBF_DIV64_Val << RTC_MODE1_CTRLB_DEBF_Pos)
-#define RTC_MODE1_CTRLB_DEBF_DIV128 (RTC_MODE1_CTRLB_DEBF_DIV128_Val << RTC_MODE1_CTRLB_DEBF_Pos)
-#define RTC_MODE1_CTRLB_DEBF_DIV256 (RTC_MODE1_CTRLB_DEBF_DIV256_Val << RTC_MODE1_CTRLB_DEBF_Pos)
-#define RTC_MODE1_CTRLB_ACTF_Pos 12 /**< \brief (RTC_MODE1_CTRLB) Active Layer Freqnuency */
-#define RTC_MODE1_CTRLB_ACTF_Msk (_U_(0x7) << RTC_MODE1_CTRLB_ACTF_Pos)
-#define RTC_MODE1_CTRLB_ACTF(value) (RTC_MODE1_CTRLB_ACTF_Msk & ((value) << RTC_MODE1_CTRLB_ACTF_Pos))
-#define RTC_MODE1_CTRLB_ACTF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */
-#define RTC_MODE1_CTRLB_ACTF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */
-#define RTC_MODE1_CTRLB_ACTF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */
-#define RTC_MODE1_CTRLB_ACTF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */
-#define RTC_MODE1_CTRLB_ACTF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */
-#define RTC_MODE1_CTRLB_ACTF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */
-#define RTC_MODE1_CTRLB_ACTF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */
-#define RTC_MODE1_CTRLB_ACTF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */
-#define RTC_MODE1_CTRLB_ACTF_DIV2 (RTC_MODE1_CTRLB_ACTF_DIV2_Val << RTC_MODE1_CTRLB_ACTF_Pos)
-#define RTC_MODE1_CTRLB_ACTF_DIV4 (RTC_MODE1_CTRLB_ACTF_DIV4_Val << RTC_MODE1_CTRLB_ACTF_Pos)
-#define RTC_MODE1_CTRLB_ACTF_DIV8 (RTC_MODE1_CTRLB_ACTF_DIV8_Val << RTC_MODE1_CTRLB_ACTF_Pos)
-#define RTC_MODE1_CTRLB_ACTF_DIV16 (RTC_MODE1_CTRLB_ACTF_DIV16_Val << RTC_MODE1_CTRLB_ACTF_Pos)
-#define RTC_MODE1_CTRLB_ACTF_DIV32 (RTC_MODE1_CTRLB_ACTF_DIV32_Val << RTC_MODE1_CTRLB_ACTF_Pos)
-#define RTC_MODE1_CTRLB_ACTF_DIV64 (RTC_MODE1_CTRLB_ACTF_DIV64_Val << RTC_MODE1_CTRLB_ACTF_Pos)
-#define RTC_MODE1_CTRLB_ACTF_DIV128 (RTC_MODE1_CTRLB_ACTF_DIV128_Val << RTC_MODE1_CTRLB_ACTF_Pos)
-#define RTC_MODE1_CTRLB_ACTF_DIV256 (RTC_MODE1_CTRLB_ACTF_DIV256_Val << RTC_MODE1_CTRLB_ACTF_Pos)
-#define RTC_MODE1_CTRLB_MASK _U_(0x77F3) /**< \brief (RTC_MODE1_CTRLB) MASK Register */
-
-/* -------- RTC_MODE2_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE2 MODE2 Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t GP0EN:1; /*!< bit: 0 General Purpose 0 Enable */
- uint16_t GP2EN:1; /*!< bit: 1 General Purpose 2 Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t DEBMAJ:1; /*!< bit: 4 Debouncer Majority Enable */
- uint16_t DEBASYNC:1; /*!< bit: 5 Debouncer Asynchronous Enable */
- uint16_t RTCOUT:1; /*!< bit: 6 RTC Output Enable */
- uint16_t DMAEN:1; /*!< bit: 7 DMA Enable */
- uint16_t DEBF:3; /*!< bit: 8..10 Debounce Freqnuency */
- uint16_t :1; /*!< bit: 11 Reserved */
- uint16_t ACTF:3; /*!< bit: 12..14 Active Layer Freqnuency */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} RTC_MODE2_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_CTRLB_OFFSET 0x02 /**< \brief (RTC_MODE2_CTRLB offset) MODE2 Control B */
-#define RTC_MODE2_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_CTRLB reset_value) MODE2 Control B */
-
-#define RTC_MODE2_CTRLB_GP0EN_Pos 0 /**< \brief (RTC_MODE2_CTRLB) General Purpose 0 Enable */
-#define RTC_MODE2_CTRLB_GP0EN (_U_(0x1) << RTC_MODE2_CTRLB_GP0EN_Pos)
-#define RTC_MODE2_CTRLB_GP2EN_Pos 1 /**< \brief (RTC_MODE2_CTRLB) General Purpose 2 Enable */
-#define RTC_MODE2_CTRLB_GP2EN (_U_(0x1) << RTC_MODE2_CTRLB_GP2EN_Pos)
-#define RTC_MODE2_CTRLB_DEBMAJ_Pos 4 /**< \brief (RTC_MODE2_CTRLB) Debouncer Majority Enable */
-#define RTC_MODE2_CTRLB_DEBMAJ (_U_(0x1) << RTC_MODE2_CTRLB_DEBMAJ_Pos)
-#define RTC_MODE2_CTRLB_DEBASYNC_Pos 5 /**< \brief (RTC_MODE2_CTRLB) Debouncer Asynchronous Enable */
-#define RTC_MODE2_CTRLB_DEBASYNC (_U_(0x1) << RTC_MODE2_CTRLB_DEBASYNC_Pos)
-#define RTC_MODE2_CTRLB_RTCOUT_Pos 6 /**< \brief (RTC_MODE2_CTRLB) RTC Output Enable */
-#define RTC_MODE2_CTRLB_RTCOUT (_U_(0x1) << RTC_MODE2_CTRLB_RTCOUT_Pos)
-#define RTC_MODE2_CTRLB_DMAEN_Pos 7 /**< \brief (RTC_MODE2_CTRLB) DMA Enable */
-#define RTC_MODE2_CTRLB_DMAEN (_U_(0x1) << RTC_MODE2_CTRLB_DMAEN_Pos)
-#define RTC_MODE2_CTRLB_DEBF_Pos 8 /**< \brief (RTC_MODE2_CTRLB) Debounce Freqnuency */
-#define RTC_MODE2_CTRLB_DEBF_Msk (_U_(0x7) << RTC_MODE2_CTRLB_DEBF_Pos)
-#define RTC_MODE2_CTRLB_DEBF(value) (RTC_MODE2_CTRLB_DEBF_Msk & ((value) << RTC_MODE2_CTRLB_DEBF_Pos))
-#define RTC_MODE2_CTRLB_DEBF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */
-#define RTC_MODE2_CTRLB_DEBF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */
-#define RTC_MODE2_CTRLB_DEBF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */
-#define RTC_MODE2_CTRLB_DEBF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */
-#define RTC_MODE2_CTRLB_DEBF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */
-#define RTC_MODE2_CTRLB_DEBF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */
-#define RTC_MODE2_CTRLB_DEBF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */
-#define RTC_MODE2_CTRLB_DEBF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */
-#define RTC_MODE2_CTRLB_DEBF_DIV2 (RTC_MODE2_CTRLB_DEBF_DIV2_Val << RTC_MODE2_CTRLB_DEBF_Pos)
-#define RTC_MODE2_CTRLB_DEBF_DIV4 (RTC_MODE2_CTRLB_DEBF_DIV4_Val << RTC_MODE2_CTRLB_DEBF_Pos)
-#define RTC_MODE2_CTRLB_DEBF_DIV8 (RTC_MODE2_CTRLB_DEBF_DIV8_Val << RTC_MODE2_CTRLB_DEBF_Pos)
-#define RTC_MODE2_CTRLB_DEBF_DIV16 (RTC_MODE2_CTRLB_DEBF_DIV16_Val << RTC_MODE2_CTRLB_DEBF_Pos)
-#define RTC_MODE2_CTRLB_DEBF_DIV32 (RTC_MODE2_CTRLB_DEBF_DIV32_Val << RTC_MODE2_CTRLB_DEBF_Pos)
-#define RTC_MODE2_CTRLB_DEBF_DIV64 (RTC_MODE2_CTRLB_DEBF_DIV64_Val << RTC_MODE2_CTRLB_DEBF_Pos)
-#define RTC_MODE2_CTRLB_DEBF_DIV128 (RTC_MODE2_CTRLB_DEBF_DIV128_Val << RTC_MODE2_CTRLB_DEBF_Pos)
-#define RTC_MODE2_CTRLB_DEBF_DIV256 (RTC_MODE2_CTRLB_DEBF_DIV256_Val << RTC_MODE2_CTRLB_DEBF_Pos)
-#define RTC_MODE2_CTRLB_ACTF_Pos 12 /**< \brief (RTC_MODE2_CTRLB) Active Layer Freqnuency */
-#define RTC_MODE2_CTRLB_ACTF_Msk (_U_(0x7) << RTC_MODE2_CTRLB_ACTF_Pos)
-#define RTC_MODE2_CTRLB_ACTF(value) (RTC_MODE2_CTRLB_ACTF_Msk & ((value) << RTC_MODE2_CTRLB_ACTF_Pos))
-#define RTC_MODE2_CTRLB_ACTF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */
-#define RTC_MODE2_CTRLB_ACTF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */
-#define RTC_MODE2_CTRLB_ACTF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */
-#define RTC_MODE2_CTRLB_ACTF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */
-#define RTC_MODE2_CTRLB_ACTF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */
-#define RTC_MODE2_CTRLB_ACTF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */
-#define RTC_MODE2_CTRLB_ACTF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */
-#define RTC_MODE2_CTRLB_ACTF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */
-#define RTC_MODE2_CTRLB_ACTF_DIV2 (RTC_MODE2_CTRLB_ACTF_DIV2_Val << RTC_MODE2_CTRLB_ACTF_Pos)
-#define RTC_MODE2_CTRLB_ACTF_DIV4 (RTC_MODE2_CTRLB_ACTF_DIV4_Val << RTC_MODE2_CTRLB_ACTF_Pos)
-#define RTC_MODE2_CTRLB_ACTF_DIV8 (RTC_MODE2_CTRLB_ACTF_DIV8_Val << RTC_MODE2_CTRLB_ACTF_Pos)
-#define RTC_MODE2_CTRLB_ACTF_DIV16 (RTC_MODE2_CTRLB_ACTF_DIV16_Val << RTC_MODE2_CTRLB_ACTF_Pos)
-#define RTC_MODE2_CTRLB_ACTF_DIV32 (RTC_MODE2_CTRLB_ACTF_DIV32_Val << RTC_MODE2_CTRLB_ACTF_Pos)
-#define RTC_MODE2_CTRLB_ACTF_DIV64 (RTC_MODE2_CTRLB_ACTF_DIV64_Val << RTC_MODE2_CTRLB_ACTF_Pos)
-#define RTC_MODE2_CTRLB_ACTF_DIV128 (RTC_MODE2_CTRLB_ACTF_DIV128_Val << RTC_MODE2_CTRLB_ACTF_Pos)
-#define RTC_MODE2_CTRLB_ACTF_DIV256 (RTC_MODE2_CTRLB_ACTF_DIV256_Val << RTC_MODE2_CTRLB_ACTF_Pos)
-#define RTC_MODE2_CTRLB_MASK _U_(0x77F3) /**< \brief (RTC_MODE2_CTRLB) MASK Register */
-
-/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE0 MODE0 Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
- uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
- uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
- uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
- uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
- uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
- uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
- uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
- uint32_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
- uint32_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
- uint32_t :4; /*!< bit: 10..13 Reserved */
- uint32_t TAMPEREO:1; /*!< bit: 14 Tamper Event Output Enable */
- uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
- uint32_t TAMPEVEI:1; /*!< bit: 16 Tamper Event Input Enable */
- uint32_t :15; /*!< bit: 17..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
- uint32_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
- uint32_t :22; /*!< bit: 10..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} RTC_MODE0_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */
-#define RTC_MODE0_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */
-
-#define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO0 (_U_(1) << RTC_MODE0_EVCTRL_PEREO0_Pos)
-#define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO1 (_U_(1) << RTC_MODE0_EVCTRL_PEREO1_Pos)
-#define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO2 (_U_(1) << RTC_MODE0_EVCTRL_PEREO2_Pos)
-#define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO3 (_U_(1) << RTC_MODE0_EVCTRL_PEREO3_Pos)
-#define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO4 (_U_(1) << RTC_MODE0_EVCTRL_PEREO4_Pos)
-#define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO5 (_U_(1) << RTC_MODE0_EVCTRL_PEREO5_Pos)
-#define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO6 (_U_(1) << RTC_MODE0_EVCTRL_PEREO6_Pos)
-#define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO7 (_U_(1) << RTC_MODE0_EVCTRL_PEREO7_Pos)
-#define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE0_EVCTRL_PEREO_Pos)
-#define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))
-#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
-#define RTC_MODE0_EVCTRL_CMPEO0 (_U_(1) << RTC_MODE0_EVCTRL_CMPEO0_Pos)
-#define RTC_MODE0_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE0_EVCTRL) Compare 1 Event Output Enable */
-#define RTC_MODE0_EVCTRL_CMPEO1 (_U_(1) << RTC_MODE0_EVCTRL_CMPEO1_Pos)
-#define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
-#define RTC_MODE0_EVCTRL_CMPEO_Msk (_U_(0x3) << RTC_MODE0_EVCTRL_CMPEO_Pos)
-#define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))
-#define RTC_MODE0_EVCTRL_TAMPEREO_Pos 14 /**< \brief (RTC_MODE0_EVCTRL) Tamper Event Output Enable */
-#define RTC_MODE0_EVCTRL_TAMPEREO (_U_(0x1) << RTC_MODE0_EVCTRL_TAMPEREO_Pos)
-#define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
-#define RTC_MODE0_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE0_EVCTRL_OVFEO_Pos)
-#define RTC_MODE0_EVCTRL_TAMPEVEI_Pos 16 /**< \brief (RTC_MODE0_EVCTRL) Tamper Event Input Enable */
-#define RTC_MODE0_EVCTRL_TAMPEVEI (_U_(0x1) << RTC_MODE0_EVCTRL_TAMPEVEI_Pos)
-#define RTC_MODE0_EVCTRL_MASK _U_(0x0001C3FF) /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
-
-/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE1 MODE1 Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
- uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
- uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
- uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
- uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
- uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
- uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
- uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
- uint32_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
- uint32_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
- uint32_t CMPEO2:1; /*!< bit: 10 Compare 2 Event Output Enable */
- uint32_t CMPEO3:1; /*!< bit: 11 Compare 3 Event Output Enable */
- uint32_t :2; /*!< bit: 12..13 Reserved */
- uint32_t TAMPEREO:1; /*!< bit: 14 Tamper Event Output Enable */
- uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
- uint32_t TAMPEVEI:1; /*!< bit: 16 Tamper Event Input Enable */
- uint32_t :15; /*!< bit: 17..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
- uint32_t CMPEO:4; /*!< bit: 8..11 Compare x Event Output Enable */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} RTC_MODE1_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */
-#define RTC_MODE1_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */
-
-#define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO0 (_U_(1) << RTC_MODE1_EVCTRL_PEREO0_Pos)
-#define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO1 (_U_(1) << RTC_MODE1_EVCTRL_PEREO1_Pos)
-#define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO2 (_U_(1) << RTC_MODE1_EVCTRL_PEREO2_Pos)
-#define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO3 (_U_(1) << RTC_MODE1_EVCTRL_PEREO3_Pos)
-#define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO4 (_U_(1) << RTC_MODE1_EVCTRL_PEREO4_Pos)
-#define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO5 (_U_(1) << RTC_MODE1_EVCTRL_PEREO5_Pos)
-#define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO6 (_U_(1) << RTC_MODE1_EVCTRL_PEREO6_Pos)
-#define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO7 (_U_(1) << RTC_MODE1_EVCTRL_PEREO7_Pos)
-#define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE1_EVCTRL_PEREO_Pos)
-#define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))
-#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
-#define RTC_MODE1_EVCTRL_CMPEO0 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO0_Pos)
-#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
-#define RTC_MODE1_EVCTRL_CMPEO1 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO1_Pos)
-#define RTC_MODE1_EVCTRL_CMPEO2_Pos 10 /**< \brief (RTC_MODE1_EVCTRL) Compare 2 Event Output Enable */
-#define RTC_MODE1_EVCTRL_CMPEO2 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO2_Pos)
-#define RTC_MODE1_EVCTRL_CMPEO3_Pos 11 /**< \brief (RTC_MODE1_EVCTRL) Compare 3 Event Output Enable */
-#define RTC_MODE1_EVCTRL_CMPEO3 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO3_Pos)
-#define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
-#define RTC_MODE1_EVCTRL_CMPEO_Msk (_U_(0xF) << RTC_MODE1_EVCTRL_CMPEO_Pos)
-#define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))
-#define RTC_MODE1_EVCTRL_TAMPEREO_Pos 14 /**< \brief (RTC_MODE1_EVCTRL) Tamper Event Output Enable */
-#define RTC_MODE1_EVCTRL_TAMPEREO (_U_(0x1) << RTC_MODE1_EVCTRL_TAMPEREO_Pos)
-#define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
-#define RTC_MODE1_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE1_EVCTRL_OVFEO_Pos)
-#define RTC_MODE1_EVCTRL_TAMPEVEI_Pos 16 /**< \brief (RTC_MODE1_EVCTRL) Tamper Event Input Enable */
-#define RTC_MODE1_EVCTRL_TAMPEVEI (_U_(0x1) << RTC_MODE1_EVCTRL_TAMPEVEI_Pos)
-#define RTC_MODE1_EVCTRL_MASK _U_(0x0001CFFF) /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
-
-/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE2 MODE2 Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
- uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
- uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
- uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
- uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
- uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
- uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
- uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
- uint32_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
- uint32_t ALARMEO1:1; /*!< bit: 9 Alarm 1 Event Output Enable */
- uint32_t :4; /*!< bit: 10..13 Reserved */
- uint32_t TAMPEREO:1; /*!< bit: 14 Tamper Event Output Enable */
- uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
- uint32_t TAMPEVEI:1; /*!< bit: 16 Tamper Event Input Enable */
- uint32_t :15; /*!< bit: 17..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
- uint32_t ALARMEO:2; /*!< bit: 8.. 9 Alarm x Event Output Enable */
- uint32_t :22; /*!< bit: 10..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} RTC_MODE2_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */
-#define RTC_MODE2_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */
-
-#define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO0 (_U_(1) << RTC_MODE2_EVCTRL_PEREO0_Pos)
-#define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO1 (_U_(1) << RTC_MODE2_EVCTRL_PEREO1_Pos)
-#define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO2 (_U_(1) << RTC_MODE2_EVCTRL_PEREO2_Pos)
-#define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO3 (_U_(1) << RTC_MODE2_EVCTRL_PEREO3_Pos)
-#define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO4 (_U_(1) << RTC_MODE2_EVCTRL_PEREO4_Pos)
-#define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO5 (_U_(1) << RTC_MODE2_EVCTRL_PEREO5_Pos)
-#define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO6 (_U_(1) << RTC_MODE2_EVCTRL_PEREO6_Pos)
-#define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO7 (_U_(1) << RTC_MODE2_EVCTRL_PEREO7_Pos)
-#define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE2_EVCTRL_PEREO_Pos)
-#define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))
-#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
-#define RTC_MODE2_EVCTRL_ALARMEO0 (_U_(1) << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
-#define RTC_MODE2_EVCTRL_ALARMEO1_Pos 9 /**< \brief (RTC_MODE2_EVCTRL) Alarm 1 Event Output Enable */
-#define RTC_MODE2_EVCTRL_ALARMEO1 (_U_(1) << RTC_MODE2_EVCTRL_ALARMEO1_Pos)
-#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
-#define RTC_MODE2_EVCTRL_ALARMEO_Msk (_U_(0x3) << RTC_MODE2_EVCTRL_ALARMEO_Pos)
-#define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))
-#define RTC_MODE2_EVCTRL_TAMPEREO_Pos 14 /**< \brief (RTC_MODE2_EVCTRL) Tamper Event Output Enable */
-#define RTC_MODE2_EVCTRL_TAMPEREO (_U_(0x1) << RTC_MODE2_EVCTRL_TAMPEREO_Pos)
-#define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
-#define RTC_MODE2_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE2_EVCTRL_OVFEO_Pos)
-#define RTC_MODE2_EVCTRL_TAMPEVEI_Pos 16 /**< \brief (RTC_MODE2_EVCTRL) Tamper Event Input Enable */
-#define RTC_MODE2_EVCTRL_TAMPEVEI (_U_(0x1) << RTC_MODE2_EVCTRL_TAMPEVEI_Pos)
-#define RTC_MODE2_EVCTRL_MASK _U_(0x0001C3FF) /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
-
-/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE0 MODE0 Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
- uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
- uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
- uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
- uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
- uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
- uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
- uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
- uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */
- uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */
- uint16_t :4; /*!< bit: 10..13 Reserved */
- uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
- uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
- uint16_t CMP:2; /*!< bit: 8.. 9 Compare x Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} RTC_MODE0_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */
-#define RTC_MODE0_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */
-
-#define RTC_MODE0_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 0 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_PER0 (_U_(1) << RTC_MODE0_INTENCLR_PER0_Pos)
-#define RTC_MODE0_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 1 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_PER1 (_U_(1) << RTC_MODE0_INTENCLR_PER1_Pos)
-#define RTC_MODE0_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 2 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_PER2 (_U_(1) << RTC_MODE0_INTENCLR_PER2_Pos)
-#define RTC_MODE0_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 3 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_PER3 (_U_(1) << RTC_MODE0_INTENCLR_PER3_Pos)
-#define RTC_MODE0_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 4 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_PER4 (_U_(1) << RTC_MODE0_INTENCLR_PER4_Pos)
-#define RTC_MODE0_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 5 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_PER5 (_U_(1) << RTC_MODE0_INTENCLR_PER5_Pos)
-#define RTC_MODE0_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 6 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_PER6 (_U_(1) << RTC_MODE0_INTENCLR_PER6_Pos)
-#define RTC_MODE0_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 7 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_PER7 (_U_(1) << RTC_MODE0_INTENCLR_PER7_Pos)
-#define RTC_MODE0_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval x Interrupt Enable */
-#define RTC_MODE0_INTENCLR_PER_Msk (_U_(0xFF) << RTC_MODE0_INTENCLR_PER_Pos)
-#define RTC_MODE0_INTENCLR_PER(value) (RTC_MODE0_INTENCLR_PER_Msk & ((value) << RTC_MODE0_INTENCLR_PER_Pos))
-#define RTC_MODE0_INTENCLR_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_CMP0 (_U_(1) << RTC_MODE0_INTENCLR_CMP0_Pos)
-#define RTC_MODE0_INTENCLR_CMP1_Pos 9 /**< \brief (RTC_MODE0_INTENCLR) Compare 1 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_CMP1 (_U_(1) << RTC_MODE0_INTENCLR_CMP1_Pos)
-#define RTC_MODE0_INTENCLR_CMP_Pos 8 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
-#define RTC_MODE0_INTENCLR_CMP_Msk (_U_(0x3) << RTC_MODE0_INTENCLR_CMP_Pos)
-#define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))
-#define RTC_MODE0_INTENCLR_TAMPER_Pos 14 /**< \brief (RTC_MODE0_INTENCLR) Tamper Enable */
-#define RTC_MODE0_INTENCLR_TAMPER (_U_(0x1) << RTC_MODE0_INTENCLR_TAMPER_Pos)
-#define RTC_MODE0_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
-#define RTC_MODE0_INTENCLR_OVF (_U_(0x1) << RTC_MODE0_INTENCLR_OVF_Pos)
-#define RTC_MODE0_INTENCLR_MASK _U_(0xC3FF) /**< \brief (RTC_MODE0_INTENCLR) MASK Register */
-
-/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE1 MODE1 Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
- uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
- uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
- uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
- uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
- uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
- uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
- uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
- uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */
- uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */
- uint16_t CMP2:1; /*!< bit: 10 Compare 2 Interrupt Enable */
- uint16_t CMP3:1; /*!< bit: 11 Compare 3 Interrupt Enable */
- uint16_t :2; /*!< bit: 12..13 Reserved */
- uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
- uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
- uint16_t CMP:4; /*!< bit: 8..11 Compare x Interrupt Enable */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} RTC_MODE1_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */
-#define RTC_MODE1_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */
-
-#define RTC_MODE1_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 0 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_PER0 (_U_(1) << RTC_MODE1_INTENCLR_PER0_Pos)
-#define RTC_MODE1_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 1 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_PER1 (_U_(1) << RTC_MODE1_INTENCLR_PER1_Pos)
-#define RTC_MODE1_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 2 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_PER2 (_U_(1) << RTC_MODE1_INTENCLR_PER2_Pos)
-#define RTC_MODE1_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 3 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_PER3 (_U_(1) << RTC_MODE1_INTENCLR_PER3_Pos)
-#define RTC_MODE1_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 4 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_PER4 (_U_(1) << RTC_MODE1_INTENCLR_PER4_Pos)
-#define RTC_MODE1_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 5 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_PER5 (_U_(1) << RTC_MODE1_INTENCLR_PER5_Pos)
-#define RTC_MODE1_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 6 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_PER6 (_U_(1) << RTC_MODE1_INTENCLR_PER6_Pos)
-#define RTC_MODE1_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 7 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_PER7 (_U_(1) << RTC_MODE1_INTENCLR_PER7_Pos)
-#define RTC_MODE1_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval x Interrupt Enable */
-#define RTC_MODE1_INTENCLR_PER_Msk (_U_(0xFF) << RTC_MODE1_INTENCLR_PER_Pos)
-#define RTC_MODE1_INTENCLR_PER(value) (RTC_MODE1_INTENCLR_PER_Msk & ((value) << RTC_MODE1_INTENCLR_PER_Pos))
-#define RTC_MODE1_INTENCLR_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_CMP0 (_U_(1) << RTC_MODE1_INTENCLR_CMP0_Pos)
-#define RTC_MODE1_INTENCLR_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_CMP1 (_U_(1) << RTC_MODE1_INTENCLR_CMP1_Pos)
-#define RTC_MODE1_INTENCLR_CMP2_Pos 10 /**< \brief (RTC_MODE1_INTENCLR) Compare 2 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_CMP2 (_U_(1) << RTC_MODE1_INTENCLR_CMP2_Pos)
-#define RTC_MODE1_INTENCLR_CMP3_Pos 11 /**< \brief (RTC_MODE1_INTENCLR) Compare 3 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_CMP3 (_U_(1) << RTC_MODE1_INTENCLR_CMP3_Pos)
-#define RTC_MODE1_INTENCLR_CMP_Pos 8 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
-#define RTC_MODE1_INTENCLR_CMP_Msk (_U_(0xF) << RTC_MODE1_INTENCLR_CMP_Pos)
-#define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))
-#define RTC_MODE1_INTENCLR_TAMPER_Pos 14 /**< \brief (RTC_MODE1_INTENCLR) Tamper Enable */
-#define RTC_MODE1_INTENCLR_TAMPER (_U_(0x1) << RTC_MODE1_INTENCLR_TAMPER_Pos)
-#define RTC_MODE1_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
-#define RTC_MODE1_INTENCLR_OVF (_U_(0x1) << RTC_MODE1_INTENCLR_OVF_Pos)
-#define RTC_MODE1_INTENCLR_MASK _U_(0xCFFF) /**< \brief (RTC_MODE1_INTENCLR) MASK Register */
-
-/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE2 MODE2 Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
- uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
- uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
- uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
- uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
- uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
- uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
- uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
- uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 Interrupt Enable */
- uint16_t ALARM1:1; /*!< bit: 9 Alarm 1 Interrupt Enable */
- uint16_t :4; /*!< bit: 10..13 Reserved */
- uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
- uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
- uint16_t ALARM:2; /*!< bit: 8.. 9 Alarm x Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} RTC_MODE2_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */
-#define RTC_MODE2_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */
-
-#define RTC_MODE2_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 0 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_PER0 (_U_(1) << RTC_MODE2_INTENCLR_PER0_Pos)
-#define RTC_MODE2_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 1 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_PER1 (_U_(1) << RTC_MODE2_INTENCLR_PER1_Pos)
-#define RTC_MODE2_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 2 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_PER2 (_U_(1) << RTC_MODE2_INTENCLR_PER2_Pos)
-#define RTC_MODE2_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 3 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_PER3 (_U_(1) << RTC_MODE2_INTENCLR_PER3_Pos)
-#define RTC_MODE2_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 4 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_PER4 (_U_(1) << RTC_MODE2_INTENCLR_PER4_Pos)
-#define RTC_MODE2_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 5 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_PER5 (_U_(1) << RTC_MODE2_INTENCLR_PER5_Pos)
-#define RTC_MODE2_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 6 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_PER6 (_U_(1) << RTC_MODE2_INTENCLR_PER6_Pos)
-#define RTC_MODE2_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 7 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_PER7 (_U_(1) << RTC_MODE2_INTENCLR_PER7_Pos)
-#define RTC_MODE2_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval x Interrupt Enable */
-#define RTC_MODE2_INTENCLR_PER_Msk (_U_(0xFF) << RTC_MODE2_INTENCLR_PER_Pos)
-#define RTC_MODE2_INTENCLR_PER(value) (RTC_MODE2_INTENCLR_PER_Msk & ((value) << RTC_MODE2_INTENCLR_PER_Pos))
-#define RTC_MODE2_INTENCLR_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_ALARM0 (_U_(1) << RTC_MODE2_INTENCLR_ALARM0_Pos)
-#define RTC_MODE2_INTENCLR_ALARM1_Pos 9 /**< \brief (RTC_MODE2_INTENCLR) Alarm 1 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_ALARM1 (_U_(1) << RTC_MODE2_INTENCLR_ALARM1_Pos)
-#define RTC_MODE2_INTENCLR_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
-#define RTC_MODE2_INTENCLR_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTENCLR_ALARM_Pos)
-#define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))
-#define RTC_MODE2_INTENCLR_TAMPER_Pos 14 /**< \brief (RTC_MODE2_INTENCLR) Tamper Enable */
-#define RTC_MODE2_INTENCLR_TAMPER (_U_(0x1) << RTC_MODE2_INTENCLR_TAMPER_Pos)
-#define RTC_MODE2_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
-#define RTC_MODE2_INTENCLR_OVF (_U_(0x1) << RTC_MODE2_INTENCLR_OVF_Pos)
-#define RTC_MODE2_INTENCLR_MASK _U_(0xC3FF) /**< \brief (RTC_MODE2_INTENCLR) MASK Register */
-
-/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE0 MODE0 Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
- uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
- uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
- uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
- uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
- uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
- uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
- uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
- uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */
- uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */
- uint16_t :4; /*!< bit: 10..13 Reserved */
- uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
- uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
- uint16_t CMP:2; /*!< bit: 8.. 9 Compare x Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} RTC_MODE0_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */
-#define RTC_MODE0_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */
-
-#define RTC_MODE0_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 0 Interrupt Enable */
-#define RTC_MODE0_INTENSET_PER0 (_U_(1) << RTC_MODE0_INTENSET_PER0_Pos)
-#define RTC_MODE0_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 1 Interrupt Enable */
-#define RTC_MODE0_INTENSET_PER1 (_U_(1) << RTC_MODE0_INTENSET_PER1_Pos)
-#define RTC_MODE0_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 2 Interrupt Enable */
-#define RTC_MODE0_INTENSET_PER2 (_U_(1) << RTC_MODE0_INTENSET_PER2_Pos)
-#define RTC_MODE0_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 3 Interrupt Enable */
-#define RTC_MODE0_INTENSET_PER3 (_U_(1) << RTC_MODE0_INTENSET_PER3_Pos)
-#define RTC_MODE0_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 4 Interrupt Enable */
-#define RTC_MODE0_INTENSET_PER4 (_U_(1) << RTC_MODE0_INTENSET_PER4_Pos)
-#define RTC_MODE0_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 5 Interrupt Enable */
-#define RTC_MODE0_INTENSET_PER5 (_U_(1) << RTC_MODE0_INTENSET_PER5_Pos)
-#define RTC_MODE0_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 6 Interrupt Enable */
-#define RTC_MODE0_INTENSET_PER6 (_U_(1) << RTC_MODE0_INTENSET_PER6_Pos)
-#define RTC_MODE0_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 7 Interrupt Enable */
-#define RTC_MODE0_INTENSET_PER7 (_U_(1) << RTC_MODE0_INTENSET_PER7_Pos)
-#define RTC_MODE0_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval x Interrupt Enable */
-#define RTC_MODE0_INTENSET_PER_Msk (_U_(0xFF) << RTC_MODE0_INTENSET_PER_Pos)
-#define RTC_MODE0_INTENSET_PER(value) (RTC_MODE0_INTENSET_PER_Msk & ((value) << RTC_MODE0_INTENSET_PER_Pos))
-#define RTC_MODE0_INTENSET_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */
-#define RTC_MODE0_INTENSET_CMP0 (_U_(1) << RTC_MODE0_INTENSET_CMP0_Pos)
-#define RTC_MODE0_INTENSET_CMP1_Pos 9 /**< \brief (RTC_MODE0_INTENSET) Compare 1 Interrupt Enable */
-#define RTC_MODE0_INTENSET_CMP1 (_U_(1) << RTC_MODE0_INTENSET_CMP1_Pos)
-#define RTC_MODE0_INTENSET_CMP_Pos 8 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
-#define RTC_MODE0_INTENSET_CMP_Msk (_U_(0x3) << RTC_MODE0_INTENSET_CMP_Pos)
-#define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))
-#define RTC_MODE0_INTENSET_TAMPER_Pos 14 /**< \brief (RTC_MODE0_INTENSET) Tamper Enable */
-#define RTC_MODE0_INTENSET_TAMPER (_U_(0x1) << RTC_MODE0_INTENSET_TAMPER_Pos)
-#define RTC_MODE0_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
-#define RTC_MODE0_INTENSET_OVF (_U_(0x1) << RTC_MODE0_INTENSET_OVF_Pos)
-#define RTC_MODE0_INTENSET_MASK _U_(0xC3FF) /**< \brief (RTC_MODE0_INTENSET) MASK Register */
-
-/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE1 MODE1 Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
- uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
- uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
- uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
- uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
- uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
- uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
- uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
- uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */
- uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */
- uint16_t CMP2:1; /*!< bit: 10 Compare 2 Interrupt Enable */
- uint16_t CMP3:1; /*!< bit: 11 Compare 3 Interrupt Enable */
- uint16_t :2; /*!< bit: 12..13 Reserved */
- uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
- uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
- uint16_t CMP:4; /*!< bit: 8..11 Compare x Interrupt Enable */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} RTC_MODE1_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */
-#define RTC_MODE1_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */
-
-#define RTC_MODE1_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 0 Interrupt Enable */
-#define RTC_MODE1_INTENSET_PER0 (_U_(1) << RTC_MODE1_INTENSET_PER0_Pos)
-#define RTC_MODE1_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 1 Interrupt Enable */
-#define RTC_MODE1_INTENSET_PER1 (_U_(1) << RTC_MODE1_INTENSET_PER1_Pos)
-#define RTC_MODE1_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 2 Interrupt Enable */
-#define RTC_MODE1_INTENSET_PER2 (_U_(1) << RTC_MODE1_INTENSET_PER2_Pos)
-#define RTC_MODE1_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 3 Interrupt Enable */
-#define RTC_MODE1_INTENSET_PER3 (_U_(1) << RTC_MODE1_INTENSET_PER3_Pos)
-#define RTC_MODE1_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 4 Interrupt Enable */
-#define RTC_MODE1_INTENSET_PER4 (_U_(1) << RTC_MODE1_INTENSET_PER4_Pos)
-#define RTC_MODE1_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 5 Interrupt Enable */
-#define RTC_MODE1_INTENSET_PER5 (_U_(1) << RTC_MODE1_INTENSET_PER5_Pos)
-#define RTC_MODE1_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 6 Interrupt Enable */
-#define RTC_MODE1_INTENSET_PER6 (_U_(1) << RTC_MODE1_INTENSET_PER6_Pos)
-#define RTC_MODE1_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 7 Interrupt Enable */
-#define RTC_MODE1_INTENSET_PER7 (_U_(1) << RTC_MODE1_INTENSET_PER7_Pos)
-#define RTC_MODE1_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval x Interrupt Enable */
-#define RTC_MODE1_INTENSET_PER_Msk (_U_(0xFF) << RTC_MODE1_INTENSET_PER_Pos)
-#define RTC_MODE1_INTENSET_PER(value) (RTC_MODE1_INTENSET_PER_Msk & ((value) << RTC_MODE1_INTENSET_PER_Pos))
-#define RTC_MODE1_INTENSET_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */
-#define RTC_MODE1_INTENSET_CMP0 (_U_(1) << RTC_MODE1_INTENSET_CMP0_Pos)
-#define RTC_MODE1_INTENSET_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */
-#define RTC_MODE1_INTENSET_CMP1 (_U_(1) << RTC_MODE1_INTENSET_CMP1_Pos)
-#define RTC_MODE1_INTENSET_CMP2_Pos 10 /**< \brief (RTC_MODE1_INTENSET) Compare 2 Interrupt Enable */
-#define RTC_MODE1_INTENSET_CMP2 (_U_(1) << RTC_MODE1_INTENSET_CMP2_Pos)
-#define RTC_MODE1_INTENSET_CMP3_Pos 11 /**< \brief (RTC_MODE1_INTENSET) Compare 3 Interrupt Enable */
-#define RTC_MODE1_INTENSET_CMP3 (_U_(1) << RTC_MODE1_INTENSET_CMP3_Pos)
-#define RTC_MODE1_INTENSET_CMP_Pos 8 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
-#define RTC_MODE1_INTENSET_CMP_Msk (_U_(0xF) << RTC_MODE1_INTENSET_CMP_Pos)
-#define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))
-#define RTC_MODE1_INTENSET_TAMPER_Pos 14 /**< \brief (RTC_MODE1_INTENSET) Tamper Enable */
-#define RTC_MODE1_INTENSET_TAMPER (_U_(0x1) << RTC_MODE1_INTENSET_TAMPER_Pos)
-#define RTC_MODE1_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
-#define RTC_MODE1_INTENSET_OVF (_U_(0x1) << RTC_MODE1_INTENSET_OVF_Pos)
-#define RTC_MODE1_INTENSET_MASK _U_(0xCFFF) /**< \brief (RTC_MODE1_INTENSET) MASK Register */
-
-/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE2 MODE2 Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Enable */
- uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Enable */
- uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Enable */
- uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Enable */
- uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Enable */
- uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Enable */
- uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Enable */
- uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Enable */
- uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 Interrupt Enable */
- uint16_t ALARM1:1; /*!< bit: 9 Alarm 1 Interrupt Enable */
- uint16_t :4; /*!< bit: 10..13 Reserved */
- uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
- uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Enable */
- uint16_t ALARM:2; /*!< bit: 8.. 9 Alarm x Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} RTC_MODE2_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */
-#define RTC_MODE2_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */
-
-#define RTC_MODE2_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 0 Enable */
-#define RTC_MODE2_INTENSET_PER0 (_U_(1) << RTC_MODE2_INTENSET_PER0_Pos)
-#define RTC_MODE2_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 1 Enable */
-#define RTC_MODE2_INTENSET_PER1 (_U_(1) << RTC_MODE2_INTENSET_PER1_Pos)
-#define RTC_MODE2_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 2 Enable */
-#define RTC_MODE2_INTENSET_PER2 (_U_(1) << RTC_MODE2_INTENSET_PER2_Pos)
-#define RTC_MODE2_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 3 Enable */
-#define RTC_MODE2_INTENSET_PER3 (_U_(1) << RTC_MODE2_INTENSET_PER3_Pos)
-#define RTC_MODE2_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 4 Enable */
-#define RTC_MODE2_INTENSET_PER4 (_U_(1) << RTC_MODE2_INTENSET_PER4_Pos)
-#define RTC_MODE2_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 5 Enable */
-#define RTC_MODE2_INTENSET_PER5 (_U_(1) << RTC_MODE2_INTENSET_PER5_Pos)
-#define RTC_MODE2_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 6 Enable */
-#define RTC_MODE2_INTENSET_PER6 (_U_(1) << RTC_MODE2_INTENSET_PER6_Pos)
-#define RTC_MODE2_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 7 Enable */
-#define RTC_MODE2_INTENSET_PER7 (_U_(1) << RTC_MODE2_INTENSET_PER7_Pos)
-#define RTC_MODE2_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval x Enable */
-#define RTC_MODE2_INTENSET_PER_Msk (_U_(0xFF) << RTC_MODE2_INTENSET_PER_Pos)
-#define RTC_MODE2_INTENSET_PER(value) (RTC_MODE2_INTENSET_PER_Msk & ((value) << RTC_MODE2_INTENSET_PER_Pos))
-#define RTC_MODE2_INTENSET_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */
-#define RTC_MODE2_INTENSET_ALARM0 (_U_(1) << RTC_MODE2_INTENSET_ALARM0_Pos)
-#define RTC_MODE2_INTENSET_ALARM1_Pos 9 /**< \brief (RTC_MODE2_INTENSET) Alarm 1 Interrupt Enable */
-#define RTC_MODE2_INTENSET_ALARM1 (_U_(1) << RTC_MODE2_INTENSET_ALARM1_Pos)
-#define RTC_MODE2_INTENSET_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
-#define RTC_MODE2_INTENSET_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTENSET_ALARM_Pos)
-#define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))
-#define RTC_MODE2_INTENSET_TAMPER_Pos 14 /**< \brief (RTC_MODE2_INTENSET) Tamper Enable */
-#define RTC_MODE2_INTENSET_TAMPER (_U_(0x1) << RTC_MODE2_INTENSET_TAMPER_Pos)
-#define RTC_MODE2_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
-#define RTC_MODE2_INTENSET_OVF (_U_(0x1) << RTC_MODE2_INTENSET_OVF_Pos)
-#define RTC_MODE2_INTENSET_MASK _U_(0xC3FF) /**< \brief (RTC_MODE2_INTENSET) MASK Register */
-
-/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */
- __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */
- __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */
- __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */
- __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */
- __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */
- __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */
- __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */
- __I uint16_t CMP0:1; /*!< bit: 8 Compare 0 */
- __I uint16_t CMP1:1; /*!< bit: 9 Compare 1 */
- __I uint16_t :4; /*!< bit: 10..13 Reserved */
- __I uint16_t TAMPER:1; /*!< bit: 14 Tamper */
- __I uint16_t OVF:1; /*!< bit: 15 Overflow */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */
- __I uint16_t CMP:2; /*!< bit: 8.. 9 Compare x */
- __I uint16_t :6; /*!< bit: 10..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} RTC_MODE0_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */
-#define RTC_MODE0_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */
-
-#define RTC_MODE0_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 0 */
-#define RTC_MODE0_INTFLAG_PER0 (_U_(1) << RTC_MODE0_INTFLAG_PER0_Pos)
-#define RTC_MODE0_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 1 */
-#define RTC_MODE0_INTFLAG_PER1 (_U_(1) << RTC_MODE0_INTFLAG_PER1_Pos)
-#define RTC_MODE0_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 2 */
-#define RTC_MODE0_INTFLAG_PER2 (_U_(1) << RTC_MODE0_INTFLAG_PER2_Pos)
-#define RTC_MODE0_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 3 */
-#define RTC_MODE0_INTFLAG_PER3 (_U_(1) << RTC_MODE0_INTFLAG_PER3_Pos)
-#define RTC_MODE0_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 4 */
-#define RTC_MODE0_INTFLAG_PER4 (_U_(1) << RTC_MODE0_INTFLAG_PER4_Pos)
-#define RTC_MODE0_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 5 */
-#define RTC_MODE0_INTFLAG_PER5 (_U_(1) << RTC_MODE0_INTFLAG_PER5_Pos)
-#define RTC_MODE0_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 6 */
-#define RTC_MODE0_INTFLAG_PER6 (_U_(1) << RTC_MODE0_INTFLAG_PER6_Pos)
-#define RTC_MODE0_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 7 */
-#define RTC_MODE0_INTFLAG_PER7 (_U_(1) << RTC_MODE0_INTFLAG_PER7_Pos)
-#define RTC_MODE0_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval x */
-#define RTC_MODE0_INTFLAG_PER_Msk (_U_(0xFF) << RTC_MODE0_INTFLAG_PER_Pos)
-#define RTC_MODE0_INTFLAG_PER(value) (RTC_MODE0_INTFLAG_PER_Msk & ((value) << RTC_MODE0_INTFLAG_PER_Pos))
-#define RTC_MODE0_INTFLAG_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */
-#define RTC_MODE0_INTFLAG_CMP0 (_U_(1) << RTC_MODE0_INTFLAG_CMP0_Pos)
-#define RTC_MODE0_INTFLAG_CMP1_Pos 9 /**< \brief (RTC_MODE0_INTFLAG) Compare 1 */
-#define RTC_MODE0_INTFLAG_CMP1 (_U_(1) << RTC_MODE0_INTFLAG_CMP1_Pos)
-#define RTC_MODE0_INTFLAG_CMP_Pos 8 /**< \brief (RTC_MODE0_INTFLAG) Compare x */
-#define RTC_MODE0_INTFLAG_CMP_Msk (_U_(0x3) << RTC_MODE0_INTFLAG_CMP_Pos)
-#define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))
-#define RTC_MODE0_INTFLAG_TAMPER_Pos 14 /**< \brief (RTC_MODE0_INTFLAG) Tamper */
-#define RTC_MODE0_INTFLAG_TAMPER (_U_(0x1) << RTC_MODE0_INTFLAG_TAMPER_Pos)
-#define RTC_MODE0_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE0_INTFLAG) Overflow */
-#define RTC_MODE0_INTFLAG_OVF (_U_(0x1) << RTC_MODE0_INTFLAG_OVF_Pos)
-#define RTC_MODE0_INTFLAG_MASK _U_(0xC3FF) /**< \brief (RTC_MODE0_INTFLAG) MASK Register */
-
-/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */
- __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */
- __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */
- __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */
- __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */
- __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */
- __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */
- __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */
- __I uint16_t CMP0:1; /*!< bit: 8 Compare 0 */
- __I uint16_t CMP1:1; /*!< bit: 9 Compare 1 */
- __I uint16_t CMP2:1; /*!< bit: 10 Compare 2 */
- __I uint16_t CMP3:1; /*!< bit: 11 Compare 3 */
- __I uint16_t :2; /*!< bit: 12..13 Reserved */
- __I uint16_t TAMPER:1; /*!< bit: 14 Tamper */
- __I uint16_t OVF:1; /*!< bit: 15 Overflow */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */
- __I uint16_t CMP:4; /*!< bit: 8..11 Compare x */
- __I uint16_t :4; /*!< bit: 12..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} RTC_MODE1_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */
-#define RTC_MODE1_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */
-
-#define RTC_MODE1_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 0 */
-#define RTC_MODE1_INTFLAG_PER0 (_U_(1) << RTC_MODE1_INTFLAG_PER0_Pos)
-#define RTC_MODE1_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 1 */
-#define RTC_MODE1_INTFLAG_PER1 (_U_(1) << RTC_MODE1_INTFLAG_PER1_Pos)
-#define RTC_MODE1_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 2 */
-#define RTC_MODE1_INTFLAG_PER2 (_U_(1) << RTC_MODE1_INTFLAG_PER2_Pos)
-#define RTC_MODE1_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 3 */
-#define RTC_MODE1_INTFLAG_PER3 (_U_(1) << RTC_MODE1_INTFLAG_PER3_Pos)
-#define RTC_MODE1_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 4 */
-#define RTC_MODE1_INTFLAG_PER4 (_U_(1) << RTC_MODE1_INTFLAG_PER4_Pos)
-#define RTC_MODE1_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 5 */
-#define RTC_MODE1_INTFLAG_PER5 (_U_(1) << RTC_MODE1_INTFLAG_PER5_Pos)
-#define RTC_MODE1_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 6 */
-#define RTC_MODE1_INTFLAG_PER6 (_U_(1) << RTC_MODE1_INTFLAG_PER6_Pos)
-#define RTC_MODE1_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 7 */
-#define RTC_MODE1_INTFLAG_PER7 (_U_(1) << RTC_MODE1_INTFLAG_PER7_Pos)
-#define RTC_MODE1_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval x */
-#define RTC_MODE1_INTFLAG_PER_Msk (_U_(0xFF) << RTC_MODE1_INTFLAG_PER_Pos)
-#define RTC_MODE1_INTFLAG_PER(value) (RTC_MODE1_INTFLAG_PER_Msk & ((value) << RTC_MODE1_INTFLAG_PER_Pos))
-#define RTC_MODE1_INTFLAG_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */
-#define RTC_MODE1_INTFLAG_CMP0 (_U_(1) << RTC_MODE1_INTFLAG_CMP0_Pos)
-#define RTC_MODE1_INTFLAG_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */
-#define RTC_MODE1_INTFLAG_CMP1 (_U_(1) << RTC_MODE1_INTFLAG_CMP1_Pos)
-#define RTC_MODE1_INTFLAG_CMP2_Pos 10 /**< \brief (RTC_MODE1_INTFLAG) Compare 2 */
-#define RTC_MODE1_INTFLAG_CMP2 (_U_(1) << RTC_MODE1_INTFLAG_CMP2_Pos)
-#define RTC_MODE1_INTFLAG_CMP3_Pos 11 /**< \brief (RTC_MODE1_INTFLAG) Compare 3 */
-#define RTC_MODE1_INTFLAG_CMP3 (_U_(1) << RTC_MODE1_INTFLAG_CMP3_Pos)
-#define RTC_MODE1_INTFLAG_CMP_Pos 8 /**< \brief (RTC_MODE1_INTFLAG) Compare x */
-#define RTC_MODE1_INTFLAG_CMP_Msk (_U_(0xF) << RTC_MODE1_INTFLAG_CMP_Pos)
-#define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))
-#define RTC_MODE1_INTFLAG_TAMPER_Pos 14 /**< \brief (RTC_MODE1_INTFLAG) Tamper */
-#define RTC_MODE1_INTFLAG_TAMPER (_U_(0x1) << RTC_MODE1_INTFLAG_TAMPER_Pos)
-#define RTC_MODE1_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE1_INTFLAG) Overflow */
-#define RTC_MODE1_INTFLAG_OVF (_U_(0x1) << RTC_MODE1_INTFLAG_OVF_Pos)
-#define RTC_MODE1_INTFLAG_MASK _U_(0xCFFF) /**< \brief (RTC_MODE1_INTFLAG) MASK Register */
-
-/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */
- __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */
- __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */
- __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */
- __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */
- __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */
- __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */
- __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */
- __I uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 */
- __I uint16_t ALARM1:1; /*!< bit: 9 Alarm 1 */
- __I uint16_t :4; /*!< bit: 10..13 Reserved */
- __I uint16_t TAMPER:1; /*!< bit: 14 Tamper */
- __I uint16_t OVF:1; /*!< bit: 15 Overflow */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */
- __I uint16_t ALARM:2; /*!< bit: 8.. 9 Alarm x */
- __I uint16_t :6; /*!< bit: 10..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} RTC_MODE2_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */
-#define RTC_MODE2_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */
-
-#define RTC_MODE2_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 0 */
-#define RTC_MODE2_INTFLAG_PER0 (_U_(1) << RTC_MODE2_INTFLAG_PER0_Pos)
-#define RTC_MODE2_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 1 */
-#define RTC_MODE2_INTFLAG_PER1 (_U_(1) << RTC_MODE2_INTFLAG_PER1_Pos)
-#define RTC_MODE2_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 2 */
-#define RTC_MODE2_INTFLAG_PER2 (_U_(1) << RTC_MODE2_INTFLAG_PER2_Pos)
-#define RTC_MODE2_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 3 */
-#define RTC_MODE2_INTFLAG_PER3 (_U_(1) << RTC_MODE2_INTFLAG_PER3_Pos)
-#define RTC_MODE2_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 4 */
-#define RTC_MODE2_INTFLAG_PER4 (_U_(1) << RTC_MODE2_INTFLAG_PER4_Pos)
-#define RTC_MODE2_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 5 */
-#define RTC_MODE2_INTFLAG_PER5 (_U_(1) << RTC_MODE2_INTFLAG_PER5_Pos)
-#define RTC_MODE2_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 6 */
-#define RTC_MODE2_INTFLAG_PER6 (_U_(1) << RTC_MODE2_INTFLAG_PER6_Pos)
-#define RTC_MODE2_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 7 */
-#define RTC_MODE2_INTFLAG_PER7 (_U_(1) << RTC_MODE2_INTFLAG_PER7_Pos)
-#define RTC_MODE2_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval x */
-#define RTC_MODE2_INTFLAG_PER_Msk (_U_(0xFF) << RTC_MODE2_INTFLAG_PER_Pos)
-#define RTC_MODE2_INTFLAG_PER(value) (RTC_MODE2_INTFLAG_PER_Msk & ((value) << RTC_MODE2_INTFLAG_PER_Pos))
-#define RTC_MODE2_INTFLAG_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */
-#define RTC_MODE2_INTFLAG_ALARM0 (_U_(1) << RTC_MODE2_INTFLAG_ALARM0_Pos)
-#define RTC_MODE2_INTFLAG_ALARM1_Pos 9 /**< \brief (RTC_MODE2_INTFLAG) Alarm 1 */
-#define RTC_MODE2_INTFLAG_ALARM1 (_U_(1) << RTC_MODE2_INTFLAG_ALARM1_Pos)
-#define RTC_MODE2_INTFLAG_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
-#define RTC_MODE2_INTFLAG_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTFLAG_ALARM_Pos)
-#define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))
-#define RTC_MODE2_INTFLAG_TAMPER_Pos 14 /**< \brief (RTC_MODE2_INTFLAG) Tamper */
-#define RTC_MODE2_INTFLAG_TAMPER (_U_(0x1) << RTC_MODE2_INTFLAG_TAMPER_Pos)
-#define RTC_MODE2_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE2_INTFLAG) Overflow */
-#define RTC_MODE2_INTFLAG_OVF (_U_(0x1) << RTC_MODE2_INTFLAG_OVF_Pos)
-#define RTC_MODE2_INTFLAG_MASK _U_(0xC3FF) /**< \brief (RTC_MODE2_INTFLAG) MASK Register */
-
-/* -------- RTC_DBGCTRL : (RTC Offset: 0x0E) (R/W 8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} RTC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_DBGCTRL_OFFSET 0x0E /**< \brief (RTC_DBGCTRL offset) Debug Control */
-#define RTC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (RTC_DBGCTRL reset_value) Debug Control */
-
-#define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */
-#define RTC_DBGCTRL_DBGRUN (_U_(0x1) << RTC_DBGCTRL_DBGRUN_Pos)
-#define RTC_DBGCTRL_MASK _U_(0x01) /**< \brief (RTC_DBGCTRL) MASK Register */
-
-/* -------- RTC_MODE0_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE0 MODE0 Synchronization Busy Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Busy */
- uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */
- uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */
- uint32_t COUNT:1; /*!< bit: 3 COUNT Register Busy */
- uint32_t :1; /*!< bit: 4 Reserved */
- uint32_t COMP0:1; /*!< bit: 5 COMP 0 Register Busy */
- uint32_t COMP1:1; /*!< bit: 6 COMP 1 Register Busy */
- uint32_t :8; /*!< bit: 7..14 Reserved */
- uint32_t COUNTSYNC:1; /*!< bit: 15 Count Synchronization Enable Bit Busy */
- uint32_t GP0:1; /*!< bit: 16 General Purpose 0 Register Busy */
- uint32_t GP1:1; /*!< bit: 17 General Purpose 1 Register Busy */
- uint32_t GP2:1; /*!< bit: 18 General Purpose 2 Register Busy */
- uint32_t GP3:1; /*!< bit: 19 General Purpose 3 Register Busy */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :5; /*!< bit: 0.. 4 Reserved */
- uint32_t COMP:2; /*!< bit: 5.. 6 COMP x Register Busy */
- uint32_t :9; /*!< bit: 7..15 Reserved */
- uint32_t GP:4; /*!< bit: 16..19 General Purpose x Register Busy */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} RTC_MODE0_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE0_SYNCBUSY offset) MODE0 Synchronization Busy Status */
-#define RTC_MODE0_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_SYNCBUSY reset_value) MODE0 Synchronization Busy Status */
-
-#define RTC_MODE0_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE0_SYNCBUSY) Software Reset Busy */
-#define RTC_MODE0_SYNCBUSY_SWRST (_U_(0x1) << RTC_MODE0_SYNCBUSY_SWRST_Pos)
-#define RTC_MODE0_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE0_SYNCBUSY) Enable Bit Busy */
-#define RTC_MODE0_SYNCBUSY_ENABLE (_U_(0x1) << RTC_MODE0_SYNCBUSY_ENABLE_Pos)
-#define RTC_MODE0_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE0_SYNCBUSY) FREQCORR Register Busy */
-#define RTC_MODE0_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE0_SYNCBUSY_FREQCORR_Pos)
-#define RTC_MODE0_SYNCBUSY_COUNT_Pos 3 /**< \brief (RTC_MODE0_SYNCBUSY) COUNT Register Busy */
-#define RTC_MODE0_SYNCBUSY_COUNT (_U_(0x1) << RTC_MODE0_SYNCBUSY_COUNT_Pos)
-#define RTC_MODE0_SYNCBUSY_COMP0_Pos 5 /**< \brief (RTC_MODE0_SYNCBUSY) COMP 0 Register Busy */
-#define RTC_MODE0_SYNCBUSY_COMP0 (_U_(1) << RTC_MODE0_SYNCBUSY_COMP0_Pos)
-#define RTC_MODE0_SYNCBUSY_COMP1_Pos 6 /**< \brief (RTC_MODE0_SYNCBUSY) COMP 1 Register Busy */
-#define RTC_MODE0_SYNCBUSY_COMP1 (_U_(1) << RTC_MODE0_SYNCBUSY_COMP1_Pos)
-#define RTC_MODE0_SYNCBUSY_COMP_Pos 5 /**< \brief (RTC_MODE0_SYNCBUSY) COMP x Register Busy */
-#define RTC_MODE0_SYNCBUSY_COMP_Msk (_U_(0x3) << RTC_MODE0_SYNCBUSY_COMP_Pos)
-#define RTC_MODE0_SYNCBUSY_COMP(value) (RTC_MODE0_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE0_SYNCBUSY_COMP_Pos))
-#define RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE0_SYNCBUSY) Count Synchronization Enable Bit Busy */
-#define RTC_MODE0_SYNCBUSY_COUNTSYNC (_U_(0x1) << RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos)
-#define RTC_MODE0_SYNCBUSY_GP0_Pos 16 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 0 Register Busy */
-#define RTC_MODE0_SYNCBUSY_GP0 (_U_(1) << RTC_MODE0_SYNCBUSY_GP0_Pos)
-#define RTC_MODE0_SYNCBUSY_GP1_Pos 17 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 1 Register Busy */
-#define RTC_MODE0_SYNCBUSY_GP1 (_U_(1) << RTC_MODE0_SYNCBUSY_GP1_Pos)
-#define RTC_MODE0_SYNCBUSY_GP2_Pos 18 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 2 Register Busy */
-#define RTC_MODE0_SYNCBUSY_GP2 (_U_(1) << RTC_MODE0_SYNCBUSY_GP2_Pos)
-#define RTC_MODE0_SYNCBUSY_GP3_Pos 19 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 3 Register Busy */
-#define RTC_MODE0_SYNCBUSY_GP3 (_U_(1) << RTC_MODE0_SYNCBUSY_GP3_Pos)
-#define RTC_MODE0_SYNCBUSY_GP_Pos 16 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose x Register Busy */
-#define RTC_MODE0_SYNCBUSY_GP_Msk (_U_(0xF) << RTC_MODE0_SYNCBUSY_GP_Pos)
-#define RTC_MODE0_SYNCBUSY_GP(value) (RTC_MODE0_SYNCBUSY_GP_Msk & ((value) << RTC_MODE0_SYNCBUSY_GP_Pos))
-#define RTC_MODE0_SYNCBUSY_MASK _U_(0x000F806F) /**< \brief (RTC_MODE0_SYNCBUSY) MASK Register */
-
-/* -------- RTC_MODE1_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE1 MODE1 Synchronization Busy Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Bit Busy */
- uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */
- uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */
- uint32_t COUNT:1; /*!< bit: 3 COUNT Register Busy */
- uint32_t PER:1; /*!< bit: 4 PER Register Busy */
- uint32_t COMP0:1; /*!< bit: 5 COMP 0 Register Busy */
- uint32_t COMP1:1; /*!< bit: 6 COMP 1 Register Busy */
- uint32_t COMP2:1; /*!< bit: 7 COMP 2 Register Busy */
- uint32_t COMP3:1; /*!< bit: 8 COMP 3 Register Busy */
- uint32_t :6; /*!< bit: 9..14 Reserved */
- uint32_t COUNTSYNC:1; /*!< bit: 15 Count Synchronization Enable Bit Busy */
- uint32_t GP0:1; /*!< bit: 16 General Purpose 0 Register Busy */
- uint32_t GP1:1; /*!< bit: 17 General Purpose 1 Register Busy */
- uint32_t GP2:1; /*!< bit: 18 General Purpose 2 Register Busy */
- uint32_t GP3:1; /*!< bit: 19 General Purpose 3 Register Busy */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :5; /*!< bit: 0.. 4 Reserved */
- uint32_t COMP:4; /*!< bit: 5.. 8 COMP x Register Busy */
- uint32_t :7; /*!< bit: 9..15 Reserved */
- uint32_t GP:4; /*!< bit: 16..19 General Purpose x Register Busy */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} RTC_MODE1_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE1_SYNCBUSY offset) MODE1 Synchronization Busy Status */
-#define RTC_MODE1_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE1_SYNCBUSY reset_value) MODE1 Synchronization Busy Status */
-
-#define RTC_MODE1_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE1_SYNCBUSY) Software Reset Bit Busy */
-#define RTC_MODE1_SYNCBUSY_SWRST (_U_(0x1) << RTC_MODE1_SYNCBUSY_SWRST_Pos)
-#define RTC_MODE1_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE1_SYNCBUSY) Enable Bit Busy */
-#define RTC_MODE1_SYNCBUSY_ENABLE (_U_(0x1) << RTC_MODE1_SYNCBUSY_ENABLE_Pos)
-#define RTC_MODE1_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE1_SYNCBUSY) FREQCORR Register Busy */
-#define RTC_MODE1_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE1_SYNCBUSY_FREQCORR_Pos)
-#define RTC_MODE1_SYNCBUSY_COUNT_Pos 3 /**< \brief (RTC_MODE1_SYNCBUSY) COUNT Register Busy */
-#define RTC_MODE1_SYNCBUSY_COUNT (_U_(0x1) << RTC_MODE1_SYNCBUSY_COUNT_Pos)
-#define RTC_MODE1_SYNCBUSY_PER_Pos 4 /**< \brief (RTC_MODE1_SYNCBUSY) PER Register Busy */
-#define RTC_MODE1_SYNCBUSY_PER (_U_(0x1) << RTC_MODE1_SYNCBUSY_PER_Pos)
-#define RTC_MODE1_SYNCBUSY_COMP0_Pos 5 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 0 Register Busy */
-#define RTC_MODE1_SYNCBUSY_COMP0 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP0_Pos)
-#define RTC_MODE1_SYNCBUSY_COMP1_Pos 6 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 1 Register Busy */
-#define RTC_MODE1_SYNCBUSY_COMP1 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP1_Pos)
-#define RTC_MODE1_SYNCBUSY_COMP2_Pos 7 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 2 Register Busy */
-#define RTC_MODE1_SYNCBUSY_COMP2 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP2_Pos)
-#define RTC_MODE1_SYNCBUSY_COMP3_Pos 8 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 3 Register Busy */
-#define RTC_MODE1_SYNCBUSY_COMP3 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP3_Pos)
-#define RTC_MODE1_SYNCBUSY_COMP_Pos 5 /**< \brief (RTC_MODE1_SYNCBUSY) COMP x Register Busy */
-#define RTC_MODE1_SYNCBUSY_COMP_Msk (_U_(0xF) << RTC_MODE1_SYNCBUSY_COMP_Pos)
-#define RTC_MODE1_SYNCBUSY_COMP(value) (RTC_MODE1_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE1_SYNCBUSY_COMP_Pos))
-#define RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE1_SYNCBUSY) Count Synchronization Enable Bit Busy */
-#define RTC_MODE1_SYNCBUSY_COUNTSYNC (_U_(0x1) << RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos)
-#define RTC_MODE1_SYNCBUSY_GP0_Pos 16 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 0 Register Busy */
-#define RTC_MODE1_SYNCBUSY_GP0 (_U_(1) << RTC_MODE1_SYNCBUSY_GP0_Pos)
-#define RTC_MODE1_SYNCBUSY_GP1_Pos 17 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 1 Register Busy */
-#define RTC_MODE1_SYNCBUSY_GP1 (_U_(1) << RTC_MODE1_SYNCBUSY_GP1_Pos)
-#define RTC_MODE1_SYNCBUSY_GP2_Pos 18 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 2 Register Busy */
-#define RTC_MODE1_SYNCBUSY_GP2 (_U_(1) << RTC_MODE1_SYNCBUSY_GP2_Pos)
-#define RTC_MODE1_SYNCBUSY_GP3_Pos 19 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 3 Register Busy */
-#define RTC_MODE1_SYNCBUSY_GP3 (_U_(1) << RTC_MODE1_SYNCBUSY_GP3_Pos)
-#define RTC_MODE1_SYNCBUSY_GP_Pos 16 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose x Register Busy */
-#define RTC_MODE1_SYNCBUSY_GP_Msk (_U_(0xF) << RTC_MODE1_SYNCBUSY_GP_Pos)
-#define RTC_MODE1_SYNCBUSY_GP(value) (RTC_MODE1_SYNCBUSY_GP_Msk & ((value) << RTC_MODE1_SYNCBUSY_GP_Pos))
-#define RTC_MODE1_SYNCBUSY_MASK _U_(0x000F81FF) /**< \brief (RTC_MODE1_SYNCBUSY) MASK Register */
-
-/* -------- RTC_MODE2_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE2 MODE2 Synchronization Busy Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Bit Busy */
- uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */
- uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */
- uint32_t CLOCK:1; /*!< bit: 3 CLOCK Register Busy */
- uint32_t :1; /*!< bit: 4 Reserved */
- uint32_t ALARM0:1; /*!< bit: 5 ALARM 0 Register Busy */
- uint32_t ALARM1:1; /*!< bit: 6 ALARM 1 Register Busy */
- uint32_t :4; /*!< bit: 7..10 Reserved */
- uint32_t MASK0:1; /*!< bit: 11 MASK 0 Register Busy */
- uint32_t MASK1:1; /*!< bit: 12 MASK 1 Register Busy */
- uint32_t :2; /*!< bit: 13..14 Reserved */
- uint32_t CLOCKSYNC:1; /*!< bit: 15 Clock Synchronization Enable Bit Busy */
- uint32_t GP0:1; /*!< bit: 16 General Purpose 0 Register Busy */
- uint32_t GP1:1; /*!< bit: 17 General Purpose 1 Register Busy */
- uint32_t GP2:1; /*!< bit: 18 General Purpose 2 Register Busy */
- uint32_t GP3:1; /*!< bit: 19 General Purpose 3 Register Busy */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :5; /*!< bit: 0.. 4 Reserved */
- uint32_t ALARM:2; /*!< bit: 5.. 6 ALARM x Register Busy */
- uint32_t :4; /*!< bit: 7..10 Reserved */
- uint32_t MASK:2; /*!< bit: 11..12 MASK x Register Busy */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t GP:4; /*!< bit: 16..19 General Purpose x Register Busy */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} RTC_MODE2_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE2_SYNCBUSY offset) MODE2 Synchronization Busy Status */
-#define RTC_MODE2_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_SYNCBUSY reset_value) MODE2 Synchronization Busy Status */
-
-#define RTC_MODE2_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE2_SYNCBUSY) Software Reset Bit Busy */
-#define RTC_MODE2_SYNCBUSY_SWRST (_U_(0x1) << RTC_MODE2_SYNCBUSY_SWRST_Pos)
-#define RTC_MODE2_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE2_SYNCBUSY) Enable Bit Busy */
-#define RTC_MODE2_SYNCBUSY_ENABLE (_U_(0x1) << RTC_MODE2_SYNCBUSY_ENABLE_Pos)
-#define RTC_MODE2_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE2_SYNCBUSY) FREQCORR Register Busy */
-#define RTC_MODE2_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE2_SYNCBUSY_FREQCORR_Pos)
-#define RTC_MODE2_SYNCBUSY_CLOCK_Pos 3 /**< \brief (RTC_MODE2_SYNCBUSY) CLOCK Register Busy */
-#define RTC_MODE2_SYNCBUSY_CLOCK (_U_(0x1) << RTC_MODE2_SYNCBUSY_CLOCK_Pos)
-#define RTC_MODE2_SYNCBUSY_ALARM0_Pos 5 /**< \brief (RTC_MODE2_SYNCBUSY) ALARM 0 Register Busy */
-#define RTC_MODE2_SYNCBUSY_ALARM0 (_U_(1) << RTC_MODE2_SYNCBUSY_ALARM0_Pos)
-#define RTC_MODE2_SYNCBUSY_ALARM1_Pos 6 /**< \brief (RTC_MODE2_SYNCBUSY) ALARM 1 Register Busy */
-#define RTC_MODE2_SYNCBUSY_ALARM1 (_U_(1) << RTC_MODE2_SYNCBUSY_ALARM1_Pos)
-#define RTC_MODE2_SYNCBUSY_ALARM_Pos 5 /**< \brief (RTC_MODE2_SYNCBUSY) ALARM x Register Busy */
-#define RTC_MODE2_SYNCBUSY_ALARM_Msk (_U_(0x3) << RTC_MODE2_SYNCBUSY_ALARM_Pos)
-#define RTC_MODE2_SYNCBUSY_ALARM(value) (RTC_MODE2_SYNCBUSY_ALARM_Msk & ((value) << RTC_MODE2_SYNCBUSY_ALARM_Pos))
-#define RTC_MODE2_SYNCBUSY_MASK0_Pos 11 /**< \brief (RTC_MODE2_SYNCBUSY) MASK 0 Register Busy */
-#define RTC_MODE2_SYNCBUSY_MASK0 (_U_(1) << RTC_MODE2_SYNCBUSY_MASK0_Pos)
-#define RTC_MODE2_SYNCBUSY_MASK1_Pos 12 /**< \brief (RTC_MODE2_SYNCBUSY) MASK 1 Register Busy */
-#define RTC_MODE2_SYNCBUSY_MASK1 (_U_(1) << RTC_MODE2_SYNCBUSY_MASK1_Pos)
-#define RTC_MODE2_SYNCBUSY_MASK_Pos 11 /**< \brief (RTC_MODE2_SYNCBUSY) MASK x Register Busy */
-#define RTC_MODE2_SYNCBUSY_MASK_Msk (_U_(0x3) << RTC_MODE2_SYNCBUSY_MASK_Pos)
-#define RTC_MODE2_SYNCBUSY_MASK(value) (RTC_MODE2_SYNCBUSY_MASK_Msk & ((value) << RTC_MODE2_SYNCBUSY_MASK_Pos))
-#define RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos 15 /**< \brief (RTC_MODE2_SYNCBUSY) Clock Synchronization Enable Bit Busy */
-#define RTC_MODE2_SYNCBUSY_CLOCKSYNC (_U_(0x1) << RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos)
-#define RTC_MODE2_SYNCBUSY_GP0_Pos 16 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 0 Register Busy */
-#define RTC_MODE2_SYNCBUSY_GP0 (_U_(1) << RTC_MODE2_SYNCBUSY_GP0_Pos)
-#define RTC_MODE2_SYNCBUSY_GP1_Pos 17 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 1 Register Busy */
-#define RTC_MODE2_SYNCBUSY_GP1 (_U_(1) << RTC_MODE2_SYNCBUSY_GP1_Pos)
-#define RTC_MODE2_SYNCBUSY_GP2_Pos 18 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 2 Register Busy */
-#define RTC_MODE2_SYNCBUSY_GP2 (_U_(1) << RTC_MODE2_SYNCBUSY_GP2_Pos)
-#define RTC_MODE2_SYNCBUSY_GP3_Pos 19 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 3 Register Busy */
-#define RTC_MODE2_SYNCBUSY_GP3 (_U_(1) << RTC_MODE2_SYNCBUSY_GP3_Pos)
-#define RTC_MODE2_SYNCBUSY_GP_Pos 16 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose x Register Busy */
-#define RTC_MODE2_SYNCBUSY_GP_Msk (_U_(0xF) << RTC_MODE2_SYNCBUSY_GP_Pos)
-#define RTC_MODE2_SYNCBUSY_GP(value) (RTC_MODE2_SYNCBUSY_GP_Msk & ((value) << RTC_MODE2_SYNCBUSY_GP_Pos))
-#define RTC_MODE2_SYNCBUSY_MASK_ _U_(0x000F986F) /**< \brief (RTC_MODE2_SYNCBUSY) MASK Register */
-
-/* -------- RTC_FREQCORR : (RTC Offset: 0x14) (R/W 8) Frequency Correction -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
- uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} RTC_FREQCORR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_FREQCORR_OFFSET 0x14 /**< \brief (RTC_FREQCORR offset) Frequency Correction */
-#define RTC_FREQCORR_RESETVALUE _U_(0x00) /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */
-
-#define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */
-#define RTC_FREQCORR_VALUE_Msk (_U_(0x7F) << RTC_FREQCORR_VALUE_Pos)
-#define RTC_FREQCORR_VALUE(value) (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))
-#define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */
-#define RTC_FREQCORR_SIGN (_U_(0x1) << RTC_FREQCORR_SIGN_Pos)
-#define RTC_FREQCORR_MASK _U_(0xFF) /**< \brief (RTC_FREQCORR) MASK Register */
-
-/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Counter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} RTC_MODE0_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_COUNT_OFFSET 0x18 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */
-#define RTC_MODE0_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */
-
-#define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */
-#define RTC_MODE0_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_COUNT_COUNT_Pos)
-#define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))
-#define RTC_MODE0_COUNT_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_COUNT) MASK Register */
-
-/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Counter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} RTC_MODE1_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_COUNT_OFFSET 0x18 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */
-#define RTC_MODE1_COUNT_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */
-
-#define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */
-#define RTC_MODE1_COUNT_COUNT_Msk (_U_(0xFFFF) << RTC_MODE1_COUNT_COUNT_Pos)
-#define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))
-#define RTC_MODE1_COUNT_MASK _U_(0xFFFF) /**< \brief (RTC_MODE1_COUNT) MASK Register */
-
-/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2 Clock Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
- uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
- uint32_t HOUR:5; /*!< bit: 12..16 Hour */
- uint32_t DAY:5; /*!< bit: 17..21 Day */
- uint32_t MONTH:4; /*!< bit: 22..25 Month */
- uint32_t YEAR:6; /*!< bit: 26..31 Year */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} RTC_MODE2_CLOCK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_CLOCK_OFFSET 0x18 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */
-#define RTC_MODE2_CLOCK_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */
-
-#define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */
-#define RTC_MODE2_CLOCK_SECOND_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_SECOND_Pos)
-#define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))
-#define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */
-#define RTC_MODE2_CLOCK_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_MINUTE_Pos)
-#define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))
-#define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */
-#define RTC_MODE2_CLOCK_HOUR_Msk (_U_(0x1F) << RTC_MODE2_CLOCK_HOUR_Pos)
-#define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))
-#define RTC_MODE2_CLOCK_HOUR_AM_Val _U_(0x0) /**< \brief (RTC_MODE2_CLOCK) AM when CLKREP in 12-hour */
-#define RTC_MODE2_CLOCK_HOUR_PM_Val _U_(0x10) /**< \brief (RTC_MODE2_CLOCK) PM when CLKREP in 12-hour */
-#define RTC_MODE2_CLOCK_HOUR_AM (RTC_MODE2_CLOCK_HOUR_AM_Val << RTC_MODE2_CLOCK_HOUR_Pos)
-#define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos)
-#define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */
-#define RTC_MODE2_CLOCK_DAY_Msk (_U_(0x1F) << RTC_MODE2_CLOCK_DAY_Pos)
-#define RTC_MODE2_CLOCK_DAY(value) (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))
-#define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */
-#define RTC_MODE2_CLOCK_MONTH_Msk (_U_(0xF) << RTC_MODE2_CLOCK_MONTH_Pos)
-#define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))
-#define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */
-#define RTC_MODE2_CLOCK_YEAR_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_YEAR_Pos)
-#define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))
-#define RTC_MODE2_CLOCK_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_CLOCK) MASK Register */
-
-/* -------- RTC_MODE1_PER : (RTC Offset: 0x1C) (R/W 16) MODE1 MODE1 Counter Period -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t PER:16; /*!< bit: 0..15 Counter Period */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} RTC_MODE1_PER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_PER_OFFSET 0x1C /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */
-#define RTC_MODE1_PER_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */
-
-#define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */
-#define RTC_MODE1_PER_PER_Msk (_U_(0xFFFF) << RTC_MODE1_PER_PER_Pos)
-#define RTC_MODE1_PER_PER(value) (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))
-#define RTC_MODE1_PER_MASK _U_(0xFFFF) /**< \brief (RTC_MODE1_PER) MASK Register */
-
-/* -------- RTC_MODE0_COMP : (RTC Offset: 0x20) (R/W 32) MODE0 MODE0 Compare n Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} RTC_MODE0_COMP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_COMP_OFFSET 0x20 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */
-#define RTC_MODE0_COMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */
-
-#define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */
-#define RTC_MODE0_COMP_COMP_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_COMP_COMP_Pos)
-#define RTC_MODE0_COMP_COMP(value) (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))
-#define RTC_MODE0_COMP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_COMP) MASK Register */
-
-/* -------- RTC_MODE1_COMP : (RTC Offset: 0x20) (R/W 16) MODE1 MODE1 Compare n Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} RTC_MODE1_COMP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_COMP_OFFSET 0x20 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */
-#define RTC_MODE1_COMP_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */
-
-#define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */
-#define RTC_MODE1_COMP_COMP_Msk (_U_(0xFFFF) << RTC_MODE1_COMP_COMP_Pos)
-#define RTC_MODE1_COMP_COMP(value) (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))
-#define RTC_MODE1_COMP_MASK _U_(0xFFFF) /**< \brief (RTC_MODE1_COMP) MASK Register */
-
-/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x20) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
- uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
- uint32_t HOUR:5; /*!< bit: 12..16 Hour */
- uint32_t DAY:5; /*!< bit: 17..21 Day */
- uint32_t MONTH:4; /*!< bit: 22..25 Month */
- uint32_t YEAR:6; /*!< bit: 26..31 Year */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} RTC_MODE2_ALARM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_ALARM_OFFSET 0x20 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */
-#define RTC_MODE2_ALARM_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */
-
-#define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */
-#define RTC_MODE2_ALARM_SECOND_Msk (_U_(0x3F) << RTC_MODE2_ALARM_SECOND_Pos)
-#define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))
-#define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */
-#define RTC_MODE2_ALARM_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_ALARM_MINUTE_Pos)
-#define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))
-#define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */
-#define RTC_MODE2_ALARM_HOUR_Msk (_U_(0x1F) << RTC_MODE2_ALARM_HOUR_Pos)
-#define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))
-#define RTC_MODE2_ALARM_HOUR_AM_Val _U_(0x0) /**< \brief (RTC_MODE2_ALARM) Morning hour */
-#define RTC_MODE2_ALARM_HOUR_PM_Val _U_(0x10) /**< \brief (RTC_MODE2_ALARM) Afternoon hour */
-#define RTC_MODE2_ALARM_HOUR_AM (RTC_MODE2_ALARM_HOUR_AM_Val << RTC_MODE2_ALARM_HOUR_Pos)
-#define RTC_MODE2_ALARM_HOUR_PM (RTC_MODE2_ALARM_HOUR_PM_Val << RTC_MODE2_ALARM_HOUR_Pos)
-#define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */
-#define RTC_MODE2_ALARM_DAY_Msk (_U_(0x1F) << RTC_MODE2_ALARM_DAY_Pos)
-#define RTC_MODE2_ALARM_DAY(value) (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))
-#define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */
-#define RTC_MODE2_ALARM_MONTH_Msk (_U_(0xF) << RTC_MODE2_ALARM_MONTH_Pos)
-#define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))
-#define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */
-#define RTC_MODE2_ALARM_YEAR_Msk (_U_(0x3F) << RTC_MODE2_ALARM_YEAR_Pos)
-#define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))
-#define RTC_MODE2_ALARM_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_ALARM) MASK Register */
-
-/* -------- RTC_MODE2_MASK : (RTC Offset: 0x24) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} RTC_MODE2_MASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_MASK_OFFSET 0x24 /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */
-#define RTC_MODE2_MASK_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */
-
-#define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
-#define RTC_MODE2_MASK_SEL_Msk (_U_(0x7) << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL(value) (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))
-#define RTC_MODE2_MASK_SEL_OFF_Val _U_(0x0) /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
-#define RTC_MODE2_MASK_SEL_SS_Val _U_(0x1) /**< \brief (RTC_MODE2_MASK) Match seconds only */
-#define RTC_MODE2_MASK_SEL_MMSS_Val _U_(0x2) /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
-#define RTC_MODE2_MASK_SEL_HHMMSS_Val _U_(0x3) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */
-#define RTC_MODE2_MASK_SEL_DDHHMMSS_Val _U_(0x4) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */
-#define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val _U_(0x5) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */
-#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val _U_(0x6) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */
-#define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_MASK _U_(0x07) /**< \brief (RTC_MODE2_MASK) MASK Register */
-
-/* -------- RTC_GP : (RTC Offset: 0x40) (R/W 32) General Purpose -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t GP:32; /*!< bit: 0..31 General Purpose */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} RTC_GP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_GP_OFFSET 0x40 /**< \brief (RTC_GP offset) General Purpose */
-#define RTC_GP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_GP reset_value) General Purpose */
-
-#define RTC_GP_GP_Pos 0 /**< \brief (RTC_GP) General Purpose */
-#define RTC_GP_GP_Msk (_U_(0xFFFFFFFF) << RTC_GP_GP_Pos)
-#define RTC_GP_GP(value) (RTC_GP_GP_Msk & ((value) << RTC_GP_GP_Pos))
-#define RTC_GP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_GP) MASK Register */
-
-/* -------- RTC_TAMPCTRL : (RTC Offset: 0x60) (R/W 32) Tamper Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t IN0ACT:2; /*!< bit: 0.. 1 Tamper Input 0 Action */
- uint32_t IN1ACT:2; /*!< bit: 2.. 3 Tamper Input 1 Action */
- uint32_t IN2ACT:2; /*!< bit: 4.. 5 Tamper Input 2 Action */
- uint32_t IN3ACT:2; /*!< bit: 6.. 7 Tamper Input 3 Action */
- uint32_t IN4ACT:2; /*!< bit: 8.. 9 Tamper Input 4 Action */
- uint32_t :6; /*!< bit: 10..15 Reserved */
- uint32_t TAMLVL0:1; /*!< bit: 16 Tamper Level Select 0 */
- uint32_t TAMLVL1:1; /*!< bit: 17 Tamper Level Select 1 */
- uint32_t TAMLVL2:1; /*!< bit: 18 Tamper Level Select 2 */
- uint32_t TAMLVL3:1; /*!< bit: 19 Tamper Level Select 3 */
- uint32_t TAMLVL4:1; /*!< bit: 20 Tamper Level Select 4 */
- uint32_t :3; /*!< bit: 21..23 Reserved */
- uint32_t DEBNC0:1; /*!< bit: 24 Debouncer Enable 0 */
- uint32_t DEBNC1:1; /*!< bit: 25 Debouncer Enable 1 */
- uint32_t DEBNC2:1; /*!< bit: 26 Debouncer Enable 2 */
- uint32_t DEBNC3:1; /*!< bit: 27 Debouncer Enable 3 */
- uint32_t DEBNC4:1; /*!< bit: 28 Debouncer Enable 4 */
- uint32_t :3; /*!< bit: 29..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t TAMLVL:5; /*!< bit: 16..20 Tamper Level Select x */
- uint32_t :3; /*!< bit: 21..23 Reserved */
- uint32_t DEBNC:5; /*!< bit: 24..28 Debouncer Enable x */
- uint32_t :3; /*!< bit: 29..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} RTC_TAMPCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_TAMPCTRL_OFFSET 0x60 /**< \brief (RTC_TAMPCTRL offset) Tamper Control */
-#define RTC_TAMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_TAMPCTRL reset_value) Tamper Control */
-
-#define RTC_TAMPCTRL_IN0ACT_Pos 0 /**< \brief (RTC_TAMPCTRL) Tamper Input 0 Action */
-#define RTC_TAMPCTRL_IN0ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN0ACT_Pos)
-#define RTC_TAMPCTRL_IN0ACT(value) (RTC_TAMPCTRL_IN0ACT_Msk & ((value) << RTC_TAMPCTRL_IN0ACT_Pos))
-#define RTC_TAMPCTRL_IN0ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
-#define RTC_TAMPCTRL_IN0ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
-#define RTC_TAMPCTRL_IN0ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
-#define RTC_TAMPCTRL_IN0ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN0 to OUT */
-#define RTC_TAMPCTRL_IN0ACT_OFF (RTC_TAMPCTRL_IN0ACT_OFF_Val << RTC_TAMPCTRL_IN0ACT_Pos)
-#define RTC_TAMPCTRL_IN0ACT_WAKE (RTC_TAMPCTRL_IN0ACT_WAKE_Val << RTC_TAMPCTRL_IN0ACT_Pos)
-#define RTC_TAMPCTRL_IN0ACT_CAPTURE (RTC_TAMPCTRL_IN0ACT_CAPTURE_Val << RTC_TAMPCTRL_IN0ACT_Pos)
-#define RTC_TAMPCTRL_IN0ACT_ACTL (RTC_TAMPCTRL_IN0ACT_ACTL_Val << RTC_TAMPCTRL_IN0ACT_Pos)
-#define RTC_TAMPCTRL_IN1ACT_Pos 2 /**< \brief (RTC_TAMPCTRL) Tamper Input 1 Action */
-#define RTC_TAMPCTRL_IN1ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN1ACT_Pos)
-#define RTC_TAMPCTRL_IN1ACT(value) (RTC_TAMPCTRL_IN1ACT_Msk & ((value) << RTC_TAMPCTRL_IN1ACT_Pos))
-#define RTC_TAMPCTRL_IN1ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
-#define RTC_TAMPCTRL_IN1ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
-#define RTC_TAMPCTRL_IN1ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
-#define RTC_TAMPCTRL_IN1ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN1 to OUT */
-#define RTC_TAMPCTRL_IN1ACT_OFF (RTC_TAMPCTRL_IN1ACT_OFF_Val << RTC_TAMPCTRL_IN1ACT_Pos)
-#define RTC_TAMPCTRL_IN1ACT_WAKE (RTC_TAMPCTRL_IN1ACT_WAKE_Val << RTC_TAMPCTRL_IN1ACT_Pos)
-#define RTC_TAMPCTRL_IN1ACT_CAPTURE (RTC_TAMPCTRL_IN1ACT_CAPTURE_Val << RTC_TAMPCTRL_IN1ACT_Pos)
-#define RTC_TAMPCTRL_IN1ACT_ACTL (RTC_TAMPCTRL_IN1ACT_ACTL_Val << RTC_TAMPCTRL_IN1ACT_Pos)
-#define RTC_TAMPCTRL_IN2ACT_Pos 4 /**< \brief (RTC_TAMPCTRL) Tamper Input 2 Action */
-#define RTC_TAMPCTRL_IN2ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN2ACT_Pos)
-#define RTC_TAMPCTRL_IN2ACT(value) (RTC_TAMPCTRL_IN2ACT_Msk & ((value) << RTC_TAMPCTRL_IN2ACT_Pos))
-#define RTC_TAMPCTRL_IN2ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
-#define RTC_TAMPCTRL_IN2ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
-#define RTC_TAMPCTRL_IN2ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
-#define RTC_TAMPCTRL_IN2ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN2 to OUT */
-#define RTC_TAMPCTRL_IN2ACT_OFF (RTC_TAMPCTRL_IN2ACT_OFF_Val << RTC_TAMPCTRL_IN2ACT_Pos)
-#define RTC_TAMPCTRL_IN2ACT_WAKE (RTC_TAMPCTRL_IN2ACT_WAKE_Val << RTC_TAMPCTRL_IN2ACT_Pos)
-#define RTC_TAMPCTRL_IN2ACT_CAPTURE (RTC_TAMPCTRL_IN2ACT_CAPTURE_Val << RTC_TAMPCTRL_IN2ACT_Pos)
-#define RTC_TAMPCTRL_IN2ACT_ACTL (RTC_TAMPCTRL_IN2ACT_ACTL_Val << RTC_TAMPCTRL_IN2ACT_Pos)
-#define RTC_TAMPCTRL_IN3ACT_Pos 6 /**< \brief (RTC_TAMPCTRL) Tamper Input 3 Action */
-#define RTC_TAMPCTRL_IN3ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN3ACT_Pos)
-#define RTC_TAMPCTRL_IN3ACT(value) (RTC_TAMPCTRL_IN3ACT_Msk & ((value) << RTC_TAMPCTRL_IN3ACT_Pos))
-#define RTC_TAMPCTRL_IN3ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
-#define RTC_TAMPCTRL_IN3ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
-#define RTC_TAMPCTRL_IN3ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
-#define RTC_TAMPCTRL_IN3ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN3 to OUT */
-#define RTC_TAMPCTRL_IN3ACT_OFF (RTC_TAMPCTRL_IN3ACT_OFF_Val << RTC_TAMPCTRL_IN3ACT_Pos)
-#define RTC_TAMPCTRL_IN3ACT_WAKE (RTC_TAMPCTRL_IN3ACT_WAKE_Val << RTC_TAMPCTRL_IN3ACT_Pos)
-#define RTC_TAMPCTRL_IN3ACT_CAPTURE (RTC_TAMPCTRL_IN3ACT_CAPTURE_Val << RTC_TAMPCTRL_IN3ACT_Pos)
-#define RTC_TAMPCTRL_IN3ACT_ACTL (RTC_TAMPCTRL_IN3ACT_ACTL_Val << RTC_TAMPCTRL_IN3ACT_Pos)
-#define RTC_TAMPCTRL_IN4ACT_Pos 8 /**< \brief (RTC_TAMPCTRL) Tamper Input 4 Action */
-#define RTC_TAMPCTRL_IN4ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN4ACT_Pos)
-#define RTC_TAMPCTRL_IN4ACT(value) (RTC_TAMPCTRL_IN4ACT_Msk & ((value) << RTC_TAMPCTRL_IN4ACT_Pos))
-#define RTC_TAMPCTRL_IN4ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
-#define RTC_TAMPCTRL_IN4ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
-#define RTC_TAMPCTRL_IN4ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
-#define RTC_TAMPCTRL_IN4ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN4 to OUT */
-#define RTC_TAMPCTRL_IN4ACT_OFF (RTC_TAMPCTRL_IN4ACT_OFF_Val << RTC_TAMPCTRL_IN4ACT_Pos)
-#define RTC_TAMPCTRL_IN4ACT_WAKE (RTC_TAMPCTRL_IN4ACT_WAKE_Val << RTC_TAMPCTRL_IN4ACT_Pos)
-#define RTC_TAMPCTRL_IN4ACT_CAPTURE (RTC_TAMPCTRL_IN4ACT_CAPTURE_Val << RTC_TAMPCTRL_IN4ACT_Pos)
-#define RTC_TAMPCTRL_IN4ACT_ACTL (RTC_TAMPCTRL_IN4ACT_ACTL_Val << RTC_TAMPCTRL_IN4ACT_Pos)
-#define RTC_TAMPCTRL_TAMLVL0_Pos 16 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 0 */
-#define RTC_TAMPCTRL_TAMLVL0 (_U_(1) << RTC_TAMPCTRL_TAMLVL0_Pos)
-#define RTC_TAMPCTRL_TAMLVL1_Pos 17 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 1 */
-#define RTC_TAMPCTRL_TAMLVL1 (_U_(1) << RTC_TAMPCTRL_TAMLVL1_Pos)
-#define RTC_TAMPCTRL_TAMLVL2_Pos 18 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 2 */
-#define RTC_TAMPCTRL_TAMLVL2 (_U_(1) << RTC_TAMPCTRL_TAMLVL2_Pos)
-#define RTC_TAMPCTRL_TAMLVL3_Pos 19 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 3 */
-#define RTC_TAMPCTRL_TAMLVL3 (_U_(1) << RTC_TAMPCTRL_TAMLVL3_Pos)
-#define RTC_TAMPCTRL_TAMLVL4_Pos 20 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 4 */
-#define RTC_TAMPCTRL_TAMLVL4 (_U_(1) << RTC_TAMPCTRL_TAMLVL4_Pos)
-#define RTC_TAMPCTRL_TAMLVL_Pos 16 /**< \brief (RTC_TAMPCTRL) Tamper Level Select x */
-#define RTC_TAMPCTRL_TAMLVL_Msk (_U_(0x1F) << RTC_TAMPCTRL_TAMLVL_Pos)
-#define RTC_TAMPCTRL_TAMLVL(value) (RTC_TAMPCTRL_TAMLVL_Msk & ((value) << RTC_TAMPCTRL_TAMLVL_Pos))
-#define RTC_TAMPCTRL_DEBNC0_Pos 24 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 0 */
-#define RTC_TAMPCTRL_DEBNC0 (_U_(1) << RTC_TAMPCTRL_DEBNC0_Pos)
-#define RTC_TAMPCTRL_DEBNC1_Pos 25 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 1 */
-#define RTC_TAMPCTRL_DEBNC1 (_U_(1) << RTC_TAMPCTRL_DEBNC1_Pos)
-#define RTC_TAMPCTRL_DEBNC2_Pos 26 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 2 */
-#define RTC_TAMPCTRL_DEBNC2 (_U_(1) << RTC_TAMPCTRL_DEBNC2_Pos)
-#define RTC_TAMPCTRL_DEBNC3_Pos 27 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 3 */
-#define RTC_TAMPCTRL_DEBNC3 (_U_(1) << RTC_TAMPCTRL_DEBNC3_Pos)
-#define RTC_TAMPCTRL_DEBNC4_Pos 28 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 4 */
-#define RTC_TAMPCTRL_DEBNC4 (_U_(1) << RTC_TAMPCTRL_DEBNC4_Pos)
-#define RTC_TAMPCTRL_DEBNC_Pos 24 /**< \brief (RTC_TAMPCTRL) Debouncer Enable x */
-#define RTC_TAMPCTRL_DEBNC_Msk (_U_(0x1F) << RTC_TAMPCTRL_DEBNC_Pos)
-#define RTC_TAMPCTRL_DEBNC(value) (RTC_TAMPCTRL_DEBNC_Msk & ((value) << RTC_TAMPCTRL_DEBNC_Pos))
-#define RTC_TAMPCTRL_MASK _U_(0x1F1F03FF) /**< \brief (RTC_TAMPCTRL) MASK Register */
-
-/* -------- RTC_MODE0_TIMESTAMP : (RTC Offset: 0x64) (R/ 32) MODE0 MODE0 Timestamp -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t COUNT:32; /*!< bit: 0..31 Count Timestamp Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} RTC_MODE0_TIMESTAMP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_TIMESTAMP_OFFSET 0x64 /**< \brief (RTC_MODE0_TIMESTAMP offset) MODE0 Timestamp */
-#define RTC_MODE0_TIMESTAMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_TIMESTAMP reset_value) MODE0 Timestamp */
-
-#define RTC_MODE0_TIMESTAMP_COUNT_Pos 0 /**< \brief (RTC_MODE0_TIMESTAMP) Count Timestamp Value */
-#define RTC_MODE0_TIMESTAMP_COUNT_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_TIMESTAMP_COUNT_Pos)
-#define RTC_MODE0_TIMESTAMP_COUNT(value) (RTC_MODE0_TIMESTAMP_COUNT_Msk & ((value) << RTC_MODE0_TIMESTAMP_COUNT_Pos))
-#define RTC_MODE0_TIMESTAMP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_TIMESTAMP) MASK Register */
-
-/* -------- RTC_MODE1_TIMESTAMP : (RTC Offset: 0x64) (R/ 32) MODE1 MODE1 Timestamp -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t COUNT:16; /*!< bit: 0..15 Count Timestamp Value */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} RTC_MODE1_TIMESTAMP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_TIMESTAMP_OFFSET 0x64 /**< \brief (RTC_MODE1_TIMESTAMP offset) MODE1 Timestamp */
-#define RTC_MODE1_TIMESTAMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE1_TIMESTAMP reset_value) MODE1 Timestamp */
-
-#define RTC_MODE1_TIMESTAMP_COUNT_Pos 0 /**< \brief (RTC_MODE1_TIMESTAMP) Count Timestamp Value */
-#define RTC_MODE1_TIMESTAMP_COUNT_Msk (_U_(0xFFFF) << RTC_MODE1_TIMESTAMP_COUNT_Pos)
-#define RTC_MODE1_TIMESTAMP_COUNT(value) (RTC_MODE1_TIMESTAMP_COUNT_Msk & ((value) << RTC_MODE1_TIMESTAMP_COUNT_Pos))
-#define RTC_MODE1_TIMESTAMP_MASK _U_(0x0000FFFF) /**< \brief (RTC_MODE1_TIMESTAMP) MASK Register */
-
-/* -------- RTC_MODE2_TIMESTAMP : (RTC Offset: 0x64) (R/ 32) MODE2 MODE2 Timestamp -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SECOND:6; /*!< bit: 0.. 5 Second Timestamp Value */
- uint32_t MINUTE:6; /*!< bit: 6..11 Minute Timestamp Value */
- uint32_t HOUR:5; /*!< bit: 12..16 Hour Timestamp Value */
- uint32_t DAY:5; /*!< bit: 17..21 Day Timestamp Value */
- uint32_t MONTH:4; /*!< bit: 22..25 Month Timestamp Value */
- uint32_t YEAR:6; /*!< bit: 26..31 Year Timestamp Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} RTC_MODE2_TIMESTAMP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_TIMESTAMP_OFFSET 0x64 /**< \brief (RTC_MODE2_TIMESTAMP offset) MODE2 Timestamp */
-#define RTC_MODE2_TIMESTAMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_TIMESTAMP reset_value) MODE2 Timestamp */
-
-#define RTC_MODE2_TIMESTAMP_SECOND_Pos 0 /**< \brief (RTC_MODE2_TIMESTAMP) Second Timestamp Value */
-#define RTC_MODE2_TIMESTAMP_SECOND_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_SECOND_Pos)
-#define RTC_MODE2_TIMESTAMP_SECOND(value) (RTC_MODE2_TIMESTAMP_SECOND_Msk & ((value) << RTC_MODE2_TIMESTAMP_SECOND_Pos))
-#define RTC_MODE2_TIMESTAMP_MINUTE_Pos 6 /**< \brief (RTC_MODE2_TIMESTAMP) Minute Timestamp Value */
-#define RTC_MODE2_TIMESTAMP_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_MINUTE_Pos)
-#define RTC_MODE2_TIMESTAMP_MINUTE(value) (RTC_MODE2_TIMESTAMP_MINUTE_Msk & ((value) << RTC_MODE2_TIMESTAMP_MINUTE_Pos))
-#define RTC_MODE2_TIMESTAMP_HOUR_Pos 12 /**< \brief (RTC_MODE2_TIMESTAMP) Hour Timestamp Value */
-#define RTC_MODE2_TIMESTAMP_HOUR_Msk (_U_(0x1F) << RTC_MODE2_TIMESTAMP_HOUR_Pos)
-#define RTC_MODE2_TIMESTAMP_HOUR(value) (RTC_MODE2_TIMESTAMP_HOUR_Msk & ((value) << RTC_MODE2_TIMESTAMP_HOUR_Pos))
-#define RTC_MODE2_TIMESTAMP_HOUR_AM_Val _U_(0x0) /**< \brief (RTC_MODE2_TIMESTAMP) AM when CLKREP in 12-hour */
-#define RTC_MODE2_TIMESTAMP_HOUR_PM_Val _U_(0x10) /**< \brief (RTC_MODE2_TIMESTAMP) PM when CLKREP in 12-hour */
-#define RTC_MODE2_TIMESTAMP_HOUR_AM (RTC_MODE2_TIMESTAMP_HOUR_AM_Val << RTC_MODE2_TIMESTAMP_HOUR_Pos)
-#define RTC_MODE2_TIMESTAMP_HOUR_PM (RTC_MODE2_TIMESTAMP_HOUR_PM_Val << RTC_MODE2_TIMESTAMP_HOUR_Pos)
-#define RTC_MODE2_TIMESTAMP_DAY_Pos 17 /**< \brief (RTC_MODE2_TIMESTAMP) Day Timestamp Value */
-#define RTC_MODE2_TIMESTAMP_DAY_Msk (_U_(0x1F) << RTC_MODE2_TIMESTAMP_DAY_Pos)
-#define RTC_MODE2_TIMESTAMP_DAY(value) (RTC_MODE2_TIMESTAMP_DAY_Msk & ((value) << RTC_MODE2_TIMESTAMP_DAY_Pos))
-#define RTC_MODE2_TIMESTAMP_MONTH_Pos 22 /**< \brief (RTC_MODE2_TIMESTAMP) Month Timestamp Value */
-#define RTC_MODE2_TIMESTAMP_MONTH_Msk (_U_(0xF) << RTC_MODE2_TIMESTAMP_MONTH_Pos)
-#define RTC_MODE2_TIMESTAMP_MONTH(value) (RTC_MODE2_TIMESTAMP_MONTH_Msk & ((value) << RTC_MODE2_TIMESTAMP_MONTH_Pos))
-#define RTC_MODE2_TIMESTAMP_YEAR_Pos 26 /**< \brief (RTC_MODE2_TIMESTAMP) Year Timestamp Value */
-#define RTC_MODE2_TIMESTAMP_YEAR_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_YEAR_Pos)
-#define RTC_MODE2_TIMESTAMP_YEAR(value) (RTC_MODE2_TIMESTAMP_YEAR_Msk & ((value) << RTC_MODE2_TIMESTAMP_YEAR_Pos))
-#define RTC_MODE2_TIMESTAMP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_TIMESTAMP) MASK Register */
-
-/* -------- RTC_TAMPID : (RTC Offset: 0x68) (R/W 32) Tamper ID -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TAMPID0:1; /*!< bit: 0 Tamper Input 0 Detected */
- uint32_t TAMPID1:1; /*!< bit: 1 Tamper Input 1 Detected */
- uint32_t TAMPID2:1; /*!< bit: 2 Tamper Input 2 Detected */
- uint32_t TAMPID3:1; /*!< bit: 3 Tamper Input 3 Detected */
- uint32_t TAMPID4:1; /*!< bit: 4 Tamper Input 4 Detected */
- uint32_t :26; /*!< bit: 5..30 Reserved */
- uint32_t TAMPEVT:1; /*!< bit: 31 Tamper Event Detected */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t TAMPID:5; /*!< bit: 0.. 4 Tamper Input x Detected */
- uint32_t :27; /*!< bit: 5..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} RTC_TAMPID_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_TAMPID_OFFSET 0x68 /**< \brief (RTC_TAMPID offset) Tamper ID */
-#define RTC_TAMPID_RESETVALUE _U_(0x00000000) /**< \brief (RTC_TAMPID reset_value) Tamper ID */
-
-#define RTC_TAMPID_TAMPID0_Pos 0 /**< \brief (RTC_TAMPID) Tamper Input 0 Detected */
-#define RTC_TAMPID_TAMPID0 (_U_(1) << RTC_TAMPID_TAMPID0_Pos)
-#define RTC_TAMPID_TAMPID1_Pos 1 /**< \brief (RTC_TAMPID) Tamper Input 1 Detected */
-#define RTC_TAMPID_TAMPID1 (_U_(1) << RTC_TAMPID_TAMPID1_Pos)
-#define RTC_TAMPID_TAMPID2_Pos 2 /**< \brief (RTC_TAMPID) Tamper Input 2 Detected */
-#define RTC_TAMPID_TAMPID2 (_U_(1) << RTC_TAMPID_TAMPID2_Pos)
-#define RTC_TAMPID_TAMPID3_Pos 3 /**< \brief (RTC_TAMPID) Tamper Input 3 Detected */
-#define RTC_TAMPID_TAMPID3 (_U_(1) << RTC_TAMPID_TAMPID3_Pos)
-#define RTC_TAMPID_TAMPID4_Pos 4 /**< \brief (RTC_TAMPID) Tamper Input 4 Detected */
-#define RTC_TAMPID_TAMPID4 (_U_(1) << RTC_TAMPID_TAMPID4_Pos)
-#define RTC_TAMPID_TAMPID_Pos 0 /**< \brief (RTC_TAMPID) Tamper Input x Detected */
-#define RTC_TAMPID_TAMPID_Msk (_U_(0x1F) << RTC_TAMPID_TAMPID_Pos)
-#define RTC_TAMPID_TAMPID(value) (RTC_TAMPID_TAMPID_Msk & ((value) << RTC_TAMPID_TAMPID_Pos))
-#define RTC_TAMPID_TAMPEVT_Pos 31 /**< \brief (RTC_TAMPID) Tamper Event Detected */
-#define RTC_TAMPID_TAMPEVT (_U_(0x1) << RTC_TAMPID_TAMPEVT_Pos)
-#define RTC_TAMPID_MASK _U_(0x8000001F) /**< \brief (RTC_TAMPID) MASK Register */
-
-/* -------- RTC_BKUP : (RTC Offset: 0x80) (R/W 32) Backup -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t BKUP:32; /*!< bit: 0..31 Backup */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} RTC_BKUP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_BKUP_OFFSET 0x80 /**< \brief (RTC_BKUP offset) Backup */
-#define RTC_BKUP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_BKUP reset_value) Backup */
-
-#define RTC_BKUP_BKUP_Pos 0 /**< \brief (RTC_BKUP) Backup */
-#define RTC_BKUP_BKUP_Msk (_U_(0xFFFFFFFF) << RTC_BKUP_BKUP_Pos)
-#define RTC_BKUP_BKUP(value) (RTC_BKUP_BKUP_Msk & ((value) << RTC_BKUP_BKUP_Pos))
-#define RTC_BKUP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_BKUP) MASK Register */
-
-/** \brief RtcMode2Alarm hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
- __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
- RoReg8 Reserved1[0x3];
-} RtcMode2Alarm;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief RTC_MODE0 hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* 32-bit Counter with Single 32-bit Compare */
- __IO RTC_MODE0_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control A */
- __IO RTC_MODE0_CTRLB_Type CTRLB; /**< \brief Offset: 0x02 (R/W 16) MODE0 Control B */
- __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE0 Event Control */
- __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE0 Interrupt Enable Clear */
- __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE0 Interrupt Enable Set */
- __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE0 Interrupt Flag Status and Clear */
- __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */
- RoReg8 Reserved1[0x1];
- __I RTC_MODE0_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE0 Synchronization Busy Status */
- __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */
- RoReg8 Reserved2[0x3];
- __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x18 (R/W 32) MODE0 Counter Value */
- RoReg8 Reserved3[0x4];
- __IO RTC_MODE0_COMP_Type COMP[2]; /**< \brief Offset: 0x20 (R/W 32) MODE0 Compare n Value */
- RoReg8 Reserved4[0x18];
- __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */
- RoReg8 Reserved5[0x10];
- __IO RTC_TAMPCTRL_Type TAMPCTRL; /**< \brief Offset: 0x60 (R/W 32) Tamper Control */
- __I RTC_MODE0_TIMESTAMP_Type TIMESTAMP; /**< \brief Offset: 0x64 (R/ 32) MODE0 Timestamp */
- __IO RTC_TAMPID_Type TAMPID; /**< \brief Offset: 0x68 (R/W 32) Tamper ID */
- RoReg8 Reserved6[0x14];
- __IO RTC_BKUP_Type BKUP[8]; /**< \brief Offset: 0x80 (R/W 32) Backup */
-} RtcMode0;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief RTC_MODE1 hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* 16-bit Counter with Two 16-bit Compares */
- __IO RTC_MODE1_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control A */
- __IO RTC_MODE1_CTRLB_Type CTRLB; /**< \brief Offset: 0x02 (R/W 16) MODE1 Control B */
- __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE1 Event Control */
- __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE1 Interrupt Enable Clear */
- __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE1 Interrupt Enable Set */
- __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE1 Interrupt Flag Status and Clear */
- __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */
- RoReg8 Reserved1[0x1];
- __I RTC_MODE1_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE1 Synchronization Busy Status */
- __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */
- RoReg8 Reserved2[0x3];
- __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x18 (R/W 16) MODE1 Counter Value */
- RoReg8 Reserved3[0x2];
- __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x1C (R/W 16) MODE1 Counter Period */
- RoReg8 Reserved4[0x2];
- __IO RTC_MODE1_COMP_Type COMP[4]; /**< \brief Offset: 0x20 (R/W 16) MODE1 Compare n Value */
- RoReg8 Reserved5[0x18];
- __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */
- RoReg8 Reserved6[0x10];
- __IO RTC_TAMPCTRL_Type TAMPCTRL; /**< \brief Offset: 0x60 (R/W 32) Tamper Control */
- __I RTC_MODE1_TIMESTAMP_Type TIMESTAMP; /**< \brief Offset: 0x64 (R/ 32) MODE1 Timestamp */
- __IO RTC_TAMPID_Type TAMPID; /**< \brief Offset: 0x68 (R/W 32) Tamper ID */
- RoReg8 Reserved7[0x14];
- __IO RTC_BKUP_Type BKUP[8]; /**< \brief Offset: 0x80 (R/W 32) Backup */
-} RtcMode1;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief RTC_MODE2 hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* Clock/Calendar with Alarm */
- __IO RTC_MODE2_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control A */
- __IO RTC_MODE2_CTRLB_Type CTRLB; /**< \brief Offset: 0x02 (R/W 16) MODE2 Control B */
- __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE2 Event Control */
- __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE2 Interrupt Enable Clear */
- __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE2 Interrupt Enable Set */
- __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE2 Interrupt Flag Status and Clear */
- __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */
- RoReg8 Reserved1[0x1];
- __I RTC_MODE2_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE2 Synchronization Busy Status */
- __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */
- RoReg8 Reserved2[0x3];
- __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x18 (R/W 32) MODE2 Clock Value */
- RoReg8 Reserved3[0x4];
- RtcMode2Alarm Mode2Alarm[2]; /**< \brief Offset: 0x20 RtcMode2Alarm groups [NUM_OF_ALARMS] */
- RoReg8 Reserved4[0x10];
- __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */
- RoReg8 Reserved5[0x10];
- __IO RTC_TAMPCTRL_Type TAMPCTRL; /**< \brief Offset: 0x60 (R/W 32) Tamper Control */
- __I RTC_MODE2_TIMESTAMP_Type TIMESTAMP; /**< \brief Offset: 0x64 (R/ 32) MODE2 Timestamp */
- __IO RTC_TAMPID_Type TAMPID; /**< \brief Offset: 0x68 (R/W 32) Tamper ID */
- RoReg8 Reserved6[0x14];
- __IO RTC_BKUP_Type BKUP[8]; /**< \brief Offset: 0x80 (R/W 32) Backup */
-} RtcMode2;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
- RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
- RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
-} Rtc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_RTC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for RTC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_RTC_COMPONENT_
+#define _SAME54_RTC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR RTC */
+/* ========================================================================== */
+/** \addtogroup SAME54_RTC Real-Time Counter */
+/*@{*/
+
+#define RTC_U2250
+#define REV_RTC 0x210
+
+/* -------- RTC_MODE0_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :3; /*!< bit: 4.. 6 Reserved */
+ uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :1; /*!< bit: 12 Reserved */
+ uint16_t BKTRST:1; /*!< bit: 13 BKUP Registers Reset On Tamper Enable */
+ uint16_t GPTRST:1; /*!< bit: 14 GP Registers Reset On Tamper Enable */
+ uint16_t COUNTSYNC:1; /*!< bit: 15 Count Read Synchronization Enable */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE0_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRLA offset) MODE0 Control A */
+#define RTC_MODE0_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_CTRLA reset_value) MODE0 Control A */
+
+#define RTC_MODE0_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRLA) Software Reset */
+#define RTC_MODE0_CTRLA_SWRST (_U_(0x1) << RTC_MODE0_CTRLA_SWRST_Pos)
+#define RTC_MODE0_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRLA) Enable */
+#define RTC_MODE0_CTRLA_ENABLE (_U_(0x1) << RTC_MODE0_CTRLA_ENABLE_Pos)
+#define RTC_MODE0_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRLA) Operating Mode */
+#define RTC_MODE0_CTRLA_MODE_Msk (_U_(0x3) << RTC_MODE0_CTRLA_MODE_Pos)
+#define RTC_MODE0_CTRLA_MODE(value) (RTC_MODE0_CTRLA_MODE_Msk & ((value) << RTC_MODE0_CTRLA_MODE_Pos))
+#define RTC_MODE0_CTRLA_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRLA) Mode 0: 32-bit Counter */
+#define RTC_MODE0_CTRLA_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRLA) Mode 1: 16-bit Counter */
+#define RTC_MODE0_CTRLA_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRLA) Mode 2: Clock/Calendar */
+#define RTC_MODE0_CTRLA_MODE_COUNT32 (RTC_MODE0_CTRLA_MODE_COUNT32_Val << RTC_MODE0_CTRLA_MODE_Pos)
+#define RTC_MODE0_CTRLA_MODE_COUNT16 (RTC_MODE0_CTRLA_MODE_COUNT16_Val << RTC_MODE0_CTRLA_MODE_Pos)
+#define RTC_MODE0_CTRLA_MODE_CLOCK (RTC_MODE0_CTRLA_MODE_CLOCK_Val << RTC_MODE0_CTRLA_MODE_Pos)
+#define RTC_MODE0_CTRLA_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRLA) Clear on Match */
+#define RTC_MODE0_CTRLA_MATCHCLR (_U_(0x1) << RTC_MODE0_CTRLA_MATCHCLR_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRLA) Prescaler */
+#define RTC_MODE0_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER(value) (RTC_MODE0_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE0_CTRLA_PRESCALER_Pos))
+#define RTC_MODE0_CTRLA_PRESCALER_OFF_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV1_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV2_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV4_Val _U_(0x3) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV8_Val _U_(0x4) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV16_Val _U_(0x5) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV32_Val _U_(0x6) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV64_Val _U_(0x7) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV128_Val _U_(0x8) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV256_Val _U_(0x9) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV512_Val _U_(0xA) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val _U_(0xB) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE0_CTRLA_PRESCALER_OFF (RTC_MODE0_CTRLA_PRESCALER_OFF_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV1 (RTC_MODE0_CTRLA_PRESCALER_DIV1_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV2 (RTC_MODE0_CTRLA_PRESCALER_DIV2_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV4 (RTC_MODE0_CTRLA_PRESCALER_DIV4_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV8 (RTC_MODE0_CTRLA_PRESCALER_DIV8_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV16 (RTC_MODE0_CTRLA_PRESCALER_DIV16_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV32 (RTC_MODE0_CTRLA_PRESCALER_DIV32_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV64 (RTC_MODE0_CTRLA_PRESCALER_DIV64_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV128 (RTC_MODE0_CTRLA_PRESCALER_DIV128_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV256 (RTC_MODE0_CTRLA_PRESCALER_DIV256_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV512 (RTC_MODE0_CTRLA_PRESCALER_DIV512_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV1024 (RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_BKTRST_Pos 13 /**< \brief (RTC_MODE0_CTRLA) BKUP Registers Reset On Tamper Enable */
+#define RTC_MODE0_CTRLA_BKTRST (_U_(0x1) << RTC_MODE0_CTRLA_BKTRST_Pos)
+#define RTC_MODE0_CTRLA_GPTRST_Pos 14 /**< \brief (RTC_MODE0_CTRLA) GP Registers Reset On Tamper Enable */
+#define RTC_MODE0_CTRLA_GPTRST (_U_(0x1) << RTC_MODE0_CTRLA_GPTRST_Pos)
+#define RTC_MODE0_CTRLA_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE0_CTRLA) Count Read Synchronization Enable */
+#define RTC_MODE0_CTRLA_COUNTSYNC (_U_(0x1) << RTC_MODE0_CTRLA_COUNTSYNC_Pos)
+#define RTC_MODE0_CTRLA_MASK _U_(0xEF8F) /**< \brief (RTC_MODE0_CTRLA) MASK Register */
+
+/* -------- RTC_MODE1_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :1; /*!< bit: 12 Reserved */
+ uint16_t BKTRST:1; /*!< bit: 13 BKUP Registers Reset On Tamper Enable */
+ uint16_t GPTRST:1; /*!< bit: 14 GP Registers Reset On Tamper Enable */
+ uint16_t COUNTSYNC:1; /*!< bit: 15 Count Read Synchronization Enable */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRLA offset) MODE1 Control A */
+#define RTC_MODE1_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_CTRLA reset_value) MODE1 Control A */
+
+#define RTC_MODE1_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRLA) Software Reset */
+#define RTC_MODE1_CTRLA_SWRST (_U_(0x1) << RTC_MODE1_CTRLA_SWRST_Pos)
+#define RTC_MODE1_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRLA) Enable */
+#define RTC_MODE1_CTRLA_ENABLE (_U_(0x1) << RTC_MODE1_CTRLA_ENABLE_Pos)
+#define RTC_MODE1_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRLA) Operating Mode */
+#define RTC_MODE1_CTRLA_MODE_Msk (_U_(0x3) << RTC_MODE1_CTRLA_MODE_Pos)
+#define RTC_MODE1_CTRLA_MODE(value) (RTC_MODE1_CTRLA_MODE_Msk & ((value) << RTC_MODE1_CTRLA_MODE_Pos))
+#define RTC_MODE1_CTRLA_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRLA) Mode 0: 32-bit Counter */
+#define RTC_MODE1_CTRLA_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRLA) Mode 1: 16-bit Counter */
+#define RTC_MODE1_CTRLA_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRLA) Mode 2: Clock/Calendar */
+#define RTC_MODE1_CTRLA_MODE_COUNT32 (RTC_MODE1_CTRLA_MODE_COUNT32_Val << RTC_MODE1_CTRLA_MODE_Pos)
+#define RTC_MODE1_CTRLA_MODE_COUNT16 (RTC_MODE1_CTRLA_MODE_COUNT16_Val << RTC_MODE1_CTRLA_MODE_Pos)
+#define RTC_MODE1_CTRLA_MODE_CLOCK (RTC_MODE1_CTRLA_MODE_CLOCK_Val << RTC_MODE1_CTRLA_MODE_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRLA) Prescaler */
+#define RTC_MODE1_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER(value) (RTC_MODE1_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE1_CTRLA_PRESCALER_Pos))
+#define RTC_MODE1_CTRLA_PRESCALER_OFF_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV1_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV2_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV4_Val _U_(0x3) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV8_Val _U_(0x4) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV16_Val _U_(0x5) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV32_Val _U_(0x6) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV64_Val _U_(0x7) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV128_Val _U_(0x8) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV256_Val _U_(0x9) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV512_Val _U_(0xA) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val _U_(0xB) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE1_CTRLA_PRESCALER_OFF (RTC_MODE1_CTRLA_PRESCALER_OFF_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV1 (RTC_MODE1_CTRLA_PRESCALER_DIV1_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV2 (RTC_MODE1_CTRLA_PRESCALER_DIV2_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV4 (RTC_MODE1_CTRLA_PRESCALER_DIV4_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV8 (RTC_MODE1_CTRLA_PRESCALER_DIV8_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV16 (RTC_MODE1_CTRLA_PRESCALER_DIV16_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV32 (RTC_MODE1_CTRLA_PRESCALER_DIV32_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV64 (RTC_MODE1_CTRLA_PRESCALER_DIV64_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV128 (RTC_MODE1_CTRLA_PRESCALER_DIV128_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV256 (RTC_MODE1_CTRLA_PRESCALER_DIV256_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV512 (RTC_MODE1_CTRLA_PRESCALER_DIV512_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV1024 (RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_BKTRST_Pos 13 /**< \brief (RTC_MODE1_CTRLA) BKUP Registers Reset On Tamper Enable */
+#define RTC_MODE1_CTRLA_BKTRST (_U_(0x1) << RTC_MODE1_CTRLA_BKTRST_Pos)
+#define RTC_MODE1_CTRLA_GPTRST_Pos 14 /**< \brief (RTC_MODE1_CTRLA) GP Registers Reset On Tamper Enable */
+#define RTC_MODE1_CTRLA_GPTRST (_U_(0x1) << RTC_MODE1_CTRLA_GPTRST_Pos)
+#define RTC_MODE1_CTRLA_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE1_CTRLA) Count Read Synchronization Enable */
+#define RTC_MODE1_CTRLA_COUNTSYNC (_U_(0x1) << RTC_MODE1_CTRLA_COUNTSYNC_Pos)
+#define RTC_MODE1_CTRLA_MASK _U_(0xEF0F) /**< \brief (RTC_MODE1_CTRLA) MASK Register */
+
+/* -------- RTC_MODE2_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :2; /*!< bit: 4.. 5 Reserved */
+ uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
+ uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :1; /*!< bit: 12 Reserved */
+ uint16_t BKTRST:1; /*!< bit: 13 BKUP Registers Reset On Tamper Enable */
+ uint16_t GPTRST:1; /*!< bit: 14 GP Registers Reset On Tamper Enable */
+ uint16_t CLOCKSYNC:1; /*!< bit: 15 Clock Read Synchronization Enable */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE2_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRLA offset) MODE2 Control A */
+#define RTC_MODE2_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_CTRLA reset_value) MODE2 Control A */
+
+#define RTC_MODE2_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRLA) Software Reset */
+#define RTC_MODE2_CTRLA_SWRST (_U_(0x1) << RTC_MODE2_CTRLA_SWRST_Pos)
+#define RTC_MODE2_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRLA) Enable */
+#define RTC_MODE2_CTRLA_ENABLE (_U_(0x1) << RTC_MODE2_CTRLA_ENABLE_Pos)
+#define RTC_MODE2_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRLA) Operating Mode */
+#define RTC_MODE2_CTRLA_MODE_Msk (_U_(0x3) << RTC_MODE2_CTRLA_MODE_Pos)
+#define RTC_MODE2_CTRLA_MODE(value) (RTC_MODE2_CTRLA_MODE_Msk & ((value) << RTC_MODE2_CTRLA_MODE_Pos))
+#define RTC_MODE2_CTRLA_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRLA) Mode 0: 32-bit Counter */
+#define RTC_MODE2_CTRLA_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRLA) Mode 1: 16-bit Counter */
+#define RTC_MODE2_CTRLA_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRLA) Mode 2: Clock/Calendar */
+#define RTC_MODE2_CTRLA_MODE_COUNT32 (RTC_MODE2_CTRLA_MODE_COUNT32_Val << RTC_MODE2_CTRLA_MODE_Pos)
+#define RTC_MODE2_CTRLA_MODE_COUNT16 (RTC_MODE2_CTRLA_MODE_COUNT16_Val << RTC_MODE2_CTRLA_MODE_Pos)
+#define RTC_MODE2_CTRLA_MODE_CLOCK (RTC_MODE2_CTRLA_MODE_CLOCK_Val << RTC_MODE2_CTRLA_MODE_Pos)
+#define RTC_MODE2_CTRLA_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRLA) Clock Representation */
+#define RTC_MODE2_CTRLA_CLKREP (_U_(0x1) << RTC_MODE2_CTRLA_CLKREP_Pos)
+#define RTC_MODE2_CTRLA_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRLA) Clear on Match */
+#define RTC_MODE2_CTRLA_MATCHCLR (_U_(0x1) << RTC_MODE2_CTRLA_MATCHCLR_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRLA) Prescaler */
+#define RTC_MODE2_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER(value) (RTC_MODE2_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE2_CTRLA_PRESCALER_Pos))
+#define RTC_MODE2_CTRLA_PRESCALER_OFF_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV1_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV2_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV4_Val _U_(0x3) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV8_Val _U_(0x4) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV16_Val _U_(0x5) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV32_Val _U_(0x6) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV64_Val _U_(0x7) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV128_Val _U_(0x8) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV256_Val _U_(0x9) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV512_Val _U_(0xA) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val _U_(0xB) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE2_CTRLA_PRESCALER_OFF (RTC_MODE2_CTRLA_PRESCALER_OFF_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV1 (RTC_MODE2_CTRLA_PRESCALER_DIV1_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV2 (RTC_MODE2_CTRLA_PRESCALER_DIV2_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV4 (RTC_MODE2_CTRLA_PRESCALER_DIV4_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV8 (RTC_MODE2_CTRLA_PRESCALER_DIV8_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV16 (RTC_MODE2_CTRLA_PRESCALER_DIV16_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV32 (RTC_MODE2_CTRLA_PRESCALER_DIV32_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV64 (RTC_MODE2_CTRLA_PRESCALER_DIV64_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV128 (RTC_MODE2_CTRLA_PRESCALER_DIV128_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV256 (RTC_MODE2_CTRLA_PRESCALER_DIV256_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV512 (RTC_MODE2_CTRLA_PRESCALER_DIV512_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV1024 (RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_BKTRST_Pos 13 /**< \brief (RTC_MODE2_CTRLA) BKUP Registers Reset On Tamper Enable */
+#define RTC_MODE2_CTRLA_BKTRST (_U_(0x1) << RTC_MODE2_CTRLA_BKTRST_Pos)
+#define RTC_MODE2_CTRLA_GPTRST_Pos 14 /**< \brief (RTC_MODE2_CTRLA) GP Registers Reset On Tamper Enable */
+#define RTC_MODE2_CTRLA_GPTRST (_U_(0x1) << RTC_MODE2_CTRLA_GPTRST_Pos)
+#define RTC_MODE2_CTRLA_CLOCKSYNC_Pos 15 /**< \brief (RTC_MODE2_CTRLA) Clock Read Synchronization Enable */
+#define RTC_MODE2_CTRLA_CLOCKSYNC (_U_(0x1) << RTC_MODE2_CTRLA_CLOCKSYNC_Pos)
+#define RTC_MODE2_CTRLA_MASK _U_(0xEFCF) /**< \brief (RTC_MODE2_CTRLA) MASK Register */
+
+/* -------- RTC_MODE0_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE0 MODE0 Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t GP0EN:1; /*!< bit: 0 General Purpose 0 Enable */
+ uint16_t GP2EN:1; /*!< bit: 1 General Purpose 2 Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t DEBMAJ:1; /*!< bit: 4 Debouncer Majority Enable */
+ uint16_t DEBASYNC:1; /*!< bit: 5 Debouncer Asynchronous Enable */
+ uint16_t RTCOUT:1; /*!< bit: 6 RTC Output Enable */
+ uint16_t DMAEN:1; /*!< bit: 7 DMA Enable */
+ uint16_t DEBF:3; /*!< bit: 8..10 Debounce Freqnuency */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t ACTF:3; /*!< bit: 12..14 Active Layer Freqnuency */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE0_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_CTRLB_OFFSET 0x02 /**< \brief (RTC_MODE0_CTRLB offset) MODE0 Control B */
+#define RTC_MODE0_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_CTRLB reset_value) MODE0 Control B */
+
+#define RTC_MODE0_CTRLB_GP0EN_Pos 0 /**< \brief (RTC_MODE0_CTRLB) General Purpose 0 Enable */
+#define RTC_MODE0_CTRLB_GP0EN (_U_(0x1) << RTC_MODE0_CTRLB_GP0EN_Pos)
+#define RTC_MODE0_CTRLB_GP2EN_Pos 1 /**< \brief (RTC_MODE0_CTRLB) General Purpose 2 Enable */
+#define RTC_MODE0_CTRLB_GP2EN (_U_(0x1) << RTC_MODE0_CTRLB_GP2EN_Pos)
+#define RTC_MODE0_CTRLB_DEBMAJ_Pos 4 /**< \brief (RTC_MODE0_CTRLB) Debouncer Majority Enable */
+#define RTC_MODE0_CTRLB_DEBMAJ (_U_(0x1) << RTC_MODE0_CTRLB_DEBMAJ_Pos)
+#define RTC_MODE0_CTRLB_DEBASYNC_Pos 5 /**< \brief (RTC_MODE0_CTRLB) Debouncer Asynchronous Enable */
+#define RTC_MODE0_CTRLB_DEBASYNC (_U_(0x1) << RTC_MODE0_CTRLB_DEBASYNC_Pos)
+#define RTC_MODE0_CTRLB_RTCOUT_Pos 6 /**< \brief (RTC_MODE0_CTRLB) RTC Output Enable */
+#define RTC_MODE0_CTRLB_RTCOUT (_U_(0x1) << RTC_MODE0_CTRLB_RTCOUT_Pos)
+#define RTC_MODE0_CTRLB_DMAEN_Pos 7 /**< \brief (RTC_MODE0_CTRLB) DMA Enable */
+#define RTC_MODE0_CTRLB_DMAEN (_U_(0x1) << RTC_MODE0_CTRLB_DMAEN_Pos)
+#define RTC_MODE0_CTRLB_DEBF_Pos 8 /**< \brief (RTC_MODE0_CTRLB) Debounce Freqnuency */
+#define RTC_MODE0_CTRLB_DEBF_Msk (_U_(0x7) << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF(value) (RTC_MODE0_CTRLB_DEBF_Msk & ((value) << RTC_MODE0_CTRLB_DEBF_Pos))
+#define RTC_MODE0_CTRLB_DEBF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */
+#define RTC_MODE0_CTRLB_DEBF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */
+#define RTC_MODE0_CTRLB_DEBF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */
+#define RTC_MODE0_CTRLB_DEBF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */
+#define RTC_MODE0_CTRLB_DEBF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */
+#define RTC_MODE0_CTRLB_DEBF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */
+#define RTC_MODE0_CTRLB_DEBF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */
+#define RTC_MODE0_CTRLB_DEBF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */
+#define RTC_MODE0_CTRLB_DEBF_DIV2 (RTC_MODE0_CTRLB_DEBF_DIV2_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV4 (RTC_MODE0_CTRLB_DEBF_DIV4_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV8 (RTC_MODE0_CTRLB_DEBF_DIV8_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV16 (RTC_MODE0_CTRLB_DEBF_DIV16_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV32 (RTC_MODE0_CTRLB_DEBF_DIV32_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV64 (RTC_MODE0_CTRLB_DEBF_DIV64_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV128 (RTC_MODE0_CTRLB_DEBF_DIV128_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV256 (RTC_MODE0_CTRLB_DEBF_DIV256_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_Pos 12 /**< \brief (RTC_MODE0_CTRLB) Active Layer Freqnuency */
+#define RTC_MODE0_CTRLB_ACTF_Msk (_U_(0x7) << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF(value) (RTC_MODE0_CTRLB_ACTF_Msk & ((value) << RTC_MODE0_CTRLB_ACTF_Pos))
+#define RTC_MODE0_CTRLB_ACTF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */
+#define RTC_MODE0_CTRLB_ACTF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */
+#define RTC_MODE0_CTRLB_ACTF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */
+#define RTC_MODE0_CTRLB_ACTF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */
+#define RTC_MODE0_CTRLB_ACTF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */
+#define RTC_MODE0_CTRLB_ACTF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */
+#define RTC_MODE0_CTRLB_ACTF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */
+#define RTC_MODE0_CTRLB_ACTF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */
+#define RTC_MODE0_CTRLB_ACTF_DIV2 (RTC_MODE0_CTRLB_ACTF_DIV2_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV4 (RTC_MODE0_CTRLB_ACTF_DIV4_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV8 (RTC_MODE0_CTRLB_ACTF_DIV8_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV16 (RTC_MODE0_CTRLB_ACTF_DIV16_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV32 (RTC_MODE0_CTRLB_ACTF_DIV32_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV64 (RTC_MODE0_CTRLB_ACTF_DIV64_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV128 (RTC_MODE0_CTRLB_ACTF_DIV128_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV256 (RTC_MODE0_CTRLB_ACTF_DIV256_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_MASK _U_(0x77F3) /**< \brief (RTC_MODE0_CTRLB) MASK Register */
+
+/* -------- RTC_MODE1_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE1 MODE1 Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t GP0EN:1; /*!< bit: 0 General Purpose 0 Enable */
+ uint16_t GP2EN:1; /*!< bit: 1 General Purpose 2 Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t DEBMAJ:1; /*!< bit: 4 Debouncer Majority Enable */
+ uint16_t DEBASYNC:1; /*!< bit: 5 Debouncer Asynchronous Enable */
+ uint16_t RTCOUT:1; /*!< bit: 6 RTC Output Enable */
+ uint16_t DMAEN:1; /*!< bit: 7 DMA Enable */
+ uint16_t DEBF:3; /*!< bit: 8..10 Debounce Freqnuency */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t ACTF:3; /*!< bit: 12..14 Active Layer Freqnuency */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_CTRLB_OFFSET 0x02 /**< \brief (RTC_MODE1_CTRLB offset) MODE1 Control B */
+#define RTC_MODE1_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_CTRLB reset_value) MODE1 Control B */
+
+#define RTC_MODE1_CTRLB_GP0EN_Pos 0 /**< \brief (RTC_MODE1_CTRLB) General Purpose 0 Enable */
+#define RTC_MODE1_CTRLB_GP0EN (_U_(0x1) << RTC_MODE1_CTRLB_GP0EN_Pos)
+#define RTC_MODE1_CTRLB_GP2EN_Pos 1 /**< \brief (RTC_MODE1_CTRLB) General Purpose 2 Enable */
+#define RTC_MODE1_CTRLB_GP2EN (_U_(0x1) << RTC_MODE1_CTRLB_GP2EN_Pos)
+#define RTC_MODE1_CTRLB_DEBMAJ_Pos 4 /**< \brief (RTC_MODE1_CTRLB) Debouncer Majority Enable */
+#define RTC_MODE1_CTRLB_DEBMAJ (_U_(0x1) << RTC_MODE1_CTRLB_DEBMAJ_Pos)
+#define RTC_MODE1_CTRLB_DEBASYNC_Pos 5 /**< \brief (RTC_MODE1_CTRLB) Debouncer Asynchronous Enable */
+#define RTC_MODE1_CTRLB_DEBASYNC (_U_(0x1) << RTC_MODE1_CTRLB_DEBASYNC_Pos)
+#define RTC_MODE1_CTRLB_RTCOUT_Pos 6 /**< \brief (RTC_MODE1_CTRLB) RTC Output Enable */
+#define RTC_MODE1_CTRLB_RTCOUT (_U_(0x1) << RTC_MODE1_CTRLB_RTCOUT_Pos)
+#define RTC_MODE1_CTRLB_DMAEN_Pos 7 /**< \brief (RTC_MODE1_CTRLB) DMA Enable */
+#define RTC_MODE1_CTRLB_DMAEN (_U_(0x1) << RTC_MODE1_CTRLB_DMAEN_Pos)
+#define RTC_MODE1_CTRLB_DEBF_Pos 8 /**< \brief (RTC_MODE1_CTRLB) Debounce Freqnuency */
+#define RTC_MODE1_CTRLB_DEBF_Msk (_U_(0x7) << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF(value) (RTC_MODE1_CTRLB_DEBF_Msk & ((value) << RTC_MODE1_CTRLB_DEBF_Pos))
+#define RTC_MODE1_CTRLB_DEBF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */
+#define RTC_MODE1_CTRLB_DEBF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */
+#define RTC_MODE1_CTRLB_DEBF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */
+#define RTC_MODE1_CTRLB_DEBF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */
+#define RTC_MODE1_CTRLB_DEBF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */
+#define RTC_MODE1_CTRLB_DEBF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */
+#define RTC_MODE1_CTRLB_DEBF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */
+#define RTC_MODE1_CTRLB_DEBF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */
+#define RTC_MODE1_CTRLB_DEBF_DIV2 (RTC_MODE1_CTRLB_DEBF_DIV2_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV4 (RTC_MODE1_CTRLB_DEBF_DIV4_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV8 (RTC_MODE1_CTRLB_DEBF_DIV8_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV16 (RTC_MODE1_CTRLB_DEBF_DIV16_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV32 (RTC_MODE1_CTRLB_DEBF_DIV32_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV64 (RTC_MODE1_CTRLB_DEBF_DIV64_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV128 (RTC_MODE1_CTRLB_DEBF_DIV128_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV256 (RTC_MODE1_CTRLB_DEBF_DIV256_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_Pos 12 /**< \brief (RTC_MODE1_CTRLB) Active Layer Freqnuency */
+#define RTC_MODE1_CTRLB_ACTF_Msk (_U_(0x7) << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF(value) (RTC_MODE1_CTRLB_ACTF_Msk & ((value) << RTC_MODE1_CTRLB_ACTF_Pos))
+#define RTC_MODE1_CTRLB_ACTF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */
+#define RTC_MODE1_CTRLB_ACTF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */
+#define RTC_MODE1_CTRLB_ACTF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */
+#define RTC_MODE1_CTRLB_ACTF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */
+#define RTC_MODE1_CTRLB_ACTF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */
+#define RTC_MODE1_CTRLB_ACTF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */
+#define RTC_MODE1_CTRLB_ACTF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */
+#define RTC_MODE1_CTRLB_ACTF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */
+#define RTC_MODE1_CTRLB_ACTF_DIV2 (RTC_MODE1_CTRLB_ACTF_DIV2_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV4 (RTC_MODE1_CTRLB_ACTF_DIV4_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV8 (RTC_MODE1_CTRLB_ACTF_DIV8_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV16 (RTC_MODE1_CTRLB_ACTF_DIV16_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV32 (RTC_MODE1_CTRLB_ACTF_DIV32_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV64 (RTC_MODE1_CTRLB_ACTF_DIV64_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV128 (RTC_MODE1_CTRLB_ACTF_DIV128_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV256 (RTC_MODE1_CTRLB_ACTF_DIV256_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_MASK _U_(0x77F3) /**< \brief (RTC_MODE1_CTRLB) MASK Register */
+
+/* -------- RTC_MODE2_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE2 MODE2 Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t GP0EN:1; /*!< bit: 0 General Purpose 0 Enable */
+ uint16_t GP2EN:1; /*!< bit: 1 General Purpose 2 Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t DEBMAJ:1; /*!< bit: 4 Debouncer Majority Enable */
+ uint16_t DEBASYNC:1; /*!< bit: 5 Debouncer Asynchronous Enable */
+ uint16_t RTCOUT:1; /*!< bit: 6 RTC Output Enable */
+ uint16_t DMAEN:1; /*!< bit: 7 DMA Enable */
+ uint16_t DEBF:3; /*!< bit: 8..10 Debounce Freqnuency */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t ACTF:3; /*!< bit: 12..14 Active Layer Freqnuency */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE2_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CTRLB_OFFSET 0x02 /**< \brief (RTC_MODE2_CTRLB offset) MODE2 Control B */
+#define RTC_MODE2_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_CTRLB reset_value) MODE2 Control B */
+
+#define RTC_MODE2_CTRLB_GP0EN_Pos 0 /**< \brief (RTC_MODE2_CTRLB) General Purpose 0 Enable */
+#define RTC_MODE2_CTRLB_GP0EN (_U_(0x1) << RTC_MODE2_CTRLB_GP0EN_Pos)
+#define RTC_MODE2_CTRLB_GP2EN_Pos 1 /**< \brief (RTC_MODE2_CTRLB) General Purpose 2 Enable */
+#define RTC_MODE2_CTRLB_GP2EN (_U_(0x1) << RTC_MODE2_CTRLB_GP2EN_Pos)
+#define RTC_MODE2_CTRLB_DEBMAJ_Pos 4 /**< \brief (RTC_MODE2_CTRLB) Debouncer Majority Enable */
+#define RTC_MODE2_CTRLB_DEBMAJ (_U_(0x1) << RTC_MODE2_CTRLB_DEBMAJ_Pos)
+#define RTC_MODE2_CTRLB_DEBASYNC_Pos 5 /**< \brief (RTC_MODE2_CTRLB) Debouncer Asynchronous Enable */
+#define RTC_MODE2_CTRLB_DEBASYNC (_U_(0x1) << RTC_MODE2_CTRLB_DEBASYNC_Pos)
+#define RTC_MODE2_CTRLB_RTCOUT_Pos 6 /**< \brief (RTC_MODE2_CTRLB) RTC Output Enable */
+#define RTC_MODE2_CTRLB_RTCOUT (_U_(0x1) << RTC_MODE2_CTRLB_RTCOUT_Pos)
+#define RTC_MODE2_CTRLB_DMAEN_Pos 7 /**< \brief (RTC_MODE2_CTRLB) DMA Enable */
+#define RTC_MODE2_CTRLB_DMAEN (_U_(0x1) << RTC_MODE2_CTRLB_DMAEN_Pos)
+#define RTC_MODE2_CTRLB_DEBF_Pos 8 /**< \brief (RTC_MODE2_CTRLB) Debounce Freqnuency */
+#define RTC_MODE2_CTRLB_DEBF_Msk (_U_(0x7) << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF(value) (RTC_MODE2_CTRLB_DEBF_Msk & ((value) << RTC_MODE2_CTRLB_DEBF_Pos))
+#define RTC_MODE2_CTRLB_DEBF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */
+#define RTC_MODE2_CTRLB_DEBF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */
+#define RTC_MODE2_CTRLB_DEBF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */
+#define RTC_MODE2_CTRLB_DEBF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */
+#define RTC_MODE2_CTRLB_DEBF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */
+#define RTC_MODE2_CTRLB_DEBF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */
+#define RTC_MODE2_CTRLB_DEBF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */
+#define RTC_MODE2_CTRLB_DEBF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */
+#define RTC_MODE2_CTRLB_DEBF_DIV2 (RTC_MODE2_CTRLB_DEBF_DIV2_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV4 (RTC_MODE2_CTRLB_DEBF_DIV4_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV8 (RTC_MODE2_CTRLB_DEBF_DIV8_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV16 (RTC_MODE2_CTRLB_DEBF_DIV16_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV32 (RTC_MODE2_CTRLB_DEBF_DIV32_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV64 (RTC_MODE2_CTRLB_DEBF_DIV64_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV128 (RTC_MODE2_CTRLB_DEBF_DIV128_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV256 (RTC_MODE2_CTRLB_DEBF_DIV256_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_Pos 12 /**< \brief (RTC_MODE2_CTRLB) Active Layer Freqnuency */
+#define RTC_MODE2_CTRLB_ACTF_Msk (_U_(0x7) << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF(value) (RTC_MODE2_CTRLB_ACTF_Msk & ((value) << RTC_MODE2_CTRLB_ACTF_Pos))
+#define RTC_MODE2_CTRLB_ACTF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */
+#define RTC_MODE2_CTRLB_ACTF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */
+#define RTC_MODE2_CTRLB_ACTF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */
+#define RTC_MODE2_CTRLB_ACTF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */
+#define RTC_MODE2_CTRLB_ACTF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */
+#define RTC_MODE2_CTRLB_ACTF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */
+#define RTC_MODE2_CTRLB_ACTF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */
+#define RTC_MODE2_CTRLB_ACTF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */
+#define RTC_MODE2_CTRLB_ACTF_DIV2 (RTC_MODE2_CTRLB_ACTF_DIV2_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV4 (RTC_MODE2_CTRLB_ACTF_DIV4_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV8 (RTC_MODE2_CTRLB_ACTF_DIV8_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV16 (RTC_MODE2_CTRLB_ACTF_DIV16_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV32 (RTC_MODE2_CTRLB_ACTF_DIV32_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV64 (RTC_MODE2_CTRLB_ACTF_DIV64_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV128 (RTC_MODE2_CTRLB_ACTF_DIV128_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV256 (RTC_MODE2_CTRLB_ACTF_DIV256_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_MASK _U_(0x77F3) /**< \brief (RTC_MODE2_CTRLB) MASK Register */
+
+/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE0 MODE0 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint32_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
+ uint32_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
+ uint32_t :4; /*!< bit: 10..13 Reserved */
+ uint32_t TAMPEREO:1; /*!< bit: 14 Tamper Event Output Enable */
+ uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ uint32_t TAMPEVEI:1; /*!< bit: 16 Tamper Event Input Enable */
+ uint32_t :15; /*!< bit: 17..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint32_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE0_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */
+#define RTC_MODE0_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */
+
+#define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO0 (_U_(1) << RTC_MODE0_EVCTRL_PEREO0_Pos)
+#define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO1 (_U_(1) << RTC_MODE0_EVCTRL_PEREO1_Pos)
+#define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO2 (_U_(1) << RTC_MODE0_EVCTRL_PEREO2_Pos)
+#define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO3 (_U_(1) << RTC_MODE0_EVCTRL_PEREO3_Pos)
+#define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO4 (_U_(1) << RTC_MODE0_EVCTRL_PEREO4_Pos)
+#define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO5 (_U_(1) << RTC_MODE0_EVCTRL_PEREO5_Pos)
+#define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO6 (_U_(1) << RTC_MODE0_EVCTRL_PEREO6_Pos)
+#define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO7 (_U_(1) << RTC_MODE0_EVCTRL_PEREO7_Pos)
+#define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE0_EVCTRL_PEREO_Pos)
+#define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))
+#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO0 (_U_(1) << RTC_MODE0_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE0_EVCTRL) Compare 1 Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO1 (_U_(1) << RTC_MODE0_EVCTRL_CMPEO1_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO_Msk (_U_(0x3) << RTC_MODE0_EVCTRL_CMPEO_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))
+#define RTC_MODE0_EVCTRL_TAMPEREO_Pos 14 /**< \brief (RTC_MODE0_EVCTRL) Tamper Event Output Enable */
+#define RTC_MODE0_EVCTRL_TAMPEREO (_U_(0x1) << RTC_MODE0_EVCTRL_TAMPEREO_Pos)
+#define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE0_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE0_EVCTRL_OVFEO_Pos)
+#define RTC_MODE0_EVCTRL_TAMPEVEI_Pos 16 /**< \brief (RTC_MODE0_EVCTRL) Tamper Event Input Enable */
+#define RTC_MODE0_EVCTRL_TAMPEVEI (_U_(0x1) << RTC_MODE0_EVCTRL_TAMPEVEI_Pos)
+#define RTC_MODE0_EVCTRL_MASK _U_(0x0001C3FF) /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE1 MODE1 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint32_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
+ uint32_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
+ uint32_t CMPEO2:1; /*!< bit: 10 Compare 2 Event Output Enable */
+ uint32_t CMPEO3:1; /*!< bit: 11 Compare 3 Event Output Enable */
+ uint32_t :2; /*!< bit: 12..13 Reserved */
+ uint32_t TAMPEREO:1; /*!< bit: 14 Tamper Event Output Enable */
+ uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ uint32_t TAMPEVEI:1; /*!< bit: 16 Tamper Event Input Enable */
+ uint32_t :15; /*!< bit: 17..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint32_t CMPEO:4; /*!< bit: 8..11 Compare x Event Output Enable */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE1_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */
+#define RTC_MODE1_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */
+
+#define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO0 (_U_(1) << RTC_MODE1_EVCTRL_PEREO0_Pos)
+#define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO1 (_U_(1) << RTC_MODE1_EVCTRL_PEREO1_Pos)
+#define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO2 (_U_(1) << RTC_MODE1_EVCTRL_PEREO2_Pos)
+#define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO3 (_U_(1) << RTC_MODE1_EVCTRL_PEREO3_Pos)
+#define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO4 (_U_(1) << RTC_MODE1_EVCTRL_PEREO4_Pos)
+#define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO5 (_U_(1) << RTC_MODE1_EVCTRL_PEREO5_Pos)
+#define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO6 (_U_(1) << RTC_MODE1_EVCTRL_PEREO6_Pos)
+#define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO7 (_U_(1) << RTC_MODE1_EVCTRL_PEREO7_Pos)
+#define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE1_EVCTRL_PEREO_Pos)
+#define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))
+#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO0 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO1 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO1_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO2_Pos 10 /**< \brief (RTC_MODE1_EVCTRL) Compare 2 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO2 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO2_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO3_Pos 11 /**< \brief (RTC_MODE1_EVCTRL) Compare 3 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO3 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO3_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO_Msk (_U_(0xF) << RTC_MODE1_EVCTRL_CMPEO_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))
+#define RTC_MODE1_EVCTRL_TAMPEREO_Pos 14 /**< \brief (RTC_MODE1_EVCTRL) Tamper Event Output Enable */
+#define RTC_MODE1_EVCTRL_TAMPEREO (_U_(0x1) << RTC_MODE1_EVCTRL_TAMPEREO_Pos)
+#define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE1_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE1_EVCTRL_OVFEO_Pos)
+#define RTC_MODE1_EVCTRL_TAMPEVEI_Pos 16 /**< \brief (RTC_MODE1_EVCTRL) Tamper Event Input Enable */
+#define RTC_MODE1_EVCTRL_TAMPEVEI (_U_(0x1) << RTC_MODE1_EVCTRL_TAMPEVEI_Pos)
+#define RTC_MODE1_EVCTRL_MASK _U_(0x0001CFFF) /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE2 MODE2 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint32_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
+ uint32_t ALARMEO1:1; /*!< bit: 9 Alarm 1 Event Output Enable */
+ uint32_t :4; /*!< bit: 10..13 Reserved */
+ uint32_t TAMPEREO:1; /*!< bit: 14 Tamper Event Output Enable */
+ uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ uint32_t TAMPEVEI:1; /*!< bit: 16 Tamper Event Input Enable */
+ uint32_t :15; /*!< bit: 17..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint32_t ALARMEO:2; /*!< bit: 8.. 9 Alarm x Event Output Enable */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE2_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */
+#define RTC_MODE2_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */
+
+#define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO0 (_U_(1) << RTC_MODE2_EVCTRL_PEREO0_Pos)
+#define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO1 (_U_(1) << RTC_MODE2_EVCTRL_PEREO1_Pos)
+#define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO2 (_U_(1) << RTC_MODE2_EVCTRL_PEREO2_Pos)
+#define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO3 (_U_(1) << RTC_MODE2_EVCTRL_PEREO3_Pos)
+#define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO4 (_U_(1) << RTC_MODE2_EVCTRL_PEREO4_Pos)
+#define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO5 (_U_(1) << RTC_MODE2_EVCTRL_PEREO5_Pos)
+#define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO6 (_U_(1) << RTC_MODE2_EVCTRL_PEREO6_Pos)
+#define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO7 (_U_(1) << RTC_MODE2_EVCTRL_PEREO7_Pos)
+#define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE2_EVCTRL_PEREO_Pos)
+#define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))
+#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO0 (_U_(1) << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO1_Pos 9 /**< \brief (RTC_MODE2_EVCTRL) Alarm 1 Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO1 (_U_(1) << RTC_MODE2_EVCTRL_ALARMEO1_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO_Msk (_U_(0x3) << RTC_MODE2_EVCTRL_ALARMEO_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))
+#define RTC_MODE2_EVCTRL_TAMPEREO_Pos 14 /**< \brief (RTC_MODE2_EVCTRL) Tamper Event Output Enable */
+#define RTC_MODE2_EVCTRL_TAMPEREO (_U_(0x1) << RTC_MODE2_EVCTRL_TAMPEREO_Pos)
+#define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE2_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE2_EVCTRL_OVFEO_Pos)
+#define RTC_MODE2_EVCTRL_TAMPEVEI_Pos 16 /**< \brief (RTC_MODE2_EVCTRL) Tamper Event Input Enable */
+#define RTC_MODE2_EVCTRL_TAMPEVEI (_U_(0x1) << RTC_MODE2_EVCTRL_TAMPEVEI_Pos)
+#define RTC_MODE2_EVCTRL_MASK _U_(0x0001C3FF) /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE0 MODE0 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
+ uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
+ uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
+ uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
+ uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
+ uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
+ uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
+ uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
+ uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */
+ uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */
+ uint16_t :4; /*!< bit: 10..13 Reserved */
+ uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
+ uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
+ uint16_t CMP:2; /*!< bit: 8.. 9 Compare x Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE0_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */
+#define RTC_MODE0_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */
+
+#define RTC_MODE0_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 0 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER0 (_U_(1) << RTC_MODE0_INTENCLR_PER0_Pos)
+#define RTC_MODE0_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 1 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER1 (_U_(1) << RTC_MODE0_INTENCLR_PER1_Pos)
+#define RTC_MODE0_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 2 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER2 (_U_(1) << RTC_MODE0_INTENCLR_PER2_Pos)
+#define RTC_MODE0_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 3 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER3 (_U_(1) << RTC_MODE0_INTENCLR_PER3_Pos)
+#define RTC_MODE0_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 4 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER4 (_U_(1) << RTC_MODE0_INTENCLR_PER4_Pos)
+#define RTC_MODE0_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 5 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER5 (_U_(1) << RTC_MODE0_INTENCLR_PER5_Pos)
+#define RTC_MODE0_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 6 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER6 (_U_(1) << RTC_MODE0_INTENCLR_PER6_Pos)
+#define RTC_MODE0_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 7 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER7 (_U_(1) << RTC_MODE0_INTENCLR_PER7_Pos)
+#define RTC_MODE0_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval x Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER_Msk (_U_(0xFF) << RTC_MODE0_INTENCLR_PER_Pos)
+#define RTC_MODE0_INTENCLR_PER(value) (RTC_MODE0_INTENCLR_PER_Msk & ((value) << RTC_MODE0_INTENCLR_PER_Pos))
+#define RTC_MODE0_INTENCLR_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP0 (_U_(1) << RTC_MODE0_INTENCLR_CMP0_Pos)
+#define RTC_MODE0_INTENCLR_CMP1_Pos 9 /**< \brief (RTC_MODE0_INTENCLR) Compare 1 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP1 (_U_(1) << RTC_MODE0_INTENCLR_CMP1_Pos)
+#define RTC_MODE0_INTENCLR_CMP_Pos 8 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP_Msk (_U_(0x3) << RTC_MODE0_INTENCLR_CMP_Pos)
+#define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))
+#define RTC_MODE0_INTENCLR_TAMPER_Pos 14 /**< \brief (RTC_MODE0_INTENCLR) Tamper Enable */
+#define RTC_MODE0_INTENCLR_TAMPER (_U_(0x1) << RTC_MODE0_INTENCLR_TAMPER_Pos)
+#define RTC_MODE0_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENCLR_OVF (_U_(0x1) << RTC_MODE0_INTENCLR_OVF_Pos)
+#define RTC_MODE0_INTENCLR_MASK _U_(0xC3FF) /**< \brief (RTC_MODE0_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE1 MODE1 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
+ uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
+ uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
+ uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
+ uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
+ uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
+ uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
+ uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
+ uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */
+ uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */
+ uint16_t CMP2:1; /*!< bit: 10 Compare 2 Interrupt Enable */
+ uint16_t CMP3:1; /*!< bit: 11 Compare 3 Interrupt Enable */
+ uint16_t :2; /*!< bit: 12..13 Reserved */
+ uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
+ uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
+ uint16_t CMP:4; /*!< bit: 8..11 Compare x Interrupt Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */
+#define RTC_MODE1_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */
+
+#define RTC_MODE1_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 0 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER0 (_U_(1) << RTC_MODE1_INTENCLR_PER0_Pos)
+#define RTC_MODE1_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 1 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER1 (_U_(1) << RTC_MODE1_INTENCLR_PER1_Pos)
+#define RTC_MODE1_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 2 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER2 (_U_(1) << RTC_MODE1_INTENCLR_PER2_Pos)
+#define RTC_MODE1_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 3 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER3 (_U_(1) << RTC_MODE1_INTENCLR_PER3_Pos)
+#define RTC_MODE1_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 4 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER4 (_U_(1) << RTC_MODE1_INTENCLR_PER4_Pos)
+#define RTC_MODE1_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 5 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER5 (_U_(1) << RTC_MODE1_INTENCLR_PER5_Pos)
+#define RTC_MODE1_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 6 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER6 (_U_(1) << RTC_MODE1_INTENCLR_PER6_Pos)
+#define RTC_MODE1_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 7 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER7 (_U_(1) << RTC_MODE1_INTENCLR_PER7_Pos)
+#define RTC_MODE1_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval x Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER_Msk (_U_(0xFF) << RTC_MODE1_INTENCLR_PER_Pos)
+#define RTC_MODE1_INTENCLR_PER(value) (RTC_MODE1_INTENCLR_PER_Msk & ((value) << RTC_MODE1_INTENCLR_PER_Pos))
+#define RTC_MODE1_INTENCLR_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP0 (_U_(1) << RTC_MODE1_INTENCLR_CMP0_Pos)
+#define RTC_MODE1_INTENCLR_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP1 (_U_(1) << RTC_MODE1_INTENCLR_CMP1_Pos)
+#define RTC_MODE1_INTENCLR_CMP2_Pos 10 /**< \brief (RTC_MODE1_INTENCLR) Compare 2 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP2 (_U_(1) << RTC_MODE1_INTENCLR_CMP2_Pos)
+#define RTC_MODE1_INTENCLR_CMP3_Pos 11 /**< \brief (RTC_MODE1_INTENCLR) Compare 3 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP3 (_U_(1) << RTC_MODE1_INTENCLR_CMP3_Pos)
+#define RTC_MODE1_INTENCLR_CMP_Pos 8 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP_Msk (_U_(0xF) << RTC_MODE1_INTENCLR_CMP_Pos)
+#define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))
+#define RTC_MODE1_INTENCLR_TAMPER_Pos 14 /**< \brief (RTC_MODE1_INTENCLR) Tamper Enable */
+#define RTC_MODE1_INTENCLR_TAMPER (_U_(0x1) << RTC_MODE1_INTENCLR_TAMPER_Pos)
+#define RTC_MODE1_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENCLR_OVF (_U_(0x1) << RTC_MODE1_INTENCLR_OVF_Pos)
+#define RTC_MODE1_INTENCLR_MASK _U_(0xCFFF) /**< \brief (RTC_MODE1_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE2 MODE2 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
+ uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
+ uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
+ uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
+ uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
+ uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
+ uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
+ uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
+ uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 Interrupt Enable */
+ uint16_t ALARM1:1; /*!< bit: 9 Alarm 1 Interrupt Enable */
+ uint16_t :4; /*!< bit: 10..13 Reserved */
+ uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
+ uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
+ uint16_t ALARM:2; /*!< bit: 8.. 9 Alarm x Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE2_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */
+#define RTC_MODE2_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */
+
+#define RTC_MODE2_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 0 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER0 (_U_(1) << RTC_MODE2_INTENCLR_PER0_Pos)
+#define RTC_MODE2_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 1 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER1 (_U_(1) << RTC_MODE2_INTENCLR_PER1_Pos)
+#define RTC_MODE2_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 2 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER2 (_U_(1) << RTC_MODE2_INTENCLR_PER2_Pos)
+#define RTC_MODE2_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 3 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER3 (_U_(1) << RTC_MODE2_INTENCLR_PER3_Pos)
+#define RTC_MODE2_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 4 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER4 (_U_(1) << RTC_MODE2_INTENCLR_PER4_Pos)
+#define RTC_MODE2_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 5 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER5 (_U_(1) << RTC_MODE2_INTENCLR_PER5_Pos)
+#define RTC_MODE2_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 6 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER6 (_U_(1) << RTC_MODE2_INTENCLR_PER6_Pos)
+#define RTC_MODE2_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 7 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER7 (_U_(1) << RTC_MODE2_INTENCLR_PER7_Pos)
+#define RTC_MODE2_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval x Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER_Msk (_U_(0xFF) << RTC_MODE2_INTENCLR_PER_Pos)
+#define RTC_MODE2_INTENCLR_PER(value) (RTC_MODE2_INTENCLR_PER_Msk & ((value) << RTC_MODE2_INTENCLR_PER_Pos))
+#define RTC_MODE2_INTENCLR_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM0 (_U_(1) << RTC_MODE2_INTENCLR_ALARM0_Pos)
+#define RTC_MODE2_INTENCLR_ALARM1_Pos 9 /**< \brief (RTC_MODE2_INTENCLR) Alarm 1 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM1 (_U_(1) << RTC_MODE2_INTENCLR_ALARM1_Pos)
+#define RTC_MODE2_INTENCLR_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTENCLR_ALARM_Pos)
+#define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))
+#define RTC_MODE2_INTENCLR_TAMPER_Pos 14 /**< \brief (RTC_MODE2_INTENCLR) Tamper Enable */
+#define RTC_MODE2_INTENCLR_TAMPER (_U_(0x1) << RTC_MODE2_INTENCLR_TAMPER_Pos)
+#define RTC_MODE2_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENCLR_OVF (_U_(0x1) << RTC_MODE2_INTENCLR_OVF_Pos)
+#define RTC_MODE2_INTENCLR_MASK _U_(0xC3FF) /**< \brief (RTC_MODE2_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE0 MODE0 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
+ uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
+ uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
+ uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
+ uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
+ uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
+ uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
+ uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
+ uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */
+ uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */
+ uint16_t :4; /*!< bit: 10..13 Reserved */
+ uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
+ uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
+ uint16_t CMP:2; /*!< bit: 8.. 9 Compare x Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE0_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */
+#define RTC_MODE0_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */
+
+#define RTC_MODE0_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 0 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER0 (_U_(1) << RTC_MODE0_INTENSET_PER0_Pos)
+#define RTC_MODE0_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 1 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER1 (_U_(1) << RTC_MODE0_INTENSET_PER1_Pos)
+#define RTC_MODE0_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 2 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER2 (_U_(1) << RTC_MODE0_INTENSET_PER2_Pos)
+#define RTC_MODE0_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 3 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER3 (_U_(1) << RTC_MODE0_INTENSET_PER3_Pos)
+#define RTC_MODE0_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 4 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER4 (_U_(1) << RTC_MODE0_INTENSET_PER4_Pos)
+#define RTC_MODE0_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 5 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER5 (_U_(1) << RTC_MODE0_INTENSET_PER5_Pos)
+#define RTC_MODE0_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 6 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER6 (_U_(1) << RTC_MODE0_INTENSET_PER6_Pos)
+#define RTC_MODE0_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 7 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER7 (_U_(1) << RTC_MODE0_INTENSET_PER7_Pos)
+#define RTC_MODE0_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval x Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER_Msk (_U_(0xFF) << RTC_MODE0_INTENSET_PER_Pos)
+#define RTC_MODE0_INTENSET_PER(value) (RTC_MODE0_INTENSET_PER_Msk & ((value) << RTC_MODE0_INTENSET_PER_Pos))
+#define RTC_MODE0_INTENSET_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP0 (_U_(1) << RTC_MODE0_INTENSET_CMP0_Pos)
+#define RTC_MODE0_INTENSET_CMP1_Pos 9 /**< \brief (RTC_MODE0_INTENSET) Compare 1 Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP1 (_U_(1) << RTC_MODE0_INTENSET_CMP1_Pos)
+#define RTC_MODE0_INTENSET_CMP_Pos 8 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP_Msk (_U_(0x3) << RTC_MODE0_INTENSET_CMP_Pos)
+#define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))
+#define RTC_MODE0_INTENSET_TAMPER_Pos 14 /**< \brief (RTC_MODE0_INTENSET) Tamper Enable */
+#define RTC_MODE0_INTENSET_TAMPER (_U_(0x1) << RTC_MODE0_INTENSET_TAMPER_Pos)
+#define RTC_MODE0_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENSET_OVF (_U_(0x1) << RTC_MODE0_INTENSET_OVF_Pos)
+#define RTC_MODE0_INTENSET_MASK _U_(0xC3FF) /**< \brief (RTC_MODE0_INTENSET) MASK Register */
+
+/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE1 MODE1 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
+ uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
+ uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
+ uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
+ uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
+ uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
+ uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
+ uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
+ uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */
+ uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */
+ uint16_t CMP2:1; /*!< bit: 10 Compare 2 Interrupt Enable */
+ uint16_t CMP3:1; /*!< bit: 11 Compare 3 Interrupt Enable */
+ uint16_t :2; /*!< bit: 12..13 Reserved */
+ uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
+ uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
+ uint16_t CMP:4; /*!< bit: 8..11 Compare x Interrupt Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */
+#define RTC_MODE1_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */
+
+#define RTC_MODE1_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 0 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER0 (_U_(1) << RTC_MODE1_INTENSET_PER0_Pos)
+#define RTC_MODE1_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 1 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER1 (_U_(1) << RTC_MODE1_INTENSET_PER1_Pos)
+#define RTC_MODE1_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 2 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER2 (_U_(1) << RTC_MODE1_INTENSET_PER2_Pos)
+#define RTC_MODE1_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 3 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER3 (_U_(1) << RTC_MODE1_INTENSET_PER3_Pos)
+#define RTC_MODE1_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 4 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER4 (_U_(1) << RTC_MODE1_INTENSET_PER4_Pos)
+#define RTC_MODE1_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 5 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER5 (_U_(1) << RTC_MODE1_INTENSET_PER5_Pos)
+#define RTC_MODE1_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 6 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER6 (_U_(1) << RTC_MODE1_INTENSET_PER6_Pos)
+#define RTC_MODE1_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 7 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER7 (_U_(1) << RTC_MODE1_INTENSET_PER7_Pos)
+#define RTC_MODE1_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval x Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER_Msk (_U_(0xFF) << RTC_MODE1_INTENSET_PER_Pos)
+#define RTC_MODE1_INTENSET_PER(value) (RTC_MODE1_INTENSET_PER_Msk & ((value) << RTC_MODE1_INTENSET_PER_Pos))
+#define RTC_MODE1_INTENSET_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP0 (_U_(1) << RTC_MODE1_INTENSET_CMP0_Pos)
+#define RTC_MODE1_INTENSET_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP1 (_U_(1) << RTC_MODE1_INTENSET_CMP1_Pos)
+#define RTC_MODE1_INTENSET_CMP2_Pos 10 /**< \brief (RTC_MODE1_INTENSET) Compare 2 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP2 (_U_(1) << RTC_MODE1_INTENSET_CMP2_Pos)
+#define RTC_MODE1_INTENSET_CMP3_Pos 11 /**< \brief (RTC_MODE1_INTENSET) Compare 3 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP3 (_U_(1) << RTC_MODE1_INTENSET_CMP3_Pos)
+#define RTC_MODE1_INTENSET_CMP_Pos 8 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP_Msk (_U_(0xF) << RTC_MODE1_INTENSET_CMP_Pos)
+#define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))
+#define RTC_MODE1_INTENSET_TAMPER_Pos 14 /**< \brief (RTC_MODE1_INTENSET) Tamper Enable */
+#define RTC_MODE1_INTENSET_TAMPER (_U_(0x1) << RTC_MODE1_INTENSET_TAMPER_Pos)
+#define RTC_MODE1_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENSET_OVF (_U_(0x1) << RTC_MODE1_INTENSET_OVF_Pos)
+#define RTC_MODE1_INTENSET_MASK _U_(0xCFFF) /**< \brief (RTC_MODE1_INTENSET) MASK Register */
+
+/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE2 MODE2 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Enable */
+ uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Enable */
+ uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Enable */
+ uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Enable */
+ uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Enable */
+ uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Enable */
+ uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Enable */
+ uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Enable */
+ uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 Interrupt Enable */
+ uint16_t ALARM1:1; /*!< bit: 9 Alarm 1 Interrupt Enable */
+ uint16_t :4; /*!< bit: 10..13 Reserved */
+ uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
+ uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Enable */
+ uint16_t ALARM:2; /*!< bit: 8.. 9 Alarm x Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE2_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */
+#define RTC_MODE2_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */
+
+#define RTC_MODE2_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 0 Enable */
+#define RTC_MODE2_INTENSET_PER0 (_U_(1) << RTC_MODE2_INTENSET_PER0_Pos)
+#define RTC_MODE2_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 1 Enable */
+#define RTC_MODE2_INTENSET_PER1 (_U_(1) << RTC_MODE2_INTENSET_PER1_Pos)
+#define RTC_MODE2_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 2 Enable */
+#define RTC_MODE2_INTENSET_PER2 (_U_(1) << RTC_MODE2_INTENSET_PER2_Pos)
+#define RTC_MODE2_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 3 Enable */
+#define RTC_MODE2_INTENSET_PER3 (_U_(1) << RTC_MODE2_INTENSET_PER3_Pos)
+#define RTC_MODE2_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 4 Enable */
+#define RTC_MODE2_INTENSET_PER4 (_U_(1) << RTC_MODE2_INTENSET_PER4_Pos)
+#define RTC_MODE2_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 5 Enable */
+#define RTC_MODE2_INTENSET_PER5 (_U_(1) << RTC_MODE2_INTENSET_PER5_Pos)
+#define RTC_MODE2_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 6 Enable */
+#define RTC_MODE2_INTENSET_PER6 (_U_(1) << RTC_MODE2_INTENSET_PER6_Pos)
+#define RTC_MODE2_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 7 Enable */
+#define RTC_MODE2_INTENSET_PER7 (_U_(1) << RTC_MODE2_INTENSET_PER7_Pos)
+#define RTC_MODE2_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval x Enable */
+#define RTC_MODE2_INTENSET_PER_Msk (_U_(0xFF) << RTC_MODE2_INTENSET_PER_Pos)
+#define RTC_MODE2_INTENSET_PER(value) (RTC_MODE2_INTENSET_PER_Msk & ((value) << RTC_MODE2_INTENSET_PER_Pos))
+#define RTC_MODE2_INTENSET_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM0 (_U_(1) << RTC_MODE2_INTENSET_ALARM0_Pos)
+#define RTC_MODE2_INTENSET_ALARM1_Pos 9 /**< \brief (RTC_MODE2_INTENSET) Alarm 1 Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM1 (_U_(1) << RTC_MODE2_INTENSET_ALARM1_Pos)
+#define RTC_MODE2_INTENSET_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTENSET_ALARM_Pos)
+#define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))
+#define RTC_MODE2_INTENSET_TAMPER_Pos 14 /**< \brief (RTC_MODE2_INTENSET) Tamper Enable */
+#define RTC_MODE2_INTENSET_TAMPER (_U_(0x1) << RTC_MODE2_INTENSET_TAMPER_Pos)
+#define RTC_MODE2_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENSET_OVF (_U_(0x1) << RTC_MODE2_INTENSET_OVF_Pos)
+#define RTC_MODE2_INTENSET_MASK _U_(0xC3FF) /**< \brief (RTC_MODE2_INTENSET) MASK Register */
+
+/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */
+ __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */
+ __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */
+ __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */
+ __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */
+ __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */
+ __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */
+ __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */
+ __I uint16_t CMP0:1; /*!< bit: 8 Compare 0 */
+ __I uint16_t CMP1:1; /*!< bit: 9 Compare 1 */
+ __I uint16_t :4; /*!< bit: 10..13 Reserved */
+ __I uint16_t TAMPER:1; /*!< bit: 14 Tamper */
+ __I uint16_t OVF:1; /*!< bit: 15 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */
+ __I uint16_t CMP:2; /*!< bit: 8.. 9 Compare x */
+ __I uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE0_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */
+#define RTC_MODE0_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */
+
+#define RTC_MODE0_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 0 */
+#define RTC_MODE0_INTFLAG_PER0 (_U_(1) << RTC_MODE0_INTFLAG_PER0_Pos)
+#define RTC_MODE0_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 1 */
+#define RTC_MODE0_INTFLAG_PER1 (_U_(1) << RTC_MODE0_INTFLAG_PER1_Pos)
+#define RTC_MODE0_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 2 */
+#define RTC_MODE0_INTFLAG_PER2 (_U_(1) << RTC_MODE0_INTFLAG_PER2_Pos)
+#define RTC_MODE0_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 3 */
+#define RTC_MODE0_INTFLAG_PER3 (_U_(1) << RTC_MODE0_INTFLAG_PER3_Pos)
+#define RTC_MODE0_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 4 */
+#define RTC_MODE0_INTFLAG_PER4 (_U_(1) << RTC_MODE0_INTFLAG_PER4_Pos)
+#define RTC_MODE0_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 5 */
+#define RTC_MODE0_INTFLAG_PER5 (_U_(1) << RTC_MODE0_INTFLAG_PER5_Pos)
+#define RTC_MODE0_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 6 */
+#define RTC_MODE0_INTFLAG_PER6 (_U_(1) << RTC_MODE0_INTFLAG_PER6_Pos)
+#define RTC_MODE0_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 7 */
+#define RTC_MODE0_INTFLAG_PER7 (_U_(1) << RTC_MODE0_INTFLAG_PER7_Pos)
+#define RTC_MODE0_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval x */
+#define RTC_MODE0_INTFLAG_PER_Msk (_U_(0xFF) << RTC_MODE0_INTFLAG_PER_Pos)
+#define RTC_MODE0_INTFLAG_PER(value) (RTC_MODE0_INTFLAG_PER_Msk & ((value) << RTC_MODE0_INTFLAG_PER_Pos))
+#define RTC_MODE0_INTFLAG_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */
+#define RTC_MODE0_INTFLAG_CMP0 (_U_(1) << RTC_MODE0_INTFLAG_CMP0_Pos)
+#define RTC_MODE0_INTFLAG_CMP1_Pos 9 /**< \brief (RTC_MODE0_INTFLAG) Compare 1 */
+#define RTC_MODE0_INTFLAG_CMP1 (_U_(1) << RTC_MODE0_INTFLAG_CMP1_Pos)
+#define RTC_MODE0_INTFLAG_CMP_Pos 8 /**< \brief (RTC_MODE0_INTFLAG) Compare x */
+#define RTC_MODE0_INTFLAG_CMP_Msk (_U_(0x3) << RTC_MODE0_INTFLAG_CMP_Pos)
+#define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))
+#define RTC_MODE0_INTFLAG_TAMPER_Pos 14 /**< \brief (RTC_MODE0_INTFLAG) Tamper */
+#define RTC_MODE0_INTFLAG_TAMPER (_U_(0x1) << RTC_MODE0_INTFLAG_TAMPER_Pos)
+#define RTC_MODE0_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE0_INTFLAG) Overflow */
+#define RTC_MODE0_INTFLAG_OVF (_U_(0x1) << RTC_MODE0_INTFLAG_OVF_Pos)
+#define RTC_MODE0_INTFLAG_MASK _U_(0xC3FF) /**< \brief (RTC_MODE0_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */
+ __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */
+ __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */
+ __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */
+ __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */
+ __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */
+ __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */
+ __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */
+ __I uint16_t CMP0:1; /*!< bit: 8 Compare 0 */
+ __I uint16_t CMP1:1; /*!< bit: 9 Compare 1 */
+ __I uint16_t CMP2:1; /*!< bit: 10 Compare 2 */
+ __I uint16_t CMP3:1; /*!< bit: 11 Compare 3 */
+ __I uint16_t :2; /*!< bit: 12..13 Reserved */
+ __I uint16_t TAMPER:1; /*!< bit: 14 Tamper */
+ __I uint16_t OVF:1; /*!< bit: 15 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */
+ __I uint16_t CMP:4; /*!< bit: 8..11 Compare x */
+ __I uint16_t :4; /*!< bit: 12..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */
+#define RTC_MODE1_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */
+
+#define RTC_MODE1_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 0 */
+#define RTC_MODE1_INTFLAG_PER0 (_U_(1) << RTC_MODE1_INTFLAG_PER0_Pos)
+#define RTC_MODE1_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 1 */
+#define RTC_MODE1_INTFLAG_PER1 (_U_(1) << RTC_MODE1_INTFLAG_PER1_Pos)
+#define RTC_MODE1_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 2 */
+#define RTC_MODE1_INTFLAG_PER2 (_U_(1) << RTC_MODE1_INTFLAG_PER2_Pos)
+#define RTC_MODE1_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 3 */
+#define RTC_MODE1_INTFLAG_PER3 (_U_(1) << RTC_MODE1_INTFLAG_PER3_Pos)
+#define RTC_MODE1_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 4 */
+#define RTC_MODE1_INTFLAG_PER4 (_U_(1) << RTC_MODE1_INTFLAG_PER4_Pos)
+#define RTC_MODE1_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 5 */
+#define RTC_MODE1_INTFLAG_PER5 (_U_(1) << RTC_MODE1_INTFLAG_PER5_Pos)
+#define RTC_MODE1_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 6 */
+#define RTC_MODE1_INTFLAG_PER6 (_U_(1) << RTC_MODE1_INTFLAG_PER6_Pos)
+#define RTC_MODE1_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 7 */
+#define RTC_MODE1_INTFLAG_PER7 (_U_(1) << RTC_MODE1_INTFLAG_PER7_Pos)
+#define RTC_MODE1_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval x */
+#define RTC_MODE1_INTFLAG_PER_Msk (_U_(0xFF) << RTC_MODE1_INTFLAG_PER_Pos)
+#define RTC_MODE1_INTFLAG_PER(value) (RTC_MODE1_INTFLAG_PER_Msk & ((value) << RTC_MODE1_INTFLAG_PER_Pos))
+#define RTC_MODE1_INTFLAG_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */
+#define RTC_MODE1_INTFLAG_CMP0 (_U_(1) << RTC_MODE1_INTFLAG_CMP0_Pos)
+#define RTC_MODE1_INTFLAG_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */
+#define RTC_MODE1_INTFLAG_CMP1 (_U_(1) << RTC_MODE1_INTFLAG_CMP1_Pos)
+#define RTC_MODE1_INTFLAG_CMP2_Pos 10 /**< \brief (RTC_MODE1_INTFLAG) Compare 2 */
+#define RTC_MODE1_INTFLAG_CMP2 (_U_(1) << RTC_MODE1_INTFLAG_CMP2_Pos)
+#define RTC_MODE1_INTFLAG_CMP3_Pos 11 /**< \brief (RTC_MODE1_INTFLAG) Compare 3 */
+#define RTC_MODE1_INTFLAG_CMP3 (_U_(1) << RTC_MODE1_INTFLAG_CMP3_Pos)
+#define RTC_MODE1_INTFLAG_CMP_Pos 8 /**< \brief (RTC_MODE1_INTFLAG) Compare x */
+#define RTC_MODE1_INTFLAG_CMP_Msk (_U_(0xF) << RTC_MODE1_INTFLAG_CMP_Pos)
+#define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))
+#define RTC_MODE1_INTFLAG_TAMPER_Pos 14 /**< \brief (RTC_MODE1_INTFLAG) Tamper */
+#define RTC_MODE1_INTFLAG_TAMPER (_U_(0x1) << RTC_MODE1_INTFLAG_TAMPER_Pos)
+#define RTC_MODE1_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE1_INTFLAG) Overflow */
+#define RTC_MODE1_INTFLAG_OVF (_U_(0x1) << RTC_MODE1_INTFLAG_OVF_Pos)
+#define RTC_MODE1_INTFLAG_MASK _U_(0xCFFF) /**< \brief (RTC_MODE1_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */
+ __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */
+ __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */
+ __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */
+ __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */
+ __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */
+ __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */
+ __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */
+ __I uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 */
+ __I uint16_t ALARM1:1; /*!< bit: 9 Alarm 1 */
+ __I uint16_t :4; /*!< bit: 10..13 Reserved */
+ __I uint16_t TAMPER:1; /*!< bit: 14 Tamper */
+ __I uint16_t OVF:1; /*!< bit: 15 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */
+ __I uint16_t ALARM:2; /*!< bit: 8.. 9 Alarm x */
+ __I uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE2_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */
+#define RTC_MODE2_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */
+
+#define RTC_MODE2_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 0 */
+#define RTC_MODE2_INTFLAG_PER0 (_U_(1) << RTC_MODE2_INTFLAG_PER0_Pos)
+#define RTC_MODE2_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 1 */
+#define RTC_MODE2_INTFLAG_PER1 (_U_(1) << RTC_MODE2_INTFLAG_PER1_Pos)
+#define RTC_MODE2_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 2 */
+#define RTC_MODE2_INTFLAG_PER2 (_U_(1) << RTC_MODE2_INTFLAG_PER2_Pos)
+#define RTC_MODE2_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 3 */
+#define RTC_MODE2_INTFLAG_PER3 (_U_(1) << RTC_MODE2_INTFLAG_PER3_Pos)
+#define RTC_MODE2_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 4 */
+#define RTC_MODE2_INTFLAG_PER4 (_U_(1) << RTC_MODE2_INTFLAG_PER4_Pos)
+#define RTC_MODE2_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 5 */
+#define RTC_MODE2_INTFLAG_PER5 (_U_(1) << RTC_MODE2_INTFLAG_PER5_Pos)
+#define RTC_MODE2_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 6 */
+#define RTC_MODE2_INTFLAG_PER6 (_U_(1) << RTC_MODE2_INTFLAG_PER6_Pos)
+#define RTC_MODE2_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 7 */
+#define RTC_MODE2_INTFLAG_PER7 (_U_(1) << RTC_MODE2_INTFLAG_PER7_Pos)
+#define RTC_MODE2_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval x */
+#define RTC_MODE2_INTFLAG_PER_Msk (_U_(0xFF) << RTC_MODE2_INTFLAG_PER_Pos)
+#define RTC_MODE2_INTFLAG_PER(value) (RTC_MODE2_INTFLAG_PER_Msk & ((value) << RTC_MODE2_INTFLAG_PER_Pos))
+#define RTC_MODE2_INTFLAG_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */
+#define RTC_MODE2_INTFLAG_ALARM0 (_U_(1) << RTC_MODE2_INTFLAG_ALARM0_Pos)
+#define RTC_MODE2_INTFLAG_ALARM1_Pos 9 /**< \brief (RTC_MODE2_INTFLAG) Alarm 1 */
+#define RTC_MODE2_INTFLAG_ALARM1 (_U_(1) << RTC_MODE2_INTFLAG_ALARM1_Pos)
+#define RTC_MODE2_INTFLAG_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
+#define RTC_MODE2_INTFLAG_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTFLAG_ALARM_Pos)
+#define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))
+#define RTC_MODE2_INTFLAG_TAMPER_Pos 14 /**< \brief (RTC_MODE2_INTFLAG) Tamper */
+#define RTC_MODE2_INTFLAG_TAMPER (_U_(0x1) << RTC_MODE2_INTFLAG_TAMPER_Pos)
+#define RTC_MODE2_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE2_INTFLAG) Overflow */
+#define RTC_MODE2_INTFLAG_OVF (_U_(0x1) << RTC_MODE2_INTFLAG_OVF_Pos)
+#define RTC_MODE2_INTFLAG_MASK _U_(0xC3FF) /**< \brief (RTC_MODE2_INTFLAG) MASK Register */
+
+/* -------- RTC_DBGCTRL : (RTC Offset: 0x0E) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_DBGCTRL_OFFSET 0x0E /**< \brief (RTC_DBGCTRL offset) Debug Control */
+#define RTC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (RTC_DBGCTRL reset_value) Debug Control */
+
+#define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */
+#define RTC_DBGCTRL_DBGRUN (_U_(0x1) << RTC_DBGCTRL_DBGRUN_Pos)
+#define RTC_DBGCTRL_MASK _U_(0x01) /**< \brief (RTC_DBGCTRL) MASK Register */
+
+/* -------- RTC_MODE0_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE0 MODE0 Synchronization Busy Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */
+ uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */
+ uint32_t COUNT:1; /*!< bit: 3 COUNT Register Busy */
+ uint32_t :1; /*!< bit: 4 Reserved */
+ uint32_t COMP0:1; /*!< bit: 5 COMP 0 Register Busy */
+ uint32_t COMP1:1; /*!< bit: 6 COMP 1 Register Busy */
+ uint32_t :8; /*!< bit: 7..14 Reserved */
+ uint32_t COUNTSYNC:1; /*!< bit: 15 Count Synchronization Enable Bit Busy */
+ uint32_t GP0:1; /*!< bit: 16 General Purpose 0 Register Busy */
+ uint32_t GP1:1; /*!< bit: 17 General Purpose 1 Register Busy */
+ uint32_t GP2:1; /*!< bit: 18 General Purpose 2 Register Busy */
+ uint32_t GP3:1; /*!< bit: 19 General Purpose 3 Register Busy */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :5; /*!< bit: 0.. 4 Reserved */
+ uint32_t COMP:2; /*!< bit: 5.. 6 COMP x Register Busy */
+ uint32_t :9; /*!< bit: 7..15 Reserved */
+ uint32_t GP:4; /*!< bit: 16..19 General Purpose x Register Busy */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE0_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE0_SYNCBUSY offset) MODE0 Synchronization Busy Status */
+#define RTC_MODE0_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_SYNCBUSY reset_value) MODE0 Synchronization Busy Status */
+
+#define RTC_MODE0_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE0_SYNCBUSY) Software Reset Busy */
+#define RTC_MODE0_SYNCBUSY_SWRST (_U_(0x1) << RTC_MODE0_SYNCBUSY_SWRST_Pos)
+#define RTC_MODE0_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE0_SYNCBUSY) Enable Bit Busy */
+#define RTC_MODE0_SYNCBUSY_ENABLE (_U_(0x1) << RTC_MODE0_SYNCBUSY_ENABLE_Pos)
+#define RTC_MODE0_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE0_SYNCBUSY) FREQCORR Register Busy */
+#define RTC_MODE0_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE0_SYNCBUSY_FREQCORR_Pos)
+#define RTC_MODE0_SYNCBUSY_COUNT_Pos 3 /**< \brief (RTC_MODE0_SYNCBUSY) COUNT Register Busy */
+#define RTC_MODE0_SYNCBUSY_COUNT (_U_(0x1) << RTC_MODE0_SYNCBUSY_COUNT_Pos)
+#define RTC_MODE0_SYNCBUSY_COMP0_Pos 5 /**< \brief (RTC_MODE0_SYNCBUSY) COMP 0 Register Busy */
+#define RTC_MODE0_SYNCBUSY_COMP0 (_U_(1) << RTC_MODE0_SYNCBUSY_COMP0_Pos)
+#define RTC_MODE0_SYNCBUSY_COMP1_Pos 6 /**< \brief (RTC_MODE0_SYNCBUSY) COMP 1 Register Busy */
+#define RTC_MODE0_SYNCBUSY_COMP1 (_U_(1) << RTC_MODE0_SYNCBUSY_COMP1_Pos)
+#define RTC_MODE0_SYNCBUSY_COMP_Pos 5 /**< \brief (RTC_MODE0_SYNCBUSY) COMP x Register Busy */
+#define RTC_MODE0_SYNCBUSY_COMP_Msk (_U_(0x3) << RTC_MODE0_SYNCBUSY_COMP_Pos)
+#define RTC_MODE0_SYNCBUSY_COMP(value) (RTC_MODE0_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE0_SYNCBUSY_COMP_Pos))
+#define RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE0_SYNCBUSY) Count Synchronization Enable Bit Busy */
+#define RTC_MODE0_SYNCBUSY_COUNTSYNC (_U_(0x1) << RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos)
+#define RTC_MODE0_SYNCBUSY_GP0_Pos 16 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 0 Register Busy */
+#define RTC_MODE0_SYNCBUSY_GP0 (_U_(1) << RTC_MODE0_SYNCBUSY_GP0_Pos)
+#define RTC_MODE0_SYNCBUSY_GP1_Pos 17 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 1 Register Busy */
+#define RTC_MODE0_SYNCBUSY_GP1 (_U_(1) << RTC_MODE0_SYNCBUSY_GP1_Pos)
+#define RTC_MODE0_SYNCBUSY_GP2_Pos 18 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 2 Register Busy */
+#define RTC_MODE0_SYNCBUSY_GP2 (_U_(1) << RTC_MODE0_SYNCBUSY_GP2_Pos)
+#define RTC_MODE0_SYNCBUSY_GP3_Pos 19 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 3 Register Busy */
+#define RTC_MODE0_SYNCBUSY_GP3 (_U_(1) << RTC_MODE0_SYNCBUSY_GP3_Pos)
+#define RTC_MODE0_SYNCBUSY_GP_Pos 16 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose x Register Busy */
+#define RTC_MODE0_SYNCBUSY_GP_Msk (_U_(0xF) << RTC_MODE0_SYNCBUSY_GP_Pos)
+#define RTC_MODE0_SYNCBUSY_GP(value) (RTC_MODE0_SYNCBUSY_GP_Msk & ((value) << RTC_MODE0_SYNCBUSY_GP_Pos))
+#define RTC_MODE0_SYNCBUSY_MASK _U_(0x000F806F) /**< \brief (RTC_MODE0_SYNCBUSY) MASK Register */
+
+/* -------- RTC_MODE1_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE1 MODE1 Synchronization Busy Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Bit Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */
+ uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */
+ uint32_t COUNT:1; /*!< bit: 3 COUNT Register Busy */
+ uint32_t PER:1; /*!< bit: 4 PER Register Busy */
+ uint32_t COMP0:1; /*!< bit: 5 COMP 0 Register Busy */
+ uint32_t COMP1:1; /*!< bit: 6 COMP 1 Register Busy */
+ uint32_t COMP2:1; /*!< bit: 7 COMP 2 Register Busy */
+ uint32_t COMP3:1; /*!< bit: 8 COMP 3 Register Busy */
+ uint32_t :6; /*!< bit: 9..14 Reserved */
+ uint32_t COUNTSYNC:1; /*!< bit: 15 Count Synchronization Enable Bit Busy */
+ uint32_t GP0:1; /*!< bit: 16 General Purpose 0 Register Busy */
+ uint32_t GP1:1; /*!< bit: 17 General Purpose 1 Register Busy */
+ uint32_t GP2:1; /*!< bit: 18 General Purpose 2 Register Busy */
+ uint32_t GP3:1; /*!< bit: 19 General Purpose 3 Register Busy */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :5; /*!< bit: 0.. 4 Reserved */
+ uint32_t COMP:4; /*!< bit: 5.. 8 COMP x Register Busy */
+ uint32_t :7; /*!< bit: 9..15 Reserved */
+ uint32_t GP:4; /*!< bit: 16..19 General Purpose x Register Busy */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE1_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE1_SYNCBUSY offset) MODE1 Synchronization Busy Status */
+#define RTC_MODE1_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE1_SYNCBUSY reset_value) MODE1 Synchronization Busy Status */
+
+#define RTC_MODE1_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE1_SYNCBUSY) Software Reset Bit Busy */
+#define RTC_MODE1_SYNCBUSY_SWRST (_U_(0x1) << RTC_MODE1_SYNCBUSY_SWRST_Pos)
+#define RTC_MODE1_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE1_SYNCBUSY) Enable Bit Busy */
+#define RTC_MODE1_SYNCBUSY_ENABLE (_U_(0x1) << RTC_MODE1_SYNCBUSY_ENABLE_Pos)
+#define RTC_MODE1_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE1_SYNCBUSY) FREQCORR Register Busy */
+#define RTC_MODE1_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE1_SYNCBUSY_FREQCORR_Pos)
+#define RTC_MODE1_SYNCBUSY_COUNT_Pos 3 /**< \brief (RTC_MODE1_SYNCBUSY) COUNT Register Busy */
+#define RTC_MODE1_SYNCBUSY_COUNT (_U_(0x1) << RTC_MODE1_SYNCBUSY_COUNT_Pos)
+#define RTC_MODE1_SYNCBUSY_PER_Pos 4 /**< \brief (RTC_MODE1_SYNCBUSY) PER Register Busy */
+#define RTC_MODE1_SYNCBUSY_PER (_U_(0x1) << RTC_MODE1_SYNCBUSY_PER_Pos)
+#define RTC_MODE1_SYNCBUSY_COMP0_Pos 5 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 0 Register Busy */
+#define RTC_MODE1_SYNCBUSY_COMP0 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP0_Pos)
+#define RTC_MODE1_SYNCBUSY_COMP1_Pos 6 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 1 Register Busy */
+#define RTC_MODE1_SYNCBUSY_COMP1 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP1_Pos)
+#define RTC_MODE1_SYNCBUSY_COMP2_Pos 7 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 2 Register Busy */
+#define RTC_MODE1_SYNCBUSY_COMP2 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP2_Pos)
+#define RTC_MODE1_SYNCBUSY_COMP3_Pos 8 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 3 Register Busy */
+#define RTC_MODE1_SYNCBUSY_COMP3 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP3_Pos)
+#define RTC_MODE1_SYNCBUSY_COMP_Pos 5 /**< \brief (RTC_MODE1_SYNCBUSY) COMP x Register Busy */
+#define RTC_MODE1_SYNCBUSY_COMP_Msk (_U_(0xF) << RTC_MODE1_SYNCBUSY_COMP_Pos)
+#define RTC_MODE1_SYNCBUSY_COMP(value) (RTC_MODE1_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE1_SYNCBUSY_COMP_Pos))
+#define RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE1_SYNCBUSY) Count Synchronization Enable Bit Busy */
+#define RTC_MODE1_SYNCBUSY_COUNTSYNC (_U_(0x1) << RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos)
+#define RTC_MODE1_SYNCBUSY_GP0_Pos 16 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 0 Register Busy */
+#define RTC_MODE1_SYNCBUSY_GP0 (_U_(1) << RTC_MODE1_SYNCBUSY_GP0_Pos)
+#define RTC_MODE1_SYNCBUSY_GP1_Pos 17 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 1 Register Busy */
+#define RTC_MODE1_SYNCBUSY_GP1 (_U_(1) << RTC_MODE1_SYNCBUSY_GP1_Pos)
+#define RTC_MODE1_SYNCBUSY_GP2_Pos 18 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 2 Register Busy */
+#define RTC_MODE1_SYNCBUSY_GP2 (_U_(1) << RTC_MODE1_SYNCBUSY_GP2_Pos)
+#define RTC_MODE1_SYNCBUSY_GP3_Pos 19 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 3 Register Busy */
+#define RTC_MODE1_SYNCBUSY_GP3 (_U_(1) << RTC_MODE1_SYNCBUSY_GP3_Pos)
+#define RTC_MODE1_SYNCBUSY_GP_Pos 16 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose x Register Busy */
+#define RTC_MODE1_SYNCBUSY_GP_Msk (_U_(0xF) << RTC_MODE1_SYNCBUSY_GP_Pos)
+#define RTC_MODE1_SYNCBUSY_GP(value) (RTC_MODE1_SYNCBUSY_GP_Msk & ((value) << RTC_MODE1_SYNCBUSY_GP_Pos))
+#define RTC_MODE1_SYNCBUSY_MASK _U_(0x000F81FF) /**< \brief (RTC_MODE1_SYNCBUSY) MASK Register */
+
+/* -------- RTC_MODE2_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE2 MODE2 Synchronization Busy Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Bit Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */
+ uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */
+ uint32_t CLOCK:1; /*!< bit: 3 CLOCK Register Busy */
+ uint32_t :1; /*!< bit: 4 Reserved */
+ uint32_t ALARM0:1; /*!< bit: 5 ALARM 0 Register Busy */
+ uint32_t ALARM1:1; /*!< bit: 6 ALARM 1 Register Busy */
+ uint32_t :4; /*!< bit: 7..10 Reserved */
+ uint32_t MASK0:1; /*!< bit: 11 MASK 0 Register Busy */
+ uint32_t MASK1:1; /*!< bit: 12 MASK 1 Register Busy */
+ uint32_t :2; /*!< bit: 13..14 Reserved */
+ uint32_t CLOCKSYNC:1; /*!< bit: 15 Clock Synchronization Enable Bit Busy */
+ uint32_t GP0:1; /*!< bit: 16 General Purpose 0 Register Busy */
+ uint32_t GP1:1; /*!< bit: 17 General Purpose 1 Register Busy */
+ uint32_t GP2:1; /*!< bit: 18 General Purpose 2 Register Busy */
+ uint32_t GP3:1; /*!< bit: 19 General Purpose 3 Register Busy */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :5; /*!< bit: 0.. 4 Reserved */
+ uint32_t ALARM:2; /*!< bit: 5.. 6 ALARM x Register Busy */
+ uint32_t :4; /*!< bit: 7..10 Reserved */
+ uint32_t MASK:2; /*!< bit: 11..12 MASK x Register Busy */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t GP:4; /*!< bit: 16..19 General Purpose x Register Busy */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE2_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE2_SYNCBUSY offset) MODE2 Synchronization Busy Status */
+#define RTC_MODE2_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_SYNCBUSY reset_value) MODE2 Synchronization Busy Status */
+
+#define RTC_MODE2_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE2_SYNCBUSY) Software Reset Bit Busy */
+#define RTC_MODE2_SYNCBUSY_SWRST (_U_(0x1) << RTC_MODE2_SYNCBUSY_SWRST_Pos)
+#define RTC_MODE2_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE2_SYNCBUSY) Enable Bit Busy */
+#define RTC_MODE2_SYNCBUSY_ENABLE (_U_(0x1) << RTC_MODE2_SYNCBUSY_ENABLE_Pos)
+#define RTC_MODE2_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE2_SYNCBUSY) FREQCORR Register Busy */
+#define RTC_MODE2_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE2_SYNCBUSY_FREQCORR_Pos)
+#define RTC_MODE2_SYNCBUSY_CLOCK_Pos 3 /**< \brief (RTC_MODE2_SYNCBUSY) CLOCK Register Busy */
+#define RTC_MODE2_SYNCBUSY_CLOCK (_U_(0x1) << RTC_MODE2_SYNCBUSY_CLOCK_Pos)
+#define RTC_MODE2_SYNCBUSY_ALARM0_Pos 5 /**< \brief (RTC_MODE2_SYNCBUSY) ALARM 0 Register Busy */
+#define RTC_MODE2_SYNCBUSY_ALARM0 (_U_(1) << RTC_MODE2_SYNCBUSY_ALARM0_Pos)
+#define RTC_MODE2_SYNCBUSY_ALARM1_Pos 6 /**< \brief (RTC_MODE2_SYNCBUSY) ALARM 1 Register Busy */
+#define RTC_MODE2_SYNCBUSY_ALARM1 (_U_(1) << RTC_MODE2_SYNCBUSY_ALARM1_Pos)
+#define RTC_MODE2_SYNCBUSY_ALARM_Pos 5 /**< \brief (RTC_MODE2_SYNCBUSY) ALARM x Register Busy */
+#define RTC_MODE2_SYNCBUSY_ALARM_Msk (_U_(0x3) << RTC_MODE2_SYNCBUSY_ALARM_Pos)
+#define RTC_MODE2_SYNCBUSY_ALARM(value) (RTC_MODE2_SYNCBUSY_ALARM_Msk & ((value) << RTC_MODE2_SYNCBUSY_ALARM_Pos))
+#define RTC_MODE2_SYNCBUSY_MASK0_Pos 11 /**< \brief (RTC_MODE2_SYNCBUSY) MASK 0 Register Busy */
+#define RTC_MODE2_SYNCBUSY_MASK0 (_U_(1) << RTC_MODE2_SYNCBUSY_MASK0_Pos)
+#define RTC_MODE2_SYNCBUSY_MASK1_Pos 12 /**< \brief (RTC_MODE2_SYNCBUSY) MASK 1 Register Busy */
+#define RTC_MODE2_SYNCBUSY_MASK1 (_U_(1) << RTC_MODE2_SYNCBUSY_MASK1_Pos)
+#define RTC_MODE2_SYNCBUSY_MASK_Pos 11 /**< \brief (RTC_MODE2_SYNCBUSY) MASK x Register Busy */
+#define RTC_MODE2_SYNCBUSY_MASK_Msk (_U_(0x3) << RTC_MODE2_SYNCBUSY_MASK_Pos)
+#define RTC_MODE2_SYNCBUSY_MASK(value) (RTC_MODE2_SYNCBUSY_MASK_Msk & ((value) << RTC_MODE2_SYNCBUSY_MASK_Pos))
+#define RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos 15 /**< \brief (RTC_MODE2_SYNCBUSY) Clock Synchronization Enable Bit Busy */
+#define RTC_MODE2_SYNCBUSY_CLOCKSYNC (_U_(0x1) << RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos)
+#define RTC_MODE2_SYNCBUSY_GP0_Pos 16 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 0 Register Busy */
+#define RTC_MODE2_SYNCBUSY_GP0 (_U_(1) << RTC_MODE2_SYNCBUSY_GP0_Pos)
+#define RTC_MODE2_SYNCBUSY_GP1_Pos 17 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 1 Register Busy */
+#define RTC_MODE2_SYNCBUSY_GP1 (_U_(1) << RTC_MODE2_SYNCBUSY_GP1_Pos)
+#define RTC_MODE2_SYNCBUSY_GP2_Pos 18 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 2 Register Busy */
+#define RTC_MODE2_SYNCBUSY_GP2 (_U_(1) << RTC_MODE2_SYNCBUSY_GP2_Pos)
+#define RTC_MODE2_SYNCBUSY_GP3_Pos 19 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 3 Register Busy */
+#define RTC_MODE2_SYNCBUSY_GP3 (_U_(1) << RTC_MODE2_SYNCBUSY_GP3_Pos)
+#define RTC_MODE2_SYNCBUSY_GP_Pos 16 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose x Register Busy */
+#define RTC_MODE2_SYNCBUSY_GP_Msk (_U_(0xF) << RTC_MODE2_SYNCBUSY_GP_Pos)
+#define RTC_MODE2_SYNCBUSY_GP(value) (RTC_MODE2_SYNCBUSY_GP_Msk & ((value) << RTC_MODE2_SYNCBUSY_GP_Pos))
+#define RTC_MODE2_SYNCBUSY_MASK_ _U_(0x000F986F) /**< \brief (RTC_MODE2_SYNCBUSY) MASK Register */
+
+/* -------- RTC_FREQCORR : (RTC Offset: 0x14) (R/W 8) Frequency Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
+ uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_FREQCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_FREQCORR_OFFSET 0x14 /**< \brief (RTC_FREQCORR offset) Frequency Correction */
+#define RTC_FREQCORR_RESETVALUE _U_(0x00) /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */
+
+#define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */
+#define RTC_FREQCORR_VALUE_Msk (_U_(0x7F) << RTC_FREQCORR_VALUE_Pos)
+#define RTC_FREQCORR_VALUE(value) (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))
+#define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */
+#define RTC_FREQCORR_SIGN (_U_(0x1) << RTC_FREQCORR_SIGN_Pos)
+#define RTC_FREQCORR_MASK _U_(0xFF) /**< \brief (RTC_FREQCORR) MASK Register */
+
+/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE0_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COUNT_OFFSET 0x18 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */
+#define RTC_MODE0_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */
+
+#define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */
+#define RTC_MODE0_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_COUNT_COUNT_Pos)
+#define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))
+#define RTC_MODE0_COUNT_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_COUNT) MASK Register */
+
+/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COUNT_OFFSET 0x18 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */
+#define RTC_MODE1_COUNT_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */
+
+#define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */
+#define RTC_MODE1_COUNT_COUNT_Msk (_U_(0xFFFF) << RTC_MODE1_COUNT_COUNT_Pos)
+#define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))
+#define RTC_MODE1_COUNT_MASK _U_(0xFFFF) /**< \brief (RTC_MODE1_COUNT) MASK Register */
+
+/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2 Clock Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour */
+ uint32_t DAY:5; /*!< bit: 17..21 Day */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE2_CLOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CLOCK_OFFSET 0x18 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */
+#define RTC_MODE2_CLOCK_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */
+
+#define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */
+#define RTC_MODE2_CLOCK_SECOND_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_SECOND_Pos)
+#define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))
+#define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */
+#define RTC_MODE2_CLOCK_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_MINUTE_Pos)
+#define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))
+#define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */
+#define RTC_MODE2_CLOCK_HOUR_Msk (_U_(0x1F) << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))
+#define RTC_MODE2_CLOCK_HOUR_AM_Val _U_(0x0) /**< \brief (RTC_MODE2_CLOCK) AM when CLKREP in 12-hour */
+#define RTC_MODE2_CLOCK_HOUR_PM_Val _U_(0x10) /**< \brief (RTC_MODE2_CLOCK) PM when CLKREP in 12-hour */
+#define RTC_MODE2_CLOCK_HOUR_AM (RTC_MODE2_CLOCK_HOUR_AM_Val << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */
+#define RTC_MODE2_CLOCK_DAY_Msk (_U_(0x1F) << RTC_MODE2_CLOCK_DAY_Pos)
+#define RTC_MODE2_CLOCK_DAY(value) (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))
+#define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */
+#define RTC_MODE2_CLOCK_MONTH_Msk (_U_(0xF) << RTC_MODE2_CLOCK_MONTH_Pos)
+#define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))
+#define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */
+#define RTC_MODE2_CLOCK_YEAR_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_YEAR_Pos)
+#define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))
+#define RTC_MODE2_CLOCK_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_CLOCK) MASK Register */
+
+/* -------- RTC_MODE1_PER : (RTC Offset: 0x1C) (R/W 16) MODE1 MODE1 Counter Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PER:16; /*!< bit: 0..15 Counter Period */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_PER_OFFSET 0x1C /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */
+#define RTC_MODE1_PER_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */
+
+#define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */
+#define RTC_MODE1_PER_PER_Msk (_U_(0xFFFF) << RTC_MODE1_PER_PER_Pos)
+#define RTC_MODE1_PER_PER(value) (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))
+#define RTC_MODE1_PER_MASK _U_(0xFFFF) /**< \brief (RTC_MODE1_PER) MASK Register */
+
+/* -------- RTC_MODE0_COMP : (RTC Offset: 0x20) (R/W 32) MODE0 MODE0 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE0_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COMP_OFFSET 0x20 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */
+#define RTC_MODE0_COMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */
+
+#define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */
+#define RTC_MODE0_COMP_COMP_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_COMP_COMP_Pos)
+#define RTC_MODE0_COMP_COMP(value) (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))
+#define RTC_MODE0_COMP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_COMP) MASK Register */
+
+/* -------- RTC_MODE1_COMP : (RTC Offset: 0x20) (R/W 16) MODE1 MODE1 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COMP_OFFSET 0x20 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */
+#define RTC_MODE1_COMP_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */
+
+#define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */
+#define RTC_MODE1_COMP_COMP_Msk (_U_(0xFFFF) << RTC_MODE1_COMP_COMP_Pos)
+#define RTC_MODE1_COMP_COMP(value) (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))
+#define RTC_MODE1_COMP_MASK _U_(0xFFFF) /**< \brief (RTC_MODE1_COMP) MASK Register */
+
+/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x20) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour */
+ uint32_t DAY:5; /*!< bit: 17..21 Day */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE2_ALARM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_ALARM_OFFSET 0x20 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */
+#define RTC_MODE2_ALARM_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */
+
+#define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */
+#define RTC_MODE2_ALARM_SECOND_Msk (_U_(0x3F) << RTC_MODE2_ALARM_SECOND_Pos)
+#define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))
+#define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */
+#define RTC_MODE2_ALARM_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_ALARM_MINUTE_Pos)
+#define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))
+#define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */
+#define RTC_MODE2_ALARM_HOUR_Msk (_U_(0x1F) << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))
+#define RTC_MODE2_ALARM_HOUR_AM_Val _U_(0x0) /**< \brief (RTC_MODE2_ALARM) Morning hour */
+#define RTC_MODE2_ALARM_HOUR_PM_Val _U_(0x10) /**< \brief (RTC_MODE2_ALARM) Afternoon hour */
+#define RTC_MODE2_ALARM_HOUR_AM (RTC_MODE2_ALARM_HOUR_AM_Val << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_HOUR_PM (RTC_MODE2_ALARM_HOUR_PM_Val << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */
+#define RTC_MODE2_ALARM_DAY_Msk (_U_(0x1F) << RTC_MODE2_ALARM_DAY_Pos)
+#define RTC_MODE2_ALARM_DAY(value) (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))
+#define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */
+#define RTC_MODE2_ALARM_MONTH_Msk (_U_(0xF) << RTC_MODE2_ALARM_MONTH_Pos)
+#define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))
+#define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */
+#define RTC_MODE2_ALARM_YEAR_Msk (_U_(0x3F) << RTC_MODE2_ALARM_YEAR_Pos)
+#define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))
+#define RTC_MODE2_ALARM_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_ALARM) MASK Register */
+
+/* -------- RTC_MODE2_MASK : (RTC Offset: 0x24) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE2_MASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_MASK_OFFSET 0x24 /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */
+#define RTC_MODE2_MASK_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */
+
+#define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
+#define RTC_MODE2_MASK_SEL_Msk (_U_(0x7) << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL(value) (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))
+#define RTC_MODE2_MASK_SEL_OFF_Val _U_(0x0) /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
+#define RTC_MODE2_MASK_SEL_SS_Val _U_(0x1) /**< \brief (RTC_MODE2_MASK) Match seconds only */
+#define RTC_MODE2_MASK_SEL_MMSS_Val _U_(0x2) /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
+#define RTC_MODE2_MASK_SEL_HHMMSS_Val _U_(0x3) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */
+#define RTC_MODE2_MASK_SEL_DDHHMMSS_Val _U_(0x4) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */
+#define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val _U_(0x5) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */
+#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val _U_(0x6) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */
+#define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_MASK _U_(0x07) /**< \brief (RTC_MODE2_MASK) MASK Register */
+
+/* -------- RTC_GP : (RTC Offset: 0x40) (R/W 32) General Purpose -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t GP:32; /*!< bit: 0..31 General Purpose */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_GP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_GP_OFFSET 0x40 /**< \brief (RTC_GP offset) General Purpose */
+#define RTC_GP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_GP reset_value) General Purpose */
+
+#define RTC_GP_GP_Pos 0 /**< \brief (RTC_GP) General Purpose */
+#define RTC_GP_GP_Msk (_U_(0xFFFFFFFF) << RTC_GP_GP_Pos)
+#define RTC_GP_GP(value) (RTC_GP_GP_Msk & ((value) << RTC_GP_GP_Pos))
+#define RTC_GP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_GP) MASK Register */
+
+/* -------- RTC_TAMPCTRL : (RTC Offset: 0x60) (R/W 32) Tamper Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t IN0ACT:2; /*!< bit: 0.. 1 Tamper Input 0 Action */
+ uint32_t IN1ACT:2; /*!< bit: 2.. 3 Tamper Input 1 Action */
+ uint32_t IN2ACT:2; /*!< bit: 4.. 5 Tamper Input 2 Action */
+ uint32_t IN3ACT:2; /*!< bit: 6.. 7 Tamper Input 3 Action */
+ uint32_t IN4ACT:2; /*!< bit: 8.. 9 Tamper Input 4 Action */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t TAMLVL0:1; /*!< bit: 16 Tamper Level Select 0 */
+ uint32_t TAMLVL1:1; /*!< bit: 17 Tamper Level Select 1 */
+ uint32_t TAMLVL2:1; /*!< bit: 18 Tamper Level Select 2 */
+ uint32_t TAMLVL3:1; /*!< bit: 19 Tamper Level Select 3 */
+ uint32_t TAMLVL4:1; /*!< bit: 20 Tamper Level Select 4 */
+ uint32_t :3; /*!< bit: 21..23 Reserved */
+ uint32_t DEBNC0:1; /*!< bit: 24 Debouncer Enable 0 */
+ uint32_t DEBNC1:1; /*!< bit: 25 Debouncer Enable 1 */
+ uint32_t DEBNC2:1; /*!< bit: 26 Debouncer Enable 2 */
+ uint32_t DEBNC3:1; /*!< bit: 27 Debouncer Enable 3 */
+ uint32_t DEBNC4:1; /*!< bit: 28 Debouncer Enable 4 */
+ uint32_t :3; /*!< bit: 29..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t TAMLVL:5; /*!< bit: 16..20 Tamper Level Select x */
+ uint32_t :3; /*!< bit: 21..23 Reserved */
+ uint32_t DEBNC:5; /*!< bit: 24..28 Debouncer Enable x */
+ uint32_t :3; /*!< bit: 29..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_TAMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_TAMPCTRL_OFFSET 0x60 /**< \brief (RTC_TAMPCTRL offset) Tamper Control */
+#define RTC_TAMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_TAMPCTRL reset_value) Tamper Control */
+
+#define RTC_TAMPCTRL_IN0ACT_Pos 0 /**< \brief (RTC_TAMPCTRL) Tamper Input 0 Action */
+#define RTC_TAMPCTRL_IN0ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN0ACT_Pos)
+#define RTC_TAMPCTRL_IN0ACT(value) (RTC_TAMPCTRL_IN0ACT_Msk & ((value) << RTC_TAMPCTRL_IN0ACT_Pos))
+#define RTC_TAMPCTRL_IN0ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
+#define RTC_TAMPCTRL_IN0ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
+#define RTC_TAMPCTRL_IN0ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
+#define RTC_TAMPCTRL_IN0ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN0 to OUT */
+#define RTC_TAMPCTRL_IN0ACT_OFF (RTC_TAMPCTRL_IN0ACT_OFF_Val << RTC_TAMPCTRL_IN0ACT_Pos)
+#define RTC_TAMPCTRL_IN0ACT_WAKE (RTC_TAMPCTRL_IN0ACT_WAKE_Val << RTC_TAMPCTRL_IN0ACT_Pos)
+#define RTC_TAMPCTRL_IN0ACT_CAPTURE (RTC_TAMPCTRL_IN0ACT_CAPTURE_Val << RTC_TAMPCTRL_IN0ACT_Pos)
+#define RTC_TAMPCTRL_IN0ACT_ACTL (RTC_TAMPCTRL_IN0ACT_ACTL_Val << RTC_TAMPCTRL_IN0ACT_Pos)
+#define RTC_TAMPCTRL_IN1ACT_Pos 2 /**< \brief (RTC_TAMPCTRL) Tamper Input 1 Action */
+#define RTC_TAMPCTRL_IN1ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN1ACT_Pos)
+#define RTC_TAMPCTRL_IN1ACT(value) (RTC_TAMPCTRL_IN1ACT_Msk & ((value) << RTC_TAMPCTRL_IN1ACT_Pos))
+#define RTC_TAMPCTRL_IN1ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
+#define RTC_TAMPCTRL_IN1ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
+#define RTC_TAMPCTRL_IN1ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
+#define RTC_TAMPCTRL_IN1ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN1 to OUT */
+#define RTC_TAMPCTRL_IN1ACT_OFF (RTC_TAMPCTRL_IN1ACT_OFF_Val << RTC_TAMPCTRL_IN1ACT_Pos)
+#define RTC_TAMPCTRL_IN1ACT_WAKE (RTC_TAMPCTRL_IN1ACT_WAKE_Val << RTC_TAMPCTRL_IN1ACT_Pos)
+#define RTC_TAMPCTRL_IN1ACT_CAPTURE (RTC_TAMPCTRL_IN1ACT_CAPTURE_Val << RTC_TAMPCTRL_IN1ACT_Pos)
+#define RTC_TAMPCTRL_IN1ACT_ACTL (RTC_TAMPCTRL_IN1ACT_ACTL_Val << RTC_TAMPCTRL_IN1ACT_Pos)
+#define RTC_TAMPCTRL_IN2ACT_Pos 4 /**< \brief (RTC_TAMPCTRL) Tamper Input 2 Action */
+#define RTC_TAMPCTRL_IN2ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN2ACT_Pos)
+#define RTC_TAMPCTRL_IN2ACT(value) (RTC_TAMPCTRL_IN2ACT_Msk & ((value) << RTC_TAMPCTRL_IN2ACT_Pos))
+#define RTC_TAMPCTRL_IN2ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
+#define RTC_TAMPCTRL_IN2ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
+#define RTC_TAMPCTRL_IN2ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
+#define RTC_TAMPCTRL_IN2ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN2 to OUT */
+#define RTC_TAMPCTRL_IN2ACT_OFF (RTC_TAMPCTRL_IN2ACT_OFF_Val << RTC_TAMPCTRL_IN2ACT_Pos)
+#define RTC_TAMPCTRL_IN2ACT_WAKE (RTC_TAMPCTRL_IN2ACT_WAKE_Val << RTC_TAMPCTRL_IN2ACT_Pos)
+#define RTC_TAMPCTRL_IN2ACT_CAPTURE (RTC_TAMPCTRL_IN2ACT_CAPTURE_Val << RTC_TAMPCTRL_IN2ACT_Pos)
+#define RTC_TAMPCTRL_IN2ACT_ACTL (RTC_TAMPCTRL_IN2ACT_ACTL_Val << RTC_TAMPCTRL_IN2ACT_Pos)
+#define RTC_TAMPCTRL_IN3ACT_Pos 6 /**< \brief (RTC_TAMPCTRL) Tamper Input 3 Action */
+#define RTC_TAMPCTRL_IN3ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN3ACT_Pos)
+#define RTC_TAMPCTRL_IN3ACT(value) (RTC_TAMPCTRL_IN3ACT_Msk & ((value) << RTC_TAMPCTRL_IN3ACT_Pos))
+#define RTC_TAMPCTRL_IN3ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
+#define RTC_TAMPCTRL_IN3ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
+#define RTC_TAMPCTRL_IN3ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
+#define RTC_TAMPCTRL_IN3ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN3 to OUT */
+#define RTC_TAMPCTRL_IN3ACT_OFF (RTC_TAMPCTRL_IN3ACT_OFF_Val << RTC_TAMPCTRL_IN3ACT_Pos)
+#define RTC_TAMPCTRL_IN3ACT_WAKE (RTC_TAMPCTRL_IN3ACT_WAKE_Val << RTC_TAMPCTRL_IN3ACT_Pos)
+#define RTC_TAMPCTRL_IN3ACT_CAPTURE (RTC_TAMPCTRL_IN3ACT_CAPTURE_Val << RTC_TAMPCTRL_IN3ACT_Pos)
+#define RTC_TAMPCTRL_IN3ACT_ACTL (RTC_TAMPCTRL_IN3ACT_ACTL_Val << RTC_TAMPCTRL_IN3ACT_Pos)
+#define RTC_TAMPCTRL_IN4ACT_Pos 8 /**< \brief (RTC_TAMPCTRL) Tamper Input 4 Action */
+#define RTC_TAMPCTRL_IN4ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN4ACT_Pos)
+#define RTC_TAMPCTRL_IN4ACT(value) (RTC_TAMPCTRL_IN4ACT_Msk & ((value) << RTC_TAMPCTRL_IN4ACT_Pos))
+#define RTC_TAMPCTRL_IN4ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
+#define RTC_TAMPCTRL_IN4ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
+#define RTC_TAMPCTRL_IN4ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
+#define RTC_TAMPCTRL_IN4ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN4 to OUT */
+#define RTC_TAMPCTRL_IN4ACT_OFF (RTC_TAMPCTRL_IN4ACT_OFF_Val << RTC_TAMPCTRL_IN4ACT_Pos)
+#define RTC_TAMPCTRL_IN4ACT_WAKE (RTC_TAMPCTRL_IN4ACT_WAKE_Val << RTC_TAMPCTRL_IN4ACT_Pos)
+#define RTC_TAMPCTRL_IN4ACT_CAPTURE (RTC_TAMPCTRL_IN4ACT_CAPTURE_Val << RTC_TAMPCTRL_IN4ACT_Pos)
+#define RTC_TAMPCTRL_IN4ACT_ACTL (RTC_TAMPCTRL_IN4ACT_ACTL_Val << RTC_TAMPCTRL_IN4ACT_Pos)
+#define RTC_TAMPCTRL_TAMLVL0_Pos 16 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 0 */
+#define RTC_TAMPCTRL_TAMLVL0 (_U_(1) << RTC_TAMPCTRL_TAMLVL0_Pos)
+#define RTC_TAMPCTRL_TAMLVL1_Pos 17 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 1 */
+#define RTC_TAMPCTRL_TAMLVL1 (_U_(1) << RTC_TAMPCTRL_TAMLVL1_Pos)
+#define RTC_TAMPCTRL_TAMLVL2_Pos 18 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 2 */
+#define RTC_TAMPCTRL_TAMLVL2 (_U_(1) << RTC_TAMPCTRL_TAMLVL2_Pos)
+#define RTC_TAMPCTRL_TAMLVL3_Pos 19 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 3 */
+#define RTC_TAMPCTRL_TAMLVL3 (_U_(1) << RTC_TAMPCTRL_TAMLVL3_Pos)
+#define RTC_TAMPCTRL_TAMLVL4_Pos 20 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 4 */
+#define RTC_TAMPCTRL_TAMLVL4 (_U_(1) << RTC_TAMPCTRL_TAMLVL4_Pos)
+#define RTC_TAMPCTRL_TAMLVL_Pos 16 /**< \brief (RTC_TAMPCTRL) Tamper Level Select x */
+#define RTC_TAMPCTRL_TAMLVL_Msk (_U_(0x1F) << RTC_TAMPCTRL_TAMLVL_Pos)
+#define RTC_TAMPCTRL_TAMLVL(value) (RTC_TAMPCTRL_TAMLVL_Msk & ((value) << RTC_TAMPCTRL_TAMLVL_Pos))
+#define RTC_TAMPCTRL_DEBNC0_Pos 24 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 0 */
+#define RTC_TAMPCTRL_DEBNC0 (_U_(1) << RTC_TAMPCTRL_DEBNC0_Pos)
+#define RTC_TAMPCTRL_DEBNC1_Pos 25 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 1 */
+#define RTC_TAMPCTRL_DEBNC1 (_U_(1) << RTC_TAMPCTRL_DEBNC1_Pos)
+#define RTC_TAMPCTRL_DEBNC2_Pos 26 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 2 */
+#define RTC_TAMPCTRL_DEBNC2 (_U_(1) << RTC_TAMPCTRL_DEBNC2_Pos)
+#define RTC_TAMPCTRL_DEBNC3_Pos 27 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 3 */
+#define RTC_TAMPCTRL_DEBNC3 (_U_(1) << RTC_TAMPCTRL_DEBNC3_Pos)
+#define RTC_TAMPCTRL_DEBNC4_Pos 28 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 4 */
+#define RTC_TAMPCTRL_DEBNC4 (_U_(1) << RTC_TAMPCTRL_DEBNC4_Pos)
+#define RTC_TAMPCTRL_DEBNC_Pos 24 /**< \brief (RTC_TAMPCTRL) Debouncer Enable x */
+#define RTC_TAMPCTRL_DEBNC_Msk (_U_(0x1F) << RTC_TAMPCTRL_DEBNC_Pos)
+#define RTC_TAMPCTRL_DEBNC(value) (RTC_TAMPCTRL_DEBNC_Msk & ((value) << RTC_TAMPCTRL_DEBNC_Pos))
+#define RTC_TAMPCTRL_MASK _U_(0x1F1F03FF) /**< \brief (RTC_TAMPCTRL) MASK Register */
+
+/* -------- RTC_MODE0_TIMESTAMP : (RTC Offset: 0x64) (R/ 32) MODE0 MODE0 Timestamp -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Count Timestamp Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE0_TIMESTAMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_TIMESTAMP_OFFSET 0x64 /**< \brief (RTC_MODE0_TIMESTAMP offset) MODE0 Timestamp */
+#define RTC_MODE0_TIMESTAMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_TIMESTAMP reset_value) MODE0 Timestamp */
+
+#define RTC_MODE0_TIMESTAMP_COUNT_Pos 0 /**< \brief (RTC_MODE0_TIMESTAMP) Count Timestamp Value */
+#define RTC_MODE0_TIMESTAMP_COUNT_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_TIMESTAMP_COUNT_Pos)
+#define RTC_MODE0_TIMESTAMP_COUNT(value) (RTC_MODE0_TIMESTAMP_COUNT_Msk & ((value) << RTC_MODE0_TIMESTAMP_COUNT_Pos))
+#define RTC_MODE0_TIMESTAMP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_TIMESTAMP) MASK Register */
+
+/* -------- RTC_MODE1_TIMESTAMP : (RTC Offset: 0x64) (R/ 32) MODE1 MODE1 Timestamp -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COUNT:16; /*!< bit: 0..15 Count Timestamp Value */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE1_TIMESTAMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_TIMESTAMP_OFFSET 0x64 /**< \brief (RTC_MODE1_TIMESTAMP offset) MODE1 Timestamp */
+#define RTC_MODE1_TIMESTAMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE1_TIMESTAMP reset_value) MODE1 Timestamp */
+
+#define RTC_MODE1_TIMESTAMP_COUNT_Pos 0 /**< \brief (RTC_MODE1_TIMESTAMP) Count Timestamp Value */
+#define RTC_MODE1_TIMESTAMP_COUNT_Msk (_U_(0xFFFF) << RTC_MODE1_TIMESTAMP_COUNT_Pos)
+#define RTC_MODE1_TIMESTAMP_COUNT(value) (RTC_MODE1_TIMESTAMP_COUNT_Msk & ((value) << RTC_MODE1_TIMESTAMP_COUNT_Pos))
+#define RTC_MODE1_TIMESTAMP_MASK _U_(0x0000FFFF) /**< \brief (RTC_MODE1_TIMESTAMP) MASK Register */
+
+/* -------- RTC_MODE2_TIMESTAMP : (RTC Offset: 0x64) (R/ 32) MODE2 MODE2 Timestamp -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second Timestamp Value */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute Timestamp Value */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour Timestamp Value */
+ uint32_t DAY:5; /*!< bit: 17..21 Day Timestamp Value */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month Timestamp Value */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year Timestamp Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE2_TIMESTAMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_TIMESTAMP_OFFSET 0x64 /**< \brief (RTC_MODE2_TIMESTAMP offset) MODE2 Timestamp */
+#define RTC_MODE2_TIMESTAMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_TIMESTAMP reset_value) MODE2 Timestamp */
+
+#define RTC_MODE2_TIMESTAMP_SECOND_Pos 0 /**< \brief (RTC_MODE2_TIMESTAMP) Second Timestamp Value */
+#define RTC_MODE2_TIMESTAMP_SECOND_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_SECOND_Pos)
+#define RTC_MODE2_TIMESTAMP_SECOND(value) (RTC_MODE2_TIMESTAMP_SECOND_Msk & ((value) << RTC_MODE2_TIMESTAMP_SECOND_Pos))
+#define RTC_MODE2_TIMESTAMP_MINUTE_Pos 6 /**< \brief (RTC_MODE2_TIMESTAMP) Minute Timestamp Value */
+#define RTC_MODE2_TIMESTAMP_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_MINUTE_Pos)
+#define RTC_MODE2_TIMESTAMP_MINUTE(value) (RTC_MODE2_TIMESTAMP_MINUTE_Msk & ((value) << RTC_MODE2_TIMESTAMP_MINUTE_Pos))
+#define RTC_MODE2_TIMESTAMP_HOUR_Pos 12 /**< \brief (RTC_MODE2_TIMESTAMP) Hour Timestamp Value */
+#define RTC_MODE2_TIMESTAMP_HOUR_Msk (_U_(0x1F) << RTC_MODE2_TIMESTAMP_HOUR_Pos)
+#define RTC_MODE2_TIMESTAMP_HOUR(value) (RTC_MODE2_TIMESTAMP_HOUR_Msk & ((value) << RTC_MODE2_TIMESTAMP_HOUR_Pos))
+#define RTC_MODE2_TIMESTAMP_HOUR_AM_Val _U_(0x0) /**< \brief (RTC_MODE2_TIMESTAMP) AM when CLKREP in 12-hour */
+#define RTC_MODE2_TIMESTAMP_HOUR_PM_Val _U_(0x10) /**< \brief (RTC_MODE2_TIMESTAMP) PM when CLKREP in 12-hour */
+#define RTC_MODE2_TIMESTAMP_HOUR_AM (RTC_MODE2_TIMESTAMP_HOUR_AM_Val << RTC_MODE2_TIMESTAMP_HOUR_Pos)
+#define RTC_MODE2_TIMESTAMP_HOUR_PM (RTC_MODE2_TIMESTAMP_HOUR_PM_Val << RTC_MODE2_TIMESTAMP_HOUR_Pos)
+#define RTC_MODE2_TIMESTAMP_DAY_Pos 17 /**< \brief (RTC_MODE2_TIMESTAMP) Day Timestamp Value */
+#define RTC_MODE2_TIMESTAMP_DAY_Msk (_U_(0x1F) << RTC_MODE2_TIMESTAMP_DAY_Pos)
+#define RTC_MODE2_TIMESTAMP_DAY(value) (RTC_MODE2_TIMESTAMP_DAY_Msk & ((value) << RTC_MODE2_TIMESTAMP_DAY_Pos))
+#define RTC_MODE2_TIMESTAMP_MONTH_Pos 22 /**< \brief (RTC_MODE2_TIMESTAMP) Month Timestamp Value */
+#define RTC_MODE2_TIMESTAMP_MONTH_Msk (_U_(0xF) << RTC_MODE2_TIMESTAMP_MONTH_Pos)
+#define RTC_MODE2_TIMESTAMP_MONTH(value) (RTC_MODE2_TIMESTAMP_MONTH_Msk & ((value) << RTC_MODE2_TIMESTAMP_MONTH_Pos))
+#define RTC_MODE2_TIMESTAMP_YEAR_Pos 26 /**< \brief (RTC_MODE2_TIMESTAMP) Year Timestamp Value */
+#define RTC_MODE2_TIMESTAMP_YEAR_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_YEAR_Pos)
+#define RTC_MODE2_TIMESTAMP_YEAR(value) (RTC_MODE2_TIMESTAMP_YEAR_Msk & ((value) << RTC_MODE2_TIMESTAMP_YEAR_Pos))
+#define RTC_MODE2_TIMESTAMP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_TIMESTAMP) MASK Register */
+
+/* -------- RTC_TAMPID : (RTC Offset: 0x68) (R/W 32) Tamper ID -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TAMPID0:1; /*!< bit: 0 Tamper Input 0 Detected */
+ uint32_t TAMPID1:1; /*!< bit: 1 Tamper Input 1 Detected */
+ uint32_t TAMPID2:1; /*!< bit: 2 Tamper Input 2 Detected */
+ uint32_t TAMPID3:1; /*!< bit: 3 Tamper Input 3 Detected */
+ uint32_t TAMPID4:1; /*!< bit: 4 Tamper Input 4 Detected */
+ uint32_t :26; /*!< bit: 5..30 Reserved */
+ uint32_t TAMPEVT:1; /*!< bit: 31 Tamper Event Detected */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t TAMPID:5; /*!< bit: 0.. 4 Tamper Input x Detected */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_TAMPID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_TAMPID_OFFSET 0x68 /**< \brief (RTC_TAMPID offset) Tamper ID */
+#define RTC_TAMPID_RESETVALUE _U_(0x00000000) /**< \brief (RTC_TAMPID reset_value) Tamper ID */
+
+#define RTC_TAMPID_TAMPID0_Pos 0 /**< \brief (RTC_TAMPID) Tamper Input 0 Detected */
+#define RTC_TAMPID_TAMPID0 (_U_(1) << RTC_TAMPID_TAMPID0_Pos)
+#define RTC_TAMPID_TAMPID1_Pos 1 /**< \brief (RTC_TAMPID) Tamper Input 1 Detected */
+#define RTC_TAMPID_TAMPID1 (_U_(1) << RTC_TAMPID_TAMPID1_Pos)
+#define RTC_TAMPID_TAMPID2_Pos 2 /**< \brief (RTC_TAMPID) Tamper Input 2 Detected */
+#define RTC_TAMPID_TAMPID2 (_U_(1) << RTC_TAMPID_TAMPID2_Pos)
+#define RTC_TAMPID_TAMPID3_Pos 3 /**< \brief (RTC_TAMPID) Tamper Input 3 Detected */
+#define RTC_TAMPID_TAMPID3 (_U_(1) << RTC_TAMPID_TAMPID3_Pos)
+#define RTC_TAMPID_TAMPID4_Pos 4 /**< \brief (RTC_TAMPID) Tamper Input 4 Detected */
+#define RTC_TAMPID_TAMPID4 (_U_(1) << RTC_TAMPID_TAMPID4_Pos)
+#define RTC_TAMPID_TAMPID_Pos 0 /**< \brief (RTC_TAMPID) Tamper Input x Detected */
+#define RTC_TAMPID_TAMPID_Msk (_U_(0x1F) << RTC_TAMPID_TAMPID_Pos)
+#define RTC_TAMPID_TAMPID(value) (RTC_TAMPID_TAMPID_Msk & ((value) << RTC_TAMPID_TAMPID_Pos))
+#define RTC_TAMPID_TAMPEVT_Pos 31 /**< \brief (RTC_TAMPID) Tamper Event Detected */
+#define RTC_TAMPID_TAMPEVT (_U_(0x1) << RTC_TAMPID_TAMPEVT_Pos)
+#define RTC_TAMPID_MASK _U_(0x8000001F) /**< \brief (RTC_TAMPID) MASK Register */
+
+/* -------- RTC_BKUP : (RTC Offset: 0x80) (R/W 32) Backup -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BKUP:32; /*!< bit: 0..31 Backup */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_BKUP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_BKUP_OFFSET 0x80 /**< \brief (RTC_BKUP offset) Backup */
+#define RTC_BKUP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_BKUP reset_value) Backup */
+
+#define RTC_BKUP_BKUP_Pos 0 /**< \brief (RTC_BKUP) Backup */
+#define RTC_BKUP_BKUP_Msk (_U_(0xFFFFFFFF) << RTC_BKUP_BKUP_Pos)
+#define RTC_BKUP_BKUP(value) (RTC_BKUP_BKUP_Msk & ((value) << RTC_BKUP_BKUP_Pos))
+#define RTC_BKUP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_BKUP) MASK Register */
+
+/** \brief RtcMode2Alarm hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
+ __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
+ RoReg8 Reserved1[0x3];
+} RtcMode2Alarm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE0 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter with Single 32-bit Compare */
+ __IO RTC_MODE0_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control A */
+ __IO RTC_MODE0_CTRLB_Type CTRLB; /**< \brief Offset: 0x02 (R/W 16) MODE0 Control B */
+ __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE0 Event Control */
+ __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE0 Interrupt Enable Clear */
+ __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE0 Interrupt Enable Set */
+ __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE0 Interrupt Flag Status and Clear */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */
+ RoReg8 Reserved1[0x1];
+ __I RTC_MODE0_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE0 Synchronization Busy Status */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x18 (R/W 32) MODE0 Counter Value */
+ RoReg8 Reserved3[0x4];
+ __IO RTC_MODE0_COMP_Type COMP[2]; /**< \brief Offset: 0x20 (R/W 32) MODE0 Compare n Value */
+ RoReg8 Reserved4[0x18];
+ __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */
+ RoReg8 Reserved5[0x10];
+ __IO RTC_TAMPCTRL_Type TAMPCTRL; /**< \brief Offset: 0x60 (R/W 32) Tamper Control */
+ __I RTC_MODE0_TIMESTAMP_Type TIMESTAMP; /**< \brief Offset: 0x64 (R/ 32) MODE0 Timestamp */
+ __IO RTC_TAMPID_Type TAMPID; /**< \brief Offset: 0x68 (R/W 32) Tamper ID */
+ RoReg8 Reserved6[0x14];
+ __IO RTC_BKUP_Type BKUP[8]; /**< \brief Offset: 0x80 (R/W 32) Backup */
+} RtcMode0;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE1 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter with Two 16-bit Compares */
+ __IO RTC_MODE1_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control A */
+ __IO RTC_MODE1_CTRLB_Type CTRLB; /**< \brief Offset: 0x02 (R/W 16) MODE1 Control B */
+ __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE1 Event Control */
+ __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE1 Interrupt Enable Clear */
+ __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE1 Interrupt Enable Set */
+ __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE1 Interrupt Flag Status and Clear */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */
+ RoReg8 Reserved1[0x1];
+ __I RTC_MODE1_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE1 Synchronization Busy Status */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x18 (R/W 16) MODE1 Counter Value */
+ RoReg8 Reserved3[0x2];
+ __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x1C (R/W 16) MODE1 Counter Period */
+ RoReg8 Reserved4[0x2];
+ __IO RTC_MODE1_COMP_Type COMP[4]; /**< \brief Offset: 0x20 (R/W 16) MODE1 Compare n Value */
+ RoReg8 Reserved5[0x18];
+ __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */
+ RoReg8 Reserved6[0x10];
+ __IO RTC_TAMPCTRL_Type TAMPCTRL; /**< \brief Offset: 0x60 (R/W 32) Tamper Control */
+ __I RTC_MODE1_TIMESTAMP_Type TIMESTAMP; /**< \brief Offset: 0x64 (R/ 32) MODE1 Timestamp */
+ __IO RTC_TAMPID_Type TAMPID; /**< \brief Offset: 0x68 (R/W 32) Tamper ID */
+ RoReg8 Reserved7[0x14];
+ __IO RTC_BKUP_Type BKUP[8]; /**< \brief Offset: 0x80 (R/W 32) Backup */
+} RtcMode1;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE2 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* Clock/Calendar with Alarm */
+ __IO RTC_MODE2_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control A */
+ __IO RTC_MODE2_CTRLB_Type CTRLB; /**< \brief Offset: 0x02 (R/W 16) MODE2 Control B */
+ __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE2 Event Control */
+ __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE2 Interrupt Enable Clear */
+ __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE2 Interrupt Enable Set */
+ __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE2 Interrupt Flag Status and Clear */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */
+ RoReg8 Reserved1[0x1];
+ __I RTC_MODE2_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE2 Synchronization Busy Status */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x18 (R/W 32) MODE2 Clock Value */
+ RoReg8 Reserved3[0x4];
+ RtcMode2Alarm Mode2Alarm[2]; /**< \brief Offset: 0x20 RtcMode2Alarm groups [NUM_OF_ALARMS] */
+ RoReg8 Reserved4[0x10];
+ __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */
+ RoReg8 Reserved5[0x10];
+ __IO RTC_TAMPCTRL_Type TAMPCTRL; /**< \brief Offset: 0x60 (R/W 32) Tamper Control */
+ __I RTC_MODE2_TIMESTAMP_Type TIMESTAMP; /**< \brief Offset: 0x64 (R/ 32) MODE2 Timestamp */
+ __IO RTC_TAMPID_Type TAMPID; /**< \brief Offset: 0x68 (R/W 32) Tamper ID */
+ RoReg8 Reserved6[0x14];
+ __IO RTC_BKUP_Type BKUP[8]; /**< \brief Offset: 0x80 (R/W 32) Backup */
+} RtcMode2;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
+ RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
+ RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_RTC_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/sdhc.h b/sysmoOCTSIM/include/component/sdhc.h
index b6a35d7..47e59ab 100644
--- a/sysmoOCTSIM/include/component/sdhc.h
+++ b/sysmoOCTSIM/include/component/sdhc.h
@@ -1,2599 +1,2599 @@
-/**
- * \file
- *
- * \brief Component description for SDHC
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_SDHC_COMPONENT_
-#define _SAME54_SDHC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR SDHC */
-/* ========================================================================== */
-/** \addtogroup SAME54_SDHC SD/MMC Host Controller */
-/*@{*/
-
-#define SDHC_U2011
-#define REV_SDHC 0x183
-
-/* -------- SDHC_SSAR : (SDHC Offset: 0x000) (R/W 32) SDMA System Address / Argument 2 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct { // CMD23 mode
- uint32_t ARG2:32; /*!< bit: 0..31 Argument 2 */
- } CMD23; /*!< Structure used for CMD23 */
- struct {
- uint32_t ADDR:32; /*!< bit: 0..31 SDMA System Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SDHC_SSAR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_SSAR_OFFSET 0x000 /**< \brief (SDHC_SSAR offset) SDMA System Address / Argument 2 */
-#define SDHC_SSAR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_SSAR reset_value) SDMA System Address / Argument 2 */
-
-// CMD23 mode
-#define SDHC_SSAR_CMD23_ARG2_Pos 0 /**< \brief (SDHC_SSAR_CMD23) Argument 2 */
-#define SDHC_SSAR_CMD23_ARG2_Msk (_U_(0xFFFFFFFF) << SDHC_SSAR_CMD23_ARG2_Pos)
-#define SDHC_SSAR_CMD23_ARG2(value) (SDHC_SSAR_CMD23_ARG2_Msk & ((value) << SDHC_SSAR_CMD23_ARG2_Pos))
-#define SDHC_SSAR_CMD23_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_SSAR_CMD23) MASK Register */
-
-#define SDHC_SSAR_ADDR_Pos 0 /**< \brief (SDHC_SSAR) SDMA System Address */
-#define SDHC_SSAR_ADDR_Msk (_U_(0xFFFFFFFF) << SDHC_SSAR_ADDR_Pos)
-#define SDHC_SSAR_ADDR(value) (SDHC_SSAR_ADDR_Msk & ((value) << SDHC_SSAR_ADDR_Pos))
-#define SDHC_SSAR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_SSAR) MASK Register */
-
-/* -------- SDHC_BSR : (SDHC Offset: 0x004) (R/W 16) Block Size -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t BLOCKSIZE:10; /*!< bit: 0.. 9 Transfer Block Size */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t BOUNDARY:3; /*!< bit: 12..14 SDMA Buffer Boundary */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} SDHC_BSR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_BSR_OFFSET 0x004 /**< \brief (SDHC_BSR offset) Block Size */
-#define SDHC_BSR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_BSR reset_value) Block Size */
-
-#define SDHC_BSR_BLOCKSIZE_Pos 0 /**< \brief (SDHC_BSR) Transfer Block Size */
-#define SDHC_BSR_BLOCKSIZE_Msk (_U_(0x3FF) << SDHC_BSR_BLOCKSIZE_Pos)
-#define SDHC_BSR_BLOCKSIZE(value) (SDHC_BSR_BLOCKSIZE_Msk & ((value) << SDHC_BSR_BLOCKSIZE_Pos))
-#define SDHC_BSR_BOUNDARY_Pos 12 /**< \brief (SDHC_BSR) SDMA Buffer Boundary */
-#define SDHC_BSR_BOUNDARY_Msk (_U_(0x7) << SDHC_BSR_BOUNDARY_Pos)
-#define SDHC_BSR_BOUNDARY(value) (SDHC_BSR_BOUNDARY_Msk & ((value) << SDHC_BSR_BOUNDARY_Pos))
-#define SDHC_BSR_BOUNDARY_4K_Val _U_(0x0) /**< \brief (SDHC_BSR) 4k bytes */
-#define SDHC_BSR_BOUNDARY_8K_Val _U_(0x1) /**< \brief (SDHC_BSR) 8k bytes */
-#define SDHC_BSR_BOUNDARY_16K_Val _U_(0x2) /**< \brief (SDHC_BSR) 16k bytes */
-#define SDHC_BSR_BOUNDARY_32K_Val _U_(0x3) /**< \brief (SDHC_BSR) 32k bytes */
-#define SDHC_BSR_BOUNDARY_64K_Val _U_(0x4) /**< \brief (SDHC_BSR) 64k bytes */
-#define SDHC_BSR_BOUNDARY_128K_Val _U_(0x5) /**< \brief (SDHC_BSR) 128k bytes */
-#define SDHC_BSR_BOUNDARY_256K_Val _U_(0x6) /**< \brief (SDHC_BSR) 256k bytes */
-#define SDHC_BSR_BOUNDARY_512K_Val _U_(0x7) /**< \brief (SDHC_BSR) 512k bytes */
-#define SDHC_BSR_BOUNDARY_4K (SDHC_BSR_BOUNDARY_4K_Val << SDHC_BSR_BOUNDARY_Pos)
-#define SDHC_BSR_BOUNDARY_8K (SDHC_BSR_BOUNDARY_8K_Val << SDHC_BSR_BOUNDARY_Pos)
-#define SDHC_BSR_BOUNDARY_16K (SDHC_BSR_BOUNDARY_16K_Val << SDHC_BSR_BOUNDARY_Pos)
-#define SDHC_BSR_BOUNDARY_32K (SDHC_BSR_BOUNDARY_32K_Val << SDHC_BSR_BOUNDARY_Pos)
-#define SDHC_BSR_BOUNDARY_64K (SDHC_BSR_BOUNDARY_64K_Val << SDHC_BSR_BOUNDARY_Pos)
-#define SDHC_BSR_BOUNDARY_128K (SDHC_BSR_BOUNDARY_128K_Val << SDHC_BSR_BOUNDARY_Pos)
-#define SDHC_BSR_BOUNDARY_256K (SDHC_BSR_BOUNDARY_256K_Val << SDHC_BSR_BOUNDARY_Pos)
-#define SDHC_BSR_BOUNDARY_512K (SDHC_BSR_BOUNDARY_512K_Val << SDHC_BSR_BOUNDARY_Pos)
-#define SDHC_BSR_MASK _U_(0x73FF) /**< \brief (SDHC_BSR) MASK Register */
-
-/* -------- SDHC_BCR : (SDHC Offset: 0x006) (R/W 16) Block Count -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t BCNT:16; /*!< bit: 0..15 Blocks Count for Current Transfer */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} SDHC_BCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_BCR_OFFSET 0x006 /**< \brief (SDHC_BCR offset) Block Count */
-#define SDHC_BCR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_BCR reset_value) Block Count */
-
-#define SDHC_BCR_BCNT_Pos 0 /**< \brief (SDHC_BCR) Blocks Count for Current Transfer */
-#define SDHC_BCR_BCNT_Msk (_U_(0xFFFF) << SDHC_BCR_BCNT_Pos)
-#define SDHC_BCR_BCNT(value) (SDHC_BCR_BCNT_Msk & ((value) << SDHC_BCR_BCNT_Pos))
-#define SDHC_BCR_MASK _U_(0xFFFF) /**< \brief (SDHC_BCR) MASK Register */
-
-/* -------- SDHC_ARG1R : (SDHC Offset: 0x008) (R/W 32) Argument 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ARG:32; /*!< bit: 0..31 Argument 1 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SDHC_ARG1R_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_ARG1R_OFFSET 0x008 /**< \brief (SDHC_ARG1R offset) Argument 1 */
-#define SDHC_ARG1R_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_ARG1R reset_value) Argument 1 */
-
-#define SDHC_ARG1R_ARG_Pos 0 /**< \brief (SDHC_ARG1R) Argument 1 */
-#define SDHC_ARG1R_ARG_Msk (_U_(0xFFFFFFFF) << SDHC_ARG1R_ARG_Pos)
-#define SDHC_ARG1R_ARG(value) (SDHC_ARG1R_ARG_Msk & ((value) << SDHC_ARG1R_ARG_Pos))
-#define SDHC_ARG1R_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_ARG1R) MASK Register */
-
-/* -------- SDHC_TMR : (SDHC Offset: 0x00C) (R/W 16) Transfer Mode -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t DMAEN:1; /*!< bit: 0 DMA Enable */
- uint16_t BCEN:1; /*!< bit: 1 Block Count Enable */
- uint16_t ACMDEN:2; /*!< bit: 2.. 3 Auto Command Enable */
- uint16_t DTDSEL:1; /*!< bit: 4 Data Transfer Direction Selection */
- uint16_t MSBSEL:1; /*!< bit: 5 Multi/Single Block Selection */
- uint16_t :10; /*!< bit: 6..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} SDHC_TMR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_TMR_OFFSET 0x00C /**< \brief (SDHC_TMR offset) Transfer Mode */
-#define SDHC_TMR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_TMR reset_value) Transfer Mode */
-
-#define SDHC_TMR_DMAEN_Pos 0 /**< \brief (SDHC_TMR) DMA Enable */
-#define SDHC_TMR_DMAEN (_U_(0x1) << SDHC_TMR_DMAEN_Pos)
-#define SDHC_TMR_DMAEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_TMR) No data transfer or Non DMA data transfer */
-#define SDHC_TMR_DMAEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_TMR) DMA data transfer */
-#define SDHC_TMR_DMAEN_DISABLE (SDHC_TMR_DMAEN_DISABLE_Val << SDHC_TMR_DMAEN_Pos)
-#define SDHC_TMR_DMAEN_ENABLE (SDHC_TMR_DMAEN_ENABLE_Val << SDHC_TMR_DMAEN_Pos)
-#define SDHC_TMR_BCEN_Pos 1 /**< \brief (SDHC_TMR) Block Count Enable */
-#define SDHC_TMR_BCEN (_U_(0x1) << SDHC_TMR_BCEN_Pos)
-#define SDHC_TMR_BCEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_TMR) Disable */
-#define SDHC_TMR_BCEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_TMR) Enable */
-#define SDHC_TMR_BCEN_DISABLE (SDHC_TMR_BCEN_DISABLE_Val << SDHC_TMR_BCEN_Pos)
-#define SDHC_TMR_BCEN_ENABLE (SDHC_TMR_BCEN_ENABLE_Val << SDHC_TMR_BCEN_Pos)
-#define SDHC_TMR_ACMDEN_Pos 2 /**< \brief (SDHC_TMR) Auto Command Enable */
-#define SDHC_TMR_ACMDEN_Msk (_U_(0x3) << SDHC_TMR_ACMDEN_Pos)
-#define SDHC_TMR_ACMDEN(value) (SDHC_TMR_ACMDEN_Msk & ((value) << SDHC_TMR_ACMDEN_Pos))
-#define SDHC_TMR_ACMDEN_DISABLED_Val _U_(0x0) /**< \brief (SDHC_TMR) Auto Command Disabled */
-#define SDHC_TMR_ACMDEN_CMD12_Val _U_(0x1) /**< \brief (SDHC_TMR) Auto CMD12 Enable */
-#define SDHC_TMR_ACMDEN_CMD23_Val _U_(0x2) /**< \brief (SDHC_TMR) Auto CMD23 Enable */
-#define SDHC_TMR_ACMDEN_3_Val _U_(0x3) /**< \brief (SDHC_TMR) Reserved */
-#define SDHC_TMR_ACMDEN_DISABLED (SDHC_TMR_ACMDEN_DISABLED_Val << SDHC_TMR_ACMDEN_Pos)
-#define SDHC_TMR_ACMDEN_CMD12 (SDHC_TMR_ACMDEN_CMD12_Val << SDHC_TMR_ACMDEN_Pos)
-#define SDHC_TMR_ACMDEN_CMD23 (SDHC_TMR_ACMDEN_CMD23_Val << SDHC_TMR_ACMDEN_Pos)
-#define SDHC_TMR_ACMDEN_3 (SDHC_TMR_ACMDEN_3_Val << SDHC_TMR_ACMDEN_Pos)
-#define SDHC_TMR_DTDSEL_Pos 4 /**< \brief (SDHC_TMR) Data Transfer Direction Selection */
-#define SDHC_TMR_DTDSEL (_U_(0x1) << SDHC_TMR_DTDSEL_Pos)
-#define SDHC_TMR_DTDSEL_WRITE_Val _U_(0x0) /**< \brief (SDHC_TMR) Write (Host to Card) */
-#define SDHC_TMR_DTDSEL_READ_Val _U_(0x1) /**< \brief (SDHC_TMR) Read (Card to Host) */
-#define SDHC_TMR_DTDSEL_WRITE (SDHC_TMR_DTDSEL_WRITE_Val << SDHC_TMR_DTDSEL_Pos)
-#define SDHC_TMR_DTDSEL_READ (SDHC_TMR_DTDSEL_READ_Val << SDHC_TMR_DTDSEL_Pos)
-#define SDHC_TMR_MSBSEL_Pos 5 /**< \brief (SDHC_TMR) Multi/Single Block Selection */
-#define SDHC_TMR_MSBSEL (_U_(0x1) << SDHC_TMR_MSBSEL_Pos)
-#define SDHC_TMR_MSBSEL_SINGLE_Val _U_(0x0) /**< \brief (SDHC_TMR) Single Block */
-#define SDHC_TMR_MSBSEL_MULTIPLE_Val _U_(0x1) /**< \brief (SDHC_TMR) Multiple Block */
-#define SDHC_TMR_MSBSEL_SINGLE (SDHC_TMR_MSBSEL_SINGLE_Val << SDHC_TMR_MSBSEL_Pos)
-#define SDHC_TMR_MSBSEL_MULTIPLE (SDHC_TMR_MSBSEL_MULTIPLE_Val << SDHC_TMR_MSBSEL_Pos)
-#define SDHC_TMR_MASK _U_(0x003F) /**< \brief (SDHC_TMR) MASK Register */
-
-/* -------- SDHC_CR : (SDHC Offset: 0x00E) (R/W 16) Command -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t RESPTYP:2; /*!< bit: 0.. 1 Response Type */
- uint16_t :1; /*!< bit: 2 Reserved */
- uint16_t CMDCCEN:1; /*!< bit: 3 Command CRC Check Enable */
- uint16_t CMDICEN:1; /*!< bit: 4 Command Index Check Enable */
- uint16_t DPSEL:1; /*!< bit: 5 Data Present Select */
- uint16_t CMDTYP:2; /*!< bit: 6.. 7 Command Type */
- uint16_t CMDIDX:6; /*!< bit: 8..13 Command Index */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} SDHC_CR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_CR_OFFSET 0x00E /**< \brief (SDHC_CR offset) Command */
-#define SDHC_CR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_CR reset_value) Command */
-
-#define SDHC_CR_RESPTYP_Pos 0 /**< \brief (SDHC_CR) Response Type */
-#define SDHC_CR_RESPTYP_Msk (_U_(0x3) << SDHC_CR_RESPTYP_Pos)
-#define SDHC_CR_RESPTYP(value) (SDHC_CR_RESPTYP_Msk & ((value) << SDHC_CR_RESPTYP_Pos))
-#define SDHC_CR_RESPTYP_NONE_Val _U_(0x0) /**< \brief (SDHC_CR) No response */
-#define SDHC_CR_RESPTYP_136_BIT_Val _U_(0x1) /**< \brief (SDHC_CR) 136-bit response */
-#define SDHC_CR_RESPTYP_48_BIT_Val _U_(0x2) /**< \brief (SDHC_CR) 48-bit response */
-#define SDHC_CR_RESPTYP_48_BIT_BUSY_Val _U_(0x3) /**< \brief (SDHC_CR) 48-bit response check busy after response */
-#define SDHC_CR_RESPTYP_NONE (SDHC_CR_RESPTYP_NONE_Val << SDHC_CR_RESPTYP_Pos)
-#define SDHC_CR_RESPTYP_136_BIT (SDHC_CR_RESPTYP_136_BIT_Val << SDHC_CR_RESPTYP_Pos)
-#define SDHC_CR_RESPTYP_48_BIT (SDHC_CR_RESPTYP_48_BIT_Val << SDHC_CR_RESPTYP_Pos)
-#define SDHC_CR_RESPTYP_48_BIT_BUSY (SDHC_CR_RESPTYP_48_BIT_BUSY_Val << SDHC_CR_RESPTYP_Pos)
-#define SDHC_CR_CMDCCEN_Pos 3 /**< \brief (SDHC_CR) Command CRC Check Enable */
-#define SDHC_CR_CMDCCEN (_U_(0x1) << SDHC_CR_CMDCCEN_Pos)
-#define SDHC_CR_CMDCCEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_CR) Disable */
-#define SDHC_CR_CMDCCEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_CR) Enable */
-#define SDHC_CR_CMDCCEN_DISABLE (SDHC_CR_CMDCCEN_DISABLE_Val << SDHC_CR_CMDCCEN_Pos)
-#define SDHC_CR_CMDCCEN_ENABLE (SDHC_CR_CMDCCEN_ENABLE_Val << SDHC_CR_CMDCCEN_Pos)
-#define SDHC_CR_CMDICEN_Pos 4 /**< \brief (SDHC_CR) Command Index Check Enable */
-#define SDHC_CR_CMDICEN (_U_(0x1) << SDHC_CR_CMDICEN_Pos)
-#define SDHC_CR_CMDICEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_CR) Disable */
-#define SDHC_CR_CMDICEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_CR) Enable */
-#define SDHC_CR_CMDICEN_DISABLE (SDHC_CR_CMDICEN_DISABLE_Val << SDHC_CR_CMDICEN_Pos)
-#define SDHC_CR_CMDICEN_ENABLE (SDHC_CR_CMDICEN_ENABLE_Val << SDHC_CR_CMDICEN_Pos)
-#define SDHC_CR_DPSEL_Pos 5 /**< \brief (SDHC_CR) Data Present Select */
-#define SDHC_CR_DPSEL (_U_(0x1) << SDHC_CR_DPSEL_Pos)
-#define SDHC_CR_DPSEL_NO_DATA_Val _U_(0x0) /**< \brief (SDHC_CR) No Data Present */
-#define SDHC_CR_DPSEL_DATA_Val _U_(0x1) /**< \brief (SDHC_CR) Data Present */
-#define SDHC_CR_DPSEL_NO_DATA (SDHC_CR_DPSEL_NO_DATA_Val << SDHC_CR_DPSEL_Pos)
-#define SDHC_CR_DPSEL_DATA (SDHC_CR_DPSEL_DATA_Val << SDHC_CR_DPSEL_Pos)
-#define SDHC_CR_CMDTYP_Pos 6 /**< \brief (SDHC_CR) Command Type */
-#define SDHC_CR_CMDTYP_Msk (_U_(0x3) << SDHC_CR_CMDTYP_Pos)
-#define SDHC_CR_CMDTYP(value) (SDHC_CR_CMDTYP_Msk & ((value) << SDHC_CR_CMDTYP_Pos))
-#define SDHC_CR_CMDTYP_NORMAL_Val _U_(0x0) /**< \brief (SDHC_CR) Other commands */
-#define SDHC_CR_CMDTYP_SUSPEND_Val _U_(0x1) /**< \brief (SDHC_CR) CMD52 for writing Bus Suspend in CCCR */
-#define SDHC_CR_CMDTYP_RESUME_Val _U_(0x2) /**< \brief (SDHC_CR) CMD52 for writing Function Select in CCCR */
-#define SDHC_CR_CMDTYP_ABORT_Val _U_(0x3) /**< \brief (SDHC_CR) CMD12, CMD52 for writing I/O Abort in CCCR */
-#define SDHC_CR_CMDTYP_NORMAL (SDHC_CR_CMDTYP_NORMAL_Val << SDHC_CR_CMDTYP_Pos)
-#define SDHC_CR_CMDTYP_SUSPEND (SDHC_CR_CMDTYP_SUSPEND_Val << SDHC_CR_CMDTYP_Pos)
-#define SDHC_CR_CMDTYP_RESUME (SDHC_CR_CMDTYP_RESUME_Val << SDHC_CR_CMDTYP_Pos)
-#define SDHC_CR_CMDTYP_ABORT (SDHC_CR_CMDTYP_ABORT_Val << SDHC_CR_CMDTYP_Pos)
-#define SDHC_CR_CMDIDX_Pos 8 /**< \brief (SDHC_CR) Command Index */
-#define SDHC_CR_CMDIDX_Msk (_U_(0x3F) << SDHC_CR_CMDIDX_Pos)
-#define SDHC_CR_CMDIDX(value) (SDHC_CR_CMDIDX_Msk & ((value) << SDHC_CR_CMDIDX_Pos))
-#define SDHC_CR_MASK _U_(0x3FFB) /**< \brief (SDHC_CR) MASK Register */
-
-/* -------- SDHC_RR : (SDHC Offset: 0x010) (R/ 32) Response -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CMDRESP:32; /*!< bit: 0..31 Command Response */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SDHC_RR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_RR_OFFSET 0x010 /**< \brief (SDHC_RR offset) Response */
-#define SDHC_RR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_RR reset_value) Response */
-
-#define SDHC_RR_CMDRESP_Pos 0 /**< \brief (SDHC_RR) Command Response */
-#define SDHC_RR_CMDRESP_Msk (_U_(0xFFFFFFFF) << SDHC_RR_CMDRESP_Pos)
-#define SDHC_RR_CMDRESP(value) (SDHC_RR_CMDRESP_Msk & ((value) << SDHC_RR_CMDRESP_Pos))
-#define SDHC_RR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_RR) MASK Register */
-
-/* -------- SDHC_BDPR : (SDHC Offset: 0x020) (R/W 32) Buffer Data Port -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t BUFDATA:32; /*!< bit: 0..31 Buffer Data */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SDHC_BDPR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_BDPR_OFFSET 0x020 /**< \brief (SDHC_BDPR offset) Buffer Data Port */
-#define SDHC_BDPR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_BDPR reset_value) Buffer Data Port */
-
-#define SDHC_BDPR_BUFDATA_Pos 0 /**< \brief (SDHC_BDPR) Buffer Data */
-#define SDHC_BDPR_BUFDATA_Msk (_U_(0xFFFFFFFF) << SDHC_BDPR_BUFDATA_Pos)
-#define SDHC_BDPR_BUFDATA(value) (SDHC_BDPR_BUFDATA_Msk & ((value) << SDHC_BDPR_BUFDATA_Pos))
-#define SDHC_BDPR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_BDPR) MASK Register */
-
-/* -------- SDHC_PSR : (SDHC Offset: 0x024) (R/ 32) Present State -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CMDINHC:1; /*!< bit: 0 Command Inhibit (CMD) */
- uint32_t CMDINHD:1; /*!< bit: 1 Command Inhibit (DAT) */
- uint32_t DLACT:1; /*!< bit: 2 DAT Line Active */
- uint32_t RTREQ:1; /*!< bit: 3 Re-Tuning Request */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t WTACT:1; /*!< bit: 8 Write Transfer Active */
- uint32_t RTACT:1; /*!< bit: 9 Read Transfer Active */
- uint32_t BUFWREN:1; /*!< bit: 10 Buffer Write Enable */
- uint32_t BUFRDEN:1; /*!< bit: 11 Buffer Read Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t CARDINS:1; /*!< bit: 16 Card Inserted */
- uint32_t CARDSS:1; /*!< bit: 17 Card State Stable */
- uint32_t CARDDPL:1; /*!< bit: 18 Card Detect Pin Level */
- uint32_t WRPPL:1; /*!< bit: 19 Write Protect Pin Level */
- uint32_t DATLL:4; /*!< bit: 20..23 DAT[3:0] Line Level */
- uint32_t CMDLL:1; /*!< bit: 24 CMD Line Level */
- uint32_t :7; /*!< bit: 25..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SDHC_PSR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_PSR_OFFSET 0x024 /**< \brief (SDHC_PSR offset) Present State */
-#define SDHC_PSR_RESETVALUE _U_(0x00F80000) /**< \brief (SDHC_PSR reset_value) Present State */
-
-#define SDHC_PSR_CMDINHC_Pos 0 /**< \brief (SDHC_PSR) Command Inhibit (CMD) */
-#define SDHC_PSR_CMDINHC (_U_(0x1) << SDHC_PSR_CMDINHC_Pos)
-#define SDHC_PSR_CMDINHC_CAN_Val _U_(0x0) /**< \brief (SDHC_PSR) Can issue command using only CMD line */
-#define SDHC_PSR_CMDINHC_CANNOT_Val _U_(0x1) /**< \brief (SDHC_PSR) Cannot issue command */
-#define SDHC_PSR_CMDINHC_CAN (SDHC_PSR_CMDINHC_CAN_Val << SDHC_PSR_CMDINHC_Pos)
-#define SDHC_PSR_CMDINHC_CANNOT (SDHC_PSR_CMDINHC_CANNOT_Val << SDHC_PSR_CMDINHC_Pos)
-#define SDHC_PSR_CMDINHD_Pos 1 /**< \brief (SDHC_PSR) Command Inhibit (DAT) */
-#define SDHC_PSR_CMDINHD (_U_(0x1) << SDHC_PSR_CMDINHD_Pos)
-#define SDHC_PSR_CMDINHD_CAN_Val _U_(0x0) /**< \brief (SDHC_PSR) Can issue command which uses the DAT line */
-#define SDHC_PSR_CMDINHD_CANNOT_Val _U_(0x1) /**< \brief (SDHC_PSR) Cannot issue command which uses the DAT line */
-#define SDHC_PSR_CMDINHD_CAN (SDHC_PSR_CMDINHD_CAN_Val << SDHC_PSR_CMDINHD_Pos)
-#define SDHC_PSR_CMDINHD_CANNOT (SDHC_PSR_CMDINHD_CANNOT_Val << SDHC_PSR_CMDINHD_Pos)
-#define SDHC_PSR_DLACT_Pos 2 /**< \brief (SDHC_PSR) DAT Line Active */
-#define SDHC_PSR_DLACT (_U_(0x1) << SDHC_PSR_DLACT_Pos)
-#define SDHC_PSR_DLACT_INACTIVE_Val _U_(0x0) /**< \brief (SDHC_PSR) DAT Line Inactive */
-#define SDHC_PSR_DLACT_ACTIVE_Val _U_(0x1) /**< \brief (SDHC_PSR) DAT Line Active */
-#define SDHC_PSR_DLACT_INACTIVE (SDHC_PSR_DLACT_INACTIVE_Val << SDHC_PSR_DLACT_Pos)
-#define SDHC_PSR_DLACT_ACTIVE (SDHC_PSR_DLACT_ACTIVE_Val << SDHC_PSR_DLACT_Pos)
-#define SDHC_PSR_RTREQ_Pos 3 /**< \brief (SDHC_PSR) Re-Tuning Request */
-#define SDHC_PSR_RTREQ (_U_(0x1) << SDHC_PSR_RTREQ_Pos)
-#define SDHC_PSR_RTREQ_OK_Val _U_(0x0) /**< \brief (SDHC_PSR) Fixed or well-tuned sampling clock */
-#define SDHC_PSR_RTREQ_REQUIRED_Val _U_(0x1) /**< \brief (SDHC_PSR) Sampling clock needs re-tuning */
-#define SDHC_PSR_RTREQ_OK (SDHC_PSR_RTREQ_OK_Val << SDHC_PSR_RTREQ_Pos)
-#define SDHC_PSR_RTREQ_REQUIRED (SDHC_PSR_RTREQ_REQUIRED_Val << SDHC_PSR_RTREQ_Pos)
-#define SDHC_PSR_WTACT_Pos 8 /**< \brief (SDHC_PSR) Write Transfer Active */
-#define SDHC_PSR_WTACT (_U_(0x1) << SDHC_PSR_WTACT_Pos)
-#define SDHC_PSR_WTACT_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) No valid data */
-#define SDHC_PSR_WTACT_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Transferring data */
-#define SDHC_PSR_WTACT_NO (SDHC_PSR_WTACT_NO_Val << SDHC_PSR_WTACT_Pos)
-#define SDHC_PSR_WTACT_YES (SDHC_PSR_WTACT_YES_Val << SDHC_PSR_WTACT_Pos)
-#define SDHC_PSR_RTACT_Pos 9 /**< \brief (SDHC_PSR) Read Transfer Active */
-#define SDHC_PSR_RTACT (_U_(0x1) << SDHC_PSR_RTACT_Pos)
-#define SDHC_PSR_RTACT_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) No valid data */
-#define SDHC_PSR_RTACT_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Transferring data */
-#define SDHC_PSR_RTACT_NO (SDHC_PSR_RTACT_NO_Val << SDHC_PSR_RTACT_Pos)
-#define SDHC_PSR_RTACT_YES (SDHC_PSR_RTACT_YES_Val << SDHC_PSR_RTACT_Pos)
-#define SDHC_PSR_BUFWREN_Pos 10 /**< \brief (SDHC_PSR) Buffer Write Enable */
-#define SDHC_PSR_BUFWREN (_U_(0x1) << SDHC_PSR_BUFWREN_Pos)
-#define SDHC_PSR_BUFWREN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_PSR) Write disable */
-#define SDHC_PSR_BUFWREN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_PSR) Write enable */
-#define SDHC_PSR_BUFWREN_DISABLE (SDHC_PSR_BUFWREN_DISABLE_Val << SDHC_PSR_BUFWREN_Pos)
-#define SDHC_PSR_BUFWREN_ENABLE (SDHC_PSR_BUFWREN_ENABLE_Val << SDHC_PSR_BUFWREN_Pos)
-#define SDHC_PSR_BUFRDEN_Pos 11 /**< \brief (SDHC_PSR) Buffer Read Enable */
-#define SDHC_PSR_BUFRDEN (_U_(0x1) << SDHC_PSR_BUFRDEN_Pos)
-#define SDHC_PSR_BUFRDEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_PSR) Read disable */
-#define SDHC_PSR_BUFRDEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_PSR) Read enable */
-#define SDHC_PSR_BUFRDEN_DISABLE (SDHC_PSR_BUFRDEN_DISABLE_Val << SDHC_PSR_BUFRDEN_Pos)
-#define SDHC_PSR_BUFRDEN_ENABLE (SDHC_PSR_BUFRDEN_ENABLE_Val << SDHC_PSR_BUFRDEN_Pos)
-#define SDHC_PSR_CARDINS_Pos 16 /**< \brief (SDHC_PSR) Card Inserted */
-#define SDHC_PSR_CARDINS (_U_(0x1) << SDHC_PSR_CARDINS_Pos)
-#define SDHC_PSR_CARDINS_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) Reset or Debouncing or No Card */
-#define SDHC_PSR_CARDINS_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Card inserted */
-#define SDHC_PSR_CARDINS_NO (SDHC_PSR_CARDINS_NO_Val << SDHC_PSR_CARDINS_Pos)
-#define SDHC_PSR_CARDINS_YES (SDHC_PSR_CARDINS_YES_Val << SDHC_PSR_CARDINS_Pos)
-#define SDHC_PSR_CARDSS_Pos 17 /**< \brief (SDHC_PSR) Card State Stable */
-#define SDHC_PSR_CARDSS (_U_(0x1) << SDHC_PSR_CARDSS_Pos)
-#define SDHC_PSR_CARDSS_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) Reset or Debouncing */
-#define SDHC_PSR_CARDSS_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) No Card or Insered */
-#define SDHC_PSR_CARDSS_NO (SDHC_PSR_CARDSS_NO_Val << SDHC_PSR_CARDSS_Pos)
-#define SDHC_PSR_CARDSS_YES (SDHC_PSR_CARDSS_YES_Val << SDHC_PSR_CARDSS_Pos)
-#define SDHC_PSR_CARDDPL_Pos 18 /**< \brief (SDHC_PSR) Card Detect Pin Level */
-#define SDHC_PSR_CARDDPL (_U_(0x1) << SDHC_PSR_CARDDPL_Pos)
-#define SDHC_PSR_CARDDPL_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) No card present (SDCD#=1) */
-#define SDHC_PSR_CARDDPL_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Card present (SDCD#=0) */
-#define SDHC_PSR_CARDDPL_NO (SDHC_PSR_CARDDPL_NO_Val << SDHC_PSR_CARDDPL_Pos)
-#define SDHC_PSR_CARDDPL_YES (SDHC_PSR_CARDDPL_YES_Val << SDHC_PSR_CARDDPL_Pos)
-#define SDHC_PSR_WRPPL_Pos 19 /**< \brief (SDHC_PSR) Write Protect Pin Level */
-#define SDHC_PSR_WRPPL (_U_(0x1) << SDHC_PSR_WRPPL_Pos)
-#define SDHC_PSR_WRPPL_PROTECTED_Val _U_(0x0) /**< \brief (SDHC_PSR) Write protected (SDWP#=0) */
-#define SDHC_PSR_WRPPL_ENABLED_Val _U_(0x1) /**< \brief (SDHC_PSR) Write enabled (SDWP#=1) */
-#define SDHC_PSR_WRPPL_PROTECTED (SDHC_PSR_WRPPL_PROTECTED_Val << SDHC_PSR_WRPPL_Pos)
-#define SDHC_PSR_WRPPL_ENABLED (SDHC_PSR_WRPPL_ENABLED_Val << SDHC_PSR_WRPPL_Pos)
-#define SDHC_PSR_DATLL_Pos 20 /**< \brief (SDHC_PSR) DAT[3:0] Line Level */
-#define SDHC_PSR_DATLL_Msk (_U_(0xF) << SDHC_PSR_DATLL_Pos)
-#define SDHC_PSR_DATLL(value) (SDHC_PSR_DATLL_Msk & ((value) << SDHC_PSR_DATLL_Pos))
-#define SDHC_PSR_CMDLL_Pos 24 /**< \brief (SDHC_PSR) CMD Line Level */
-#define SDHC_PSR_CMDLL (_U_(0x1) << SDHC_PSR_CMDLL_Pos)
-#define SDHC_PSR_MASK _U_(0x01FF0F0F) /**< \brief (SDHC_PSR) MASK Register */
-
-/* -------- SDHC_HC1R : (SDHC Offset: 0x028) (R/W 8) Host Control 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t LEDCTRL:1; /*!< bit: 0 LED Control */
- uint8_t DW:1; /*!< bit: 1 Data Width */
- uint8_t HSEN:1; /*!< bit: 2 High Speed Enable */
- uint8_t DMASEL:2; /*!< bit: 3.. 4 DMA Select */
- uint8_t :1; /*!< bit: 5 Reserved */
- uint8_t CARDDTL:1; /*!< bit: 6 Card Detect Test Level */
- uint8_t CARDDSEL:1; /*!< bit: 7 Card Detect Signal Selection */
- } bit; /*!< Structure used for bit access */
- struct { // EMMC mode
- uint8_t :1; /*!< bit: 0 Reserved */
- uint8_t DW:1; /*!< bit: 1 Data Width */
- uint8_t HSEN:1; /*!< bit: 2 High Speed Enable */
- uint8_t DMASEL:2; /*!< bit: 3.. 4 DMA Select */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } EMMC; /*!< Structure used for EMMC */
- uint8_t reg; /*!< Type used for register access */
-} SDHC_HC1R_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_HC1R_OFFSET 0x028 /**< \brief (SDHC_HC1R offset) Host Control 1 */
-#define SDHC_HC1R_RESETVALUE _U_(0xE00) /**< \brief (SDHC_HC1R reset_value) Host Control 1 */
-
-#define SDHC_HC1R_LEDCTRL_Pos 0 /**< \brief (SDHC_HC1R) LED Control */
-#define SDHC_HC1R_LEDCTRL (_U_(0x1) << SDHC_HC1R_LEDCTRL_Pos)
-#define SDHC_HC1R_LEDCTRL_OFF_Val _U_(0x0) /**< \brief (SDHC_HC1R) LED off */
-#define SDHC_HC1R_LEDCTRL_ON_Val _U_(0x1) /**< \brief (SDHC_HC1R) LED on */
-#define SDHC_HC1R_LEDCTRL_OFF (SDHC_HC1R_LEDCTRL_OFF_Val << SDHC_HC1R_LEDCTRL_Pos)
-#define SDHC_HC1R_LEDCTRL_ON (SDHC_HC1R_LEDCTRL_ON_Val << SDHC_HC1R_LEDCTRL_Pos)
-#define SDHC_HC1R_DW_Pos 1 /**< \brief (SDHC_HC1R) Data Width */
-#define SDHC_HC1R_DW (_U_(0x1) << SDHC_HC1R_DW_Pos)
-#define SDHC_HC1R_DW_1BIT_Val _U_(0x0) /**< \brief (SDHC_HC1R) 1-bit mode */
-#define SDHC_HC1R_DW_4BIT_Val _U_(0x1) /**< \brief (SDHC_HC1R) 4-bit mode */
-#define SDHC_HC1R_DW_1BIT (SDHC_HC1R_DW_1BIT_Val << SDHC_HC1R_DW_Pos)
-#define SDHC_HC1R_DW_4BIT (SDHC_HC1R_DW_4BIT_Val << SDHC_HC1R_DW_Pos)
-#define SDHC_HC1R_HSEN_Pos 2 /**< \brief (SDHC_HC1R) High Speed Enable */
-#define SDHC_HC1R_HSEN (_U_(0x1) << SDHC_HC1R_HSEN_Pos)
-#define SDHC_HC1R_HSEN_NORMAL_Val _U_(0x0) /**< \brief (SDHC_HC1R) Normal Speed mode */
-#define SDHC_HC1R_HSEN_HIGH_Val _U_(0x1) /**< \brief (SDHC_HC1R) High Speed mode */
-#define SDHC_HC1R_HSEN_NORMAL (SDHC_HC1R_HSEN_NORMAL_Val << SDHC_HC1R_HSEN_Pos)
-#define SDHC_HC1R_HSEN_HIGH (SDHC_HC1R_HSEN_HIGH_Val << SDHC_HC1R_HSEN_Pos)
-#define SDHC_HC1R_DMASEL_Pos 3 /**< \brief (SDHC_HC1R) DMA Select */
-#define SDHC_HC1R_DMASEL_Msk (_U_(0x3) << SDHC_HC1R_DMASEL_Pos)
-#define SDHC_HC1R_DMASEL(value) (SDHC_HC1R_DMASEL_Msk & ((value) << SDHC_HC1R_DMASEL_Pos))
-#define SDHC_HC1R_DMASEL_SDMA_Val _U_(0x0) /**< \brief (SDHC_HC1R) SDMA is selected */
-#define SDHC_HC1R_DMASEL_1_Val _U_(0x1) /**< \brief (SDHC_HC1R) Reserved */
-#define SDHC_HC1R_DMASEL_32BIT_Val _U_(0x2) /**< \brief (SDHC_HC1R) 32-bit Address ADMA2 is selected */
-#define SDHC_HC1R_DMASEL_SDMA (SDHC_HC1R_DMASEL_SDMA_Val << SDHC_HC1R_DMASEL_Pos)
-#define SDHC_HC1R_DMASEL_1 (SDHC_HC1R_DMASEL_1_Val << SDHC_HC1R_DMASEL_Pos)
-#define SDHC_HC1R_DMASEL_32BIT (SDHC_HC1R_DMASEL_32BIT_Val << SDHC_HC1R_DMASEL_Pos)
-#define SDHC_HC1R_CARDDTL_Pos 6 /**< \brief (SDHC_HC1R) Card Detect Test Level */
-#define SDHC_HC1R_CARDDTL (_U_(0x1) << SDHC_HC1R_CARDDTL_Pos)
-#define SDHC_HC1R_CARDDTL_NO_Val _U_(0x0) /**< \brief (SDHC_HC1R) No Card */
-#define SDHC_HC1R_CARDDTL_YES_Val _U_(0x1) /**< \brief (SDHC_HC1R) Card Inserted */
-#define SDHC_HC1R_CARDDTL_NO (SDHC_HC1R_CARDDTL_NO_Val << SDHC_HC1R_CARDDTL_Pos)
-#define SDHC_HC1R_CARDDTL_YES (SDHC_HC1R_CARDDTL_YES_Val << SDHC_HC1R_CARDDTL_Pos)
-#define SDHC_HC1R_CARDDSEL_Pos 7 /**< \brief (SDHC_HC1R) Card Detect Signal Selection */
-#define SDHC_HC1R_CARDDSEL (_U_(0x1) << SDHC_HC1R_CARDDSEL_Pos)
-#define SDHC_HC1R_CARDDSEL_NORMAL_Val _U_(0x0) /**< \brief (SDHC_HC1R) SDCD# is selected (for normal use) */
-#define SDHC_HC1R_CARDDSEL_TEST_Val _U_(0x1) /**< \brief (SDHC_HC1R) The Card Select Test Level is selected (for test purpose) */
-#define SDHC_HC1R_CARDDSEL_NORMAL (SDHC_HC1R_CARDDSEL_NORMAL_Val << SDHC_HC1R_CARDDSEL_Pos)
-#define SDHC_HC1R_CARDDSEL_TEST (SDHC_HC1R_CARDDSEL_TEST_Val << SDHC_HC1R_CARDDSEL_Pos)
-#define SDHC_HC1R_MASK _U_(0xDF) /**< \brief (SDHC_HC1R) MASK Register */
-
-// EMMC mode
-#define SDHC_HC1R_EMMC_DW_Pos 1 /**< \brief (SDHC_HC1R_EMMC) Data Width */
-#define SDHC_HC1R_EMMC_DW (_U_(0x1) << SDHC_HC1R_EMMC_DW_Pos)
-#define SDHC_HC1R_EMMC_DW_1BIT_Val _U_(0x0) /**< \brief (SDHC_HC1R_EMMC) 1-bit mode */
-#define SDHC_HC1R_EMMC_DW_4BIT_Val _U_(0x1) /**< \brief (SDHC_HC1R_EMMC) 4-bit mode */
-#define SDHC_HC1R_EMMC_DW_1BIT (SDHC_HC1R_EMMC_DW_1BIT_Val << SDHC_HC1R_EMMC_DW_Pos)
-#define SDHC_HC1R_EMMC_DW_4BIT (SDHC_HC1R_EMMC_DW_4BIT_Val << SDHC_HC1R_EMMC_DW_Pos)
-#define SDHC_HC1R_EMMC_HSEN_Pos 2 /**< \brief (SDHC_HC1R_EMMC) High Speed Enable */
-#define SDHC_HC1R_EMMC_HSEN (_U_(0x1) << SDHC_HC1R_EMMC_HSEN_Pos)
-#define SDHC_HC1R_EMMC_HSEN_NORMAL_Val _U_(0x0) /**< \brief (SDHC_HC1R_EMMC) Normal Speed mode */
-#define SDHC_HC1R_EMMC_HSEN_HIGH_Val _U_(0x1) /**< \brief (SDHC_HC1R_EMMC) High Speed mode */
-#define SDHC_HC1R_EMMC_HSEN_NORMAL (SDHC_HC1R_EMMC_HSEN_NORMAL_Val << SDHC_HC1R_EMMC_HSEN_Pos)
-#define SDHC_HC1R_EMMC_HSEN_HIGH (SDHC_HC1R_EMMC_HSEN_HIGH_Val << SDHC_HC1R_EMMC_HSEN_Pos)
-#define SDHC_HC1R_EMMC_DMASEL_Pos 3 /**< \brief (SDHC_HC1R_EMMC) DMA Select */
-#define SDHC_HC1R_EMMC_DMASEL_Msk (_U_(0x3) << SDHC_HC1R_EMMC_DMASEL_Pos)
-#define SDHC_HC1R_EMMC_DMASEL(value) (SDHC_HC1R_EMMC_DMASEL_Msk & ((value) << SDHC_HC1R_EMMC_DMASEL_Pos))
-#define SDHC_HC1R_EMMC_DMASEL_SDMA_Val _U_(0x0) /**< \brief (SDHC_HC1R_EMMC) SDMA is selected */
-#define SDHC_HC1R_EMMC_DMASEL_1_Val _U_(0x1) /**< \brief (SDHC_HC1R_EMMC) Reserved */
-#define SDHC_HC1R_EMMC_DMASEL_32BIT_Val _U_(0x2) /**< \brief (SDHC_HC1R_EMMC) 32-bit Address ADMA2 is selected */
-#define SDHC_HC1R_EMMC_DMASEL_SDMA (SDHC_HC1R_EMMC_DMASEL_SDMA_Val << SDHC_HC1R_EMMC_DMASEL_Pos)
-#define SDHC_HC1R_EMMC_DMASEL_1 (SDHC_HC1R_EMMC_DMASEL_1_Val << SDHC_HC1R_EMMC_DMASEL_Pos)
-#define SDHC_HC1R_EMMC_DMASEL_32BIT (SDHC_HC1R_EMMC_DMASEL_32BIT_Val << SDHC_HC1R_EMMC_DMASEL_Pos)
-#define SDHC_HC1R_EMMC_MASK _U_(0x1E) /**< \brief (SDHC_HC1R_EMMC) MASK Register */
-
-/* -------- SDHC_PCR : (SDHC Offset: 0x029) (R/W 8) Power Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SDBPWR:1; /*!< bit: 0 SD Bus Power */
- uint8_t SDBVSEL:3; /*!< bit: 1.. 3 SD Bus Voltage Select */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SDHC_PCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_PCR_OFFSET 0x029 /**< \brief (SDHC_PCR offset) Power Control */
-#define SDHC_PCR_RESETVALUE _U_(0x0E) /**< \brief (SDHC_PCR reset_value) Power Control */
-
-#define SDHC_PCR_SDBPWR_Pos 0 /**< \brief (SDHC_PCR) SD Bus Power */
-#define SDHC_PCR_SDBPWR (_U_(0x1) << SDHC_PCR_SDBPWR_Pos)
-#define SDHC_PCR_SDBPWR_OFF_Val _U_(0x0) /**< \brief (SDHC_PCR) Power off */
-#define SDHC_PCR_SDBPWR_ON_Val _U_(0x1) /**< \brief (SDHC_PCR) Power on */
-#define SDHC_PCR_SDBPWR_OFF (SDHC_PCR_SDBPWR_OFF_Val << SDHC_PCR_SDBPWR_Pos)
-#define SDHC_PCR_SDBPWR_ON (SDHC_PCR_SDBPWR_ON_Val << SDHC_PCR_SDBPWR_Pos)
-#define SDHC_PCR_SDBVSEL_Pos 1 /**< \brief (SDHC_PCR) SD Bus Voltage Select */
-#define SDHC_PCR_SDBVSEL_Msk (_U_(0x7) << SDHC_PCR_SDBVSEL_Pos)
-#define SDHC_PCR_SDBVSEL(value) (SDHC_PCR_SDBVSEL_Msk & ((value) << SDHC_PCR_SDBVSEL_Pos))
-#define SDHC_PCR_SDBVSEL_1V8_Val _U_(0x5) /**< \brief (SDHC_PCR) 1.8V (Typ.) */
-#define SDHC_PCR_SDBVSEL_3V0_Val _U_(0x6) /**< \brief (SDHC_PCR) 3.0V (Typ.) */
-#define SDHC_PCR_SDBVSEL_3V3_Val _U_(0x7) /**< \brief (SDHC_PCR) 3.3V (Typ.) */
-#define SDHC_PCR_SDBVSEL_1V8 (SDHC_PCR_SDBVSEL_1V8_Val << SDHC_PCR_SDBVSEL_Pos)
-#define SDHC_PCR_SDBVSEL_3V0 (SDHC_PCR_SDBVSEL_3V0_Val << SDHC_PCR_SDBVSEL_Pos)
-#define SDHC_PCR_SDBVSEL_3V3 (SDHC_PCR_SDBVSEL_3V3_Val << SDHC_PCR_SDBVSEL_Pos)
-#define SDHC_PCR_MASK _U_(0x0F) /**< \brief (SDHC_PCR) MASK Register */
-
-/* -------- SDHC_BGCR : (SDHC Offset: 0x02A) (R/W 8) Block Gap Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t STPBGR:1; /*!< bit: 0 Stop at Block Gap Request */
- uint8_t CONTR:1; /*!< bit: 1 Continue Request */
- uint8_t RWCTRL:1; /*!< bit: 2 Read Wait Control */
- uint8_t INTBG:1; /*!< bit: 3 Interrupt at Block Gap */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct { // EMMC mode
- uint8_t STPBGR:1; /*!< bit: 0 Stop at Block Gap Request */
- uint8_t CONTR:1; /*!< bit: 1 Continue Request */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } EMMC; /*!< Structure used for EMMC */
- uint8_t reg; /*!< Type used for register access */
-} SDHC_BGCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_BGCR_OFFSET 0x02A /**< \brief (SDHC_BGCR offset) Block Gap Control */
-#define SDHC_BGCR_RESETVALUE _U_(0x00) /**< \brief (SDHC_BGCR reset_value) Block Gap Control */
-
-#define SDHC_BGCR_STPBGR_Pos 0 /**< \brief (SDHC_BGCR) Stop at Block Gap Request */
-#define SDHC_BGCR_STPBGR (_U_(0x1) << SDHC_BGCR_STPBGR_Pos)
-#define SDHC_BGCR_STPBGR_TRANSFER_Val _U_(0x0) /**< \brief (SDHC_BGCR) Transfer */
-#define SDHC_BGCR_STPBGR_STOP_Val _U_(0x1) /**< \brief (SDHC_BGCR) Stop */
-#define SDHC_BGCR_STPBGR_TRANSFER (SDHC_BGCR_STPBGR_TRANSFER_Val << SDHC_BGCR_STPBGR_Pos)
-#define SDHC_BGCR_STPBGR_STOP (SDHC_BGCR_STPBGR_STOP_Val << SDHC_BGCR_STPBGR_Pos)
-#define SDHC_BGCR_CONTR_Pos 1 /**< \brief (SDHC_BGCR) Continue Request */
-#define SDHC_BGCR_CONTR (_U_(0x1) << SDHC_BGCR_CONTR_Pos)
-#define SDHC_BGCR_CONTR_GO_ON_Val _U_(0x0) /**< \brief (SDHC_BGCR) Not affected */
-#define SDHC_BGCR_CONTR_RESTART_Val _U_(0x1) /**< \brief (SDHC_BGCR) Restart */
-#define SDHC_BGCR_CONTR_GO_ON (SDHC_BGCR_CONTR_GO_ON_Val << SDHC_BGCR_CONTR_Pos)
-#define SDHC_BGCR_CONTR_RESTART (SDHC_BGCR_CONTR_RESTART_Val << SDHC_BGCR_CONTR_Pos)
-#define SDHC_BGCR_RWCTRL_Pos 2 /**< \brief (SDHC_BGCR) Read Wait Control */
-#define SDHC_BGCR_RWCTRL (_U_(0x1) << SDHC_BGCR_RWCTRL_Pos)
-#define SDHC_BGCR_RWCTRL_DISABLE_Val _U_(0x0) /**< \brief (SDHC_BGCR) Disable Read Wait Control */
-#define SDHC_BGCR_RWCTRL_ENABLE_Val _U_(0x1) /**< \brief (SDHC_BGCR) Enable Read Wait Control */
-#define SDHC_BGCR_RWCTRL_DISABLE (SDHC_BGCR_RWCTRL_DISABLE_Val << SDHC_BGCR_RWCTRL_Pos)
-#define SDHC_BGCR_RWCTRL_ENABLE (SDHC_BGCR_RWCTRL_ENABLE_Val << SDHC_BGCR_RWCTRL_Pos)
-#define SDHC_BGCR_INTBG_Pos 3 /**< \brief (SDHC_BGCR) Interrupt at Block Gap */
-#define SDHC_BGCR_INTBG (_U_(0x1) << SDHC_BGCR_INTBG_Pos)
-#define SDHC_BGCR_INTBG_DISABLED_Val _U_(0x0) /**< \brief (SDHC_BGCR) Disabled */
-#define SDHC_BGCR_INTBG_ENABLED_Val _U_(0x1) /**< \brief (SDHC_BGCR) Enabled */
-#define SDHC_BGCR_INTBG_DISABLED (SDHC_BGCR_INTBG_DISABLED_Val << SDHC_BGCR_INTBG_Pos)
-#define SDHC_BGCR_INTBG_ENABLED (SDHC_BGCR_INTBG_ENABLED_Val << SDHC_BGCR_INTBG_Pos)
-#define SDHC_BGCR_MASK _U_(0x0F) /**< \brief (SDHC_BGCR) MASK Register */
-
-// EMMC mode
-#define SDHC_BGCR_EMMC_STPBGR_Pos 0 /**< \brief (SDHC_BGCR_EMMC) Stop at Block Gap Request */
-#define SDHC_BGCR_EMMC_STPBGR (_U_(0x1) << SDHC_BGCR_EMMC_STPBGR_Pos)
-#define SDHC_BGCR_EMMC_STPBGR_TRANSFER_Val _U_(0x0) /**< \brief (SDHC_BGCR_EMMC) Transfer */
-#define SDHC_BGCR_EMMC_STPBGR_STOP_Val _U_(0x1) /**< \brief (SDHC_BGCR_EMMC) Stop */
-#define SDHC_BGCR_EMMC_STPBGR_TRANSFER (SDHC_BGCR_EMMC_STPBGR_TRANSFER_Val << SDHC_BGCR_EMMC_STPBGR_Pos)
-#define SDHC_BGCR_EMMC_STPBGR_STOP (SDHC_BGCR_EMMC_STPBGR_STOP_Val << SDHC_BGCR_EMMC_STPBGR_Pos)
-#define SDHC_BGCR_EMMC_CONTR_Pos 1 /**< \brief (SDHC_BGCR_EMMC) Continue Request */
-#define SDHC_BGCR_EMMC_CONTR (_U_(0x1) << SDHC_BGCR_EMMC_CONTR_Pos)
-#define SDHC_BGCR_EMMC_CONTR_GO_ON_Val _U_(0x0) /**< \brief (SDHC_BGCR_EMMC) Not affected */
-#define SDHC_BGCR_EMMC_CONTR_RESTART_Val _U_(0x1) /**< \brief (SDHC_BGCR_EMMC) Restart */
-#define SDHC_BGCR_EMMC_CONTR_GO_ON (SDHC_BGCR_EMMC_CONTR_GO_ON_Val << SDHC_BGCR_EMMC_CONTR_Pos)
-#define SDHC_BGCR_EMMC_CONTR_RESTART (SDHC_BGCR_EMMC_CONTR_RESTART_Val << SDHC_BGCR_EMMC_CONTR_Pos)
-#define SDHC_BGCR_EMMC_MASK _U_(0x03) /**< \brief (SDHC_BGCR_EMMC) MASK Register */
-
-/* -------- SDHC_WCR : (SDHC Offset: 0x02B) (R/W 8) Wakeup Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t WKENCINT:1; /*!< bit: 0 Wakeup Event Enable on Card Interrupt */
- uint8_t WKENCINS:1; /*!< bit: 1 Wakeup Event Enable on Card Insertion */
- uint8_t WKENCREM:1; /*!< bit: 2 Wakeup Event Enable on Card Removal */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SDHC_WCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_WCR_OFFSET 0x02B /**< \brief (SDHC_WCR offset) Wakeup Control */
-#define SDHC_WCR_RESETVALUE _U_(0x00) /**< \brief (SDHC_WCR reset_value) Wakeup Control */
-
-#define SDHC_WCR_WKENCINT_Pos 0 /**< \brief (SDHC_WCR) Wakeup Event Enable on Card Interrupt */
-#define SDHC_WCR_WKENCINT (_U_(0x1) << SDHC_WCR_WKENCINT_Pos)
-#define SDHC_WCR_WKENCINT_DISABLE_Val _U_(0x0) /**< \brief (SDHC_WCR) Disable */
-#define SDHC_WCR_WKENCINT_ENABLE_Val _U_(0x1) /**< \brief (SDHC_WCR) Enable */
-#define SDHC_WCR_WKENCINT_DISABLE (SDHC_WCR_WKENCINT_DISABLE_Val << SDHC_WCR_WKENCINT_Pos)
-#define SDHC_WCR_WKENCINT_ENABLE (SDHC_WCR_WKENCINT_ENABLE_Val << SDHC_WCR_WKENCINT_Pos)
-#define SDHC_WCR_WKENCINS_Pos 1 /**< \brief (SDHC_WCR) Wakeup Event Enable on Card Insertion */
-#define SDHC_WCR_WKENCINS (_U_(0x1) << SDHC_WCR_WKENCINS_Pos)
-#define SDHC_WCR_WKENCINS_DISABLE_Val _U_(0x0) /**< \brief (SDHC_WCR) Disable */
-#define SDHC_WCR_WKENCINS_ENABLE_Val _U_(0x1) /**< \brief (SDHC_WCR) Enable */
-#define SDHC_WCR_WKENCINS_DISABLE (SDHC_WCR_WKENCINS_DISABLE_Val << SDHC_WCR_WKENCINS_Pos)
-#define SDHC_WCR_WKENCINS_ENABLE (SDHC_WCR_WKENCINS_ENABLE_Val << SDHC_WCR_WKENCINS_Pos)
-#define SDHC_WCR_WKENCREM_Pos 2 /**< \brief (SDHC_WCR) Wakeup Event Enable on Card Removal */
-#define SDHC_WCR_WKENCREM (_U_(0x1) << SDHC_WCR_WKENCREM_Pos)
-#define SDHC_WCR_WKENCREM_DISABLE_Val _U_(0x0) /**< \brief (SDHC_WCR) Disable */
-#define SDHC_WCR_WKENCREM_ENABLE_Val _U_(0x1) /**< \brief (SDHC_WCR) Enable */
-#define SDHC_WCR_WKENCREM_DISABLE (SDHC_WCR_WKENCREM_DISABLE_Val << SDHC_WCR_WKENCREM_Pos)
-#define SDHC_WCR_WKENCREM_ENABLE (SDHC_WCR_WKENCREM_ENABLE_Val << SDHC_WCR_WKENCREM_Pos)
-#define SDHC_WCR_MASK _U_(0x07) /**< \brief (SDHC_WCR) MASK Register */
-
-/* -------- SDHC_CCR : (SDHC Offset: 0x02C) (R/W 16) Clock Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t INTCLKEN:1; /*!< bit: 0 Internal Clock Enable */
- uint16_t INTCLKS:1; /*!< bit: 1 Internal Clock Stable */
- uint16_t SDCLKEN:1; /*!< bit: 2 SD Clock Enable */
- uint16_t :2; /*!< bit: 3.. 4 Reserved */
- uint16_t CLKGSEL:1; /*!< bit: 5 Clock Generator Select */
- uint16_t USDCLKFSEL:2; /*!< bit: 6.. 7 Upper Bits of SDCLK Frequency Select */
- uint16_t SDCLKFSEL:8; /*!< bit: 8..15 SDCLK Frequency Select */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} SDHC_CCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_CCR_OFFSET 0x02C /**< \brief (SDHC_CCR offset) Clock Control */
-#define SDHC_CCR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_CCR reset_value) Clock Control */
-
-#define SDHC_CCR_INTCLKEN_Pos 0 /**< \brief (SDHC_CCR) Internal Clock Enable */
-#define SDHC_CCR_INTCLKEN (_U_(0x1) << SDHC_CCR_INTCLKEN_Pos)
-#define SDHC_CCR_INTCLKEN_OFF_Val _U_(0x0) /**< \brief (SDHC_CCR) Stop */
-#define SDHC_CCR_INTCLKEN_ON_Val _U_(0x1) /**< \brief (SDHC_CCR) Oscillate */
-#define SDHC_CCR_INTCLKEN_OFF (SDHC_CCR_INTCLKEN_OFF_Val << SDHC_CCR_INTCLKEN_Pos)
-#define SDHC_CCR_INTCLKEN_ON (SDHC_CCR_INTCLKEN_ON_Val << SDHC_CCR_INTCLKEN_Pos)
-#define SDHC_CCR_INTCLKS_Pos 1 /**< \brief (SDHC_CCR) Internal Clock Stable */
-#define SDHC_CCR_INTCLKS (_U_(0x1) << SDHC_CCR_INTCLKS_Pos)
-#define SDHC_CCR_INTCLKS_NOT_READY_Val _U_(0x0) /**< \brief (SDHC_CCR) Not Ready */
-#define SDHC_CCR_INTCLKS_READY_Val _U_(0x1) /**< \brief (SDHC_CCR) Ready */
-#define SDHC_CCR_INTCLKS_NOT_READY (SDHC_CCR_INTCLKS_NOT_READY_Val << SDHC_CCR_INTCLKS_Pos)
-#define SDHC_CCR_INTCLKS_READY (SDHC_CCR_INTCLKS_READY_Val << SDHC_CCR_INTCLKS_Pos)
-#define SDHC_CCR_SDCLKEN_Pos 2 /**< \brief (SDHC_CCR) SD Clock Enable */
-#define SDHC_CCR_SDCLKEN (_U_(0x1) << SDHC_CCR_SDCLKEN_Pos)
-#define SDHC_CCR_SDCLKEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_CCR) Disable */
-#define SDHC_CCR_SDCLKEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_CCR) Enable */
-#define SDHC_CCR_SDCLKEN_DISABLE (SDHC_CCR_SDCLKEN_DISABLE_Val << SDHC_CCR_SDCLKEN_Pos)
-#define SDHC_CCR_SDCLKEN_ENABLE (SDHC_CCR_SDCLKEN_ENABLE_Val << SDHC_CCR_SDCLKEN_Pos)
-#define SDHC_CCR_CLKGSEL_Pos 5 /**< \brief (SDHC_CCR) Clock Generator Select */
-#define SDHC_CCR_CLKGSEL (_U_(0x1) << SDHC_CCR_CLKGSEL_Pos)
-#define SDHC_CCR_CLKGSEL_DIV_Val _U_(0x0) /**< \brief (SDHC_CCR) Divided Clock Mode */
-#define SDHC_CCR_CLKGSEL_PROG_Val _U_(0x1) /**< \brief (SDHC_CCR) Programmable Clock Mode */
-#define SDHC_CCR_CLKGSEL_DIV (SDHC_CCR_CLKGSEL_DIV_Val << SDHC_CCR_CLKGSEL_Pos)
-#define SDHC_CCR_CLKGSEL_PROG (SDHC_CCR_CLKGSEL_PROG_Val << SDHC_CCR_CLKGSEL_Pos)
-#define SDHC_CCR_USDCLKFSEL_Pos 6 /**< \brief (SDHC_CCR) Upper Bits of SDCLK Frequency Select */
-#define SDHC_CCR_USDCLKFSEL_Msk (_U_(0x3) << SDHC_CCR_USDCLKFSEL_Pos)
-#define SDHC_CCR_USDCLKFSEL(value) (SDHC_CCR_USDCLKFSEL_Msk & ((value) << SDHC_CCR_USDCLKFSEL_Pos))
-#define SDHC_CCR_SDCLKFSEL_Pos 8 /**< \brief (SDHC_CCR) SDCLK Frequency Select */
-#define SDHC_CCR_SDCLKFSEL_Msk (_U_(0xFF) << SDHC_CCR_SDCLKFSEL_Pos)
-#define SDHC_CCR_SDCLKFSEL(value) (SDHC_CCR_SDCLKFSEL_Msk & ((value) << SDHC_CCR_SDCLKFSEL_Pos))
-#define SDHC_CCR_MASK _U_(0xFFE7) /**< \brief (SDHC_CCR) MASK Register */
-
-/* -------- SDHC_TCR : (SDHC Offset: 0x02E) (R/W 8) Timeout Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DTCVAL:4; /*!< bit: 0.. 3 Data Timeout Counter Value */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SDHC_TCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_TCR_OFFSET 0x02E /**< \brief (SDHC_TCR offset) Timeout Control */
-#define SDHC_TCR_RESETVALUE _U_(0x00) /**< \brief (SDHC_TCR reset_value) Timeout Control */
-
-#define SDHC_TCR_DTCVAL_Pos 0 /**< \brief (SDHC_TCR) Data Timeout Counter Value */
-#define SDHC_TCR_DTCVAL_Msk (_U_(0xF) << SDHC_TCR_DTCVAL_Pos)
-#define SDHC_TCR_DTCVAL(value) (SDHC_TCR_DTCVAL_Msk & ((value) << SDHC_TCR_DTCVAL_Pos))
-#define SDHC_TCR_MASK _U_(0x0F) /**< \brief (SDHC_TCR) MASK Register */
-
-/* -------- SDHC_SRR : (SDHC Offset: 0x02F) (R/W 8) Software Reset -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SWRSTALL:1; /*!< bit: 0 Software Reset For All */
- uint8_t SWRSTCMD:1; /*!< bit: 1 Software Reset For CMD Line */
- uint8_t SWRSTDAT:1; /*!< bit: 2 Software Reset For DAT Line */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SDHC_SRR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_SRR_OFFSET 0x02F /**< \brief (SDHC_SRR offset) Software Reset */
-#define SDHC_SRR_RESETVALUE _U_(0x00) /**< \brief (SDHC_SRR reset_value) Software Reset */
-
-#define SDHC_SRR_SWRSTALL_Pos 0 /**< \brief (SDHC_SRR) Software Reset For All */
-#define SDHC_SRR_SWRSTALL (_U_(0x1) << SDHC_SRR_SWRSTALL_Pos)
-#define SDHC_SRR_SWRSTALL_WORK_Val _U_(0x0) /**< \brief (SDHC_SRR) Work */
-#define SDHC_SRR_SWRSTALL_RESET_Val _U_(0x1) /**< \brief (SDHC_SRR) Reset */
-#define SDHC_SRR_SWRSTALL_WORK (SDHC_SRR_SWRSTALL_WORK_Val << SDHC_SRR_SWRSTALL_Pos)
-#define SDHC_SRR_SWRSTALL_RESET (SDHC_SRR_SWRSTALL_RESET_Val << SDHC_SRR_SWRSTALL_Pos)
-#define SDHC_SRR_SWRSTCMD_Pos 1 /**< \brief (SDHC_SRR) Software Reset For CMD Line */
-#define SDHC_SRR_SWRSTCMD (_U_(0x1) << SDHC_SRR_SWRSTCMD_Pos)
-#define SDHC_SRR_SWRSTCMD_WORK_Val _U_(0x0) /**< \brief (SDHC_SRR) Work */
-#define SDHC_SRR_SWRSTCMD_RESET_Val _U_(0x1) /**< \brief (SDHC_SRR) Reset */
-#define SDHC_SRR_SWRSTCMD_WORK (SDHC_SRR_SWRSTCMD_WORK_Val << SDHC_SRR_SWRSTCMD_Pos)
-#define SDHC_SRR_SWRSTCMD_RESET (SDHC_SRR_SWRSTCMD_RESET_Val << SDHC_SRR_SWRSTCMD_Pos)
-#define SDHC_SRR_SWRSTDAT_Pos 2 /**< \brief (SDHC_SRR) Software Reset For DAT Line */
-#define SDHC_SRR_SWRSTDAT (_U_(0x1) << SDHC_SRR_SWRSTDAT_Pos)
-#define SDHC_SRR_SWRSTDAT_WORK_Val _U_(0x0) /**< \brief (SDHC_SRR) Work */
-#define SDHC_SRR_SWRSTDAT_RESET_Val _U_(0x1) /**< \brief (SDHC_SRR) Reset */
-#define SDHC_SRR_SWRSTDAT_WORK (SDHC_SRR_SWRSTDAT_WORK_Val << SDHC_SRR_SWRSTDAT_Pos)
-#define SDHC_SRR_SWRSTDAT_RESET (SDHC_SRR_SWRSTDAT_RESET_Val << SDHC_SRR_SWRSTDAT_Pos)
-#define SDHC_SRR_MASK _U_(0x07) /**< \brief (SDHC_SRR) MASK Register */
-
-/* -------- SDHC_NISTR : (SDHC Offset: 0x030) (R/W 16) Normal Interrupt Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t CMDC:1; /*!< bit: 0 Command Complete */
- uint16_t TRFC:1; /*!< bit: 1 Transfer Complete */
- uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event */
- uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt */
- uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready */
- uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready */
- uint16_t CINS:1; /*!< bit: 6 Card Insertion */
- uint16_t CREM:1; /*!< bit: 7 Card Removal */
- uint16_t CINT:1; /*!< bit: 8 Card Interrupt */
- uint16_t :6; /*!< bit: 9..14 Reserved */
- uint16_t ERRINT:1; /*!< bit: 15 Error Interrupt */
- } bit; /*!< Structure used for bit access */
- struct { // EMMC mode
- uint16_t CMDC:1; /*!< bit: 0 Command Complete */
- uint16_t TRFC:1; /*!< bit: 1 Transfer Complete */
- uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event */
- uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt */
- uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready */
- uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready */
- uint16_t :8; /*!< bit: 6..13 Reserved */
- uint16_t BOOTAR:1; /*!< bit: 14 Boot Acknowledge Received */
- uint16_t ERRINT:1; /*!< bit: 15 Error Interrupt */
- } EMMC; /*!< Structure used for EMMC */
- uint16_t reg; /*!< Type used for register access */
-} SDHC_NISTR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_NISTR_OFFSET 0x030 /**< \brief (SDHC_NISTR offset) Normal Interrupt Status */
-#define SDHC_NISTR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_NISTR reset_value) Normal Interrupt Status */
-
-#define SDHC_NISTR_CMDC_Pos 0 /**< \brief (SDHC_NISTR) Command Complete */
-#define SDHC_NISTR_CMDC (_U_(0x1) << SDHC_NISTR_CMDC_Pos)
-#define SDHC_NISTR_CMDC_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No command complete */
-#define SDHC_NISTR_CMDC_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Command complete */
-#define SDHC_NISTR_CMDC_NO (SDHC_NISTR_CMDC_NO_Val << SDHC_NISTR_CMDC_Pos)
-#define SDHC_NISTR_CMDC_YES (SDHC_NISTR_CMDC_YES_Val << SDHC_NISTR_CMDC_Pos)
-#define SDHC_NISTR_TRFC_Pos 1 /**< \brief (SDHC_NISTR) Transfer Complete */
-#define SDHC_NISTR_TRFC (_U_(0x1) << SDHC_NISTR_TRFC_Pos)
-#define SDHC_NISTR_TRFC_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Not complete */
-#define SDHC_NISTR_TRFC_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Command execution is completed */
-#define SDHC_NISTR_TRFC_NO (SDHC_NISTR_TRFC_NO_Val << SDHC_NISTR_TRFC_Pos)
-#define SDHC_NISTR_TRFC_YES (SDHC_NISTR_TRFC_YES_Val << SDHC_NISTR_TRFC_Pos)
-#define SDHC_NISTR_BLKGE_Pos 2 /**< \brief (SDHC_NISTR) Block Gap Event */
-#define SDHC_NISTR_BLKGE (_U_(0x1) << SDHC_NISTR_BLKGE_Pos)
-#define SDHC_NISTR_BLKGE_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No Block Gap Event */
-#define SDHC_NISTR_BLKGE_STOP_Val _U_(0x1) /**< \brief (SDHC_NISTR) Transaction stopped at block gap */
-#define SDHC_NISTR_BLKGE_NO (SDHC_NISTR_BLKGE_NO_Val << SDHC_NISTR_BLKGE_Pos)
-#define SDHC_NISTR_BLKGE_STOP (SDHC_NISTR_BLKGE_STOP_Val << SDHC_NISTR_BLKGE_Pos)
-#define SDHC_NISTR_DMAINT_Pos 3 /**< \brief (SDHC_NISTR) DMA Interrupt */
-#define SDHC_NISTR_DMAINT (_U_(0x1) << SDHC_NISTR_DMAINT_Pos)
-#define SDHC_NISTR_DMAINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No DMA Interrupt */
-#define SDHC_NISTR_DMAINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) DMA Interrupt is generated */
-#define SDHC_NISTR_DMAINT_NO (SDHC_NISTR_DMAINT_NO_Val << SDHC_NISTR_DMAINT_Pos)
-#define SDHC_NISTR_DMAINT_YES (SDHC_NISTR_DMAINT_YES_Val << SDHC_NISTR_DMAINT_Pos)
-#define SDHC_NISTR_BWRRDY_Pos 4 /**< \brief (SDHC_NISTR) Buffer Write Ready */
-#define SDHC_NISTR_BWRRDY (_U_(0x1) << SDHC_NISTR_BWRRDY_Pos)
-#define SDHC_NISTR_BWRRDY_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Not ready to write buffer */
-#define SDHC_NISTR_BWRRDY_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Ready to write buffer */
-#define SDHC_NISTR_BWRRDY_NO (SDHC_NISTR_BWRRDY_NO_Val << SDHC_NISTR_BWRRDY_Pos)
-#define SDHC_NISTR_BWRRDY_YES (SDHC_NISTR_BWRRDY_YES_Val << SDHC_NISTR_BWRRDY_Pos)
-#define SDHC_NISTR_BRDRDY_Pos 5 /**< \brief (SDHC_NISTR) Buffer Read Ready */
-#define SDHC_NISTR_BRDRDY (_U_(0x1) << SDHC_NISTR_BRDRDY_Pos)
-#define SDHC_NISTR_BRDRDY_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Not ready to read buffer */
-#define SDHC_NISTR_BRDRDY_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Ready to read buffer */
-#define SDHC_NISTR_BRDRDY_NO (SDHC_NISTR_BRDRDY_NO_Val << SDHC_NISTR_BRDRDY_Pos)
-#define SDHC_NISTR_BRDRDY_YES (SDHC_NISTR_BRDRDY_YES_Val << SDHC_NISTR_BRDRDY_Pos)
-#define SDHC_NISTR_CINS_Pos 6 /**< \brief (SDHC_NISTR) Card Insertion */
-#define SDHC_NISTR_CINS (_U_(0x1) << SDHC_NISTR_CINS_Pos)
-#define SDHC_NISTR_CINS_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Card state stable or Debouncing */
-#define SDHC_NISTR_CINS_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Card inserted */
-#define SDHC_NISTR_CINS_NO (SDHC_NISTR_CINS_NO_Val << SDHC_NISTR_CINS_Pos)
-#define SDHC_NISTR_CINS_YES (SDHC_NISTR_CINS_YES_Val << SDHC_NISTR_CINS_Pos)
-#define SDHC_NISTR_CREM_Pos 7 /**< \brief (SDHC_NISTR) Card Removal */
-#define SDHC_NISTR_CREM (_U_(0x1) << SDHC_NISTR_CREM_Pos)
-#define SDHC_NISTR_CREM_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Card state stable or Debouncing */
-#define SDHC_NISTR_CREM_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Card Removed */
-#define SDHC_NISTR_CREM_NO (SDHC_NISTR_CREM_NO_Val << SDHC_NISTR_CREM_Pos)
-#define SDHC_NISTR_CREM_YES (SDHC_NISTR_CREM_YES_Val << SDHC_NISTR_CREM_Pos)
-#define SDHC_NISTR_CINT_Pos 8 /**< \brief (SDHC_NISTR) Card Interrupt */
-#define SDHC_NISTR_CINT (_U_(0x1) << SDHC_NISTR_CINT_Pos)
-#define SDHC_NISTR_CINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No Card Interrupt */
-#define SDHC_NISTR_CINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Generate Card Interrupt */
-#define SDHC_NISTR_CINT_NO (SDHC_NISTR_CINT_NO_Val << SDHC_NISTR_CINT_Pos)
-#define SDHC_NISTR_CINT_YES (SDHC_NISTR_CINT_YES_Val << SDHC_NISTR_CINT_Pos)
-#define SDHC_NISTR_ERRINT_Pos 15 /**< \brief (SDHC_NISTR) Error Interrupt */
-#define SDHC_NISTR_ERRINT (_U_(0x1) << SDHC_NISTR_ERRINT_Pos)
-#define SDHC_NISTR_ERRINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No Error */
-#define SDHC_NISTR_ERRINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Error */
-#define SDHC_NISTR_ERRINT_NO (SDHC_NISTR_ERRINT_NO_Val << SDHC_NISTR_ERRINT_Pos)
-#define SDHC_NISTR_ERRINT_YES (SDHC_NISTR_ERRINT_YES_Val << SDHC_NISTR_ERRINT_Pos)
-#define SDHC_NISTR_MASK _U_(0x81FF) /**< \brief (SDHC_NISTR) MASK Register */
-
-// EMMC mode
-#define SDHC_NISTR_EMMC_CMDC_Pos 0 /**< \brief (SDHC_NISTR_EMMC) Command Complete */
-#define SDHC_NISTR_EMMC_CMDC (_U_(0x1) << SDHC_NISTR_EMMC_CMDC_Pos)
-#define SDHC_NISTR_EMMC_CMDC_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) No command complete */
-#define SDHC_NISTR_EMMC_CMDC_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Command complete */
-#define SDHC_NISTR_EMMC_CMDC_NO (SDHC_NISTR_EMMC_CMDC_NO_Val << SDHC_NISTR_EMMC_CMDC_Pos)
-#define SDHC_NISTR_EMMC_CMDC_YES (SDHC_NISTR_EMMC_CMDC_YES_Val << SDHC_NISTR_EMMC_CMDC_Pos)
-#define SDHC_NISTR_EMMC_TRFC_Pos 1 /**< \brief (SDHC_NISTR_EMMC) Transfer Complete */
-#define SDHC_NISTR_EMMC_TRFC (_U_(0x1) << SDHC_NISTR_EMMC_TRFC_Pos)
-#define SDHC_NISTR_EMMC_TRFC_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) Not complete */
-#define SDHC_NISTR_EMMC_TRFC_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Command execution is completed */
-#define SDHC_NISTR_EMMC_TRFC_NO (SDHC_NISTR_EMMC_TRFC_NO_Val << SDHC_NISTR_EMMC_TRFC_Pos)
-#define SDHC_NISTR_EMMC_TRFC_YES (SDHC_NISTR_EMMC_TRFC_YES_Val << SDHC_NISTR_EMMC_TRFC_Pos)
-#define SDHC_NISTR_EMMC_BLKGE_Pos 2 /**< \brief (SDHC_NISTR_EMMC) Block Gap Event */
-#define SDHC_NISTR_EMMC_BLKGE (_U_(0x1) << SDHC_NISTR_EMMC_BLKGE_Pos)
-#define SDHC_NISTR_EMMC_BLKGE_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) No Block Gap Event */
-#define SDHC_NISTR_EMMC_BLKGE_STOP_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Transaction stopped at block gap */
-#define SDHC_NISTR_EMMC_BLKGE_NO (SDHC_NISTR_EMMC_BLKGE_NO_Val << SDHC_NISTR_EMMC_BLKGE_Pos)
-#define SDHC_NISTR_EMMC_BLKGE_STOP (SDHC_NISTR_EMMC_BLKGE_STOP_Val << SDHC_NISTR_EMMC_BLKGE_Pos)
-#define SDHC_NISTR_EMMC_DMAINT_Pos 3 /**< \brief (SDHC_NISTR_EMMC) DMA Interrupt */
-#define SDHC_NISTR_EMMC_DMAINT (_U_(0x1) << SDHC_NISTR_EMMC_DMAINT_Pos)
-#define SDHC_NISTR_EMMC_DMAINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) No DMA Interrupt */
-#define SDHC_NISTR_EMMC_DMAINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) DMA Interrupt is generated */
-#define SDHC_NISTR_EMMC_DMAINT_NO (SDHC_NISTR_EMMC_DMAINT_NO_Val << SDHC_NISTR_EMMC_DMAINT_Pos)
-#define SDHC_NISTR_EMMC_DMAINT_YES (SDHC_NISTR_EMMC_DMAINT_YES_Val << SDHC_NISTR_EMMC_DMAINT_Pos)
-#define SDHC_NISTR_EMMC_BWRRDY_Pos 4 /**< \brief (SDHC_NISTR_EMMC) Buffer Write Ready */
-#define SDHC_NISTR_EMMC_BWRRDY (_U_(0x1) << SDHC_NISTR_EMMC_BWRRDY_Pos)
-#define SDHC_NISTR_EMMC_BWRRDY_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) Not ready to write buffer */
-#define SDHC_NISTR_EMMC_BWRRDY_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Ready to write buffer */
-#define SDHC_NISTR_EMMC_BWRRDY_NO (SDHC_NISTR_EMMC_BWRRDY_NO_Val << SDHC_NISTR_EMMC_BWRRDY_Pos)
-#define SDHC_NISTR_EMMC_BWRRDY_YES (SDHC_NISTR_EMMC_BWRRDY_YES_Val << SDHC_NISTR_EMMC_BWRRDY_Pos)
-#define SDHC_NISTR_EMMC_BRDRDY_Pos 5 /**< \brief (SDHC_NISTR_EMMC) Buffer Read Ready */
-#define SDHC_NISTR_EMMC_BRDRDY (_U_(0x1) << SDHC_NISTR_EMMC_BRDRDY_Pos)
-#define SDHC_NISTR_EMMC_BRDRDY_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) Not ready to read buffer */
-#define SDHC_NISTR_EMMC_BRDRDY_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Ready to read buffer */
-#define SDHC_NISTR_EMMC_BRDRDY_NO (SDHC_NISTR_EMMC_BRDRDY_NO_Val << SDHC_NISTR_EMMC_BRDRDY_Pos)
-#define SDHC_NISTR_EMMC_BRDRDY_YES (SDHC_NISTR_EMMC_BRDRDY_YES_Val << SDHC_NISTR_EMMC_BRDRDY_Pos)
-#define SDHC_NISTR_EMMC_BOOTAR_Pos 14 /**< \brief (SDHC_NISTR_EMMC) Boot Acknowledge Received */
-#define SDHC_NISTR_EMMC_BOOTAR (_U_(0x1) << SDHC_NISTR_EMMC_BOOTAR_Pos)
-#define SDHC_NISTR_EMMC_ERRINT_Pos 15 /**< \brief (SDHC_NISTR_EMMC) Error Interrupt */
-#define SDHC_NISTR_EMMC_ERRINT (_U_(0x1) << SDHC_NISTR_EMMC_ERRINT_Pos)
-#define SDHC_NISTR_EMMC_ERRINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) No Error */
-#define SDHC_NISTR_EMMC_ERRINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Error */
-#define SDHC_NISTR_EMMC_ERRINT_NO (SDHC_NISTR_EMMC_ERRINT_NO_Val << SDHC_NISTR_EMMC_ERRINT_Pos)
-#define SDHC_NISTR_EMMC_ERRINT_YES (SDHC_NISTR_EMMC_ERRINT_YES_Val << SDHC_NISTR_EMMC_ERRINT_Pos)
-#define SDHC_NISTR_EMMC_MASK _U_(0xC03F) /**< \brief (SDHC_NISTR_EMMC) MASK Register */
-
-/* -------- SDHC_EISTR : (SDHC Offset: 0x032) (R/W 16) Error Interrupt Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error */
- uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error */
- uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error */
- uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error */
- uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error */
- uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error */
- uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error */
- uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error */
- uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error */
- uint16_t ADMA:1; /*!< bit: 9 ADMA Error */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct { // EMMC mode
- uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error */
- uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error */
- uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error */
- uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error */
- uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error */
- uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error */
- uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error */
- uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error */
- uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error */
- uint16_t ADMA:1; /*!< bit: 9 ADMA Error */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t BOOTAE:1; /*!< bit: 12 Boot Acknowledge Error */
- uint16_t :3; /*!< bit: 13..15 Reserved */
- } EMMC; /*!< Structure used for EMMC */
- uint16_t reg; /*!< Type used for register access */
-} SDHC_EISTR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_EISTR_OFFSET 0x032 /**< \brief (SDHC_EISTR offset) Error Interrupt Status */
-#define SDHC_EISTR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_EISTR reset_value) Error Interrupt Status */
-
-#define SDHC_EISTR_CMDTEO_Pos 0 /**< \brief (SDHC_EISTR) Command Timeout Error */
-#define SDHC_EISTR_CMDTEO (_U_(0x1) << SDHC_EISTR_CMDTEO_Pos)
-#define SDHC_EISTR_CMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
-#define SDHC_EISTR_CMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Timeout */
-#define SDHC_EISTR_CMDTEO_NO (SDHC_EISTR_CMDTEO_NO_Val << SDHC_EISTR_CMDTEO_Pos)
-#define SDHC_EISTR_CMDTEO_YES (SDHC_EISTR_CMDTEO_YES_Val << SDHC_EISTR_CMDTEO_Pos)
-#define SDHC_EISTR_CMDCRC_Pos 1 /**< \brief (SDHC_EISTR) Command CRC Error */
-#define SDHC_EISTR_CMDCRC (_U_(0x1) << SDHC_EISTR_CMDCRC_Pos)
-#define SDHC_EISTR_CMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
-#define SDHC_EISTR_CMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) CRC Error Generated */
-#define SDHC_EISTR_CMDCRC_NO (SDHC_EISTR_CMDCRC_NO_Val << SDHC_EISTR_CMDCRC_Pos)
-#define SDHC_EISTR_CMDCRC_YES (SDHC_EISTR_CMDCRC_YES_Val << SDHC_EISTR_CMDCRC_Pos)
-#define SDHC_EISTR_CMDEND_Pos 2 /**< \brief (SDHC_EISTR) Command End Bit Error */
-#define SDHC_EISTR_CMDEND (_U_(0x1) << SDHC_EISTR_CMDEND_Pos)
-#define SDHC_EISTR_CMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No error */
-#define SDHC_EISTR_CMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) End Bit Error Generated */
-#define SDHC_EISTR_CMDEND_NO (SDHC_EISTR_CMDEND_NO_Val << SDHC_EISTR_CMDEND_Pos)
-#define SDHC_EISTR_CMDEND_YES (SDHC_EISTR_CMDEND_YES_Val << SDHC_EISTR_CMDEND_Pos)
-#define SDHC_EISTR_CMDIDX_Pos 3 /**< \brief (SDHC_EISTR) Command Index Error */
-#define SDHC_EISTR_CMDIDX (_U_(0x1) << SDHC_EISTR_CMDIDX_Pos)
-#define SDHC_EISTR_CMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
-#define SDHC_EISTR_CMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */
-#define SDHC_EISTR_CMDIDX_NO (SDHC_EISTR_CMDIDX_NO_Val << SDHC_EISTR_CMDIDX_Pos)
-#define SDHC_EISTR_CMDIDX_YES (SDHC_EISTR_CMDIDX_YES_Val << SDHC_EISTR_CMDIDX_Pos)
-#define SDHC_EISTR_DATTEO_Pos 4 /**< \brief (SDHC_EISTR) Data Timeout Error */
-#define SDHC_EISTR_DATTEO (_U_(0x1) << SDHC_EISTR_DATTEO_Pos)
-#define SDHC_EISTR_DATTEO_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
-#define SDHC_EISTR_DATTEO_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Timeout */
-#define SDHC_EISTR_DATTEO_NO (SDHC_EISTR_DATTEO_NO_Val << SDHC_EISTR_DATTEO_Pos)
-#define SDHC_EISTR_DATTEO_YES (SDHC_EISTR_DATTEO_YES_Val << SDHC_EISTR_DATTEO_Pos)
-#define SDHC_EISTR_DATCRC_Pos 5 /**< \brief (SDHC_EISTR) Data CRC Error */
-#define SDHC_EISTR_DATCRC (_U_(0x1) << SDHC_EISTR_DATCRC_Pos)
-#define SDHC_EISTR_DATCRC_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
-#define SDHC_EISTR_DATCRC_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */
-#define SDHC_EISTR_DATCRC_NO (SDHC_EISTR_DATCRC_NO_Val << SDHC_EISTR_DATCRC_Pos)
-#define SDHC_EISTR_DATCRC_YES (SDHC_EISTR_DATCRC_YES_Val << SDHC_EISTR_DATCRC_Pos)
-#define SDHC_EISTR_DATEND_Pos 6 /**< \brief (SDHC_EISTR) Data End Bit Error */
-#define SDHC_EISTR_DATEND (_U_(0x1) << SDHC_EISTR_DATEND_Pos)
-#define SDHC_EISTR_DATEND_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
-#define SDHC_EISTR_DATEND_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */
-#define SDHC_EISTR_DATEND_NO (SDHC_EISTR_DATEND_NO_Val << SDHC_EISTR_DATEND_Pos)
-#define SDHC_EISTR_DATEND_YES (SDHC_EISTR_DATEND_YES_Val << SDHC_EISTR_DATEND_Pos)
-#define SDHC_EISTR_CURLIM_Pos 7 /**< \brief (SDHC_EISTR) Current Limit Error */
-#define SDHC_EISTR_CURLIM (_U_(0x1) << SDHC_EISTR_CURLIM_Pos)
-#define SDHC_EISTR_CURLIM_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
-#define SDHC_EISTR_CURLIM_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Power Fail */
-#define SDHC_EISTR_CURLIM_NO (SDHC_EISTR_CURLIM_NO_Val << SDHC_EISTR_CURLIM_Pos)
-#define SDHC_EISTR_CURLIM_YES (SDHC_EISTR_CURLIM_YES_Val << SDHC_EISTR_CURLIM_Pos)
-#define SDHC_EISTR_ACMD_Pos 8 /**< \brief (SDHC_EISTR) Auto CMD Error */
-#define SDHC_EISTR_ACMD (_U_(0x1) << SDHC_EISTR_ACMD_Pos)
-#define SDHC_EISTR_ACMD_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
-#define SDHC_EISTR_ACMD_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */
-#define SDHC_EISTR_ACMD_NO (SDHC_EISTR_ACMD_NO_Val << SDHC_EISTR_ACMD_Pos)
-#define SDHC_EISTR_ACMD_YES (SDHC_EISTR_ACMD_YES_Val << SDHC_EISTR_ACMD_Pos)
-#define SDHC_EISTR_ADMA_Pos 9 /**< \brief (SDHC_EISTR) ADMA Error */
-#define SDHC_EISTR_ADMA (_U_(0x1) << SDHC_EISTR_ADMA_Pos)
-#define SDHC_EISTR_ADMA_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
-#define SDHC_EISTR_ADMA_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */
-#define SDHC_EISTR_ADMA_NO (SDHC_EISTR_ADMA_NO_Val << SDHC_EISTR_ADMA_Pos)
-#define SDHC_EISTR_ADMA_YES (SDHC_EISTR_ADMA_YES_Val << SDHC_EISTR_ADMA_Pos)
-#define SDHC_EISTR_MASK _U_(0x03FF) /**< \brief (SDHC_EISTR) MASK Register */
-
-// EMMC mode
-#define SDHC_EISTR_EMMC_CMDTEO_Pos 0 /**< \brief (SDHC_EISTR_EMMC) Command Timeout Error */
-#define SDHC_EISTR_EMMC_CMDTEO (_U_(0x1) << SDHC_EISTR_EMMC_CMDTEO_Pos)
-#define SDHC_EISTR_EMMC_CMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
-#define SDHC_EISTR_EMMC_CMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Timeout */
-#define SDHC_EISTR_EMMC_CMDTEO_NO (SDHC_EISTR_EMMC_CMDTEO_NO_Val << SDHC_EISTR_EMMC_CMDTEO_Pos)
-#define SDHC_EISTR_EMMC_CMDTEO_YES (SDHC_EISTR_EMMC_CMDTEO_YES_Val << SDHC_EISTR_EMMC_CMDTEO_Pos)
-#define SDHC_EISTR_EMMC_CMDCRC_Pos 1 /**< \brief (SDHC_EISTR_EMMC) Command CRC Error */
-#define SDHC_EISTR_EMMC_CMDCRC (_U_(0x1) << SDHC_EISTR_EMMC_CMDCRC_Pos)
-#define SDHC_EISTR_EMMC_CMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
-#define SDHC_EISTR_EMMC_CMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) CRC Error Generated */
-#define SDHC_EISTR_EMMC_CMDCRC_NO (SDHC_EISTR_EMMC_CMDCRC_NO_Val << SDHC_EISTR_EMMC_CMDCRC_Pos)
-#define SDHC_EISTR_EMMC_CMDCRC_YES (SDHC_EISTR_EMMC_CMDCRC_YES_Val << SDHC_EISTR_EMMC_CMDCRC_Pos)
-#define SDHC_EISTR_EMMC_CMDEND_Pos 2 /**< \brief (SDHC_EISTR_EMMC) Command End Bit Error */
-#define SDHC_EISTR_EMMC_CMDEND (_U_(0x1) << SDHC_EISTR_EMMC_CMDEND_Pos)
-#define SDHC_EISTR_EMMC_CMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No error */
-#define SDHC_EISTR_EMMC_CMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) End Bit Error Generated */
-#define SDHC_EISTR_EMMC_CMDEND_NO (SDHC_EISTR_EMMC_CMDEND_NO_Val << SDHC_EISTR_EMMC_CMDEND_Pos)
-#define SDHC_EISTR_EMMC_CMDEND_YES (SDHC_EISTR_EMMC_CMDEND_YES_Val << SDHC_EISTR_EMMC_CMDEND_Pos)
-#define SDHC_EISTR_EMMC_CMDIDX_Pos 3 /**< \brief (SDHC_EISTR_EMMC) Command Index Error */
-#define SDHC_EISTR_EMMC_CMDIDX (_U_(0x1) << SDHC_EISTR_EMMC_CMDIDX_Pos)
-#define SDHC_EISTR_EMMC_CMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
-#define SDHC_EISTR_EMMC_CMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */
-#define SDHC_EISTR_EMMC_CMDIDX_NO (SDHC_EISTR_EMMC_CMDIDX_NO_Val << SDHC_EISTR_EMMC_CMDIDX_Pos)
-#define SDHC_EISTR_EMMC_CMDIDX_YES (SDHC_EISTR_EMMC_CMDIDX_YES_Val << SDHC_EISTR_EMMC_CMDIDX_Pos)
-#define SDHC_EISTR_EMMC_DATTEO_Pos 4 /**< \brief (SDHC_EISTR_EMMC) Data Timeout Error */
-#define SDHC_EISTR_EMMC_DATTEO (_U_(0x1) << SDHC_EISTR_EMMC_DATTEO_Pos)
-#define SDHC_EISTR_EMMC_DATTEO_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
-#define SDHC_EISTR_EMMC_DATTEO_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Timeout */
-#define SDHC_EISTR_EMMC_DATTEO_NO (SDHC_EISTR_EMMC_DATTEO_NO_Val << SDHC_EISTR_EMMC_DATTEO_Pos)
-#define SDHC_EISTR_EMMC_DATTEO_YES (SDHC_EISTR_EMMC_DATTEO_YES_Val << SDHC_EISTR_EMMC_DATTEO_Pos)
-#define SDHC_EISTR_EMMC_DATCRC_Pos 5 /**< \brief (SDHC_EISTR_EMMC) Data CRC Error */
-#define SDHC_EISTR_EMMC_DATCRC (_U_(0x1) << SDHC_EISTR_EMMC_DATCRC_Pos)
-#define SDHC_EISTR_EMMC_DATCRC_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
-#define SDHC_EISTR_EMMC_DATCRC_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */
-#define SDHC_EISTR_EMMC_DATCRC_NO (SDHC_EISTR_EMMC_DATCRC_NO_Val << SDHC_EISTR_EMMC_DATCRC_Pos)
-#define SDHC_EISTR_EMMC_DATCRC_YES (SDHC_EISTR_EMMC_DATCRC_YES_Val << SDHC_EISTR_EMMC_DATCRC_Pos)
-#define SDHC_EISTR_EMMC_DATEND_Pos 6 /**< \brief (SDHC_EISTR_EMMC) Data End Bit Error */
-#define SDHC_EISTR_EMMC_DATEND (_U_(0x1) << SDHC_EISTR_EMMC_DATEND_Pos)
-#define SDHC_EISTR_EMMC_DATEND_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
-#define SDHC_EISTR_EMMC_DATEND_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */
-#define SDHC_EISTR_EMMC_DATEND_NO (SDHC_EISTR_EMMC_DATEND_NO_Val << SDHC_EISTR_EMMC_DATEND_Pos)
-#define SDHC_EISTR_EMMC_DATEND_YES (SDHC_EISTR_EMMC_DATEND_YES_Val << SDHC_EISTR_EMMC_DATEND_Pos)
-#define SDHC_EISTR_EMMC_CURLIM_Pos 7 /**< \brief (SDHC_EISTR_EMMC) Current Limit Error */
-#define SDHC_EISTR_EMMC_CURLIM (_U_(0x1) << SDHC_EISTR_EMMC_CURLIM_Pos)
-#define SDHC_EISTR_EMMC_CURLIM_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
-#define SDHC_EISTR_EMMC_CURLIM_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Power Fail */
-#define SDHC_EISTR_EMMC_CURLIM_NO (SDHC_EISTR_EMMC_CURLIM_NO_Val << SDHC_EISTR_EMMC_CURLIM_Pos)
-#define SDHC_EISTR_EMMC_CURLIM_YES (SDHC_EISTR_EMMC_CURLIM_YES_Val << SDHC_EISTR_EMMC_CURLIM_Pos)
-#define SDHC_EISTR_EMMC_ACMD_Pos 8 /**< \brief (SDHC_EISTR_EMMC) Auto CMD Error */
-#define SDHC_EISTR_EMMC_ACMD (_U_(0x1) << SDHC_EISTR_EMMC_ACMD_Pos)
-#define SDHC_EISTR_EMMC_ACMD_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
-#define SDHC_EISTR_EMMC_ACMD_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */
-#define SDHC_EISTR_EMMC_ACMD_NO (SDHC_EISTR_EMMC_ACMD_NO_Val << SDHC_EISTR_EMMC_ACMD_Pos)
-#define SDHC_EISTR_EMMC_ACMD_YES (SDHC_EISTR_EMMC_ACMD_YES_Val << SDHC_EISTR_EMMC_ACMD_Pos)
-#define SDHC_EISTR_EMMC_ADMA_Pos 9 /**< \brief (SDHC_EISTR_EMMC) ADMA Error */
-#define SDHC_EISTR_EMMC_ADMA (_U_(0x1) << SDHC_EISTR_EMMC_ADMA_Pos)
-#define SDHC_EISTR_EMMC_ADMA_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
-#define SDHC_EISTR_EMMC_ADMA_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */
-#define SDHC_EISTR_EMMC_ADMA_NO (SDHC_EISTR_EMMC_ADMA_NO_Val << SDHC_EISTR_EMMC_ADMA_Pos)
-#define SDHC_EISTR_EMMC_ADMA_YES (SDHC_EISTR_EMMC_ADMA_YES_Val << SDHC_EISTR_EMMC_ADMA_Pos)
-#define SDHC_EISTR_EMMC_BOOTAE_Pos 12 /**< \brief (SDHC_EISTR_EMMC) Boot Acknowledge Error */
-#define SDHC_EISTR_EMMC_BOOTAE (_U_(0x1) << SDHC_EISTR_EMMC_BOOTAE_Pos)
-#define SDHC_EISTR_EMMC_BOOTAE_0_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) FIFO contains at least one byte */
-#define SDHC_EISTR_EMMC_BOOTAE_1_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) FIFO is empty */
-#define SDHC_EISTR_EMMC_BOOTAE_0 (SDHC_EISTR_EMMC_BOOTAE_0_Val << SDHC_EISTR_EMMC_BOOTAE_Pos)
-#define SDHC_EISTR_EMMC_BOOTAE_1 (SDHC_EISTR_EMMC_BOOTAE_1_Val << SDHC_EISTR_EMMC_BOOTAE_Pos)
-#define SDHC_EISTR_EMMC_MASK _U_(0x13FF) /**< \brief (SDHC_EISTR_EMMC) MASK Register */
-
-/* -------- SDHC_NISTER : (SDHC Offset: 0x034) (R/W 16) Normal Interrupt Status Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t CMDC:1; /*!< bit: 0 Command Complete Status Enable */
- uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Status Enable */
- uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Status Enable */
- uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Status Enable */
- uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Status Enable */
- uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Status Enable */
- uint16_t CINS:1; /*!< bit: 6 Card Insertion Status Enable */
- uint16_t CREM:1; /*!< bit: 7 Card Removal Status Enable */
- uint16_t CINT:1; /*!< bit: 8 Card Interrupt Status Enable */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct { // EMMC mode
- uint16_t CMDC:1; /*!< bit: 0 Command Complete Status Enable */
- uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Status Enable */
- uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Status Enable */
- uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Status Enable */
- uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Status Enable */
- uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Status Enable */
- uint16_t :8; /*!< bit: 6..13 Reserved */
- uint16_t BOOTAR:1; /*!< bit: 14 Boot Acknowledge Received Status Enable */
- uint16_t :1; /*!< bit: 15 Reserved */
- } EMMC; /*!< Structure used for EMMC */
- uint16_t reg; /*!< Type used for register access */
-} SDHC_NISTER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_NISTER_OFFSET 0x034 /**< \brief (SDHC_NISTER offset) Normal Interrupt Status Enable */
-#define SDHC_NISTER_RESETVALUE _U_(0x0000) /**< \brief (SDHC_NISTER reset_value) Normal Interrupt Status Enable */
-
-#define SDHC_NISTER_CMDC_Pos 0 /**< \brief (SDHC_NISTER) Command Complete Status Enable */
-#define SDHC_NISTER_CMDC (_U_(0x1) << SDHC_NISTER_CMDC_Pos)
-#define SDHC_NISTER_CMDC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
-#define SDHC_NISTER_CMDC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
-#define SDHC_NISTER_CMDC_MASKED (SDHC_NISTER_CMDC_MASKED_Val << SDHC_NISTER_CMDC_Pos)
-#define SDHC_NISTER_CMDC_ENABLED (SDHC_NISTER_CMDC_ENABLED_Val << SDHC_NISTER_CMDC_Pos)
-#define SDHC_NISTER_TRFC_Pos 1 /**< \brief (SDHC_NISTER) Transfer Complete Status Enable */
-#define SDHC_NISTER_TRFC (_U_(0x1) << SDHC_NISTER_TRFC_Pos)
-#define SDHC_NISTER_TRFC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
-#define SDHC_NISTER_TRFC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
-#define SDHC_NISTER_TRFC_MASKED (SDHC_NISTER_TRFC_MASKED_Val << SDHC_NISTER_TRFC_Pos)
-#define SDHC_NISTER_TRFC_ENABLED (SDHC_NISTER_TRFC_ENABLED_Val << SDHC_NISTER_TRFC_Pos)
-#define SDHC_NISTER_BLKGE_Pos 2 /**< \brief (SDHC_NISTER) Block Gap Event Status Enable */
-#define SDHC_NISTER_BLKGE (_U_(0x1) << SDHC_NISTER_BLKGE_Pos)
-#define SDHC_NISTER_BLKGE_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
-#define SDHC_NISTER_BLKGE_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
-#define SDHC_NISTER_BLKGE_MASKED (SDHC_NISTER_BLKGE_MASKED_Val << SDHC_NISTER_BLKGE_Pos)
-#define SDHC_NISTER_BLKGE_ENABLED (SDHC_NISTER_BLKGE_ENABLED_Val << SDHC_NISTER_BLKGE_Pos)
-#define SDHC_NISTER_DMAINT_Pos 3 /**< \brief (SDHC_NISTER) DMA Interrupt Status Enable */
-#define SDHC_NISTER_DMAINT (_U_(0x1) << SDHC_NISTER_DMAINT_Pos)
-#define SDHC_NISTER_DMAINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
-#define SDHC_NISTER_DMAINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
-#define SDHC_NISTER_DMAINT_MASKED (SDHC_NISTER_DMAINT_MASKED_Val << SDHC_NISTER_DMAINT_Pos)
-#define SDHC_NISTER_DMAINT_ENABLED (SDHC_NISTER_DMAINT_ENABLED_Val << SDHC_NISTER_DMAINT_Pos)
-#define SDHC_NISTER_BWRRDY_Pos 4 /**< \brief (SDHC_NISTER) Buffer Write Ready Status Enable */
-#define SDHC_NISTER_BWRRDY (_U_(0x1) << SDHC_NISTER_BWRRDY_Pos)
-#define SDHC_NISTER_BWRRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
-#define SDHC_NISTER_BWRRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
-#define SDHC_NISTER_BWRRDY_MASKED (SDHC_NISTER_BWRRDY_MASKED_Val << SDHC_NISTER_BWRRDY_Pos)
-#define SDHC_NISTER_BWRRDY_ENABLED (SDHC_NISTER_BWRRDY_ENABLED_Val << SDHC_NISTER_BWRRDY_Pos)
-#define SDHC_NISTER_BRDRDY_Pos 5 /**< \brief (SDHC_NISTER) Buffer Read Ready Status Enable */
-#define SDHC_NISTER_BRDRDY (_U_(0x1) << SDHC_NISTER_BRDRDY_Pos)
-#define SDHC_NISTER_BRDRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
-#define SDHC_NISTER_BRDRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
-#define SDHC_NISTER_BRDRDY_MASKED (SDHC_NISTER_BRDRDY_MASKED_Val << SDHC_NISTER_BRDRDY_Pos)
-#define SDHC_NISTER_BRDRDY_ENABLED (SDHC_NISTER_BRDRDY_ENABLED_Val << SDHC_NISTER_BRDRDY_Pos)
-#define SDHC_NISTER_CINS_Pos 6 /**< \brief (SDHC_NISTER) Card Insertion Status Enable */
-#define SDHC_NISTER_CINS (_U_(0x1) << SDHC_NISTER_CINS_Pos)
-#define SDHC_NISTER_CINS_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
-#define SDHC_NISTER_CINS_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
-#define SDHC_NISTER_CINS_MASKED (SDHC_NISTER_CINS_MASKED_Val << SDHC_NISTER_CINS_Pos)
-#define SDHC_NISTER_CINS_ENABLED (SDHC_NISTER_CINS_ENABLED_Val << SDHC_NISTER_CINS_Pos)
-#define SDHC_NISTER_CREM_Pos 7 /**< \brief (SDHC_NISTER) Card Removal Status Enable */
-#define SDHC_NISTER_CREM (_U_(0x1) << SDHC_NISTER_CREM_Pos)
-#define SDHC_NISTER_CREM_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
-#define SDHC_NISTER_CREM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
-#define SDHC_NISTER_CREM_MASKED (SDHC_NISTER_CREM_MASKED_Val << SDHC_NISTER_CREM_Pos)
-#define SDHC_NISTER_CREM_ENABLED (SDHC_NISTER_CREM_ENABLED_Val << SDHC_NISTER_CREM_Pos)
-#define SDHC_NISTER_CINT_Pos 8 /**< \brief (SDHC_NISTER) Card Interrupt Status Enable */
-#define SDHC_NISTER_CINT (_U_(0x1) << SDHC_NISTER_CINT_Pos)
-#define SDHC_NISTER_CINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
-#define SDHC_NISTER_CINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
-#define SDHC_NISTER_CINT_MASKED (SDHC_NISTER_CINT_MASKED_Val << SDHC_NISTER_CINT_Pos)
-#define SDHC_NISTER_CINT_ENABLED (SDHC_NISTER_CINT_ENABLED_Val << SDHC_NISTER_CINT_Pos)
-#define SDHC_NISTER_MASK _U_(0x01FF) /**< \brief (SDHC_NISTER) MASK Register */
-
-// EMMC mode
-#define SDHC_NISTER_EMMC_CMDC_Pos 0 /**< \brief (SDHC_NISTER_EMMC) Command Complete Status Enable */
-#define SDHC_NISTER_EMMC_CMDC (_U_(0x1) << SDHC_NISTER_EMMC_CMDC_Pos)
-#define SDHC_NISTER_EMMC_CMDC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */
-#define SDHC_NISTER_EMMC_CMDC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */
-#define SDHC_NISTER_EMMC_CMDC_MASKED (SDHC_NISTER_EMMC_CMDC_MASKED_Val << SDHC_NISTER_EMMC_CMDC_Pos)
-#define SDHC_NISTER_EMMC_CMDC_ENABLED (SDHC_NISTER_EMMC_CMDC_ENABLED_Val << SDHC_NISTER_EMMC_CMDC_Pos)
-#define SDHC_NISTER_EMMC_TRFC_Pos 1 /**< \brief (SDHC_NISTER_EMMC) Transfer Complete Status Enable */
-#define SDHC_NISTER_EMMC_TRFC (_U_(0x1) << SDHC_NISTER_EMMC_TRFC_Pos)
-#define SDHC_NISTER_EMMC_TRFC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */
-#define SDHC_NISTER_EMMC_TRFC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */
-#define SDHC_NISTER_EMMC_TRFC_MASKED (SDHC_NISTER_EMMC_TRFC_MASKED_Val << SDHC_NISTER_EMMC_TRFC_Pos)
-#define SDHC_NISTER_EMMC_TRFC_ENABLED (SDHC_NISTER_EMMC_TRFC_ENABLED_Val << SDHC_NISTER_EMMC_TRFC_Pos)
-#define SDHC_NISTER_EMMC_BLKGE_Pos 2 /**< \brief (SDHC_NISTER_EMMC) Block Gap Event Status Enable */
-#define SDHC_NISTER_EMMC_BLKGE (_U_(0x1) << SDHC_NISTER_EMMC_BLKGE_Pos)
-#define SDHC_NISTER_EMMC_BLKGE_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */
-#define SDHC_NISTER_EMMC_BLKGE_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */
-#define SDHC_NISTER_EMMC_BLKGE_MASKED (SDHC_NISTER_EMMC_BLKGE_MASKED_Val << SDHC_NISTER_EMMC_BLKGE_Pos)
-#define SDHC_NISTER_EMMC_BLKGE_ENABLED (SDHC_NISTER_EMMC_BLKGE_ENABLED_Val << SDHC_NISTER_EMMC_BLKGE_Pos)
-#define SDHC_NISTER_EMMC_DMAINT_Pos 3 /**< \brief (SDHC_NISTER_EMMC) DMA Interrupt Status Enable */
-#define SDHC_NISTER_EMMC_DMAINT (_U_(0x1) << SDHC_NISTER_EMMC_DMAINT_Pos)
-#define SDHC_NISTER_EMMC_DMAINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */
-#define SDHC_NISTER_EMMC_DMAINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */
-#define SDHC_NISTER_EMMC_DMAINT_MASKED (SDHC_NISTER_EMMC_DMAINT_MASKED_Val << SDHC_NISTER_EMMC_DMAINT_Pos)
-#define SDHC_NISTER_EMMC_DMAINT_ENABLED (SDHC_NISTER_EMMC_DMAINT_ENABLED_Val << SDHC_NISTER_EMMC_DMAINT_Pos)
-#define SDHC_NISTER_EMMC_BWRRDY_Pos 4 /**< \brief (SDHC_NISTER_EMMC) Buffer Write Ready Status Enable */
-#define SDHC_NISTER_EMMC_BWRRDY (_U_(0x1) << SDHC_NISTER_EMMC_BWRRDY_Pos)
-#define SDHC_NISTER_EMMC_BWRRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */
-#define SDHC_NISTER_EMMC_BWRRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */
-#define SDHC_NISTER_EMMC_BWRRDY_MASKED (SDHC_NISTER_EMMC_BWRRDY_MASKED_Val << SDHC_NISTER_EMMC_BWRRDY_Pos)
-#define SDHC_NISTER_EMMC_BWRRDY_ENABLED (SDHC_NISTER_EMMC_BWRRDY_ENABLED_Val << SDHC_NISTER_EMMC_BWRRDY_Pos)
-#define SDHC_NISTER_EMMC_BRDRDY_Pos 5 /**< \brief (SDHC_NISTER_EMMC) Buffer Read Ready Status Enable */
-#define SDHC_NISTER_EMMC_BRDRDY (_U_(0x1) << SDHC_NISTER_EMMC_BRDRDY_Pos)
-#define SDHC_NISTER_EMMC_BRDRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */
-#define SDHC_NISTER_EMMC_BRDRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */
-#define SDHC_NISTER_EMMC_BRDRDY_MASKED (SDHC_NISTER_EMMC_BRDRDY_MASKED_Val << SDHC_NISTER_EMMC_BRDRDY_Pos)
-#define SDHC_NISTER_EMMC_BRDRDY_ENABLED (SDHC_NISTER_EMMC_BRDRDY_ENABLED_Val << SDHC_NISTER_EMMC_BRDRDY_Pos)
-#define SDHC_NISTER_EMMC_BOOTAR_Pos 14 /**< \brief (SDHC_NISTER_EMMC) Boot Acknowledge Received Status Enable */
-#define SDHC_NISTER_EMMC_BOOTAR (_U_(0x1) << SDHC_NISTER_EMMC_BOOTAR_Pos)
-#define SDHC_NISTER_EMMC_MASK _U_(0x403F) /**< \brief (SDHC_NISTER_EMMC) MASK Register */
-
-/* -------- SDHC_EISTER : (SDHC Offset: 0x036) (R/W 16) Error Interrupt Status Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Status Enable */
- uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Status Enable */
- uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Status Enable */
- uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Status Enable */
- uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Status Enable */
- uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Status Enable */
- uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Status Enable */
- uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Status Enable */
- uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Status Enable */
- uint16_t ADMA:1; /*!< bit: 9 ADMA Error Status Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct { // EMMC mode
- uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Status Enable */
- uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Status Enable */
- uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Status Enable */
- uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Status Enable */
- uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Status Enable */
- uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Status Enable */
- uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Status Enable */
- uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Status Enable */
- uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Status Enable */
- uint16_t ADMA:1; /*!< bit: 9 ADMA Error Status Enable */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t BOOTAE:1; /*!< bit: 12 Boot Acknowledge Error Status Enable */
- uint16_t :3; /*!< bit: 13..15 Reserved */
- } EMMC; /*!< Structure used for EMMC */
- uint16_t reg; /*!< Type used for register access */
-} SDHC_EISTER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_EISTER_OFFSET 0x036 /**< \brief (SDHC_EISTER offset) Error Interrupt Status Enable */
-#define SDHC_EISTER_RESETVALUE _U_(0x0000) /**< \brief (SDHC_EISTER reset_value) Error Interrupt Status Enable */
-
-#define SDHC_EISTER_CMDTEO_Pos 0 /**< \brief (SDHC_EISTER) Command Timeout Error Status Enable */
-#define SDHC_EISTER_CMDTEO (_U_(0x1) << SDHC_EISTER_CMDTEO_Pos)
-#define SDHC_EISTER_CMDTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
-#define SDHC_EISTER_CMDTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_CMDTEO_MASKED (SDHC_EISTER_CMDTEO_MASKED_Val << SDHC_EISTER_CMDTEO_Pos)
-#define SDHC_EISTER_CMDTEO_ENABLED (SDHC_EISTER_CMDTEO_ENABLED_Val << SDHC_EISTER_CMDTEO_Pos)
-#define SDHC_EISTER_CMDCRC_Pos 1 /**< \brief (SDHC_EISTER) Command CRC Error Status Enable */
-#define SDHC_EISTER_CMDCRC (_U_(0x1) << SDHC_EISTER_CMDCRC_Pos)
-#define SDHC_EISTER_CMDCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
-#define SDHC_EISTER_CMDCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_CMDCRC_MASKED (SDHC_EISTER_CMDCRC_MASKED_Val << SDHC_EISTER_CMDCRC_Pos)
-#define SDHC_EISTER_CMDCRC_ENABLED (SDHC_EISTER_CMDCRC_ENABLED_Val << SDHC_EISTER_CMDCRC_Pos)
-#define SDHC_EISTER_CMDEND_Pos 2 /**< \brief (SDHC_EISTER) Command End Bit Error Status Enable */
-#define SDHC_EISTER_CMDEND (_U_(0x1) << SDHC_EISTER_CMDEND_Pos)
-#define SDHC_EISTER_CMDEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
-#define SDHC_EISTER_CMDEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_CMDEND_MASKED (SDHC_EISTER_CMDEND_MASKED_Val << SDHC_EISTER_CMDEND_Pos)
-#define SDHC_EISTER_CMDEND_ENABLED (SDHC_EISTER_CMDEND_ENABLED_Val << SDHC_EISTER_CMDEND_Pos)
-#define SDHC_EISTER_CMDIDX_Pos 3 /**< \brief (SDHC_EISTER) Command Index Error Status Enable */
-#define SDHC_EISTER_CMDIDX (_U_(0x1) << SDHC_EISTER_CMDIDX_Pos)
-#define SDHC_EISTER_CMDIDX_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
-#define SDHC_EISTER_CMDIDX_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_CMDIDX_MASKED (SDHC_EISTER_CMDIDX_MASKED_Val << SDHC_EISTER_CMDIDX_Pos)
-#define SDHC_EISTER_CMDIDX_ENABLED (SDHC_EISTER_CMDIDX_ENABLED_Val << SDHC_EISTER_CMDIDX_Pos)
-#define SDHC_EISTER_DATTEO_Pos 4 /**< \brief (SDHC_EISTER) Data Timeout Error Status Enable */
-#define SDHC_EISTER_DATTEO (_U_(0x1) << SDHC_EISTER_DATTEO_Pos)
-#define SDHC_EISTER_DATTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
-#define SDHC_EISTER_DATTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_DATTEO_MASKED (SDHC_EISTER_DATTEO_MASKED_Val << SDHC_EISTER_DATTEO_Pos)
-#define SDHC_EISTER_DATTEO_ENABLED (SDHC_EISTER_DATTEO_ENABLED_Val << SDHC_EISTER_DATTEO_Pos)
-#define SDHC_EISTER_DATCRC_Pos 5 /**< \brief (SDHC_EISTER) Data CRC Error Status Enable */
-#define SDHC_EISTER_DATCRC (_U_(0x1) << SDHC_EISTER_DATCRC_Pos)
-#define SDHC_EISTER_DATCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
-#define SDHC_EISTER_DATCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_DATCRC_MASKED (SDHC_EISTER_DATCRC_MASKED_Val << SDHC_EISTER_DATCRC_Pos)
-#define SDHC_EISTER_DATCRC_ENABLED (SDHC_EISTER_DATCRC_ENABLED_Val << SDHC_EISTER_DATCRC_Pos)
-#define SDHC_EISTER_DATEND_Pos 6 /**< \brief (SDHC_EISTER) Data End Bit Error Status Enable */
-#define SDHC_EISTER_DATEND (_U_(0x1) << SDHC_EISTER_DATEND_Pos)
-#define SDHC_EISTER_DATEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
-#define SDHC_EISTER_DATEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_DATEND_MASKED (SDHC_EISTER_DATEND_MASKED_Val << SDHC_EISTER_DATEND_Pos)
-#define SDHC_EISTER_DATEND_ENABLED (SDHC_EISTER_DATEND_ENABLED_Val << SDHC_EISTER_DATEND_Pos)
-#define SDHC_EISTER_CURLIM_Pos 7 /**< \brief (SDHC_EISTER) Current Limit Error Status Enable */
-#define SDHC_EISTER_CURLIM (_U_(0x1) << SDHC_EISTER_CURLIM_Pos)
-#define SDHC_EISTER_CURLIM_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
-#define SDHC_EISTER_CURLIM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_CURLIM_MASKED (SDHC_EISTER_CURLIM_MASKED_Val << SDHC_EISTER_CURLIM_Pos)
-#define SDHC_EISTER_CURLIM_ENABLED (SDHC_EISTER_CURLIM_ENABLED_Val << SDHC_EISTER_CURLIM_Pos)
-#define SDHC_EISTER_ACMD_Pos 8 /**< \brief (SDHC_EISTER) Auto CMD Error Status Enable */
-#define SDHC_EISTER_ACMD (_U_(0x1) << SDHC_EISTER_ACMD_Pos)
-#define SDHC_EISTER_ACMD_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
-#define SDHC_EISTER_ACMD_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_ACMD_MASKED (SDHC_EISTER_ACMD_MASKED_Val << SDHC_EISTER_ACMD_Pos)
-#define SDHC_EISTER_ACMD_ENABLED (SDHC_EISTER_ACMD_ENABLED_Val << SDHC_EISTER_ACMD_Pos)
-#define SDHC_EISTER_ADMA_Pos 9 /**< \brief (SDHC_EISTER) ADMA Error Status Enable */
-#define SDHC_EISTER_ADMA (_U_(0x1) << SDHC_EISTER_ADMA_Pos)
-#define SDHC_EISTER_ADMA_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
-#define SDHC_EISTER_ADMA_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_ADMA_MASKED (SDHC_EISTER_ADMA_MASKED_Val << SDHC_EISTER_ADMA_Pos)
-#define SDHC_EISTER_ADMA_ENABLED (SDHC_EISTER_ADMA_ENABLED_Val << SDHC_EISTER_ADMA_Pos)
-#define SDHC_EISTER_MASK _U_(0x03FF) /**< \brief (SDHC_EISTER) MASK Register */
-
-// EMMC mode
-#define SDHC_EISTER_EMMC_CMDTEO_Pos 0 /**< \brief (SDHC_EISTER_EMMC) Command Timeout Error Status Enable */
-#define SDHC_EISTER_EMMC_CMDTEO (_U_(0x1) << SDHC_EISTER_EMMC_CMDTEO_Pos)
-#define SDHC_EISTER_EMMC_CMDTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define SDHC_EISTER_EMMC_CMDTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_CMDTEO_MASKED (SDHC_EISTER_EMMC_CMDTEO_MASKED_Val << SDHC_EISTER_EMMC_CMDTEO_Pos)
-#define SDHC_EISTER_EMMC_CMDTEO_ENABLED (SDHC_EISTER_EMMC_CMDTEO_ENABLED_Val << SDHC_EISTER_EMMC_CMDTEO_Pos)
-#define SDHC_EISTER_EMMC_CMDCRC_Pos 1 /**< \brief (SDHC_EISTER_EMMC) Command CRC Error Status Enable */
-#define SDHC_EISTER_EMMC_CMDCRC (_U_(0x1) << SDHC_EISTER_EMMC_CMDCRC_Pos)
-#define SDHC_EISTER_EMMC_CMDCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define SDHC_EISTER_EMMC_CMDCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_CMDCRC_MASKED (SDHC_EISTER_EMMC_CMDCRC_MASKED_Val << SDHC_EISTER_EMMC_CMDCRC_Pos)
-#define SDHC_EISTER_EMMC_CMDCRC_ENABLED (SDHC_EISTER_EMMC_CMDCRC_ENABLED_Val << SDHC_EISTER_EMMC_CMDCRC_Pos)
-#define SDHC_EISTER_EMMC_CMDEND_Pos 2 /**< \brief (SDHC_EISTER_EMMC) Command End Bit Error Status Enable */
-#define SDHC_EISTER_EMMC_CMDEND (_U_(0x1) << SDHC_EISTER_EMMC_CMDEND_Pos)
-#define SDHC_EISTER_EMMC_CMDEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define SDHC_EISTER_EMMC_CMDEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_CMDEND_MASKED (SDHC_EISTER_EMMC_CMDEND_MASKED_Val << SDHC_EISTER_EMMC_CMDEND_Pos)
-#define SDHC_EISTER_EMMC_CMDEND_ENABLED (SDHC_EISTER_EMMC_CMDEND_ENABLED_Val << SDHC_EISTER_EMMC_CMDEND_Pos)
-#define SDHC_EISTER_EMMC_CMDIDX_Pos 3 /**< \brief (SDHC_EISTER_EMMC) Command Index Error Status Enable */
-#define SDHC_EISTER_EMMC_CMDIDX (_U_(0x1) << SDHC_EISTER_EMMC_CMDIDX_Pos)
-#define SDHC_EISTER_EMMC_CMDIDX_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define SDHC_EISTER_EMMC_CMDIDX_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_CMDIDX_MASKED (SDHC_EISTER_EMMC_CMDIDX_MASKED_Val << SDHC_EISTER_EMMC_CMDIDX_Pos)
-#define SDHC_EISTER_EMMC_CMDIDX_ENABLED (SDHC_EISTER_EMMC_CMDIDX_ENABLED_Val << SDHC_EISTER_EMMC_CMDIDX_Pos)
-#define SDHC_EISTER_EMMC_DATTEO_Pos 4 /**< \brief (SDHC_EISTER_EMMC) Data Timeout Error Status Enable */
-#define SDHC_EISTER_EMMC_DATTEO (_U_(0x1) << SDHC_EISTER_EMMC_DATTEO_Pos)
-#define SDHC_EISTER_EMMC_DATTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define SDHC_EISTER_EMMC_DATTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_DATTEO_MASKED (SDHC_EISTER_EMMC_DATTEO_MASKED_Val << SDHC_EISTER_EMMC_DATTEO_Pos)
-#define SDHC_EISTER_EMMC_DATTEO_ENABLED (SDHC_EISTER_EMMC_DATTEO_ENABLED_Val << SDHC_EISTER_EMMC_DATTEO_Pos)
-#define SDHC_EISTER_EMMC_DATCRC_Pos 5 /**< \brief (SDHC_EISTER_EMMC) Data CRC Error Status Enable */
-#define SDHC_EISTER_EMMC_DATCRC (_U_(0x1) << SDHC_EISTER_EMMC_DATCRC_Pos)
-#define SDHC_EISTER_EMMC_DATCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define SDHC_EISTER_EMMC_DATCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_DATCRC_MASKED (SDHC_EISTER_EMMC_DATCRC_MASKED_Val << SDHC_EISTER_EMMC_DATCRC_Pos)
-#define SDHC_EISTER_EMMC_DATCRC_ENABLED (SDHC_EISTER_EMMC_DATCRC_ENABLED_Val << SDHC_EISTER_EMMC_DATCRC_Pos)
-#define SDHC_EISTER_EMMC_DATEND_Pos 6 /**< \brief (SDHC_EISTER_EMMC) Data End Bit Error Status Enable */
-#define SDHC_EISTER_EMMC_DATEND (_U_(0x1) << SDHC_EISTER_EMMC_DATEND_Pos)
-#define SDHC_EISTER_EMMC_DATEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define SDHC_EISTER_EMMC_DATEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_DATEND_MASKED (SDHC_EISTER_EMMC_DATEND_MASKED_Val << SDHC_EISTER_EMMC_DATEND_Pos)
-#define SDHC_EISTER_EMMC_DATEND_ENABLED (SDHC_EISTER_EMMC_DATEND_ENABLED_Val << SDHC_EISTER_EMMC_DATEND_Pos)
-#define SDHC_EISTER_EMMC_CURLIM_Pos 7 /**< \brief (SDHC_EISTER_EMMC) Current Limit Error Status Enable */
-#define SDHC_EISTER_EMMC_CURLIM (_U_(0x1) << SDHC_EISTER_EMMC_CURLIM_Pos)
-#define SDHC_EISTER_EMMC_CURLIM_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define SDHC_EISTER_EMMC_CURLIM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_CURLIM_MASKED (SDHC_EISTER_EMMC_CURLIM_MASKED_Val << SDHC_EISTER_EMMC_CURLIM_Pos)
-#define SDHC_EISTER_EMMC_CURLIM_ENABLED (SDHC_EISTER_EMMC_CURLIM_ENABLED_Val << SDHC_EISTER_EMMC_CURLIM_Pos)
-#define SDHC_EISTER_EMMC_ACMD_Pos 8 /**< \brief (SDHC_EISTER_EMMC) Auto CMD Error Status Enable */
-#define SDHC_EISTER_EMMC_ACMD (_U_(0x1) << SDHC_EISTER_EMMC_ACMD_Pos)
-#define SDHC_EISTER_EMMC_ACMD_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define SDHC_EISTER_EMMC_ACMD_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_ACMD_MASKED (SDHC_EISTER_EMMC_ACMD_MASKED_Val << SDHC_EISTER_EMMC_ACMD_Pos)
-#define SDHC_EISTER_EMMC_ACMD_ENABLED (SDHC_EISTER_EMMC_ACMD_ENABLED_Val << SDHC_EISTER_EMMC_ACMD_Pos)
-#define SDHC_EISTER_EMMC_ADMA_Pos 9 /**< \brief (SDHC_EISTER_EMMC) ADMA Error Status Enable */
-#define SDHC_EISTER_EMMC_ADMA (_U_(0x1) << SDHC_EISTER_EMMC_ADMA_Pos)
-#define SDHC_EISTER_EMMC_ADMA_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define SDHC_EISTER_EMMC_ADMA_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_ADMA_MASKED (SDHC_EISTER_EMMC_ADMA_MASKED_Val << SDHC_EISTER_EMMC_ADMA_Pos)
-#define SDHC_EISTER_EMMC_ADMA_ENABLED (SDHC_EISTER_EMMC_ADMA_ENABLED_Val << SDHC_EISTER_EMMC_ADMA_Pos)
-#define SDHC_EISTER_EMMC_BOOTAE_Pos 12 /**< \brief (SDHC_EISTER_EMMC) Boot Acknowledge Error Status Enable */
-#define SDHC_EISTER_EMMC_BOOTAE (_U_(0x1) << SDHC_EISTER_EMMC_BOOTAE_Pos)
-#define SDHC_EISTER_EMMC_MASK _U_(0x13FF) /**< \brief (SDHC_EISTER_EMMC) MASK Register */
-
-/* -------- SDHC_NISIER : (SDHC Offset: 0x038) (R/W 16) Normal Interrupt Signal Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t CMDC:1; /*!< bit: 0 Command Complete Signal Enable */
- uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Signal Enable */
- uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Signal Enable */
- uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Signal Enable */
- uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Signal Enable */
- uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Signal Enable */
- uint16_t CINS:1; /*!< bit: 6 Card Insertion Signal Enable */
- uint16_t CREM:1; /*!< bit: 7 Card Removal Signal Enable */
- uint16_t CINT:1; /*!< bit: 8 Card Interrupt Signal Enable */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct { // EMMC mode
- uint16_t CMDC:1; /*!< bit: 0 Command Complete Signal Enable */
- uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Signal Enable */
- uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Signal Enable */
- uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Signal Enable */
- uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Signal Enable */
- uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Signal Enable */
- uint16_t :8; /*!< bit: 6..13 Reserved */
- uint16_t BOOTAR:1; /*!< bit: 14 Boot Acknowledge Received Signal Enable */
- uint16_t :1; /*!< bit: 15 Reserved */
- } EMMC; /*!< Structure used for EMMC */
- uint16_t reg; /*!< Type used for register access */
-} SDHC_NISIER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_NISIER_OFFSET 0x038 /**< \brief (SDHC_NISIER offset) Normal Interrupt Signal Enable */
-#define SDHC_NISIER_RESETVALUE _U_(0x0000) /**< \brief (SDHC_NISIER reset_value) Normal Interrupt Signal Enable */
-
-#define SDHC_NISIER_CMDC_Pos 0 /**< \brief (SDHC_NISIER) Command Complete Signal Enable */
-#define SDHC_NISIER_CMDC (_U_(0x1) << SDHC_NISIER_CMDC_Pos)
-#define SDHC_NISIER_CMDC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
-#define SDHC_NISIER_CMDC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
-#define SDHC_NISIER_CMDC_MASKED (SDHC_NISIER_CMDC_MASKED_Val << SDHC_NISIER_CMDC_Pos)
-#define SDHC_NISIER_CMDC_ENABLED (SDHC_NISIER_CMDC_ENABLED_Val << SDHC_NISIER_CMDC_Pos)
-#define SDHC_NISIER_TRFC_Pos 1 /**< \brief (SDHC_NISIER) Transfer Complete Signal Enable */
-#define SDHC_NISIER_TRFC (_U_(0x1) << SDHC_NISIER_TRFC_Pos)
-#define SDHC_NISIER_TRFC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
-#define SDHC_NISIER_TRFC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
-#define SDHC_NISIER_TRFC_MASKED (SDHC_NISIER_TRFC_MASKED_Val << SDHC_NISIER_TRFC_Pos)
-#define SDHC_NISIER_TRFC_ENABLED (SDHC_NISIER_TRFC_ENABLED_Val << SDHC_NISIER_TRFC_Pos)
-#define SDHC_NISIER_BLKGE_Pos 2 /**< \brief (SDHC_NISIER) Block Gap Event Signal Enable */
-#define SDHC_NISIER_BLKGE (_U_(0x1) << SDHC_NISIER_BLKGE_Pos)
-#define SDHC_NISIER_BLKGE_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
-#define SDHC_NISIER_BLKGE_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
-#define SDHC_NISIER_BLKGE_MASKED (SDHC_NISIER_BLKGE_MASKED_Val << SDHC_NISIER_BLKGE_Pos)
-#define SDHC_NISIER_BLKGE_ENABLED (SDHC_NISIER_BLKGE_ENABLED_Val << SDHC_NISIER_BLKGE_Pos)
-#define SDHC_NISIER_DMAINT_Pos 3 /**< \brief (SDHC_NISIER) DMA Interrupt Signal Enable */
-#define SDHC_NISIER_DMAINT (_U_(0x1) << SDHC_NISIER_DMAINT_Pos)
-#define SDHC_NISIER_DMAINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
-#define SDHC_NISIER_DMAINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
-#define SDHC_NISIER_DMAINT_MASKED (SDHC_NISIER_DMAINT_MASKED_Val << SDHC_NISIER_DMAINT_Pos)
-#define SDHC_NISIER_DMAINT_ENABLED (SDHC_NISIER_DMAINT_ENABLED_Val << SDHC_NISIER_DMAINT_Pos)
-#define SDHC_NISIER_BWRRDY_Pos 4 /**< \brief (SDHC_NISIER) Buffer Write Ready Signal Enable */
-#define SDHC_NISIER_BWRRDY (_U_(0x1) << SDHC_NISIER_BWRRDY_Pos)
-#define SDHC_NISIER_BWRRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
-#define SDHC_NISIER_BWRRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
-#define SDHC_NISIER_BWRRDY_MASKED (SDHC_NISIER_BWRRDY_MASKED_Val << SDHC_NISIER_BWRRDY_Pos)
-#define SDHC_NISIER_BWRRDY_ENABLED (SDHC_NISIER_BWRRDY_ENABLED_Val << SDHC_NISIER_BWRRDY_Pos)
-#define SDHC_NISIER_BRDRDY_Pos 5 /**< \brief (SDHC_NISIER) Buffer Read Ready Signal Enable */
-#define SDHC_NISIER_BRDRDY (_U_(0x1) << SDHC_NISIER_BRDRDY_Pos)
-#define SDHC_NISIER_BRDRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
-#define SDHC_NISIER_BRDRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
-#define SDHC_NISIER_BRDRDY_MASKED (SDHC_NISIER_BRDRDY_MASKED_Val << SDHC_NISIER_BRDRDY_Pos)
-#define SDHC_NISIER_BRDRDY_ENABLED (SDHC_NISIER_BRDRDY_ENABLED_Val << SDHC_NISIER_BRDRDY_Pos)
-#define SDHC_NISIER_CINS_Pos 6 /**< \brief (SDHC_NISIER) Card Insertion Signal Enable */
-#define SDHC_NISIER_CINS (_U_(0x1) << SDHC_NISIER_CINS_Pos)
-#define SDHC_NISIER_CINS_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
-#define SDHC_NISIER_CINS_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
-#define SDHC_NISIER_CINS_MASKED (SDHC_NISIER_CINS_MASKED_Val << SDHC_NISIER_CINS_Pos)
-#define SDHC_NISIER_CINS_ENABLED (SDHC_NISIER_CINS_ENABLED_Val << SDHC_NISIER_CINS_Pos)
-#define SDHC_NISIER_CREM_Pos 7 /**< \brief (SDHC_NISIER) Card Removal Signal Enable */
-#define SDHC_NISIER_CREM (_U_(0x1) << SDHC_NISIER_CREM_Pos)
-#define SDHC_NISIER_CREM_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
-#define SDHC_NISIER_CREM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
-#define SDHC_NISIER_CREM_MASKED (SDHC_NISIER_CREM_MASKED_Val << SDHC_NISIER_CREM_Pos)
-#define SDHC_NISIER_CREM_ENABLED (SDHC_NISIER_CREM_ENABLED_Val << SDHC_NISIER_CREM_Pos)
-#define SDHC_NISIER_CINT_Pos 8 /**< \brief (SDHC_NISIER) Card Interrupt Signal Enable */
-#define SDHC_NISIER_CINT (_U_(0x1) << SDHC_NISIER_CINT_Pos)
-#define SDHC_NISIER_CINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
-#define SDHC_NISIER_CINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
-#define SDHC_NISIER_CINT_MASKED (SDHC_NISIER_CINT_MASKED_Val << SDHC_NISIER_CINT_Pos)
-#define SDHC_NISIER_CINT_ENABLED (SDHC_NISIER_CINT_ENABLED_Val << SDHC_NISIER_CINT_Pos)
-#define SDHC_NISIER_MASK _U_(0x01FF) /**< \brief (SDHC_NISIER) MASK Register */
-
-// EMMC mode
-#define SDHC_NISIER_EMMC_CMDC_Pos 0 /**< \brief (SDHC_NISIER_EMMC) Command Complete Signal Enable */
-#define SDHC_NISIER_EMMC_CMDC (_U_(0x1) << SDHC_NISIER_EMMC_CMDC_Pos)
-#define SDHC_NISIER_EMMC_CMDC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */
-#define SDHC_NISIER_EMMC_CMDC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */
-#define SDHC_NISIER_EMMC_CMDC_MASKED (SDHC_NISIER_EMMC_CMDC_MASKED_Val << SDHC_NISIER_EMMC_CMDC_Pos)
-#define SDHC_NISIER_EMMC_CMDC_ENABLED (SDHC_NISIER_EMMC_CMDC_ENABLED_Val << SDHC_NISIER_EMMC_CMDC_Pos)
-#define SDHC_NISIER_EMMC_TRFC_Pos 1 /**< \brief (SDHC_NISIER_EMMC) Transfer Complete Signal Enable */
-#define SDHC_NISIER_EMMC_TRFC (_U_(0x1) << SDHC_NISIER_EMMC_TRFC_Pos)
-#define SDHC_NISIER_EMMC_TRFC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */
-#define SDHC_NISIER_EMMC_TRFC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */
-#define SDHC_NISIER_EMMC_TRFC_MASKED (SDHC_NISIER_EMMC_TRFC_MASKED_Val << SDHC_NISIER_EMMC_TRFC_Pos)
-#define SDHC_NISIER_EMMC_TRFC_ENABLED (SDHC_NISIER_EMMC_TRFC_ENABLED_Val << SDHC_NISIER_EMMC_TRFC_Pos)
-#define SDHC_NISIER_EMMC_BLKGE_Pos 2 /**< \brief (SDHC_NISIER_EMMC) Block Gap Event Signal Enable */
-#define SDHC_NISIER_EMMC_BLKGE (_U_(0x1) << SDHC_NISIER_EMMC_BLKGE_Pos)
-#define SDHC_NISIER_EMMC_BLKGE_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */
-#define SDHC_NISIER_EMMC_BLKGE_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */
-#define SDHC_NISIER_EMMC_BLKGE_MASKED (SDHC_NISIER_EMMC_BLKGE_MASKED_Val << SDHC_NISIER_EMMC_BLKGE_Pos)
-#define SDHC_NISIER_EMMC_BLKGE_ENABLED (SDHC_NISIER_EMMC_BLKGE_ENABLED_Val << SDHC_NISIER_EMMC_BLKGE_Pos)
-#define SDHC_NISIER_EMMC_DMAINT_Pos 3 /**< \brief (SDHC_NISIER_EMMC) DMA Interrupt Signal Enable */
-#define SDHC_NISIER_EMMC_DMAINT (_U_(0x1) << SDHC_NISIER_EMMC_DMAINT_Pos)
-#define SDHC_NISIER_EMMC_DMAINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */
-#define SDHC_NISIER_EMMC_DMAINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */
-#define SDHC_NISIER_EMMC_DMAINT_MASKED (SDHC_NISIER_EMMC_DMAINT_MASKED_Val << SDHC_NISIER_EMMC_DMAINT_Pos)
-#define SDHC_NISIER_EMMC_DMAINT_ENABLED (SDHC_NISIER_EMMC_DMAINT_ENABLED_Val << SDHC_NISIER_EMMC_DMAINT_Pos)
-#define SDHC_NISIER_EMMC_BWRRDY_Pos 4 /**< \brief (SDHC_NISIER_EMMC) Buffer Write Ready Signal Enable */
-#define SDHC_NISIER_EMMC_BWRRDY (_U_(0x1) << SDHC_NISIER_EMMC_BWRRDY_Pos)
-#define SDHC_NISIER_EMMC_BWRRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */
-#define SDHC_NISIER_EMMC_BWRRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */
-#define SDHC_NISIER_EMMC_BWRRDY_MASKED (SDHC_NISIER_EMMC_BWRRDY_MASKED_Val << SDHC_NISIER_EMMC_BWRRDY_Pos)
-#define SDHC_NISIER_EMMC_BWRRDY_ENABLED (SDHC_NISIER_EMMC_BWRRDY_ENABLED_Val << SDHC_NISIER_EMMC_BWRRDY_Pos)
-#define SDHC_NISIER_EMMC_BRDRDY_Pos 5 /**< \brief (SDHC_NISIER_EMMC) Buffer Read Ready Signal Enable */
-#define SDHC_NISIER_EMMC_BRDRDY (_U_(0x1) << SDHC_NISIER_EMMC_BRDRDY_Pos)
-#define SDHC_NISIER_EMMC_BRDRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */
-#define SDHC_NISIER_EMMC_BRDRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */
-#define SDHC_NISIER_EMMC_BRDRDY_MASKED (SDHC_NISIER_EMMC_BRDRDY_MASKED_Val << SDHC_NISIER_EMMC_BRDRDY_Pos)
-#define SDHC_NISIER_EMMC_BRDRDY_ENABLED (SDHC_NISIER_EMMC_BRDRDY_ENABLED_Val << SDHC_NISIER_EMMC_BRDRDY_Pos)
-#define SDHC_NISIER_EMMC_BOOTAR_Pos 14 /**< \brief (SDHC_NISIER_EMMC) Boot Acknowledge Received Signal Enable */
-#define SDHC_NISIER_EMMC_BOOTAR (_U_(0x1) << SDHC_NISIER_EMMC_BOOTAR_Pos)
-#define SDHC_NISIER_EMMC_MASK _U_(0x403F) /**< \brief (SDHC_NISIER_EMMC) MASK Register */
-
-/* -------- SDHC_EISIER : (SDHC Offset: 0x03A) (R/W 16) Error Interrupt Signal Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Signal Enable */
- uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Signal Enable */
- uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Signal Enable */
- uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Signal Enable */
- uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Signal Enable */
- uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Signal Enable */
- uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Signal Enable */
- uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Signal Enable */
- uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Signal Enable */
- uint16_t ADMA:1; /*!< bit: 9 ADMA Error Signal Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct { // EMMC mode
- uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Signal Enable */
- uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Signal Enable */
- uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Signal Enable */
- uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Signal Enable */
- uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Signal Enable */
- uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Signal Enable */
- uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Signal Enable */
- uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Signal Enable */
- uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Signal Enable */
- uint16_t ADMA:1; /*!< bit: 9 ADMA Error Signal Enable */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t BOOTAE:1; /*!< bit: 12 Boot Acknowledge Error Signal Enable */
- uint16_t :3; /*!< bit: 13..15 Reserved */
- } EMMC; /*!< Structure used for EMMC */
- uint16_t reg; /*!< Type used for register access */
-} SDHC_EISIER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_EISIER_OFFSET 0x03A /**< \brief (SDHC_EISIER offset) Error Interrupt Signal Enable */
-#define SDHC_EISIER_RESETVALUE _U_(0x0000) /**< \brief (SDHC_EISIER reset_value) Error Interrupt Signal Enable */
-
-#define SDHC_EISIER_CMDTEO_Pos 0 /**< \brief (SDHC_EISIER) Command Timeout Error Signal Enable */
-#define SDHC_EISIER_CMDTEO (_U_(0x1) << SDHC_EISIER_CMDTEO_Pos)
-#define SDHC_EISIER_CMDTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
-#define SDHC_EISIER_CMDTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_CMDTEO_MASKED (SDHC_EISIER_CMDTEO_MASKED_Val << SDHC_EISIER_CMDTEO_Pos)
-#define SDHC_EISIER_CMDTEO_ENABLED (SDHC_EISIER_CMDTEO_ENABLED_Val << SDHC_EISIER_CMDTEO_Pos)
-#define SDHC_EISIER_CMDCRC_Pos 1 /**< \brief (SDHC_EISIER) Command CRC Error Signal Enable */
-#define SDHC_EISIER_CMDCRC (_U_(0x1) << SDHC_EISIER_CMDCRC_Pos)
-#define SDHC_EISIER_CMDCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
-#define SDHC_EISIER_CMDCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_CMDCRC_MASKED (SDHC_EISIER_CMDCRC_MASKED_Val << SDHC_EISIER_CMDCRC_Pos)
-#define SDHC_EISIER_CMDCRC_ENABLED (SDHC_EISIER_CMDCRC_ENABLED_Val << SDHC_EISIER_CMDCRC_Pos)
-#define SDHC_EISIER_CMDEND_Pos 2 /**< \brief (SDHC_EISIER) Command End Bit Error Signal Enable */
-#define SDHC_EISIER_CMDEND (_U_(0x1) << SDHC_EISIER_CMDEND_Pos)
-#define SDHC_EISIER_CMDEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
-#define SDHC_EISIER_CMDEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_CMDEND_MASKED (SDHC_EISIER_CMDEND_MASKED_Val << SDHC_EISIER_CMDEND_Pos)
-#define SDHC_EISIER_CMDEND_ENABLED (SDHC_EISIER_CMDEND_ENABLED_Val << SDHC_EISIER_CMDEND_Pos)
-#define SDHC_EISIER_CMDIDX_Pos 3 /**< \brief (SDHC_EISIER) Command Index Error Signal Enable */
-#define SDHC_EISIER_CMDIDX (_U_(0x1) << SDHC_EISIER_CMDIDX_Pos)
-#define SDHC_EISIER_CMDIDX_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
-#define SDHC_EISIER_CMDIDX_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_CMDIDX_MASKED (SDHC_EISIER_CMDIDX_MASKED_Val << SDHC_EISIER_CMDIDX_Pos)
-#define SDHC_EISIER_CMDIDX_ENABLED (SDHC_EISIER_CMDIDX_ENABLED_Val << SDHC_EISIER_CMDIDX_Pos)
-#define SDHC_EISIER_DATTEO_Pos 4 /**< \brief (SDHC_EISIER) Data Timeout Error Signal Enable */
-#define SDHC_EISIER_DATTEO (_U_(0x1) << SDHC_EISIER_DATTEO_Pos)
-#define SDHC_EISIER_DATTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
-#define SDHC_EISIER_DATTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_DATTEO_MASKED (SDHC_EISIER_DATTEO_MASKED_Val << SDHC_EISIER_DATTEO_Pos)
-#define SDHC_EISIER_DATTEO_ENABLED (SDHC_EISIER_DATTEO_ENABLED_Val << SDHC_EISIER_DATTEO_Pos)
-#define SDHC_EISIER_DATCRC_Pos 5 /**< \brief (SDHC_EISIER) Data CRC Error Signal Enable */
-#define SDHC_EISIER_DATCRC (_U_(0x1) << SDHC_EISIER_DATCRC_Pos)
-#define SDHC_EISIER_DATCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
-#define SDHC_EISIER_DATCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_DATCRC_MASKED (SDHC_EISIER_DATCRC_MASKED_Val << SDHC_EISIER_DATCRC_Pos)
-#define SDHC_EISIER_DATCRC_ENABLED (SDHC_EISIER_DATCRC_ENABLED_Val << SDHC_EISIER_DATCRC_Pos)
-#define SDHC_EISIER_DATEND_Pos 6 /**< \brief (SDHC_EISIER) Data End Bit Error Signal Enable */
-#define SDHC_EISIER_DATEND (_U_(0x1) << SDHC_EISIER_DATEND_Pos)
-#define SDHC_EISIER_DATEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
-#define SDHC_EISIER_DATEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_DATEND_MASKED (SDHC_EISIER_DATEND_MASKED_Val << SDHC_EISIER_DATEND_Pos)
-#define SDHC_EISIER_DATEND_ENABLED (SDHC_EISIER_DATEND_ENABLED_Val << SDHC_EISIER_DATEND_Pos)
-#define SDHC_EISIER_CURLIM_Pos 7 /**< \brief (SDHC_EISIER) Current Limit Error Signal Enable */
-#define SDHC_EISIER_CURLIM (_U_(0x1) << SDHC_EISIER_CURLIM_Pos)
-#define SDHC_EISIER_CURLIM_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
-#define SDHC_EISIER_CURLIM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_CURLIM_MASKED (SDHC_EISIER_CURLIM_MASKED_Val << SDHC_EISIER_CURLIM_Pos)
-#define SDHC_EISIER_CURLIM_ENABLED (SDHC_EISIER_CURLIM_ENABLED_Val << SDHC_EISIER_CURLIM_Pos)
-#define SDHC_EISIER_ACMD_Pos 8 /**< \brief (SDHC_EISIER) Auto CMD Error Signal Enable */
-#define SDHC_EISIER_ACMD (_U_(0x1) << SDHC_EISIER_ACMD_Pos)
-#define SDHC_EISIER_ACMD_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
-#define SDHC_EISIER_ACMD_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_ACMD_MASKED (SDHC_EISIER_ACMD_MASKED_Val << SDHC_EISIER_ACMD_Pos)
-#define SDHC_EISIER_ACMD_ENABLED (SDHC_EISIER_ACMD_ENABLED_Val << SDHC_EISIER_ACMD_Pos)
-#define SDHC_EISIER_ADMA_Pos 9 /**< \brief (SDHC_EISIER) ADMA Error Signal Enable */
-#define SDHC_EISIER_ADMA (_U_(0x1) << SDHC_EISIER_ADMA_Pos)
-#define SDHC_EISIER_ADMA_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
-#define SDHC_EISIER_ADMA_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_ADMA_MASKED (SDHC_EISIER_ADMA_MASKED_Val << SDHC_EISIER_ADMA_Pos)
-#define SDHC_EISIER_ADMA_ENABLED (SDHC_EISIER_ADMA_ENABLED_Val << SDHC_EISIER_ADMA_Pos)
-#define SDHC_EISIER_MASK _U_(0x03FF) /**< \brief (SDHC_EISIER) MASK Register */
-
-// EMMC mode
-#define SDHC_EISIER_EMMC_CMDTEO_Pos 0 /**< \brief (SDHC_EISIER_EMMC) Command Timeout Error Signal Enable */
-#define SDHC_EISIER_EMMC_CMDTEO (_U_(0x1) << SDHC_EISIER_EMMC_CMDTEO_Pos)
-#define SDHC_EISIER_EMMC_CMDTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define SDHC_EISIER_EMMC_CMDTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_CMDTEO_MASKED (SDHC_EISIER_EMMC_CMDTEO_MASKED_Val << SDHC_EISIER_EMMC_CMDTEO_Pos)
-#define SDHC_EISIER_EMMC_CMDTEO_ENABLED (SDHC_EISIER_EMMC_CMDTEO_ENABLED_Val << SDHC_EISIER_EMMC_CMDTEO_Pos)
-#define SDHC_EISIER_EMMC_CMDCRC_Pos 1 /**< \brief (SDHC_EISIER_EMMC) Command CRC Error Signal Enable */
-#define SDHC_EISIER_EMMC_CMDCRC (_U_(0x1) << SDHC_EISIER_EMMC_CMDCRC_Pos)
-#define SDHC_EISIER_EMMC_CMDCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define SDHC_EISIER_EMMC_CMDCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_CMDCRC_MASKED (SDHC_EISIER_EMMC_CMDCRC_MASKED_Val << SDHC_EISIER_EMMC_CMDCRC_Pos)
-#define SDHC_EISIER_EMMC_CMDCRC_ENABLED (SDHC_EISIER_EMMC_CMDCRC_ENABLED_Val << SDHC_EISIER_EMMC_CMDCRC_Pos)
-#define SDHC_EISIER_EMMC_CMDEND_Pos 2 /**< \brief (SDHC_EISIER_EMMC) Command End Bit Error Signal Enable */
-#define SDHC_EISIER_EMMC_CMDEND (_U_(0x1) << SDHC_EISIER_EMMC_CMDEND_Pos)
-#define SDHC_EISIER_EMMC_CMDEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define SDHC_EISIER_EMMC_CMDEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_CMDEND_MASKED (SDHC_EISIER_EMMC_CMDEND_MASKED_Val << SDHC_EISIER_EMMC_CMDEND_Pos)
-#define SDHC_EISIER_EMMC_CMDEND_ENABLED (SDHC_EISIER_EMMC_CMDEND_ENABLED_Val << SDHC_EISIER_EMMC_CMDEND_Pos)
-#define SDHC_EISIER_EMMC_CMDIDX_Pos 3 /**< \brief (SDHC_EISIER_EMMC) Command Index Error Signal Enable */
-#define SDHC_EISIER_EMMC_CMDIDX (_U_(0x1) << SDHC_EISIER_EMMC_CMDIDX_Pos)
-#define SDHC_EISIER_EMMC_CMDIDX_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define SDHC_EISIER_EMMC_CMDIDX_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_CMDIDX_MASKED (SDHC_EISIER_EMMC_CMDIDX_MASKED_Val << SDHC_EISIER_EMMC_CMDIDX_Pos)
-#define SDHC_EISIER_EMMC_CMDIDX_ENABLED (SDHC_EISIER_EMMC_CMDIDX_ENABLED_Val << SDHC_EISIER_EMMC_CMDIDX_Pos)
-#define SDHC_EISIER_EMMC_DATTEO_Pos 4 /**< \brief (SDHC_EISIER_EMMC) Data Timeout Error Signal Enable */
-#define SDHC_EISIER_EMMC_DATTEO (_U_(0x1) << SDHC_EISIER_EMMC_DATTEO_Pos)
-#define SDHC_EISIER_EMMC_DATTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define SDHC_EISIER_EMMC_DATTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_DATTEO_MASKED (SDHC_EISIER_EMMC_DATTEO_MASKED_Val << SDHC_EISIER_EMMC_DATTEO_Pos)
-#define SDHC_EISIER_EMMC_DATTEO_ENABLED (SDHC_EISIER_EMMC_DATTEO_ENABLED_Val << SDHC_EISIER_EMMC_DATTEO_Pos)
-#define SDHC_EISIER_EMMC_DATCRC_Pos 5 /**< \brief (SDHC_EISIER_EMMC) Data CRC Error Signal Enable */
-#define SDHC_EISIER_EMMC_DATCRC (_U_(0x1) << SDHC_EISIER_EMMC_DATCRC_Pos)
-#define SDHC_EISIER_EMMC_DATCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define SDHC_EISIER_EMMC_DATCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_DATCRC_MASKED (SDHC_EISIER_EMMC_DATCRC_MASKED_Val << SDHC_EISIER_EMMC_DATCRC_Pos)
-#define SDHC_EISIER_EMMC_DATCRC_ENABLED (SDHC_EISIER_EMMC_DATCRC_ENABLED_Val << SDHC_EISIER_EMMC_DATCRC_Pos)
-#define SDHC_EISIER_EMMC_DATEND_Pos 6 /**< \brief (SDHC_EISIER_EMMC) Data End Bit Error Signal Enable */
-#define SDHC_EISIER_EMMC_DATEND (_U_(0x1) << SDHC_EISIER_EMMC_DATEND_Pos)
-#define SDHC_EISIER_EMMC_DATEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define SDHC_EISIER_EMMC_DATEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_DATEND_MASKED (SDHC_EISIER_EMMC_DATEND_MASKED_Val << SDHC_EISIER_EMMC_DATEND_Pos)
-#define SDHC_EISIER_EMMC_DATEND_ENABLED (SDHC_EISIER_EMMC_DATEND_ENABLED_Val << SDHC_EISIER_EMMC_DATEND_Pos)
-#define SDHC_EISIER_EMMC_CURLIM_Pos 7 /**< \brief (SDHC_EISIER_EMMC) Current Limit Error Signal Enable */
-#define SDHC_EISIER_EMMC_CURLIM (_U_(0x1) << SDHC_EISIER_EMMC_CURLIM_Pos)
-#define SDHC_EISIER_EMMC_CURLIM_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define SDHC_EISIER_EMMC_CURLIM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_CURLIM_MASKED (SDHC_EISIER_EMMC_CURLIM_MASKED_Val << SDHC_EISIER_EMMC_CURLIM_Pos)
-#define SDHC_EISIER_EMMC_CURLIM_ENABLED (SDHC_EISIER_EMMC_CURLIM_ENABLED_Val << SDHC_EISIER_EMMC_CURLIM_Pos)
-#define SDHC_EISIER_EMMC_ACMD_Pos 8 /**< \brief (SDHC_EISIER_EMMC) Auto CMD Error Signal Enable */
-#define SDHC_EISIER_EMMC_ACMD (_U_(0x1) << SDHC_EISIER_EMMC_ACMD_Pos)
-#define SDHC_EISIER_EMMC_ACMD_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define SDHC_EISIER_EMMC_ACMD_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_ACMD_MASKED (SDHC_EISIER_EMMC_ACMD_MASKED_Val << SDHC_EISIER_EMMC_ACMD_Pos)
-#define SDHC_EISIER_EMMC_ACMD_ENABLED (SDHC_EISIER_EMMC_ACMD_ENABLED_Val << SDHC_EISIER_EMMC_ACMD_Pos)
-#define SDHC_EISIER_EMMC_ADMA_Pos 9 /**< \brief (SDHC_EISIER_EMMC) ADMA Error Signal Enable */
-#define SDHC_EISIER_EMMC_ADMA (_U_(0x1) << SDHC_EISIER_EMMC_ADMA_Pos)
-#define SDHC_EISIER_EMMC_ADMA_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define SDHC_EISIER_EMMC_ADMA_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_ADMA_MASKED (SDHC_EISIER_EMMC_ADMA_MASKED_Val << SDHC_EISIER_EMMC_ADMA_Pos)
-#define SDHC_EISIER_EMMC_ADMA_ENABLED (SDHC_EISIER_EMMC_ADMA_ENABLED_Val << SDHC_EISIER_EMMC_ADMA_Pos)
-#define SDHC_EISIER_EMMC_BOOTAE_Pos 12 /**< \brief (SDHC_EISIER_EMMC) Boot Acknowledge Error Signal Enable */
-#define SDHC_EISIER_EMMC_BOOTAE (_U_(0x1) << SDHC_EISIER_EMMC_BOOTAE_Pos)
-#define SDHC_EISIER_EMMC_MASK _U_(0x13FF) /**< \brief (SDHC_EISIER_EMMC) MASK Register */
-
-/* -------- SDHC_ACESR : (SDHC Offset: 0x03C) (R/ 16) Auto CMD Error Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t ACMD12NE:1; /*!< bit: 0 Auto CMD12 Not Executed */
- uint16_t ACMDTEO:1; /*!< bit: 1 Auto CMD Timeout Error */
- uint16_t ACMDCRC:1; /*!< bit: 2 Auto CMD CRC Error */
- uint16_t ACMDEND:1; /*!< bit: 3 Auto CMD End Bit Error */
- uint16_t ACMDIDX:1; /*!< bit: 4 Auto CMD Index Error */
- uint16_t :2; /*!< bit: 5.. 6 Reserved */
- uint16_t CMDNI:1; /*!< bit: 7 Command not Issued By Auto CMD12 Error */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} SDHC_ACESR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_ACESR_OFFSET 0x03C /**< \brief (SDHC_ACESR offset) Auto CMD Error Status */
-#define SDHC_ACESR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_ACESR reset_value) Auto CMD Error Status */
-
-#define SDHC_ACESR_ACMD12NE_Pos 0 /**< \brief (SDHC_ACESR) Auto CMD12 Not Executed */
-#define SDHC_ACESR_ACMD12NE (_U_(0x1) << SDHC_ACESR_ACMD12NE_Pos)
-#define SDHC_ACESR_ACMD12NE_EXEC_Val _U_(0x0) /**< \brief (SDHC_ACESR) Executed */
-#define SDHC_ACESR_ACMD12NE_NOT_EXEC_Val _U_(0x1) /**< \brief (SDHC_ACESR) Not executed */
-#define SDHC_ACESR_ACMD12NE_EXEC (SDHC_ACESR_ACMD12NE_EXEC_Val << SDHC_ACESR_ACMD12NE_Pos)
-#define SDHC_ACESR_ACMD12NE_NOT_EXEC (SDHC_ACESR_ACMD12NE_NOT_EXEC_Val << SDHC_ACESR_ACMD12NE_Pos)
-#define SDHC_ACESR_ACMDTEO_Pos 1 /**< \brief (SDHC_ACESR) Auto CMD Timeout Error */
-#define SDHC_ACESR_ACMDTEO (_U_(0x1) << SDHC_ACESR_ACMDTEO_Pos)
-#define SDHC_ACESR_ACMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */
-#define SDHC_ACESR_ACMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_ACESR) Timeout */
-#define SDHC_ACESR_ACMDTEO_NO (SDHC_ACESR_ACMDTEO_NO_Val << SDHC_ACESR_ACMDTEO_Pos)
-#define SDHC_ACESR_ACMDTEO_YES (SDHC_ACESR_ACMDTEO_YES_Val << SDHC_ACESR_ACMDTEO_Pos)
-#define SDHC_ACESR_ACMDCRC_Pos 2 /**< \brief (SDHC_ACESR) Auto CMD CRC Error */
-#define SDHC_ACESR_ACMDCRC (_U_(0x1) << SDHC_ACESR_ACMDCRC_Pos)
-#define SDHC_ACESR_ACMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */
-#define SDHC_ACESR_ACMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_ACESR) CRC Error Generated */
-#define SDHC_ACESR_ACMDCRC_NO (SDHC_ACESR_ACMDCRC_NO_Val << SDHC_ACESR_ACMDCRC_Pos)
-#define SDHC_ACESR_ACMDCRC_YES (SDHC_ACESR_ACMDCRC_YES_Val << SDHC_ACESR_ACMDCRC_Pos)
-#define SDHC_ACESR_ACMDEND_Pos 3 /**< \brief (SDHC_ACESR) Auto CMD End Bit Error */
-#define SDHC_ACESR_ACMDEND (_U_(0x1) << SDHC_ACESR_ACMDEND_Pos)
-#define SDHC_ACESR_ACMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */
-#define SDHC_ACESR_ACMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_ACESR) End Bit Error Generated */
-#define SDHC_ACESR_ACMDEND_NO (SDHC_ACESR_ACMDEND_NO_Val << SDHC_ACESR_ACMDEND_Pos)
-#define SDHC_ACESR_ACMDEND_YES (SDHC_ACESR_ACMDEND_YES_Val << SDHC_ACESR_ACMDEND_Pos)
-#define SDHC_ACESR_ACMDIDX_Pos 4 /**< \brief (SDHC_ACESR) Auto CMD Index Error */
-#define SDHC_ACESR_ACMDIDX (_U_(0x1) << SDHC_ACESR_ACMDIDX_Pos)
-#define SDHC_ACESR_ACMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */
-#define SDHC_ACESR_ACMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_ACESR) Error */
-#define SDHC_ACESR_ACMDIDX_NO (SDHC_ACESR_ACMDIDX_NO_Val << SDHC_ACESR_ACMDIDX_Pos)
-#define SDHC_ACESR_ACMDIDX_YES (SDHC_ACESR_ACMDIDX_YES_Val << SDHC_ACESR_ACMDIDX_Pos)
-#define SDHC_ACESR_CMDNI_Pos 7 /**< \brief (SDHC_ACESR) Command not Issued By Auto CMD12 Error */
-#define SDHC_ACESR_CMDNI (_U_(0x1) << SDHC_ACESR_CMDNI_Pos)
-#define SDHC_ACESR_CMDNI_OK_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */
-#define SDHC_ACESR_CMDNI_NOT_ISSUED_Val _U_(0x1) /**< \brief (SDHC_ACESR) Not Issued */
-#define SDHC_ACESR_CMDNI_OK (SDHC_ACESR_CMDNI_OK_Val << SDHC_ACESR_CMDNI_Pos)
-#define SDHC_ACESR_CMDNI_NOT_ISSUED (SDHC_ACESR_CMDNI_NOT_ISSUED_Val << SDHC_ACESR_CMDNI_Pos)
-#define SDHC_ACESR_MASK _U_(0x009F) /**< \brief (SDHC_ACESR) MASK Register */
-
-/* -------- SDHC_HC2R : (SDHC Offset: 0x03E) (R/W 16) Host Control 2 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t UHSMS:3; /*!< bit: 0.. 2 UHS Mode Select */
- uint16_t VS18EN:1; /*!< bit: 3 1.8V Signaling Enable */
- uint16_t DRVSEL:2; /*!< bit: 4.. 5 Driver Strength Select */
- uint16_t EXTUN:1; /*!< bit: 6 Execute Tuning */
- uint16_t SLCKSEL:1; /*!< bit: 7 Sampling Clock Select */
- uint16_t :6; /*!< bit: 8..13 Reserved */
- uint16_t ASINTEN:1; /*!< bit: 14 Asynchronous Interrupt Enable */
- uint16_t PVALEN:1; /*!< bit: 15 Preset Value Enable */
- } bit; /*!< Structure used for bit access */
- struct { // EMMC mode
- uint16_t HS200EN:4; /*!< bit: 0.. 3 HS200 Mode Enable */
- uint16_t DRVSEL:2; /*!< bit: 4.. 5 Driver Strength Select */
- uint16_t EXTUN:1; /*!< bit: 6 Execute Tuning */
- uint16_t SLCKSEL:1; /*!< bit: 7 Sampling Clock Select */
- uint16_t :7; /*!< bit: 8..14 Reserved */
- uint16_t PVALEN:1; /*!< bit: 15 Preset Value Enable */
- } EMMC; /*!< Structure used for EMMC */
- uint16_t reg; /*!< Type used for register access */
-} SDHC_HC2R_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_HC2R_OFFSET 0x03E /**< \brief (SDHC_HC2R offset) Host Control 2 */
-#define SDHC_HC2R_RESETVALUE _U_(0x0000) /**< \brief (SDHC_HC2R reset_value) Host Control 2 */
-
-#define SDHC_HC2R_UHSMS_Pos 0 /**< \brief (SDHC_HC2R) UHS Mode Select */
-#define SDHC_HC2R_UHSMS_Msk (_U_(0x7) << SDHC_HC2R_UHSMS_Pos)
-#define SDHC_HC2R_UHSMS(value) (SDHC_HC2R_UHSMS_Msk & ((value) << SDHC_HC2R_UHSMS_Pos))
-#define SDHC_HC2R_UHSMS_SDR12_Val _U_(0x0) /**< \brief (SDHC_HC2R) SDR12 */
-#define SDHC_HC2R_UHSMS_SDR25_Val _U_(0x1) /**< \brief (SDHC_HC2R) SDR25 */
-#define SDHC_HC2R_UHSMS_SDR50_Val _U_(0x2) /**< \brief (SDHC_HC2R) SDR50 */
-#define SDHC_HC2R_UHSMS_SDR104_Val _U_(0x3) /**< \brief (SDHC_HC2R) SDR104 */
-#define SDHC_HC2R_UHSMS_DDR50_Val _U_(0x4) /**< \brief (SDHC_HC2R) DDR50 */
-#define SDHC_HC2R_UHSMS_SDR12 (SDHC_HC2R_UHSMS_SDR12_Val << SDHC_HC2R_UHSMS_Pos)
-#define SDHC_HC2R_UHSMS_SDR25 (SDHC_HC2R_UHSMS_SDR25_Val << SDHC_HC2R_UHSMS_Pos)
-#define SDHC_HC2R_UHSMS_SDR50 (SDHC_HC2R_UHSMS_SDR50_Val << SDHC_HC2R_UHSMS_Pos)
-#define SDHC_HC2R_UHSMS_SDR104 (SDHC_HC2R_UHSMS_SDR104_Val << SDHC_HC2R_UHSMS_Pos)
-#define SDHC_HC2R_UHSMS_DDR50 (SDHC_HC2R_UHSMS_DDR50_Val << SDHC_HC2R_UHSMS_Pos)
-#define SDHC_HC2R_VS18EN_Pos 3 /**< \brief (SDHC_HC2R) 1.8V Signaling Enable */
-#define SDHC_HC2R_VS18EN (_U_(0x1) << SDHC_HC2R_VS18EN_Pos)
-#define SDHC_HC2R_VS18EN_S33V_Val _U_(0x0) /**< \brief (SDHC_HC2R) 3.3V Signaling */
-#define SDHC_HC2R_VS18EN_S18V_Val _U_(0x1) /**< \brief (SDHC_HC2R) 1.8V Signaling */
-#define SDHC_HC2R_VS18EN_S33V (SDHC_HC2R_VS18EN_S33V_Val << SDHC_HC2R_VS18EN_Pos)
-#define SDHC_HC2R_VS18EN_S18V (SDHC_HC2R_VS18EN_S18V_Val << SDHC_HC2R_VS18EN_Pos)
-#define SDHC_HC2R_DRVSEL_Pos 4 /**< \brief (SDHC_HC2R) Driver Strength Select */
-#define SDHC_HC2R_DRVSEL_Msk (_U_(0x3) << SDHC_HC2R_DRVSEL_Pos)
-#define SDHC_HC2R_DRVSEL(value) (SDHC_HC2R_DRVSEL_Msk & ((value) << SDHC_HC2R_DRVSEL_Pos))
-#define SDHC_HC2R_DRVSEL_B_Val _U_(0x0) /**< \brief (SDHC_HC2R) Driver Type B is Selected (Default) */
-#define SDHC_HC2R_DRVSEL_A_Val _U_(0x1) /**< \brief (SDHC_HC2R) Driver Type A is Selected */
-#define SDHC_HC2R_DRVSEL_C_Val _U_(0x2) /**< \brief (SDHC_HC2R) Driver Type C is Selected */
-#define SDHC_HC2R_DRVSEL_D_Val _U_(0x3) /**< \brief (SDHC_HC2R) Driver Type D is Selected */
-#define SDHC_HC2R_DRVSEL_B (SDHC_HC2R_DRVSEL_B_Val << SDHC_HC2R_DRVSEL_Pos)
-#define SDHC_HC2R_DRVSEL_A (SDHC_HC2R_DRVSEL_A_Val << SDHC_HC2R_DRVSEL_Pos)
-#define SDHC_HC2R_DRVSEL_C (SDHC_HC2R_DRVSEL_C_Val << SDHC_HC2R_DRVSEL_Pos)
-#define SDHC_HC2R_DRVSEL_D (SDHC_HC2R_DRVSEL_D_Val << SDHC_HC2R_DRVSEL_Pos)
-#define SDHC_HC2R_EXTUN_Pos 6 /**< \brief (SDHC_HC2R) Execute Tuning */
-#define SDHC_HC2R_EXTUN (_U_(0x1) << SDHC_HC2R_EXTUN_Pos)
-#define SDHC_HC2R_EXTUN_NO_Val _U_(0x0) /**< \brief (SDHC_HC2R) Not Tuned or Tuning Completed */
-#define SDHC_HC2R_EXTUN_REQUESTED_Val _U_(0x1) /**< \brief (SDHC_HC2R) Execute Tuning */
-#define SDHC_HC2R_EXTUN_NO (SDHC_HC2R_EXTUN_NO_Val << SDHC_HC2R_EXTUN_Pos)
-#define SDHC_HC2R_EXTUN_REQUESTED (SDHC_HC2R_EXTUN_REQUESTED_Val << SDHC_HC2R_EXTUN_Pos)
-#define SDHC_HC2R_SLCKSEL_Pos 7 /**< \brief (SDHC_HC2R) Sampling Clock Select */
-#define SDHC_HC2R_SLCKSEL (_U_(0x1) << SDHC_HC2R_SLCKSEL_Pos)
-#define SDHC_HC2R_SLCKSEL_FIXED_Val _U_(0x0) /**< \brief (SDHC_HC2R) Fixed clock is used to sample data */
-#define SDHC_HC2R_SLCKSEL_TUNED_Val _U_(0x1) /**< \brief (SDHC_HC2R) Tuned clock is used to sample data */
-#define SDHC_HC2R_SLCKSEL_FIXED (SDHC_HC2R_SLCKSEL_FIXED_Val << SDHC_HC2R_SLCKSEL_Pos)
-#define SDHC_HC2R_SLCKSEL_TUNED (SDHC_HC2R_SLCKSEL_TUNED_Val << SDHC_HC2R_SLCKSEL_Pos)
-#define SDHC_HC2R_ASINTEN_Pos 14 /**< \brief (SDHC_HC2R) Asynchronous Interrupt Enable */
-#define SDHC_HC2R_ASINTEN (_U_(0x1) << SDHC_HC2R_ASINTEN_Pos)
-#define SDHC_HC2R_ASINTEN_DISABLED_Val _U_(0x0) /**< \brief (SDHC_HC2R) Disabled */
-#define SDHC_HC2R_ASINTEN_ENABLED_Val _U_(0x1) /**< \brief (SDHC_HC2R) Enabled */
-#define SDHC_HC2R_ASINTEN_DISABLED (SDHC_HC2R_ASINTEN_DISABLED_Val << SDHC_HC2R_ASINTEN_Pos)
-#define SDHC_HC2R_ASINTEN_ENABLED (SDHC_HC2R_ASINTEN_ENABLED_Val << SDHC_HC2R_ASINTEN_Pos)
-#define SDHC_HC2R_PVALEN_Pos 15 /**< \brief (SDHC_HC2R) Preset Value Enable */
-#define SDHC_HC2R_PVALEN (_U_(0x1) << SDHC_HC2R_PVALEN_Pos)
-#define SDHC_HC2R_PVALEN_HOST_Val _U_(0x0) /**< \brief (SDHC_HC2R) SDCLK and Driver Strength are controlled by Host Controller */
-#define SDHC_HC2R_PVALEN_AUTO_Val _U_(0x1) /**< \brief (SDHC_HC2R) Automatic Selection by Preset Value is Enabled */
-#define SDHC_HC2R_PVALEN_HOST (SDHC_HC2R_PVALEN_HOST_Val << SDHC_HC2R_PVALEN_Pos)
-#define SDHC_HC2R_PVALEN_AUTO (SDHC_HC2R_PVALEN_AUTO_Val << SDHC_HC2R_PVALEN_Pos)
-#define SDHC_HC2R_MASK _U_(0xC0FF) /**< \brief (SDHC_HC2R) MASK Register */
-
-// EMMC mode
-#define SDHC_HC2R_EMMC_HS200EN_Pos 0 /**< \brief (SDHC_HC2R_EMMC) HS200 Mode Enable */
-#define SDHC_HC2R_EMMC_HS200EN_Msk (_U_(0xF) << SDHC_HC2R_EMMC_HS200EN_Pos)
-#define SDHC_HC2R_EMMC_HS200EN(value) (SDHC_HC2R_EMMC_HS200EN_Msk & ((value) << SDHC_HC2R_EMMC_HS200EN_Pos))
-#define SDHC_HC2R_EMMC_HS200EN_SDR12_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) SDR12 */
-#define SDHC_HC2R_EMMC_HS200EN_SDR25_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) SDR25 */
-#define SDHC_HC2R_EMMC_HS200EN_SDR50_Val _U_(0x2) /**< \brief (SDHC_HC2R_EMMC) SDR50 */
-#define SDHC_HC2R_EMMC_HS200EN_SDR104_Val _U_(0x3) /**< \brief (SDHC_HC2R_EMMC) SDR104 */
-#define SDHC_HC2R_EMMC_HS200EN_DDR50_Val _U_(0x4) /**< \brief (SDHC_HC2R_EMMC) DDR50 */
-#define SDHC_HC2R_EMMC_HS200EN_SDR12 (SDHC_HC2R_EMMC_HS200EN_SDR12_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
-#define SDHC_HC2R_EMMC_HS200EN_SDR25 (SDHC_HC2R_EMMC_HS200EN_SDR25_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
-#define SDHC_HC2R_EMMC_HS200EN_SDR50 (SDHC_HC2R_EMMC_HS200EN_SDR50_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
-#define SDHC_HC2R_EMMC_HS200EN_SDR104 (SDHC_HC2R_EMMC_HS200EN_SDR104_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
-#define SDHC_HC2R_EMMC_HS200EN_DDR50 (SDHC_HC2R_EMMC_HS200EN_DDR50_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
-#define SDHC_HC2R_EMMC_DRVSEL_Pos 4 /**< \brief (SDHC_HC2R_EMMC) Driver Strength Select */
-#define SDHC_HC2R_EMMC_DRVSEL_Msk (_U_(0x3) << SDHC_HC2R_EMMC_DRVSEL_Pos)
-#define SDHC_HC2R_EMMC_DRVSEL(value) (SDHC_HC2R_EMMC_DRVSEL_Msk & ((value) << SDHC_HC2R_EMMC_DRVSEL_Pos))
-#define SDHC_HC2R_EMMC_DRVSEL_B_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) Driver Type B is Selected (Default) */
-#define SDHC_HC2R_EMMC_DRVSEL_A_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) Driver Type A is Selected */
-#define SDHC_HC2R_EMMC_DRVSEL_C_Val _U_(0x2) /**< \brief (SDHC_HC2R_EMMC) Driver Type C is Selected */
-#define SDHC_HC2R_EMMC_DRVSEL_D_Val _U_(0x3) /**< \brief (SDHC_HC2R_EMMC) Driver Type D is Selected */
-#define SDHC_HC2R_EMMC_DRVSEL_B (SDHC_HC2R_EMMC_DRVSEL_B_Val << SDHC_HC2R_EMMC_DRVSEL_Pos)
-#define SDHC_HC2R_EMMC_DRVSEL_A (SDHC_HC2R_EMMC_DRVSEL_A_Val << SDHC_HC2R_EMMC_DRVSEL_Pos)
-#define SDHC_HC2R_EMMC_DRVSEL_C (SDHC_HC2R_EMMC_DRVSEL_C_Val << SDHC_HC2R_EMMC_DRVSEL_Pos)
-#define SDHC_HC2R_EMMC_DRVSEL_D (SDHC_HC2R_EMMC_DRVSEL_D_Val << SDHC_HC2R_EMMC_DRVSEL_Pos)
-#define SDHC_HC2R_EMMC_EXTUN_Pos 6 /**< \brief (SDHC_HC2R_EMMC) Execute Tuning */
-#define SDHC_HC2R_EMMC_EXTUN (_U_(0x1) << SDHC_HC2R_EMMC_EXTUN_Pos)
-#define SDHC_HC2R_EMMC_EXTUN_NO_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) Not Tuned or Tuning Completed */
-#define SDHC_HC2R_EMMC_EXTUN_REQUESTED_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) Execute Tuning */
-#define SDHC_HC2R_EMMC_EXTUN_NO (SDHC_HC2R_EMMC_EXTUN_NO_Val << SDHC_HC2R_EMMC_EXTUN_Pos)
-#define SDHC_HC2R_EMMC_EXTUN_REQUESTED (SDHC_HC2R_EMMC_EXTUN_REQUESTED_Val << SDHC_HC2R_EMMC_EXTUN_Pos)
-#define SDHC_HC2R_EMMC_SLCKSEL_Pos 7 /**< \brief (SDHC_HC2R_EMMC) Sampling Clock Select */
-#define SDHC_HC2R_EMMC_SLCKSEL (_U_(0x1) << SDHC_HC2R_EMMC_SLCKSEL_Pos)
-#define SDHC_HC2R_EMMC_SLCKSEL_FIXED_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) Fixed clock is used to sample data */
-#define SDHC_HC2R_EMMC_SLCKSEL_TUNED_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) Tuned clock is used to sample data */
-#define SDHC_HC2R_EMMC_SLCKSEL_FIXED (SDHC_HC2R_EMMC_SLCKSEL_FIXED_Val << SDHC_HC2R_EMMC_SLCKSEL_Pos)
-#define SDHC_HC2R_EMMC_SLCKSEL_TUNED (SDHC_HC2R_EMMC_SLCKSEL_TUNED_Val << SDHC_HC2R_EMMC_SLCKSEL_Pos)
-#define SDHC_HC2R_EMMC_PVALEN_Pos 15 /**< \brief (SDHC_HC2R_EMMC) Preset Value Enable */
-#define SDHC_HC2R_EMMC_PVALEN (_U_(0x1) << SDHC_HC2R_EMMC_PVALEN_Pos)
-#define SDHC_HC2R_EMMC_PVALEN_HOST_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) SDCLK and Driver Strength are controlled by Host Controller */
-#define SDHC_HC2R_EMMC_PVALEN_AUTO_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) Automatic Selection by Preset Value is Enabled */
-#define SDHC_HC2R_EMMC_PVALEN_HOST (SDHC_HC2R_EMMC_PVALEN_HOST_Val << SDHC_HC2R_EMMC_PVALEN_Pos)
-#define SDHC_HC2R_EMMC_PVALEN_AUTO (SDHC_HC2R_EMMC_PVALEN_AUTO_Val << SDHC_HC2R_EMMC_PVALEN_Pos)
-#define SDHC_HC2R_EMMC_MASK _U_(0x80FF) /**< \brief (SDHC_HC2R_EMMC) MASK Register */
-
-/* -------- SDHC_CA0R : (SDHC Offset: 0x040) (R/ 32) Capabilities 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TEOCLKF:6; /*!< bit: 0.. 5 Timeout Clock Frequency */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t TEOCLKU:1; /*!< bit: 7 Timeout Clock Unit */
- uint32_t BASECLKF:8; /*!< bit: 8..15 Base Clock Frequency */
- uint32_t MAXBLKL:2; /*!< bit: 16..17 Max Block Length */
- uint32_t ED8SUP:1; /*!< bit: 18 8-bit Support for Embedded Device */
- uint32_t ADMA2SUP:1; /*!< bit: 19 ADMA2 Support */
- uint32_t :1; /*!< bit: 20 Reserved */
- uint32_t HSSUP:1; /*!< bit: 21 High Speed Support */
- uint32_t SDMASUP:1; /*!< bit: 22 SDMA Support */
- uint32_t SRSUP:1; /*!< bit: 23 Suspend/Resume Support */
- uint32_t V33VSUP:1; /*!< bit: 24 Voltage Support 3.3V */
- uint32_t V30VSUP:1; /*!< bit: 25 Voltage Support 3.0V */
- uint32_t V18VSUP:1; /*!< bit: 26 Voltage Support 1.8V */
- uint32_t :1; /*!< bit: 27 Reserved */
- uint32_t SB64SUP:1; /*!< bit: 28 64-Bit System Bus Support */
- uint32_t ASINTSUP:1; /*!< bit: 29 Asynchronous Interrupt Support */
- uint32_t SLTYPE:2; /*!< bit: 30..31 Slot Type */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SDHC_CA0R_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_CA0R_OFFSET 0x040 /**< \brief (SDHC_CA0R offset) Capabilities 0 */
-#define SDHC_CA0R_RESETVALUE _U_(0x27E80080) /**< \brief (SDHC_CA0R reset_value) Capabilities 0 */
-
-#define SDHC_CA0R_TEOCLKF_Pos 0 /**< \brief (SDHC_CA0R) Timeout Clock Frequency */
-#define SDHC_CA0R_TEOCLKF_Msk (_U_(0x3F) << SDHC_CA0R_TEOCLKF_Pos)
-#define SDHC_CA0R_TEOCLKF(value) (SDHC_CA0R_TEOCLKF_Msk & ((value) << SDHC_CA0R_TEOCLKF_Pos))
-#define SDHC_CA0R_TEOCLKF_OTHER_Val _U_(0x0) /**< \brief (SDHC_CA0R) Get information via another method */
-#define SDHC_CA0R_TEOCLKF_OTHER (SDHC_CA0R_TEOCLKF_OTHER_Val << SDHC_CA0R_TEOCLKF_Pos)
-#define SDHC_CA0R_TEOCLKU_Pos 7 /**< \brief (SDHC_CA0R) Timeout Clock Unit */
-#define SDHC_CA0R_TEOCLKU (_U_(0x1) << SDHC_CA0R_TEOCLKU_Pos)
-#define SDHC_CA0R_TEOCLKU_KHZ_Val _U_(0x0) /**< \brief (SDHC_CA0R) kHz */
-#define SDHC_CA0R_TEOCLKU_MHZ_Val _U_(0x1) /**< \brief (SDHC_CA0R) MHz */
-#define SDHC_CA0R_TEOCLKU_KHZ (SDHC_CA0R_TEOCLKU_KHZ_Val << SDHC_CA0R_TEOCLKU_Pos)
-#define SDHC_CA0R_TEOCLKU_MHZ (SDHC_CA0R_TEOCLKU_MHZ_Val << SDHC_CA0R_TEOCLKU_Pos)
-#define SDHC_CA0R_BASECLKF_Pos 8 /**< \brief (SDHC_CA0R) Base Clock Frequency */
-#define SDHC_CA0R_BASECLKF_Msk (_U_(0xFF) << SDHC_CA0R_BASECLKF_Pos)
-#define SDHC_CA0R_BASECLKF(value) (SDHC_CA0R_BASECLKF_Msk & ((value) << SDHC_CA0R_BASECLKF_Pos))
-#define SDHC_CA0R_BASECLKF_OTHER_Val _U_(0x0) /**< \brief (SDHC_CA0R) Get information via another method */
-#define SDHC_CA0R_BASECLKF_OTHER (SDHC_CA0R_BASECLKF_OTHER_Val << SDHC_CA0R_BASECLKF_Pos)
-#define SDHC_CA0R_MAXBLKL_Pos 16 /**< \brief (SDHC_CA0R) Max Block Length */
-#define SDHC_CA0R_MAXBLKL_Msk (_U_(0x3) << SDHC_CA0R_MAXBLKL_Pos)
-#define SDHC_CA0R_MAXBLKL(value) (SDHC_CA0R_MAXBLKL_Msk & ((value) << SDHC_CA0R_MAXBLKL_Pos))
-#define SDHC_CA0R_MAXBLKL_512_Val _U_(0x0) /**< \brief (SDHC_CA0R) 512 bytes */
-#define SDHC_CA0R_MAXBLKL_1024_Val _U_(0x1) /**< \brief (SDHC_CA0R) 1024 bytes */
-#define SDHC_CA0R_MAXBLKL_2048_Val _U_(0x2) /**< \brief (SDHC_CA0R) 2048 bytes */
-#define SDHC_CA0R_MAXBLKL_512 (SDHC_CA0R_MAXBLKL_512_Val << SDHC_CA0R_MAXBLKL_Pos)
-#define SDHC_CA0R_MAXBLKL_1024 (SDHC_CA0R_MAXBLKL_1024_Val << SDHC_CA0R_MAXBLKL_Pos)
-#define SDHC_CA0R_MAXBLKL_2048 (SDHC_CA0R_MAXBLKL_2048_Val << SDHC_CA0R_MAXBLKL_Pos)
-#define SDHC_CA0R_ED8SUP_Pos 18 /**< \brief (SDHC_CA0R) 8-bit Support for Embedded Device */
-#define SDHC_CA0R_ED8SUP (_U_(0x1) << SDHC_CA0R_ED8SUP_Pos)
-#define SDHC_CA0R_ED8SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 8-bit Bus Width not Supported */
-#define SDHC_CA0R_ED8SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 8-bit Bus Width Supported */
-#define SDHC_CA0R_ED8SUP_NO (SDHC_CA0R_ED8SUP_NO_Val << SDHC_CA0R_ED8SUP_Pos)
-#define SDHC_CA0R_ED8SUP_YES (SDHC_CA0R_ED8SUP_YES_Val << SDHC_CA0R_ED8SUP_Pos)
-#define SDHC_CA0R_ADMA2SUP_Pos 19 /**< \brief (SDHC_CA0R) ADMA2 Support */
-#define SDHC_CA0R_ADMA2SUP (_U_(0x1) << SDHC_CA0R_ADMA2SUP_Pos)
-#define SDHC_CA0R_ADMA2SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) ADMA2 not Supported */
-#define SDHC_CA0R_ADMA2SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) ADMA2 Supported */
-#define SDHC_CA0R_ADMA2SUP_NO (SDHC_CA0R_ADMA2SUP_NO_Val << SDHC_CA0R_ADMA2SUP_Pos)
-#define SDHC_CA0R_ADMA2SUP_YES (SDHC_CA0R_ADMA2SUP_YES_Val << SDHC_CA0R_ADMA2SUP_Pos)
-#define SDHC_CA0R_HSSUP_Pos 21 /**< \brief (SDHC_CA0R) High Speed Support */
-#define SDHC_CA0R_HSSUP (_U_(0x1) << SDHC_CA0R_HSSUP_Pos)
-#define SDHC_CA0R_HSSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) High Speed not Supported */
-#define SDHC_CA0R_HSSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) High Speed Supported */
-#define SDHC_CA0R_HSSUP_NO (SDHC_CA0R_HSSUP_NO_Val << SDHC_CA0R_HSSUP_Pos)
-#define SDHC_CA0R_HSSUP_YES (SDHC_CA0R_HSSUP_YES_Val << SDHC_CA0R_HSSUP_Pos)
-#define SDHC_CA0R_SDMASUP_Pos 22 /**< \brief (SDHC_CA0R) SDMA Support */
-#define SDHC_CA0R_SDMASUP (_U_(0x1) << SDHC_CA0R_SDMASUP_Pos)
-#define SDHC_CA0R_SDMASUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) SDMA not Supported */
-#define SDHC_CA0R_SDMASUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) SDMA Supported */
-#define SDHC_CA0R_SDMASUP_NO (SDHC_CA0R_SDMASUP_NO_Val << SDHC_CA0R_SDMASUP_Pos)
-#define SDHC_CA0R_SDMASUP_YES (SDHC_CA0R_SDMASUP_YES_Val << SDHC_CA0R_SDMASUP_Pos)
-#define SDHC_CA0R_SRSUP_Pos 23 /**< \brief (SDHC_CA0R) Suspend/Resume Support */
-#define SDHC_CA0R_SRSUP (_U_(0x1) << SDHC_CA0R_SRSUP_Pos)
-#define SDHC_CA0R_SRSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) Suspend/Resume not Supported */
-#define SDHC_CA0R_SRSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) Suspend/Resume Supported */
-#define SDHC_CA0R_SRSUP_NO (SDHC_CA0R_SRSUP_NO_Val << SDHC_CA0R_SRSUP_Pos)
-#define SDHC_CA0R_SRSUP_YES (SDHC_CA0R_SRSUP_YES_Val << SDHC_CA0R_SRSUP_Pos)
-#define SDHC_CA0R_V33VSUP_Pos 24 /**< \brief (SDHC_CA0R) Voltage Support 3.3V */
-#define SDHC_CA0R_V33VSUP (_U_(0x1) << SDHC_CA0R_V33VSUP_Pos)
-#define SDHC_CA0R_V33VSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 3.3V Not Supported */
-#define SDHC_CA0R_V33VSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 3.3V Supported */
-#define SDHC_CA0R_V33VSUP_NO (SDHC_CA0R_V33VSUP_NO_Val << SDHC_CA0R_V33VSUP_Pos)
-#define SDHC_CA0R_V33VSUP_YES (SDHC_CA0R_V33VSUP_YES_Val << SDHC_CA0R_V33VSUP_Pos)
-#define SDHC_CA0R_V30VSUP_Pos 25 /**< \brief (SDHC_CA0R) Voltage Support 3.0V */
-#define SDHC_CA0R_V30VSUP (_U_(0x1) << SDHC_CA0R_V30VSUP_Pos)
-#define SDHC_CA0R_V30VSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 3.0V Not Supported */
-#define SDHC_CA0R_V30VSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 3.0V Supported */
-#define SDHC_CA0R_V30VSUP_NO (SDHC_CA0R_V30VSUP_NO_Val << SDHC_CA0R_V30VSUP_Pos)
-#define SDHC_CA0R_V30VSUP_YES (SDHC_CA0R_V30VSUP_YES_Val << SDHC_CA0R_V30VSUP_Pos)
-#define SDHC_CA0R_V18VSUP_Pos 26 /**< \brief (SDHC_CA0R) Voltage Support 1.8V */
-#define SDHC_CA0R_V18VSUP (_U_(0x1) << SDHC_CA0R_V18VSUP_Pos)
-#define SDHC_CA0R_V18VSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 1.8V Not Supported */
-#define SDHC_CA0R_V18VSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 1.8V Supported */
-#define SDHC_CA0R_V18VSUP_NO (SDHC_CA0R_V18VSUP_NO_Val << SDHC_CA0R_V18VSUP_Pos)
-#define SDHC_CA0R_V18VSUP_YES (SDHC_CA0R_V18VSUP_YES_Val << SDHC_CA0R_V18VSUP_Pos)
-#define SDHC_CA0R_SB64SUP_Pos 28 /**< \brief (SDHC_CA0R) 64-Bit System Bus Support */
-#define SDHC_CA0R_SB64SUP (_U_(0x1) << SDHC_CA0R_SB64SUP_Pos)
-#define SDHC_CA0R_SB64SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 32-bit Address Descriptors and System Bus */
-#define SDHC_CA0R_SB64SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 64-bit Address Descriptors and System Bus */
-#define SDHC_CA0R_SB64SUP_NO (SDHC_CA0R_SB64SUP_NO_Val << SDHC_CA0R_SB64SUP_Pos)
-#define SDHC_CA0R_SB64SUP_YES (SDHC_CA0R_SB64SUP_YES_Val << SDHC_CA0R_SB64SUP_Pos)
-#define SDHC_CA0R_ASINTSUP_Pos 29 /**< \brief (SDHC_CA0R) Asynchronous Interrupt Support */
-#define SDHC_CA0R_ASINTSUP (_U_(0x1) << SDHC_CA0R_ASINTSUP_Pos)
-#define SDHC_CA0R_ASINTSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) Asynchronous Interrupt not Supported */
-#define SDHC_CA0R_ASINTSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) Asynchronous Interrupt supported */
-#define SDHC_CA0R_ASINTSUP_NO (SDHC_CA0R_ASINTSUP_NO_Val << SDHC_CA0R_ASINTSUP_Pos)
-#define SDHC_CA0R_ASINTSUP_YES (SDHC_CA0R_ASINTSUP_YES_Val << SDHC_CA0R_ASINTSUP_Pos)
-#define SDHC_CA0R_SLTYPE_Pos 30 /**< \brief (SDHC_CA0R) Slot Type */
-#define SDHC_CA0R_SLTYPE_Msk (_U_(0x3) << SDHC_CA0R_SLTYPE_Pos)
-#define SDHC_CA0R_SLTYPE(value) (SDHC_CA0R_SLTYPE_Msk & ((value) << SDHC_CA0R_SLTYPE_Pos))
-#define SDHC_CA0R_SLTYPE_REMOVABLE_Val _U_(0x0) /**< \brief (SDHC_CA0R) Removable Card Slot */
-#define SDHC_CA0R_SLTYPE_EMBEDDED_Val _U_(0x1) /**< \brief (SDHC_CA0R) Embedded Slot for One Device */
-#define SDHC_CA0R_SLTYPE_REMOVABLE (SDHC_CA0R_SLTYPE_REMOVABLE_Val << SDHC_CA0R_SLTYPE_Pos)
-#define SDHC_CA0R_SLTYPE_EMBEDDED (SDHC_CA0R_SLTYPE_EMBEDDED_Val << SDHC_CA0R_SLTYPE_Pos)
-#define SDHC_CA0R_MASK _U_(0xF7EFFFBF) /**< \brief (SDHC_CA0R) MASK Register */
-
-/* -------- SDHC_CA1R : (SDHC Offset: 0x044) (R/ 32) Capabilities 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SDR50SUP:1; /*!< bit: 0 SDR50 Support */
- uint32_t SDR104SUP:1; /*!< bit: 1 SDR104 Support */
- uint32_t DDR50SUP:1; /*!< bit: 2 DDR50 Support */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t DRVASUP:1; /*!< bit: 4 Driver Type A Support */
- uint32_t DRVCSUP:1; /*!< bit: 5 Driver Type C Support */
- uint32_t DRVDSUP:1; /*!< bit: 6 Driver Type D Support */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t TCNTRT:4; /*!< bit: 8..11 Timer Count for Re-Tuning */
- uint32_t :1; /*!< bit: 12 Reserved */
- uint32_t TSDR50:1; /*!< bit: 13 Use Tuning for SDR50 */
- uint32_t :2; /*!< bit: 14..15 Reserved */
- uint32_t CLKMULT:8; /*!< bit: 16..23 Clock Multiplier */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SDHC_CA1R_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_CA1R_OFFSET 0x044 /**< \brief (SDHC_CA1R offset) Capabilities 1 */
-#define SDHC_CA1R_RESETVALUE _U_(0x00000070) /**< \brief (SDHC_CA1R reset_value) Capabilities 1 */
-
-#define SDHC_CA1R_SDR50SUP_Pos 0 /**< \brief (SDHC_CA1R) SDR50 Support */
-#define SDHC_CA1R_SDR50SUP (_U_(0x1) << SDHC_CA1R_SDR50SUP_Pos)
-#define SDHC_CA1R_SDR50SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) SDR50 is Not Supported */
-#define SDHC_CA1R_SDR50SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) SDR50 is Supported */
-#define SDHC_CA1R_SDR50SUP_NO (SDHC_CA1R_SDR50SUP_NO_Val << SDHC_CA1R_SDR50SUP_Pos)
-#define SDHC_CA1R_SDR50SUP_YES (SDHC_CA1R_SDR50SUP_YES_Val << SDHC_CA1R_SDR50SUP_Pos)
-#define SDHC_CA1R_SDR104SUP_Pos 1 /**< \brief (SDHC_CA1R) SDR104 Support */
-#define SDHC_CA1R_SDR104SUP (_U_(0x1) << SDHC_CA1R_SDR104SUP_Pos)
-#define SDHC_CA1R_SDR104SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) SDR104 is Not Supported */
-#define SDHC_CA1R_SDR104SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) SDR104 is Supported */
-#define SDHC_CA1R_SDR104SUP_NO (SDHC_CA1R_SDR104SUP_NO_Val << SDHC_CA1R_SDR104SUP_Pos)
-#define SDHC_CA1R_SDR104SUP_YES (SDHC_CA1R_SDR104SUP_YES_Val << SDHC_CA1R_SDR104SUP_Pos)
-#define SDHC_CA1R_DDR50SUP_Pos 2 /**< \brief (SDHC_CA1R) DDR50 Support */
-#define SDHC_CA1R_DDR50SUP (_U_(0x1) << SDHC_CA1R_DDR50SUP_Pos)
-#define SDHC_CA1R_DDR50SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) DDR50 is Not Supported */
-#define SDHC_CA1R_DDR50SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) DDR50 is Supported */
-#define SDHC_CA1R_DDR50SUP_NO (SDHC_CA1R_DDR50SUP_NO_Val << SDHC_CA1R_DDR50SUP_Pos)
-#define SDHC_CA1R_DDR50SUP_YES (SDHC_CA1R_DDR50SUP_YES_Val << SDHC_CA1R_DDR50SUP_Pos)
-#define SDHC_CA1R_DRVASUP_Pos 4 /**< \brief (SDHC_CA1R) Driver Type A Support */
-#define SDHC_CA1R_DRVASUP (_U_(0x1) << SDHC_CA1R_DRVASUP_Pos)
-#define SDHC_CA1R_DRVASUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) Driver Type A is Not Supported */
-#define SDHC_CA1R_DRVASUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) Driver Type A is Supported */
-#define SDHC_CA1R_DRVASUP_NO (SDHC_CA1R_DRVASUP_NO_Val << SDHC_CA1R_DRVASUP_Pos)
-#define SDHC_CA1R_DRVASUP_YES (SDHC_CA1R_DRVASUP_YES_Val << SDHC_CA1R_DRVASUP_Pos)
-#define SDHC_CA1R_DRVCSUP_Pos 5 /**< \brief (SDHC_CA1R) Driver Type C Support */
-#define SDHC_CA1R_DRVCSUP (_U_(0x1) << SDHC_CA1R_DRVCSUP_Pos)
-#define SDHC_CA1R_DRVCSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) Driver Type C is Not Supported */
-#define SDHC_CA1R_DRVCSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) Driver Type C is Supported */
-#define SDHC_CA1R_DRVCSUP_NO (SDHC_CA1R_DRVCSUP_NO_Val << SDHC_CA1R_DRVCSUP_Pos)
-#define SDHC_CA1R_DRVCSUP_YES (SDHC_CA1R_DRVCSUP_YES_Val << SDHC_CA1R_DRVCSUP_Pos)
-#define SDHC_CA1R_DRVDSUP_Pos 6 /**< \brief (SDHC_CA1R) Driver Type D Support */
-#define SDHC_CA1R_DRVDSUP (_U_(0x1) << SDHC_CA1R_DRVDSUP_Pos)
-#define SDHC_CA1R_DRVDSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) Driver Type D is Not Supported */
-#define SDHC_CA1R_DRVDSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) Driver Type D is Supported */
-#define SDHC_CA1R_DRVDSUP_NO (SDHC_CA1R_DRVDSUP_NO_Val << SDHC_CA1R_DRVDSUP_Pos)
-#define SDHC_CA1R_DRVDSUP_YES (SDHC_CA1R_DRVDSUP_YES_Val << SDHC_CA1R_DRVDSUP_Pos)
-#define SDHC_CA1R_TCNTRT_Pos 8 /**< \brief (SDHC_CA1R) Timer Count for Re-Tuning */
-#define SDHC_CA1R_TCNTRT_Msk (_U_(0xF) << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT(value) (SDHC_CA1R_TCNTRT_Msk & ((value) << SDHC_CA1R_TCNTRT_Pos))
-#define SDHC_CA1R_TCNTRT_DISABLED_Val _U_(0x0) /**< \brief (SDHC_CA1R) Re-Tuning Timer disabled */
-#define SDHC_CA1R_TCNTRT_1S_Val _U_(0x1) /**< \brief (SDHC_CA1R) 1 second */
-#define SDHC_CA1R_TCNTRT_2S_Val _U_(0x2) /**< \brief (SDHC_CA1R) 2 seconds */
-#define SDHC_CA1R_TCNTRT_4S_Val _U_(0x3) /**< \brief (SDHC_CA1R) 4 seconds */
-#define SDHC_CA1R_TCNTRT_8S_Val _U_(0x4) /**< \brief (SDHC_CA1R) 8 seconds */
-#define SDHC_CA1R_TCNTRT_16S_Val _U_(0x5) /**< \brief (SDHC_CA1R) 16 seconds */
-#define SDHC_CA1R_TCNTRT_32S_Val _U_(0x6) /**< \brief (SDHC_CA1R) 32 seconds */
-#define SDHC_CA1R_TCNTRT_64S_Val _U_(0x7) /**< \brief (SDHC_CA1R) 64 seconds */
-#define SDHC_CA1R_TCNTRT_128S_Val _U_(0x8) /**< \brief (SDHC_CA1R) 128 seconds */
-#define SDHC_CA1R_TCNTRT_256S_Val _U_(0x9) /**< \brief (SDHC_CA1R) 256 seconds */
-#define SDHC_CA1R_TCNTRT_512S_Val _U_(0xA) /**< \brief (SDHC_CA1R) 512 seconds */
-#define SDHC_CA1R_TCNTRT_1024S_Val _U_(0xB) /**< \brief (SDHC_CA1R) 1024 seconds */
-#define SDHC_CA1R_TCNTRT_OTHER_Val _U_(0xF) /**< \brief (SDHC_CA1R) Get information from other source */
-#define SDHC_CA1R_TCNTRT_DISABLED (SDHC_CA1R_TCNTRT_DISABLED_Val << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_1S (SDHC_CA1R_TCNTRT_1S_Val << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_2S (SDHC_CA1R_TCNTRT_2S_Val << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_4S (SDHC_CA1R_TCNTRT_4S_Val << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_8S (SDHC_CA1R_TCNTRT_8S_Val << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_16S (SDHC_CA1R_TCNTRT_16S_Val << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_32S (SDHC_CA1R_TCNTRT_32S_Val << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_64S (SDHC_CA1R_TCNTRT_64S_Val << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_128S (SDHC_CA1R_TCNTRT_128S_Val << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_256S (SDHC_CA1R_TCNTRT_256S_Val << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_512S (SDHC_CA1R_TCNTRT_512S_Val << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_1024S (SDHC_CA1R_TCNTRT_1024S_Val << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_OTHER (SDHC_CA1R_TCNTRT_OTHER_Val << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TSDR50_Pos 13 /**< \brief (SDHC_CA1R) Use Tuning for SDR50 */
-#define SDHC_CA1R_TSDR50 (_U_(0x1) << SDHC_CA1R_TSDR50_Pos)
-#define SDHC_CA1R_TSDR50_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) SDR50 does not require tuning */
-#define SDHC_CA1R_TSDR50_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) SDR50 requires tuning */
-#define SDHC_CA1R_TSDR50_NO (SDHC_CA1R_TSDR50_NO_Val << SDHC_CA1R_TSDR50_Pos)
-#define SDHC_CA1R_TSDR50_YES (SDHC_CA1R_TSDR50_YES_Val << SDHC_CA1R_TSDR50_Pos)
-#define SDHC_CA1R_CLKMULT_Pos 16 /**< \brief (SDHC_CA1R) Clock Multiplier */
-#define SDHC_CA1R_CLKMULT_Msk (_U_(0xFF) << SDHC_CA1R_CLKMULT_Pos)
-#define SDHC_CA1R_CLKMULT(value) (SDHC_CA1R_CLKMULT_Msk & ((value) << SDHC_CA1R_CLKMULT_Pos))
-#define SDHC_CA1R_CLKMULT_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) Clock Multiplier is Not Supported */
-#define SDHC_CA1R_CLKMULT_NO (SDHC_CA1R_CLKMULT_NO_Val << SDHC_CA1R_CLKMULT_Pos)
-#define SDHC_CA1R_MASK _U_(0x00FF2F77) /**< \brief (SDHC_CA1R) MASK Register */
-
-/* -------- SDHC_MCCAR : (SDHC Offset: 0x048) (R/ 32) Maximum Current Capabilities -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t MAXCUR33V:8; /*!< bit: 0.. 7 Maximum Current for 3.3V */
- uint32_t MAXCUR30V:8; /*!< bit: 8..15 Maximum Current for 3.0V */
- uint32_t MAXCUR18V:8; /*!< bit: 16..23 Maximum Current for 1.8V */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SDHC_MCCAR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_MCCAR_OFFSET 0x048 /**< \brief (SDHC_MCCAR offset) Maximum Current Capabilities */
-#define SDHC_MCCAR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_MCCAR reset_value) Maximum Current Capabilities */
-
-#define SDHC_MCCAR_MAXCUR33V_Pos 0 /**< \brief (SDHC_MCCAR) Maximum Current for 3.3V */
-#define SDHC_MCCAR_MAXCUR33V_Msk (_U_(0xFF) << SDHC_MCCAR_MAXCUR33V_Pos)
-#define SDHC_MCCAR_MAXCUR33V(value) (SDHC_MCCAR_MAXCUR33V_Msk & ((value) << SDHC_MCCAR_MAXCUR33V_Pos))
-#define SDHC_MCCAR_MAXCUR33V_OTHER_Val _U_(0x0) /**< \brief (SDHC_MCCAR) Get information via another method */
-#define SDHC_MCCAR_MAXCUR33V_4MA_Val _U_(0x1) /**< \brief (SDHC_MCCAR) 4mA */
-#define SDHC_MCCAR_MAXCUR33V_8MA_Val _U_(0x2) /**< \brief (SDHC_MCCAR) 8mA */
-#define SDHC_MCCAR_MAXCUR33V_12MA_Val _U_(0x3) /**< \brief (SDHC_MCCAR) 12mA */
-#define SDHC_MCCAR_MAXCUR33V_OTHER (SDHC_MCCAR_MAXCUR33V_OTHER_Val << SDHC_MCCAR_MAXCUR33V_Pos)
-#define SDHC_MCCAR_MAXCUR33V_4MA (SDHC_MCCAR_MAXCUR33V_4MA_Val << SDHC_MCCAR_MAXCUR33V_Pos)
-#define SDHC_MCCAR_MAXCUR33V_8MA (SDHC_MCCAR_MAXCUR33V_8MA_Val << SDHC_MCCAR_MAXCUR33V_Pos)
-#define SDHC_MCCAR_MAXCUR33V_12MA (SDHC_MCCAR_MAXCUR33V_12MA_Val << SDHC_MCCAR_MAXCUR33V_Pos)
-#define SDHC_MCCAR_MAXCUR30V_Pos 8 /**< \brief (SDHC_MCCAR) Maximum Current for 3.0V */
-#define SDHC_MCCAR_MAXCUR30V_Msk (_U_(0xFF) << SDHC_MCCAR_MAXCUR30V_Pos)
-#define SDHC_MCCAR_MAXCUR30V(value) (SDHC_MCCAR_MAXCUR30V_Msk & ((value) << SDHC_MCCAR_MAXCUR30V_Pos))
-#define SDHC_MCCAR_MAXCUR30V_OTHER_Val _U_(0x0) /**< \brief (SDHC_MCCAR) Get information via another method */
-#define SDHC_MCCAR_MAXCUR30V_4MA_Val _U_(0x1) /**< \brief (SDHC_MCCAR) 4mA */
-#define SDHC_MCCAR_MAXCUR30V_8MA_Val _U_(0x2) /**< \brief (SDHC_MCCAR) 8mA */
-#define SDHC_MCCAR_MAXCUR30V_12MA_Val _U_(0x3) /**< \brief (SDHC_MCCAR) 12mA */
-#define SDHC_MCCAR_MAXCUR30V_OTHER (SDHC_MCCAR_MAXCUR30V_OTHER_Val << SDHC_MCCAR_MAXCUR30V_Pos)
-#define SDHC_MCCAR_MAXCUR30V_4MA (SDHC_MCCAR_MAXCUR30V_4MA_Val << SDHC_MCCAR_MAXCUR30V_Pos)
-#define SDHC_MCCAR_MAXCUR30V_8MA (SDHC_MCCAR_MAXCUR30V_8MA_Val << SDHC_MCCAR_MAXCUR30V_Pos)
-#define SDHC_MCCAR_MAXCUR30V_12MA (SDHC_MCCAR_MAXCUR30V_12MA_Val << SDHC_MCCAR_MAXCUR30V_Pos)
-#define SDHC_MCCAR_MAXCUR18V_Pos 16 /**< \brief (SDHC_MCCAR) Maximum Current for 1.8V */
-#define SDHC_MCCAR_MAXCUR18V_Msk (_U_(0xFF) << SDHC_MCCAR_MAXCUR18V_Pos)
-#define SDHC_MCCAR_MAXCUR18V(value) (SDHC_MCCAR_MAXCUR18V_Msk & ((value) << SDHC_MCCAR_MAXCUR18V_Pos))
-#define SDHC_MCCAR_MAXCUR18V_OTHER_Val _U_(0x0) /**< \brief (SDHC_MCCAR) Get information via another method */
-#define SDHC_MCCAR_MAXCUR18V_4MA_Val _U_(0x1) /**< \brief (SDHC_MCCAR) 4mA */
-#define SDHC_MCCAR_MAXCUR18V_8MA_Val _U_(0x2) /**< \brief (SDHC_MCCAR) 8mA */
-#define SDHC_MCCAR_MAXCUR18V_12MA_Val _U_(0x3) /**< \brief (SDHC_MCCAR) 12mA */
-#define SDHC_MCCAR_MAXCUR18V_OTHER (SDHC_MCCAR_MAXCUR18V_OTHER_Val << SDHC_MCCAR_MAXCUR18V_Pos)
-#define SDHC_MCCAR_MAXCUR18V_4MA (SDHC_MCCAR_MAXCUR18V_4MA_Val << SDHC_MCCAR_MAXCUR18V_Pos)
-#define SDHC_MCCAR_MAXCUR18V_8MA (SDHC_MCCAR_MAXCUR18V_8MA_Val << SDHC_MCCAR_MAXCUR18V_Pos)
-#define SDHC_MCCAR_MAXCUR18V_12MA (SDHC_MCCAR_MAXCUR18V_12MA_Val << SDHC_MCCAR_MAXCUR18V_Pos)
-#define SDHC_MCCAR_MASK _U_(0x00FFFFFF) /**< \brief (SDHC_MCCAR) MASK Register */
-
-/* -------- SDHC_FERACES : (SDHC Offset: 0x050) ( /W 16) Force Event for Auto CMD Error Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t ACMD12NE:1; /*!< bit: 0 Force Event for Auto CMD12 Not Executed */
- uint16_t ACMDTEO:1; /*!< bit: 1 Force Event for Auto CMD Timeout Error */
- uint16_t ACMDCRC:1; /*!< bit: 2 Force Event for Auto CMD CRC Error */
- uint16_t ACMDEND:1; /*!< bit: 3 Force Event for Auto CMD End Bit Error */
- uint16_t ACMDIDX:1; /*!< bit: 4 Force Event for Auto CMD Index Error */
- uint16_t :2; /*!< bit: 5.. 6 Reserved */
- uint16_t CMDNI:1; /*!< bit: 7 Force Event for Command Not Issued By Auto CMD12 Error */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} SDHC_FERACES_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_FERACES_OFFSET 0x050 /**< \brief (SDHC_FERACES offset) Force Event for Auto CMD Error Status */
-#define SDHC_FERACES_RESETVALUE _U_(0x0000) /**< \brief (SDHC_FERACES reset_value) Force Event for Auto CMD Error Status */
-
-#define SDHC_FERACES_ACMD12NE_Pos 0 /**< \brief (SDHC_FERACES) Force Event for Auto CMD12 Not Executed */
-#define SDHC_FERACES_ACMD12NE (_U_(0x1) << SDHC_FERACES_ACMD12NE_Pos)
-#define SDHC_FERACES_ACMD12NE_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */
-#define SDHC_FERACES_ACMD12NE_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */
-#define SDHC_FERACES_ACMD12NE_NO (SDHC_FERACES_ACMD12NE_NO_Val << SDHC_FERACES_ACMD12NE_Pos)
-#define SDHC_FERACES_ACMD12NE_YES (SDHC_FERACES_ACMD12NE_YES_Val << SDHC_FERACES_ACMD12NE_Pos)
-#define SDHC_FERACES_ACMDTEO_Pos 1 /**< \brief (SDHC_FERACES) Force Event for Auto CMD Timeout Error */
-#define SDHC_FERACES_ACMDTEO (_U_(0x1) << SDHC_FERACES_ACMDTEO_Pos)
-#define SDHC_FERACES_ACMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */
-#define SDHC_FERACES_ACMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */
-#define SDHC_FERACES_ACMDTEO_NO (SDHC_FERACES_ACMDTEO_NO_Val << SDHC_FERACES_ACMDTEO_Pos)
-#define SDHC_FERACES_ACMDTEO_YES (SDHC_FERACES_ACMDTEO_YES_Val << SDHC_FERACES_ACMDTEO_Pos)
-#define SDHC_FERACES_ACMDCRC_Pos 2 /**< \brief (SDHC_FERACES) Force Event for Auto CMD CRC Error */
-#define SDHC_FERACES_ACMDCRC (_U_(0x1) << SDHC_FERACES_ACMDCRC_Pos)
-#define SDHC_FERACES_ACMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */
-#define SDHC_FERACES_ACMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */
-#define SDHC_FERACES_ACMDCRC_NO (SDHC_FERACES_ACMDCRC_NO_Val << SDHC_FERACES_ACMDCRC_Pos)
-#define SDHC_FERACES_ACMDCRC_YES (SDHC_FERACES_ACMDCRC_YES_Val << SDHC_FERACES_ACMDCRC_Pos)
-#define SDHC_FERACES_ACMDEND_Pos 3 /**< \brief (SDHC_FERACES) Force Event for Auto CMD End Bit Error */
-#define SDHC_FERACES_ACMDEND (_U_(0x1) << SDHC_FERACES_ACMDEND_Pos)
-#define SDHC_FERACES_ACMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */
-#define SDHC_FERACES_ACMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */
-#define SDHC_FERACES_ACMDEND_NO (SDHC_FERACES_ACMDEND_NO_Val << SDHC_FERACES_ACMDEND_Pos)
-#define SDHC_FERACES_ACMDEND_YES (SDHC_FERACES_ACMDEND_YES_Val << SDHC_FERACES_ACMDEND_Pos)
-#define SDHC_FERACES_ACMDIDX_Pos 4 /**< \brief (SDHC_FERACES) Force Event for Auto CMD Index Error */
-#define SDHC_FERACES_ACMDIDX (_U_(0x1) << SDHC_FERACES_ACMDIDX_Pos)
-#define SDHC_FERACES_ACMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */
-#define SDHC_FERACES_ACMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */
-#define SDHC_FERACES_ACMDIDX_NO (SDHC_FERACES_ACMDIDX_NO_Val << SDHC_FERACES_ACMDIDX_Pos)
-#define SDHC_FERACES_ACMDIDX_YES (SDHC_FERACES_ACMDIDX_YES_Val << SDHC_FERACES_ACMDIDX_Pos)
-#define SDHC_FERACES_CMDNI_Pos 7 /**< \brief (SDHC_FERACES) Force Event for Command Not Issued By Auto CMD12 Error */
-#define SDHC_FERACES_CMDNI (_U_(0x1) << SDHC_FERACES_CMDNI_Pos)
-#define SDHC_FERACES_CMDNI_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */
-#define SDHC_FERACES_CMDNI_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */
-#define SDHC_FERACES_CMDNI_NO (SDHC_FERACES_CMDNI_NO_Val << SDHC_FERACES_CMDNI_Pos)
-#define SDHC_FERACES_CMDNI_YES (SDHC_FERACES_CMDNI_YES_Val << SDHC_FERACES_CMDNI_Pos)
-#define SDHC_FERACES_MASK _U_(0x009F) /**< \brief (SDHC_FERACES) MASK Register */
-
-/* -------- SDHC_FEREIS : (SDHC Offset: 0x052) ( /W 16) Force Event for Error Interrupt Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t CMDTEO:1; /*!< bit: 0 Force Event for Command Timeout Error */
- uint16_t CMDCRC:1; /*!< bit: 1 Force Event for Command CRC Error */
- uint16_t CMDEND:1; /*!< bit: 2 Force Event for Command End Bit Error */
- uint16_t CMDIDX:1; /*!< bit: 3 Force Event for Command Index Error */
- uint16_t DATTEO:1; /*!< bit: 4 Force Event for Data Timeout Error */
- uint16_t DATCRC:1; /*!< bit: 5 Force Event for Data CRC Error */
- uint16_t DATEND:1; /*!< bit: 6 Force Event for Data End Bit Error */
- uint16_t CURLIM:1; /*!< bit: 7 Force Event for Current Limit Error */
- uint16_t ACMD:1; /*!< bit: 8 Force Event for Auto CMD Error */
- uint16_t ADMA:1; /*!< bit: 9 Force Event for ADMA Error */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t BOOTAE:1; /*!< bit: 12 Force Event for Boot Acknowledge Error */
- uint16_t :3; /*!< bit: 13..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} SDHC_FEREIS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_FEREIS_OFFSET 0x052 /**< \brief (SDHC_FEREIS offset) Force Event for Error Interrupt Status */
-#define SDHC_FEREIS_RESETVALUE _U_(0x0000) /**< \brief (SDHC_FEREIS reset_value) Force Event for Error Interrupt Status */
-
-#define SDHC_FEREIS_CMDTEO_Pos 0 /**< \brief (SDHC_FEREIS) Force Event for Command Timeout Error */
-#define SDHC_FEREIS_CMDTEO (_U_(0x1) << SDHC_FEREIS_CMDTEO_Pos)
-#define SDHC_FEREIS_CMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
-#define SDHC_FEREIS_CMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_CMDTEO_NO (SDHC_FEREIS_CMDTEO_NO_Val << SDHC_FEREIS_CMDTEO_Pos)
-#define SDHC_FEREIS_CMDTEO_YES (SDHC_FEREIS_CMDTEO_YES_Val << SDHC_FEREIS_CMDTEO_Pos)
-#define SDHC_FEREIS_CMDCRC_Pos 1 /**< \brief (SDHC_FEREIS) Force Event for Command CRC Error */
-#define SDHC_FEREIS_CMDCRC (_U_(0x1) << SDHC_FEREIS_CMDCRC_Pos)
-#define SDHC_FEREIS_CMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
-#define SDHC_FEREIS_CMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_CMDCRC_NO (SDHC_FEREIS_CMDCRC_NO_Val << SDHC_FEREIS_CMDCRC_Pos)
-#define SDHC_FEREIS_CMDCRC_YES (SDHC_FEREIS_CMDCRC_YES_Val << SDHC_FEREIS_CMDCRC_Pos)
-#define SDHC_FEREIS_CMDEND_Pos 2 /**< \brief (SDHC_FEREIS) Force Event for Command End Bit Error */
-#define SDHC_FEREIS_CMDEND (_U_(0x1) << SDHC_FEREIS_CMDEND_Pos)
-#define SDHC_FEREIS_CMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
-#define SDHC_FEREIS_CMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_CMDEND_NO (SDHC_FEREIS_CMDEND_NO_Val << SDHC_FEREIS_CMDEND_Pos)
-#define SDHC_FEREIS_CMDEND_YES (SDHC_FEREIS_CMDEND_YES_Val << SDHC_FEREIS_CMDEND_Pos)
-#define SDHC_FEREIS_CMDIDX_Pos 3 /**< \brief (SDHC_FEREIS) Force Event for Command Index Error */
-#define SDHC_FEREIS_CMDIDX (_U_(0x1) << SDHC_FEREIS_CMDIDX_Pos)
-#define SDHC_FEREIS_CMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
-#define SDHC_FEREIS_CMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_CMDIDX_NO (SDHC_FEREIS_CMDIDX_NO_Val << SDHC_FEREIS_CMDIDX_Pos)
-#define SDHC_FEREIS_CMDIDX_YES (SDHC_FEREIS_CMDIDX_YES_Val << SDHC_FEREIS_CMDIDX_Pos)
-#define SDHC_FEREIS_DATTEO_Pos 4 /**< \brief (SDHC_FEREIS) Force Event for Data Timeout Error */
-#define SDHC_FEREIS_DATTEO (_U_(0x1) << SDHC_FEREIS_DATTEO_Pos)
-#define SDHC_FEREIS_DATTEO_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
-#define SDHC_FEREIS_DATTEO_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_DATTEO_NO (SDHC_FEREIS_DATTEO_NO_Val << SDHC_FEREIS_DATTEO_Pos)
-#define SDHC_FEREIS_DATTEO_YES (SDHC_FEREIS_DATTEO_YES_Val << SDHC_FEREIS_DATTEO_Pos)
-#define SDHC_FEREIS_DATCRC_Pos 5 /**< \brief (SDHC_FEREIS) Force Event for Data CRC Error */
-#define SDHC_FEREIS_DATCRC (_U_(0x1) << SDHC_FEREIS_DATCRC_Pos)
-#define SDHC_FEREIS_DATCRC_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
-#define SDHC_FEREIS_DATCRC_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_DATCRC_NO (SDHC_FEREIS_DATCRC_NO_Val << SDHC_FEREIS_DATCRC_Pos)
-#define SDHC_FEREIS_DATCRC_YES (SDHC_FEREIS_DATCRC_YES_Val << SDHC_FEREIS_DATCRC_Pos)
-#define SDHC_FEREIS_DATEND_Pos 6 /**< \brief (SDHC_FEREIS) Force Event for Data End Bit Error */
-#define SDHC_FEREIS_DATEND (_U_(0x1) << SDHC_FEREIS_DATEND_Pos)
-#define SDHC_FEREIS_DATEND_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
-#define SDHC_FEREIS_DATEND_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_DATEND_NO (SDHC_FEREIS_DATEND_NO_Val << SDHC_FEREIS_DATEND_Pos)
-#define SDHC_FEREIS_DATEND_YES (SDHC_FEREIS_DATEND_YES_Val << SDHC_FEREIS_DATEND_Pos)
-#define SDHC_FEREIS_CURLIM_Pos 7 /**< \brief (SDHC_FEREIS) Force Event for Current Limit Error */
-#define SDHC_FEREIS_CURLIM (_U_(0x1) << SDHC_FEREIS_CURLIM_Pos)
-#define SDHC_FEREIS_CURLIM_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
-#define SDHC_FEREIS_CURLIM_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_CURLIM_NO (SDHC_FEREIS_CURLIM_NO_Val << SDHC_FEREIS_CURLIM_Pos)
-#define SDHC_FEREIS_CURLIM_YES (SDHC_FEREIS_CURLIM_YES_Val << SDHC_FEREIS_CURLIM_Pos)
-#define SDHC_FEREIS_ACMD_Pos 8 /**< \brief (SDHC_FEREIS) Force Event for Auto CMD Error */
-#define SDHC_FEREIS_ACMD (_U_(0x1) << SDHC_FEREIS_ACMD_Pos)
-#define SDHC_FEREIS_ACMD_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
-#define SDHC_FEREIS_ACMD_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_ACMD_NO (SDHC_FEREIS_ACMD_NO_Val << SDHC_FEREIS_ACMD_Pos)
-#define SDHC_FEREIS_ACMD_YES (SDHC_FEREIS_ACMD_YES_Val << SDHC_FEREIS_ACMD_Pos)
-#define SDHC_FEREIS_ADMA_Pos 9 /**< \brief (SDHC_FEREIS) Force Event for ADMA Error */
-#define SDHC_FEREIS_ADMA (_U_(0x1) << SDHC_FEREIS_ADMA_Pos)
-#define SDHC_FEREIS_ADMA_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
-#define SDHC_FEREIS_ADMA_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_ADMA_NO (SDHC_FEREIS_ADMA_NO_Val << SDHC_FEREIS_ADMA_Pos)
-#define SDHC_FEREIS_ADMA_YES (SDHC_FEREIS_ADMA_YES_Val << SDHC_FEREIS_ADMA_Pos)
-#define SDHC_FEREIS_BOOTAE_Pos 12 /**< \brief (SDHC_FEREIS) Force Event for Boot Acknowledge Error */
-#define SDHC_FEREIS_BOOTAE (_U_(0x1) << SDHC_FEREIS_BOOTAE_Pos)
-#define SDHC_FEREIS_BOOTAE_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
-#define SDHC_FEREIS_BOOTAE_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_BOOTAE_NO (SDHC_FEREIS_BOOTAE_NO_Val << SDHC_FEREIS_BOOTAE_Pos)
-#define SDHC_FEREIS_BOOTAE_YES (SDHC_FEREIS_BOOTAE_YES_Val << SDHC_FEREIS_BOOTAE_Pos)
-#define SDHC_FEREIS_MASK _U_(0x13FF) /**< \brief (SDHC_FEREIS) MASK Register */
-
-/* -------- SDHC_AESR : (SDHC Offset: 0x054) (R/ 8) ADMA Error Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t ERRST:2; /*!< bit: 0.. 1 ADMA Error State */
- uint8_t LMIS:1; /*!< bit: 2 ADMA Length Mismatch Error */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SDHC_AESR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_AESR_OFFSET 0x054 /**< \brief (SDHC_AESR offset) ADMA Error Status */
-#define SDHC_AESR_RESETVALUE _U_(0x00) /**< \brief (SDHC_AESR reset_value) ADMA Error Status */
-
-#define SDHC_AESR_ERRST_Pos 0 /**< \brief (SDHC_AESR) ADMA Error State */
-#define SDHC_AESR_ERRST_Msk (_U_(0x3) << SDHC_AESR_ERRST_Pos)
-#define SDHC_AESR_ERRST(value) (SDHC_AESR_ERRST_Msk & ((value) << SDHC_AESR_ERRST_Pos))
-#define SDHC_AESR_ERRST_STOP_Val _U_(0x0) /**< \brief (SDHC_AESR) ST_STOP (Stop DMA) */
-#define SDHC_AESR_ERRST_FDS_Val _U_(0x1) /**< \brief (SDHC_AESR) ST_FDS (Fetch Descriptor) */
-#define SDHC_AESR_ERRST_2_Val _U_(0x2) /**< \brief (SDHC_AESR) Reserved */
-#define SDHC_AESR_ERRST_TFR_Val _U_(0x3) /**< \brief (SDHC_AESR) ST_TFR (Transfer Data) */
-#define SDHC_AESR_ERRST_STOP (SDHC_AESR_ERRST_STOP_Val << SDHC_AESR_ERRST_Pos)
-#define SDHC_AESR_ERRST_FDS (SDHC_AESR_ERRST_FDS_Val << SDHC_AESR_ERRST_Pos)
-#define SDHC_AESR_ERRST_2 (SDHC_AESR_ERRST_2_Val << SDHC_AESR_ERRST_Pos)
-#define SDHC_AESR_ERRST_TFR (SDHC_AESR_ERRST_TFR_Val << SDHC_AESR_ERRST_Pos)
-#define SDHC_AESR_LMIS_Pos 2 /**< \brief (SDHC_AESR) ADMA Length Mismatch Error */
-#define SDHC_AESR_LMIS (_U_(0x1) << SDHC_AESR_LMIS_Pos)
-#define SDHC_AESR_LMIS_NO_Val _U_(0x0) /**< \brief (SDHC_AESR) No Error */
-#define SDHC_AESR_LMIS_YES_Val _U_(0x1) /**< \brief (SDHC_AESR) Error */
-#define SDHC_AESR_LMIS_NO (SDHC_AESR_LMIS_NO_Val << SDHC_AESR_LMIS_Pos)
-#define SDHC_AESR_LMIS_YES (SDHC_AESR_LMIS_YES_Val << SDHC_AESR_LMIS_Pos)
-#define SDHC_AESR_MASK _U_(0x07) /**< \brief (SDHC_AESR) MASK Register */
-
-/* -------- SDHC_ASAR : (SDHC Offset: 0x058) (R/W 32) ADMA System Address n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ADMASA:32; /*!< bit: 0..31 ADMA System Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SDHC_ASAR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_ASAR_OFFSET 0x058 /**< \brief (SDHC_ASAR offset) ADMA System Address n */
-#define SDHC_ASAR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_ASAR reset_value) ADMA System Address n */
-
-#define SDHC_ASAR_ADMASA_Pos 0 /**< \brief (SDHC_ASAR) ADMA System Address */
-#define SDHC_ASAR_ADMASA_Msk (_U_(0xFFFFFFFF) << SDHC_ASAR_ADMASA_Pos)
-#define SDHC_ASAR_ADMASA(value) (SDHC_ASAR_ADMASA_Msk & ((value) << SDHC_ASAR_ADMASA_Pos))
-#define SDHC_ASAR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_ASAR) MASK Register */
-
-/* -------- SDHC_PVR : (SDHC Offset: 0x060) (R/W 16) Preset Value n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t SDCLKFSEL:10; /*!< bit: 0.. 9 SDCLK Frequency Select Value for Initialization */
- uint16_t CLKGSEL:1; /*!< bit: 10 Clock Generator Select Value for Initialization */
- uint16_t :3; /*!< bit: 11..13 Reserved */
- uint16_t DRVSEL:2; /*!< bit: 14..15 Driver Strength Select Value for Initialization */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} SDHC_PVR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_PVR_OFFSET 0x060 /**< \brief (SDHC_PVR offset) Preset Value n */
-#define SDHC_PVR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_PVR reset_value) Preset Value n */
-
-#define SDHC_PVR_SDCLKFSEL_Pos 0 /**< \brief (SDHC_PVR) SDCLK Frequency Select Value for Initialization */
-#define SDHC_PVR_SDCLKFSEL_Msk (_U_(0x3FF) << SDHC_PVR_SDCLKFSEL_Pos)
-#define SDHC_PVR_SDCLKFSEL(value) (SDHC_PVR_SDCLKFSEL_Msk & ((value) << SDHC_PVR_SDCLKFSEL_Pos))
-#define SDHC_PVR_CLKGSEL_Pos 10 /**< \brief (SDHC_PVR) Clock Generator Select Value for Initialization */
-#define SDHC_PVR_CLKGSEL (_U_(0x1) << SDHC_PVR_CLKGSEL_Pos)
-#define SDHC_PVR_CLKGSEL_DIV_Val _U_(0x0) /**< \brief (SDHC_PVR) Host Controller Ver2.00 Compatible Clock Generator (Divider) */
-#define SDHC_PVR_CLKGSEL_PROG_Val _U_(0x1) /**< \brief (SDHC_PVR) Programmable Clock Generator */
-#define SDHC_PVR_CLKGSEL_DIV (SDHC_PVR_CLKGSEL_DIV_Val << SDHC_PVR_CLKGSEL_Pos)
-#define SDHC_PVR_CLKGSEL_PROG (SDHC_PVR_CLKGSEL_PROG_Val << SDHC_PVR_CLKGSEL_Pos)
-#define SDHC_PVR_DRVSEL_Pos 14 /**< \brief (SDHC_PVR) Driver Strength Select Value for Initialization */
-#define SDHC_PVR_DRVSEL_Msk (_U_(0x3) << SDHC_PVR_DRVSEL_Pos)
-#define SDHC_PVR_DRVSEL(value) (SDHC_PVR_DRVSEL_Msk & ((value) << SDHC_PVR_DRVSEL_Pos))
-#define SDHC_PVR_DRVSEL_B_Val _U_(0x0) /**< \brief (SDHC_PVR) Driver Type B is Selected */
-#define SDHC_PVR_DRVSEL_A_Val _U_(0x1) /**< \brief (SDHC_PVR) Driver Type A is Selected */
-#define SDHC_PVR_DRVSEL_C_Val _U_(0x2) /**< \brief (SDHC_PVR) Driver Type C is Selected */
-#define SDHC_PVR_DRVSEL_D_Val _U_(0x3) /**< \brief (SDHC_PVR) Driver Type D is Selected */
-#define SDHC_PVR_DRVSEL_B (SDHC_PVR_DRVSEL_B_Val << SDHC_PVR_DRVSEL_Pos)
-#define SDHC_PVR_DRVSEL_A (SDHC_PVR_DRVSEL_A_Val << SDHC_PVR_DRVSEL_Pos)
-#define SDHC_PVR_DRVSEL_C (SDHC_PVR_DRVSEL_C_Val << SDHC_PVR_DRVSEL_Pos)
-#define SDHC_PVR_DRVSEL_D (SDHC_PVR_DRVSEL_D_Val << SDHC_PVR_DRVSEL_Pos)
-#define SDHC_PVR_MASK _U_(0xC7FF) /**< \brief (SDHC_PVR) MASK Register */
-
-/* -------- SDHC_SISR : (SDHC Offset: 0x0FC) (R/ 16) Slot Interrupt Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t INTSSL:1; /*!< bit: 0 Interrupt Signal for Each Slot */
- uint16_t :15; /*!< bit: 1..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} SDHC_SISR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_SISR_OFFSET 0x0FC /**< \brief (SDHC_SISR offset) Slot Interrupt Status */
-#define SDHC_SISR_RESETVALUE _U_(0x20000) /**< \brief (SDHC_SISR reset_value) Slot Interrupt Status */
-
-#define SDHC_SISR_INTSSL_Pos 0 /**< \brief (SDHC_SISR) Interrupt Signal for Each Slot */
-#define SDHC_SISR_INTSSL_Msk (_U_(0x1) << SDHC_SISR_INTSSL_Pos)
-#define SDHC_SISR_INTSSL(value) (SDHC_SISR_INTSSL_Msk & ((value) << SDHC_SISR_INTSSL_Pos))
-#define SDHC_SISR_MASK _U_(0x0001) /**< \brief (SDHC_SISR) MASK Register */
-
-/* -------- SDHC_HCVR : (SDHC Offset: 0x0FE) (R/ 16) Host Controller Version -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t SVER:8; /*!< bit: 0.. 7 Spec Version */
- uint16_t VVER:8; /*!< bit: 8..15 Vendor Version */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} SDHC_HCVR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_HCVR_OFFSET 0x0FE /**< \brief (SDHC_HCVR offset) Host Controller Version */
-#define SDHC_HCVR_RESETVALUE _U_(0x1802) /**< \brief (SDHC_HCVR reset_value) Host Controller Version */
-
-#define SDHC_HCVR_SVER_Pos 0 /**< \brief (SDHC_HCVR) Spec Version */
-#define SDHC_HCVR_SVER_Msk (_U_(0xFF) << SDHC_HCVR_SVER_Pos)
-#define SDHC_HCVR_SVER(value) (SDHC_HCVR_SVER_Msk & ((value) << SDHC_HCVR_SVER_Pos))
-#define SDHC_HCVR_VVER_Pos 8 /**< \brief (SDHC_HCVR) Vendor Version */
-#define SDHC_HCVR_VVER_Msk (_U_(0xFF) << SDHC_HCVR_VVER_Pos)
-#define SDHC_HCVR_VVER(value) (SDHC_HCVR_VVER_Msk & ((value) << SDHC_HCVR_VVER_Pos))
-#define SDHC_HCVR_MASK _U_(0xFFFF) /**< \brief (SDHC_HCVR) MASK Register */
-
-/* -------- SDHC_MC1R : (SDHC Offset: 0x204) (R/W 8) MMC Control 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t CMDTYP:2; /*!< bit: 0.. 1 e.MMC Command Type */
- uint8_t :1; /*!< bit: 2 Reserved */
- uint8_t DDR:1; /*!< bit: 3 e.MMC HSDDR Mode */
- uint8_t OPD:1; /*!< bit: 4 e.MMC Open Drain Mode */
- uint8_t BOOTA:1; /*!< bit: 5 e.MMC Boot Acknowledge Enable */
- uint8_t RSTN:1; /*!< bit: 6 e.MMC Reset Signal */
- uint8_t FCD:1; /*!< bit: 7 e.MMC Force Card Detect */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SDHC_MC1R_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_MC1R_OFFSET 0x204 /**< \brief (SDHC_MC1R offset) MMC Control 1 */
-#define SDHC_MC1R_RESETVALUE _U_(0x00) /**< \brief (SDHC_MC1R reset_value) MMC Control 1 */
-
-#define SDHC_MC1R_CMDTYP_Pos 0 /**< \brief (SDHC_MC1R) e.MMC Command Type */
-#define SDHC_MC1R_CMDTYP_Msk (_U_(0x3) << SDHC_MC1R_CMDTYP_Pos)
-#define SDHC_MC1R_CMDTYP(value) (SDHC_MC1R_CMDTYP_Msk & ((value) << SDHC_MC1R_CMDTYP_Pos))
-#define SDHC_MC1R_CMDTYP_NORMAL_Val _U_(0x0) /**< \brief (SDHC_MC1R) Not a MMC specific command */
-#define SDHC_MC1R_CMDTYP_WAITIRQ_Val _U_(0x1) /**< \brief (SDHC_MC1R) Wait IRQ Command */
-#define SDHC_MC1R_CMDTYP_STREAM_Val _U_(0x2) /**< \brief (SDHC_MC1R) Stream Command */
-#define SDHC_MC1R_CMDTYP_BOOT_Val _U_(0x3) /**< \brief (SDHC_MC1R) Boot Command */
-#define SDHC_MC1R_CMDTYP_NORMAL (SDHC_MC1R_CMDTYP_NORMAL_Val << SDHC_MC1R_CMDTYP_Pos)
-#define SDHC_MC1R_CMDTYP_WAITIRQ (SDHC_MC1R_CMDTYP_WAITIRQ_Val << SDHC_MC1R_CMDTYP_Pos)
-#define SDHC_MC1R_CMDTYP_STREAM (SDHC_MC1R_CMDTYP_STREAM_Val << SDHC_MC1R_CMDTYP_Pos)
-#define SDHC_MC1R_CMDTYP_BOOT (SDHC_MC1R_CMDTYP_BOOT_Val << SDHC_MC1R_CMDTYP_Pos)
-#define SDHC_MC1R_DDR_Pos 3 /**< \brief (SDHC_MC1R) e.MMC HSDDR Mode */
-#define SDHC_MC1R_DDR (_U_(0x1) << SDHC_MC1R_DDR_Pos)
-#define SDHC_MC1R_OPD_Pos 4 /**< \brief (SDHC_MC1R) e.MMC Open Drain Mode */
-#define SDHC_MC1R_OPD (_U_(0x1) << SDHC_MC1R_OPD_Pos)
-#define SDHC_MC1R_BOOTA_Pos 5 /**< \brief (SDHC_MC1R) e.MMC Boot Acknowledge Enable */
-#define SDHC_MC1R_BOOTA (_U_(0x1) << SDHC_MC1R_BOOTA_Pos)
-#define SDHC_MC1R_RSTN_Pos 6 /**< \brief (SDHC_MC1R) e.MMC Reset Signal */
-#define SDHC_MC1R_RSTN (_U_(0x1) << SDHC_MC1R_RSTN_Pos)
-#define SDHC_MC1R_FCD_Pos 7 /**< \brief (SDHC_MC1R) e.MMC Force Card Detect */
-#define SDHC_MC1R_FCD (_U_(0x1) << SDHC_MC1R_FCD_Pos)
-#define SDHC_MC1R_MASK _U_(0xFB) /**< \brief (SDHC_MC1R) MASK Register */
-
-/* -------- SDHC_MC2R : (SDHC Offset: 0x205) ( /W 8) MMC Control 2 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SRESP:1; /*!< bit: 0 e.MMC Abort Wait IRQ */
- uint8_t ABOOT:1; /*!< bit: 1 e.MMC Abort Boot */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SDHC_MC2R_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_MC2R_OFFSET 0x205 /**< \brief (SDHC_MC2R offset) MMC Control 2 */
-#define SDHC_MC2R_RESETVALUE _U_(0x00) /**< \brief (SDHC_MC2R reset_value) MMC Control 2 */
-
-#define SDHC_MC2R_SRESP_Pos 0 /**< \brief (SDHC_MC2R) e.MMC Abort Wait IRQ */
-#define SDHC_MC2R_SRESP (_U_(0x1) << SDHC_MC2R_SRESP_Pos)
-#define SDHC_MC2R_ABOOT_Pos 1 /**< \brief (SDHC_MC2R) e.MMC Abort Boot */
-#define SDHC_MC2R_ABOOT (_U_(0x1) << SDHC_MC2R_ABOOT_Pos)
-#define SDHC_MC2R_MASK _U_(0x03) /**< \brief (SDHC_MC2R) MASK Register */
-
-/* -------- SDHC_ACR : (SDHC Offset: 0x208) (R/W 32) AHB Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t BMAX:2; /*!< bit: 0.. 1 AHB Maximum Burst */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SDHC_ACR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_ACR_OFFSET 0x208 /**< \brief (SDHC_ACR offset) AHB Control */
-#define SDHC_ACR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_ACR reset_value) AHB Control */
-
-#define SDHC_ACR_BMAX_Pos 0 /**< \brief (SDHC_ACR) AHB Maximum Burst */
-#define SDHC_ACR_BMAX_Msk (_U_(0x3) << SDHC_ACR_BMAX_Pos)
-#define SDHC_ACR_BMAX(value) (SDHC_ACR_BMAX_Msk & ((value) << SDHC_ACR_BMAX_Pos))
-#define SDHC_ACR_BMAX_INCR16_Val _U_(0x0) /**< \brief (SDHC_ACR) */
-#define SDHC_ACR_BMAX_INCR8_Val _U_(0x1) /**< \brief (SDHC_ACR) */
-#define SDHC_ACR_BMAX_INCR4_Val _U_(0x2) /**< \brief (SDHC_ACR) */
-#define SDHC_ACR_BMAX_SINGLE_Val _U_(0x3) /**< \brief (SDHC_ACR) */
-#define SDHC_ACR_BMAX_INCR16 (SDHC_ACR_BMAX_INCR16_Val << SDHC_ACR_BMAX_Pos)
-#define SDHC_ACR_BMAX_INCR8 (SDHC_ACR_BMAX_INCR8_Val << SDHC_ACR_BMAX_Pos)
-#define SDHC_ACR_BMAX_INCR4 (SDHC_ACR_BMAX_INCR4_Val << SDHC_ACR_BMAX_Pos)
-#define SDHC_ACR_BMAX_SINGLE (SDHC_ACR_BMAX_SINGLE_Val << SDHC_ACR_BMAX_Pos)
-#define SDHC_ACR_MASK _U_(0x00000003) /**< \brief (SDHC_ACR) MASK Register */
-
-/* -------- SDHC_CC2R : (SDHC Offset: 0x20C) (R/W 32) Clock Control 2 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t FSDCLKD:1; /*!< bit: 0 Force SDCK Disabled */
- uint32_t :31; /*!< bit: 1..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SDHC_CC2R_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_CC2R_OFFSET 0x20C /**< \brief (SDHC_CC2R offset) Clock Control 2 */
-#define SDHC_CC2R_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_CC2R reset_value) Clock Control 2 */
-
-#define SDHC_CC2R_FSDCLKD_Pos 0 /**< \brief (SDHC_CC2R) Force SDCK Disabled */
-#define SDHC_CC2R_FSDCLKD (_U_(0x1) << SDHC_CC2R_FSDCLKD_Pos)
-#define SDHC_CC2R_FSDCLKD_NOEFFECT_Val _U_(0x0) /**< \brief (SDHC_CC2R) No effect */
-#define SDHC_CC2R_FSDCLKD_DISABLE_Val _U_(0x1) /**< \brief (SDHC_CC2R) SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled */
-#define SDHC_CC2R_FSDCLKD_NOEFFECT (SDHC_CC2R_FSDCLKD_NOEFFECT_Val << SDHC_CC2R_FSDCLKD_Pos)
-#define SDHC_CC2R_FSDCLKD_DISABLE (SDHC_CC2R_FSDCLKD_DISABLE_Val << SDHC_CC2R_FSDCLKD_Pos)
-#define SDHC_CC2R_MASK _U_(0x00000001) /**< \brief (SDHC_CC2R) MASK Register */
-
-/* -------- SDHC_CACR : (SDHC Offset: 0x230) (R/W 32) Capabilities Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CAPWREN:1; /*!< bit: 0 Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) */
- uint32_t :7; /*!< bit: 1.. 7 Reserved */
- uint32_t KEY:8; /*!< bit: 8..15 Key (0x46) */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SDHC_CACR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_CACR_OFFSET 0x230 /**< \brief (SDHC_CACR offset) Capabilities Control */
-#define SDHC_CACR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_CACR reset_value) Capabilities Control */
-
-#define SDHC_CACR_CAPWREN_Pos 0 /**< \brief (SDHC_CACR) Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) */
-#define SDHC_CACR_CAPWREN (_U_(0x1) << SDHC_CACR_CAPWREN_Pos)
-#define SDHC_CACR_KEY_Pos 8 /**< \brief (SDHC_CACR) Key (0x46) */
-#define SDHC_CACR_KEY_Msk (_U_(0xFF) << SDHC_CACR_KEY_Pos)
-#define SDHC_CACR_KEY(value) (SDHC_CACR_KEY_Msk & ((value) << SDHC_CACR_KEY_Pos))
-#define SDHC_CACR_MASK _U_(0x0000FF01) /**< \brief (SDHC_CACR) MASK Register */
-
-/* -------- SDHC_DBGR : (SDHC Offset: 0x234) (R/W 8) Debug -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t NIDBG:1; /*!< bit: 0 Non-intrusive debug enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SDHC_DBGR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_DBGR_OFFSET 0x234 /**< \brief (SDHC_DBGR offset) Debug */
-#define SDHC_DBGR_RESETVALUE _U_(0x00) /**< \brief (SDHC_DBGR reset_value) Debug */
-
-#define SDHC_DBGR_NIDBG_Pos 0 /**< \brief (SDHC_DBGR) Non-intrusive debug enable */
-#define SDHC_DBGR_NIDBG (_U_(0x1) << SDHC_DBGR_NIDBG_Pos)
-#define SDHC_DBGR_NIDBG_IDBG_Val _U_(0x0) /**< \brief (SDHC_DBGR) Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer) */
-#define SDHC_DBGR_NIDBG_NIDBG_Val _U_(0x1) /**< \brief (SDHC_DBGR) Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer) */
-#define SDHC_DBGR_NIDBG_IDBG (SDHC_DBGR_NIDBG_IDBG_Val << SDHC_DBGR_NIDBG_Pos)
-#define SDHC_DBGR_NIDBG_NIDBG (SDHC_DBGR_NIDBG_NIDBG_Val << SDHC_DBGR_NIDBG_Pos)
-#define SDHC_DBGR_MASK _U_(0x01) /**< \brief (SDHC_DBGR) MASK Register */
-
-/** \brief SDHC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO SDHC_SSAR_Type SSAR; /**< \brief Offset: 0x000 (R/W 32) SDMA System Address / Argument 2 */
- __IO SDHC_BSR_Type BSR; /**< \brief Offset: 0x004 (R/W 16) Block Size */
- __IO SDHC_BCR_Type BCR; /**< \brief Offset: 0x006 (R/W 16) Block Count */
- __IO SDHC_ARG1R_Type ARG1R; /**< \brief Offset: 0x008 (R/W 32) Argument 1 */
- __IO SDHC_TMR_Type TMR; /**< \brief Offset: 0x00C (R/W 16) Transfer Mode */
- __IO SDHC_CR_Type CR; /**< \brief Offset: 0x00E (R/W 16) Command */
- __I SDHC_RR_Type RR[4]; /**< \brief Offset: 0x010 (R/ 32) Response */
- __IO SDHC_BDPR_Type BDPR; /**< \brief Offset: 0x020 (R/W 32) Buffer Data Port */
- __I SDHC_PSR_Type PSR; /**< \brief Offset: 0x024 (R/ 32) Present State */
- __IO SDHC_HC1R_Type HC1R; /**< \brief Offset: 0x028 (R/W 8) Host Control 1 */
- __IO SDHC_PCR_Type PCR; /**< \brief Offset: 0x029 (R/W 8) Power Control */
- __IO SDHC_BGCR_Type BGCR; /**< \brief Offset: 0x02A (R/W 8) Block Gap Control */
- __IO SDHC_WCR_Type WCR; /**< \brief Offset: 0x02B (R/W 8) Wakeup Control */
- __IO SDHC_CCR_Type CCR; /**< \brief Offset: 0x02C (R/W 16) Clock Control */
- __IO SDHC_TCR_Type TCR; /**< \brief Offset: 0x02E (R/W 8) Timeout Control */
- __IO SDHC_SRR_Type SRR; /**< \brief Offset: 0x02F (R/W 8) Software Reset */
- __IO SDHC_NISTR_Type NISTR; /**< \brief Offset: 0x030 (R/W 16) Normal Interrupt Status */
- __IO SDHC_EISTR_Type EISTR; /**< \brief Offset: 0x032 (R/W 16) Error Interrupt Status */
- __IO SDHC_NISTER_Type NISTER; /**< \brief Offset: 0x034 (R/W 16) Normal Interrupt Status Enable */
- __IO SDHC_EISTER_Type EISTER; /**< \brief Offset: 0x036 (R/W 16) Error Interrupt Status Enable */
- __IO SDHC_NISIER_Type NISIER; /**< \brief Offset: 0x038 (R/W 16) Normal Interrupt Signal Enable */
- __IO SDHC_EISIER_Type EISIER; /**< \brief Offset: 0x03A (R/W 16) Error Interrupt Signal Enable */
- __I SDHC_ACESR_Type ACESR; /**< \brief Offset: 0x03C (R/ 16) Auto CMD Error Status */
- __IO SDHC_HC2R_Type HC2R; /**< \brief Offset: 0x03E (R/W 16) Host Control 2 */
- __I SDHC_CA0R_Type CA0R; /**< \brief Offset: 0x040 (R/ 32) Capabilities 0 */
- __I SDHC_CA1R_Type CA1R; /**< \brief Offset: 0x044 (R/ 32) Capabilities 1 */
- __I SDHC_MCCAR_Type MCCAR; /**< \brief Offset: 0x048 (R/ 32) Maximum Current Capabilities */
- RoReg8 Reserved1[0x4];
- __O SDHC_FERACES_Type FERACES; /**< \brief Offset: 0x050 ( /W 16) Force Event for Auto CMD Error Status */
- __O SDHC_FEREIS_Type FEREIS; /**< \brief Offset: 0x052 ( /W 16) Force Event for Error Interrupt Status */
- __I SDHC_AESR_Type AESR; /**< \brief Offset: 0x054 (R/ 8) ADMA Error Status */
- RoReg8 Reserved2[0x3];
- __IO SDHC_ASAR_Type ASAR[1]; /**< \brief Offset: 0x058 (R/W 32) ADMA System Address n */
- RoReg8 Reserved3[0x4];
- __IO SDHC_PVR_Type PVR[8]; /**< \brief Offset: 0x060 (R/W 16) Preset Value n */
- RoReg8 Reserved4[0x8C];
- __I SDHC_SISR_Type SISR; /**< \brief Offset: 0x0FC (R/ 16) Slot Interrupt Status */
- __I SDHC_HCVR_Type HCVR; /**< \brief Offset: 0x0FE (R/ 16) Host Controller Version */
- RoReg8 Reserved5[0x104];
- __IO SDHC_MC1R_Type MC1R; /**< \brief Offset: 0x204 (R/W 8) MMC Control 1 */
- __O SDHC_MC2R_Type MC2R; /**< \brief Offset: 0x205 ( /W 8) MMC Control 2 */
- RoReg8 Reserved6[0x2];
- __IO SDHC_ACR_Type ACR; /**< \brief Offset: 0x208 (R/W 32) AHB Control */
- __IO SDHC_CC2R_Type CC2R; /**< \brief Offset: 0x20C (R/W 32) Clock Control 2 */
- RoReg8 Reserved7[0x20];
- __IO SDHC_CACR_Type CACR; /**< \brief Offset: 0x230 (R/W 32) Capabilities Control */
- __IO SDHC_DBGR_Type DBGR; /**< \brief Offset: 0x234 (R/W 8) Debug */
-} Sdhc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_SDHC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for SDHC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_SDHC_COMPONENT_
+#define _SAME54_SDHC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR SDHC */
+/* ========================================================================== */
+/** \addtogroup SAME54_SDHC SD/MMC Host Controller */
+/*@{*/
+
+#define SDHC_U2011
+#define REV_SDHC 0x183
+
+/* -------- SDHC_SSAR : (SDHC Offset: 0x000) (R/W 32) SDMA System Address / Argument 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // CMD23 mode
+ uint32_t ARG2:32; /*!< bit: 0..31 Argument 2 */
+ } CMD23; /*!< Structure used for CMD23 */
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 SDMA System Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_SSAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_SSAR_OFFSET 0x000 /**< \brief (SDHC_SSAR offset) SDMA System Address / Argument 2 */
+#define SDHC_SSAR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_SSAR reset_value) SDMA System Address / Argument 2 */
+
+// CMD23 mode
+#define SDHC_SSAR_CMD23_ARG2_Pos 0 /**< \brief (SDHC_SSAR_CMD23) Argument 2 */
+#define SDHC_SSAR_CMD23_ARG2_Msk (_U_(0xFFFFFFFF) << SDHC_SSAR_CMD23_ARG2_Pos)
+#define SDHC_SSAR_CMD23_ARG2(value) (SDHC_SSAR_CMD23_ARG2_Msk & ((value) << SDHC_SSAR_CMD23_ARG2_Pos))
+#define SDHC_SSAR_CMD23_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_SSAR_CMD23) MASK Register */
+
+#define SDHC_SSAR_ADDR_Pos 0 /**< \brief (SDHC_SSAR) SDMA System Address */
+#define SDHC_SSAR_ADDR_Msk (_U_(0xFFFFFFFF) << SDHC_SSAR_ADDR_Pos)
+#define SDHC_SSAR_ADDR(value) (SDHC_SSAR_ADDR_Msk & ((value) << SDHC_SSAR_ADDR_Pos))
+#define SDHC_SSAR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_SSAR) MASK Register */
+
+/* -------- SDHC_BSR : (SDHC Offset: 0x004) (R/W 16) Block Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BLOCKSIZE:10; /*!< bit: 0.. 9 Transfer Block Size */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t BOUNDARY:3; /*!< bit: 12..14 SDMA Buffer Boundary */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_BSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_BSR_OFFSET 0x004 /**< \brief (SDHC_BSR offset) Block Size */
+#define SDHC_BSR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_BSR reset_value) Block Size */
+
+#define SDHC_BSR_BLOCKSIZE_Pos 0 /**< \brief (SDHC_BSR) Transfer Block Size */
+#define SDHC_BSR_BLOCKSIZE_Msk (_U_(0x3FF) << SDHC_BSR_BLOCKSIZE_Pos)
+#define SDHC_BSR_BLOCKSIZE(value) (SDHC_BSR_BLOCKSIZE_Msk & ((value) << SDHC_BSR_BLOCKSIZE_Pos))
+#define SDHC_BSR_BOUNDARY_Pos 12 /**< \brief (SDHC_BSR) SDMA Buffer Boundary */
+#define SDHC_BSR_BOUNDARY_Msk (_U_(0x7) << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY(value) (SDHC_BSR_BOUNDARY_Msk & ((value) << SDHC_BSR_BOUNDARY_Pos))
+#define SDHC_BSR_BOUNDARY_4K_Val _U_(0x0) /**< \brief (SDHC_BSR) 4k bytes */
+#define SDHC_BSR_BOUNDARY_8K_Val _U_(0x1) /**< \brief (SDHC_BSR) 8k bytes */
+#define SDHC_BSR_BOUNDARY_16K_Val _U_(0x2) /**< \brief (SDHC_BSR) 16k bytes */
+#define SDHC_BSR_BOUNDARY_32K_Val _U_(0x3) /**< \brief (SDHC_BSR) 32k bytes */
+#define SDHC_BSR_BOUNDARY_64K_Val _U_(0x4) /**< \brief (SDHC_BSR) 64k bytes */
+#define SDHC_BSR_BOUNDARY_128K_Val _U_(0x5) /**< \brief (SDHC_BSR) 128k bytes */
+#define SDHC_BSR_BOUNDARY_256K_Val _U_(0x6) /**< \brief (SDHC_BSR) 256k bytes */
+#define SDHC_BSR_BOUNDARY_512K_Val _U_(0x7) /**< \brief (SDHC_BSR) 512k bytes */
+#define SDHC_BSR_BOUNDARY_4K (SDHC_BSR_BOUNDARY_4K_Val << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_8K (SDHC_BSR_BOUNDARY_8K_Val << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_16K (SDHC_BSR_BOUNDARY_16K_Val << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_32K (SDHC_BSR_BOUNDARY_32K_Val << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_64K (SDHC_BSR_BOUNDARY_64K_Val << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_128K (SDHC_BSR_BOUNDARY_128K_Val << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_256K (SDHC_BSR_BOUNDARY_256K_Val << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_512K (SDHC_BSR_BOUNDARY_512K_Val << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_MASK _U_(0x73FF) /**< \brief (SDHC_BSR) MASK Register */
+
+/* -------- SDHC_BCR : (SDHC Offset: 0x006) (R/W 16) Block Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BCNT:16; /*!< bit: 0..15 Blocks Count for Current Transfer */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_BCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_BCR_OFFSET 0x006 /**< \brief (SDHC_BCR offset) Block Count */
+#define SDHC_BCR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_BCR reset_value) Block Count */
+
+#define SDHC_BCR_BCNT_Pos 0 /**< \brief (SDHC_BCR) Blocks Count for Current Transfer */
+#define SDHC_BCR_BCNT_Msk (_U_(0xFFFF) << SDHC_BCR_BCNT_Pos)
+#define SDHC_BCR_BCNT(value) (SDHC_BCR_BCNT_Msk & ((value) << SDHC_BCR_BCNT_Pos))
+#define SDHC_BCR_MASK _U_(0xFFFF) /**< \brief (SDHC_BCR) MASK Register */
+
+/* -------- SDHC_ARG1R : (SDHC Offset: 0x008) (R/W 32) Argument 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ARG:32; /*!< bit: 0..31 Argument 1 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_ARG1R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_ARG1R_OFFSET 0x008 /**< \brief (SDHC_ARG1R offset) Argument 1 */
+#define SDHC_ARG1R_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_ARG1R reset_value) Argument 1 */
+
+#define SDHC_ARG1R_ARG_Pos 0 /**< \brief (SDHC_ARG1R) Argument 1 */
+#define SDHC_ARG1R_ARG_Msk (_U_(0xFFFFFFFF) << SDHC_ARG1R_ARG_Pos)
+#define SDHC_ARG1R_ARG(value) (SDHC_ARG1R_ARG_Msk & ((value) << SDHC_ARG1R_ARG_Pos))
+#define SDHC_ARG1R_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_ARG1R) MASK Register */
+
+/* -------- SDHC_TMR : (SDHC Offset: 0x00C) (R/W 16) Transfer Mode -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DMAEN:1; /*!< bit: 0 DMA Enable */
+ uint16_t BCEN:1; /*!< bit: 1 Block Count Enable */
+ uint16_t ACMDEN:2; /*!< bit: 2.. 3 Auto Command Enable */
+ uint16_t DTDSEL:1; /*!< bit: 4 Data Transfer Direction Selection */
+ uint16_t MSBSEL:1; /*!< bit: 5 Multi/Single Block Selection */
+ uint16_t :10; /*!< bit: 6..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_TMR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_TMR_OFFSET 0x00C /**< \brief (SDHC_TMR offset) Transfer Mode */
+#define SDHC_TMR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_TMR reset_value) Transfer Mode */
+
+#define SDHC_TMR_DMAEN_Pos 0 /**< \brief (SDHC_TMR) DMA Enable */
+#define SDHC_TMR_DMAEN (_U_(0x1) << SDHC_TMR_DMAEN_Pos)
+#define SDHC_TMR_DMAEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_TMR) No data transfer or Non DMA data transfer */
+#define SDHC_TMR_DMAEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_TMR) DMA data transfer */
+#define SDHC_TMR_DMAEN_DISABLE (SDHC_TMR_DMAEN_DISABLE_Val << SDHC_TMR_DMAEN_Pos)
+#define SDHC_TMR_DMAEN_ENABLE (SDHC_TMR_DMAEN_ENABLE_Val << SDHC_TMR_DMAEN_Pos)
+#define SDHC_TMR_BCEN_Pos 1 /**< \brief (SDHC_TMR) Block Count Enable */
+#define SDHC_TMR_BCEN (_U_(0x1) << SDHC_TMR_BCEN_Pos)
+#define SDHC_TMR_BCEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_TMR) Disable */
+#define SDHC_TMR_BCEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_TMR) Enable */
+#define SDHC_TMR_BCEN_DISABLE (SDHC_TMR_BCEN_DISABLE_Val << SDHC_TMR_BCEN_Pos)
+#define SDHC_TMR_BCEN_ENABLE (SDHC_TMR_BCEN_ENABLE_Val << SDHC_TMR_BCEN_Pos)
+#define SDHC_TMR_ACMDEN_Pos 2 /**< \brief (SDHC_TMR) Auto Command Enable */
+#define SDHC_TMR_ACMDEN_Msk (_U_(0x3) << SDHC_TMR_ACMDEN_Pos)
+#define SDHC_TMR_ACMDEN(value) (SDHC_TMR_ACMDEN_Msk & ((value) << SDHC_TMR_ACMDEN_Pos))
+#define SDHC_TMR_ACMDEN_DISABLED_Val _U_(0x0) /**< \brief (SDHC_TMR) Auto Command Disabled */
+#define SDHC_TMR_ACMDEN_CMD12_Val _U_(0x1) /**< \brief (SDHC_TMR) Auto CMD12 Enable */
+#define SDHC_TMR_ACMDEN_CMD23_Val _U_(0x2) /**< \brief (SDHC_TMR) Auto CMD23 Enable */
+#define SDHC_TMR_ACMDEN_3_Val _U_(0x3) /**< \brief (SDHC_TMR) Reserved */
+#define SDHC_TMR_ACMDEN_DISABLED (SDHC_TMR_ACMDEN_DISABLED_Val << SDHC_TMR_ACMDEN_Pos)
+#define SDHC_TMR_ACMDEN_CMD12 (SDHC_TMR_ACMDEN_CMD12_Val << SDHC_TMR_ACMDEN_Pos)
+#define SDHC_TMR_ACMDEN_CMD23 (SDHC_TMR_ACMDEN_CMD23_Val << SDHC_TMR_ACMDEN_Pos)
+#define SDHC_TMR_ACMDEN_3 (SDHC_TMR_ACMDEN_3_Val << SDHC_TMR_ACMDEN_Pos)
+#define SDHC_TMR_DTDSEL_Pos 4 /**< \brief (SDHC_TMR) Data Transfer Direction Selection */
+#define SDHC_TMR_DTDSEL (_U_(0x1) << SDHC_TMR_DTDSEL_Pos)
+#define SDHC_TMR_DTDSEL_WRITE_Val _U_(0x0) /**< \brief (SDHC_TMR) Write (Host to Card) */
+#define SDHC_TMR_DTDSEL_READ_Val _U_(0x1) /**< \brief (SDHC_TMR) Read (Card to Host) */
+#define SDHC_TMR_DTDSEL_WRITE (SDHC_TMR_DTDSEL_WRITE_Val << SDHC_TMR_DTDSEL_Pos)
+#define SDHC_TMR_DTDSEL_READ (SDHC_TMR_DTDSEL_READ_Val << SDHC_TMR_DTDSEL_Pos)
+#define SDHC_TMR_MSBSEL_Pos 5 /**< \brief (SDHC_TMR) Multi/Single Block Selection */
+#define SDHC_TMR_MSBSEL (_U_(0x1) << SDHC_TMR_MSBSEL_Pos)
+#define SDHC_TMR_MSBSEL_SINGLE_Val _U_(0x0) /**< \brief (SDHC_TMR) Single Block */
+#define SDHC_TMR_MSBSEL_MULTIPLE_Val _U_(0x1) /**< \brief (SDHC_TMR) Multiple Block */
+#define SDHC_TMR_MSBSEL_SINGLE (SDHC_TMR_MSBSEL_SINGLE_Val << SDHC_TMR_MSBSEL_Pos)
+#define SDHC_TMR_MSBSEL_MULTIPLE (SDHC_TMR_MSBSEL_MULTIPLE_Val << SDHC_TMR_MSBSEL_Pos)
+#define SDHC_TMR_MASK _U_(0x003F) /**< \brief (SDHC_TMR) MASK Register */
+
+/* -------- SDHC_CR : (SDHC Offset: 0x00E) (R/W 16) Command -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RESPTYP:2; /*!< bit: 0.. 1 Response Type */
+ uint16_t :1; /*!< bit: 2 Reserved */
+ uint16_t CMDCCEN:1; /*!< bit: 3 Command CRC Check Enable */
+ uint16_t CMDICEN:1; /*!< bit: 4 Command Index Check Enable */
+ uint16_t DPSEL:1; /*!< bit: 5 Data Present Select */
+ uint16_t CMDTYP:2; /*!< bit: 6.. 7 Command Type */
+ uint16_t CMDIDX:6; /*!< bit: 8..13 Command Index */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_CR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_CR_OFFSET 0x00E /**< \brief (SDHC_CR offset) Command */
+#define SDHC_CR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_CR reset_value) Command */
+
+#define SDHC_CR_RESPTYP_Pos 0 /**< \brief (SDHC_CR) Response Type */
+#define SDHC_CR_RESPTYP_Msk (_U_(0x3) << SDHC_CR_RESPTYP_Pos)
+#define SDHC_CR_RESPTYP(value) (SDHC_CR_RESPTYP_Msk & ((value) << SDHC_CR_RESPTYP_Pos))
+#define SDHC_CR_RESPTYP_NONE_Val _U_(0x0) /**< \brief (SDHC_CR) No response */
+#define SDHC_CR_RESPTYP_136_BIT_Val _U_(0x1) /**< \brief (SDHC_CR) 136-bit response */
+#define SDHC_CR_RESPTYP_48_BIT_Val _U_(0x2) /**< \brief (SDHC_CR) 48-bit response */
+#define SDHC_CR_RESPTYP_48_BIT_BUSY_Val _U_(0x3) /**< \brief (SDHC_CR) 48-bit response check busy after response */
+#define SDHC_CR_RESPTYP_NONE (SDHC_CR_RESPTYP_NONE_Val << SDHC_CR_RESPTYP_Pos)
+#define SDHC_CR_RESPTYP_136_BIT (SDHC_CR_RESPTYP_136_BIT_Val << SDHC_CR_RESPTYP_Pos)
+#define SDHC_CR_RESPTYP_48_BIT (SDHC_CR_RESPTYP_48_BIT_Val << SDHC_CR_RESPTYP_Pos)
+#define SDHC_CR_RESPTYP_48_BIT_BUSY (SDHC_CR_RESPTYP_48_BIT_BUSY_Val << SDHC_CR_RESPTYP_Pos)
+#define SDHC_CR_CMDCCEN_Pos 3 /**< \brief (SDHC_CR) Command CRC Check Enable */
+#define SDHC_CR_CMDCCEN (_U_(0x1) << SDHC_CR_CMDCCEN_Pos)
+#define SDHC_CR_CMDCCEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_CR) Disable */
+#define SDHC_CR_CMDCCEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_CR) Enable */
+#define SDHC_CR_CMDCCEN_DISABLE (SDHC_CR_CMDCCEN_DISABLE_Val << SDHC_CR_CMDCCEN_Pos)
+#define SDHC_CR_CMDCCEN_ENABLE (SDHC_CR_CMDCCEN_ENABLE_Val << SDHC_CR_CMDCCEN_Pos)
+#define SDHC_CR_CMDICEN_Pos 4 /**< \brief (SDHC_CR) Command Index Check Enable */
+#define SDHC_CR_CMDICEN (_U_(0x1) << SDHC_CR_CMDICEN_Pos)
+#define SDHC_CR_CMDICEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_CR) Disable */
+#define SDHC_CR_CMDICEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_CR) Enable */
+#define SDHC_CR_CMDICEN_DISABLE (SDHC_CR_CMDICEN_DISABLE_Val << SDHC_CR_CMDICEN_Pos)
+#define SDHC_CR_CMDICEN_ENABLE (SDHC_CR_CMDICEN_ENABLE_Val << SDHC_CR_CMDICEN_Pos)
+#define SDHC_CR_DPSEL_Pos 5 /**< \brief (SDHC_CR) Data Present Select */
+#define SDHC_CR_DPSEL (_U_(0x1) << SDHC_CR_DPSEL_Pos)
+#define SDHC_CR_DPSEL_NO_DATA_Val _U_(0x0) /**< \brief (SDHC_CR) No Data Present */
+#define SDHC_CR_DPSEL_DATA_Val _U_(0x1) /**< \brief (SDHC_CR) Data Present */
+#define SDHC_CR_DPSEL_NO_DATA (SDHC_CR_DPSEL_NO_DATA_Val << SDHC_CR_DPSEL_Pos)
+#define SDHC_CR_DPSEL_DATA (SDHC_CR_DPSEL_DATA_Val << SDHC_CR_DPSEL_Pos)
+#define SDHC_CR_CMDTYP_Pos 6 /**< \brief (SDHC_CR) Command Type */
+#define SDHC_CR_CMDTYP_Msk (_U_(0x3) << SDHC_CR_CMDTYP_Pos)
+#define SDHC_CR_CMDTYP(value) (SDHC_CR_CMDTYP_Msk & ((value) << SDHC_CR_CMDTYP_Pos))
+#define SDHC_CR_CMDTYP_NORMAL_Val _U_(0x0) /**< \brief (SDHC_CR) Other commands */
+#define SDHC_CR_CMDTYP_SUSPEND_Val _U_(0x1) /**< \brief (SDHC_CR) CMD52 for writing Bus Suspend in CCCR */
+#define SDHC_CR_CMDTYP_RESUME_Val _U_(0x2) /**< \brief (SDHC_CR) CMD52 for writing Function Select in CCCR */
+#define SDHC_CR_CMDTYP_ABORT_Val _U_(0x3) /**< \brief (SDHC_CR) CMD12, CMD52 for writing I/O Abort in CCCR */
+#define SDHC_CR_CMDTYP_NORMAL (SDHC_CR_CMDTYP_NORMAL_Val << SDHC_CR_CMDTYP_Pos)
+#define SDHC_CR_CMDTYP_SUSPEND (SDHC_CR_CMDTYP_SUSPEND_Val << SDHC_CR_CMDTYP_Pos)
+#define SDHC_CR_CMDTYP_RESUME (SDHC_CR_CMDTYP_RESUME_Val << SDHC_CR_CMDTYP_Pos)
+#define SDHC_CR_CMDTYP_ABORT (SDHC_CR_CMDTYP_ABORT_Val << SDHC_CR_CMDTYP_Pos)
+#define SDHC_CR_CMDIDX_Pos 8 /**< \brief (SDHC_CR) Command Index */
+#define SDHC_CR_CMDIDX_Msk (_U_(0x3F) << SDHC_CR_CMDIDX_Pos)
+#define SDHC_CR_CMDIDX(value) (SDHC_CR_CMDIDX_Msk & ((value) << SDHC_CR_CMDIDX_Pos))
+#define SDHC_CR_MASK _U_(0x3FFB) /**< \brief (SDHC_CR) MASK Register */
+
+/* -------- SDHC_RR : (SDHC Offset: 0x010) (R/ 32) Response -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CMDRESP:32; /*!< bit: 0..31 Command Response */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_RR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_RR_OFFSET 0x010 /**< \brief (SDHC_RR offset) Response */
+#define SDHC_RR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_RR reset_value) Response */
+
+#define SDHC_RR_CMDRESP_Pos 0 /**< \brief (SDHC_RR) Command Response */
+#define SDHC_RR_CMDRESP_Msk (_U_(0xFFFFFFFF) << SDHC_RR_CMDRESP_Pos)
+#define SDHC_RR_CMDRESP(value) (SDHC_RR_CMDRESP_Msk & ((value) << SDHC_RR_CMDRESP_Pos))
+#define SDHC_RR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_RR) MASK Register */
+
+/* -------- SDHC_BDPR : (SDHC Offset: 0x020) (R/W 32) Buffer Data Port -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BUFDATA:32; /*!< bit: 0..31 Buffer Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_BDPR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_BDPR_OFFSET 0x020 /**< \brief (SDHC_BDPR offset) Buffer Data Port */
+#define SDHC_BDPR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_BDPR reset_value) Buffer Data Port */
+
+#define SDHC_BDPR_BUFDATA_Pos 0 /**< \brief (SDHC_BDPR) Buffer Data */
+#define SDHC_BDPR_BUFDATA_Msk (_U_(0xFFFFFFFF) << SDHC_BDPR_BUFDATA_Pos)
+#define SDHC_BDPR_BUFDATA(value) (SDHC_BDPR_BUFDATA_Msk & ((value) << SDHC_BDPR_BUFDATA_Pos))
+#define SDHC_BDPR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_BDPR) MASK Register */
+
+/* -------- SDHC_PSR : (SDHC Offset: 0x024) (R/ 32) Present State -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CMDINHC:1; /*!< bit: 0 Command Inhibit (CMD) */
+ uint32_t CMDINHD:1; /*!< bit: 1 Command Inhibit (DAT) */
+ uint32_t DLACT:1; /*!< bit: 2 DAT Line Active */
+ uint32_t RTREQ:1; /*!< bit: 3 Re-Tuning Request */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t WTACT:1; /*!< bit: 8 Write Transfer Active */
+ uint32_t RTACT:1; /*!< bit: 9 Read Transfer Active */
+ uint32_t BUFWREN:1; /*!< bit: 10 Buffer Write Enable */
+ uint32_t BUFRDEN:1; /*!< bit: 11 Buffer Read Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t CARDINS:1; /*!< bit: 16 Card Inserted */
+ uint32_t CARDSS:1; /*!< bit: 17 Card State Stable */
+ uint32_t CARDDPL:1; /*!< bit: 18 Card Detect Pin Level */
+ uint32_t WRPPL:1; /*!< bit: 19 Write Protect Pin Level */
+ uint32_t DATLL:4; /*!< bit: 20..23 DAT[3:0] Line Level */
+ uint32_t CMDLL:1; /*!< bit: 24 CMD Line Level */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_PSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_PSR_OFFSET 0x024 /**< \brief (SDHC_PSR offset) Present State */
+#define SDHC_PSR_RESETVALUE _U_(0x00F80000) /**< \brief (SDHC_PSR reset_value) Present State */
+
+#define SDHC_PSR_CMDINHC_Pos 0 /**< \brief (SDHC_PSR) Command Inhibit (CMD) */
+#define SDHC_PSR_CMDINHC (_U_(0x1) << SDHC_PSR_CMDINHC_Pos)
+#define SDHC_PSR_CMDINHC_CAN_Val _U_(0x0) /**< \brief (SDHC_PSR) Can issue command using only CMD line */
+#define SDHC_PSR_CMDINHC_CANNOT_Val _U_(0x1) /**< \brief (SDHC_PSR) Cannot issue command */
+#define SDHC_PSR_CMDINHC_CAN (SDHC_PSR_CMDINHC_CAN_Val << SDHC_PSR_CMDINHC_Pos)
+#define SDHC_PSR_CMDINHC_CANNOT (SDHC_PSR_CMDINHC_CANNOT_Val << SDHC_PSR_CMDINHC_Pos)
+#define SDHC_PSR_CMDINHD_Pos 1 /**< \brief (SDHC_PSR) Command Inhibit (DAT) */
+#define SDHC_PSR_CMDINHD (_U_(0x1) << SDHC_PSR_CMDINHD_Pos)
+#define SDHC_PSR_CMDINHD_CAN_Val _U_(0x0) /**< \brief (SDHC_PSR) Can issue command which uses the DAT line */
+#define SDHC_PSR_CMDINHD_CANNOT_Val _U_(0x1) /**< \brief (SDHC_PSR) Cannot issue command which uses the DAT line */
+#define SDHC_PSR_CMDINHD_CAN (SDHC_PSR_CMDINHD_CAN_Val << SDHC_PSR_CMDINHD_Pos)
+#define SDHC_PSR_CMDINHD_CANNOT (SDHC_PSR_CMDINHD_CANNOT_Val << SDHC_PSR_CMDINHD_Pos)
+#define SDHC_PSR_DLACT_Pos 2 /**< \brief (SDHC_PSR) DAT Line Active */
+#define SDHC_PSR_DLACT (_U_(0x1) << SDHC_PSR_DLACT_Pos)
+#define SDHC_PSR_DLACT_INACTIVE_Val _U_(0x0) /**< \brief (SDHC_PSR) DAT Line Inactive */
+#define SDHC_PSR_DLACT_ACTIVE_Val _U_(0x1) /**< \brief (SDHC_PSR) DAT Line Active */
+#define SDHC_PSR_DLACT_INACTIVE (SDHC_PSR_DLACT_INACTIVE_Val << SDHC_PSR_DLACT_Pos)
+#define SDHC_PSR_DLACT_ACTIVE (SDHC_PSR_DLACT_ACTIVE_Val << SDHC_PSR_DLACT_Pos)
+#define SDHC_PSR_RTREQ_Pos 3 /**< \brief (SDHC_PSR) Re-Tuning Request */
+#define SDHC_PSR_RTREQ (_U_(0x1) << SDHC_PSR_RTREQ_Pos)
+#define SDHC_PSR_RTREQ_OK_Val _U_(0x0) /**< \brief (SDHC_PSR) Fixed or well-tuned sampling clock */
+#define SDHC_PSR_RTREQ_REQUIRED_Val _U_(0x1) /**< \brief (SDHC_PSR) Sampling clock needs re-tuning */
+#define SDHC_PSR_RTREQ_OK (SDHC_PSR_RTREQ_OK_Val << SDHC_PSR_RTREQ_Pos)
+#define SDHC_PSR_RTREQ_REQUIRED (SDHC_PSR_RTREQ_REQUIRED_Val << SDHC_PSR_RTREQ_Pos)
+#define SDHC_PSR_WTACT_Pos 8 /**< \brief (SDHC_PSR) Write Transfer Active */
+#define SDHC_PSR_WTACT (_U_(0x1) << SDHC_PSR_WTACT_Pos)
+#define SDHC_PSR_WTACT_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) No valid data */
+#define SDHC_PSR_WTACT_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Transferring data */
+#define SDHC_PSR_WTACT_NO (SDHC_PSR_WTACT_NO_Val << SDHC_PSR_WTACT_Pos)
+#define SDHC_PSR_WTACT_YES (SDHC_PSR_WTACT_YES_Val << SDHC_PSR_WTACT_Pos)
+#define SDHC_PSR_RTACT_Pos 9 /**< \brief (SDHC_PSR) Read Transfer Active */
+#define SDHC_PSR_RTACT (_U_(0x1) << SDHC_PSR_RTACT_Pos)
+#define SDHC_PSR_RTACT_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) No valid data */
+#define SDHC_PSR_RTACT_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Transferring data */
+#define SDHC_PSR_RTACT_NO (SDHC_PSR_RTACT_NO_Val << SDHC_PSR_RTACT_Pos)
+#define SDHC_PSR_RTACT_YES (SDHC_PSR_RTACT_YES_Val << SDHC_PSR_RTACT_Pos)
+#define SDHC_PSR_BUFWREN_Pos 10 /**< \brief (SDHC_PSR) Buffer Write Enable */
+#define SDHC_PSR_BUFWREN (_U_(0x1) << SDHC_PSR_BUFWREN_Pos)
+#define SDHC_PSR_BUFWREN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_PSR) Write disable */
+#define SDHC_PSR_BUFWREN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_PSR) Write enable */
+#define SDHC_PSR_BUFWREN_DISABLE (SDHC_PSR_BUFWREN_DISABLE_Val << SDHC_PSR_BUFWREN_Pos)
+#define SDHC_PSR_BUFWREN_ENABLE (SDHC_PSR_BUFWREN_ENABLE_Val << SDHC_PSR_BUFWREN_Pos)
+#define SDHC_PSR_BUFRDEN_Pos 11 /**< \brief (SDHC_PSR) Buffer Read Enable */
+#define SDHC_PSR_BUFRDEN (_U_(0x1) << SDHC_PSR_BUFRDEN_Pos)
+#define SDHC_PSR_BUFRDEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_PSR) Read disable */
+#define SDHC_PSR_BUFRDEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_PSR) Read enable */
+#define SDHC_PSR_BUFRDEN_DISABLE (SDHC_PSR_BUFRDEN_DISABLE_Val << SDHC_PSR_BUFRDEN_Pos)
+#define SDHC_PSR_BUFRDEN_ENABLE (SDHC_PSR_BUFRDEN_ENABLE_Val << SDHC_PSR_BUFRDEN_Pos)
+#define SDHC_PSR_CARDINS_Pos 16 /**< \brief (SDHC_PSR) Card Inserted */
+#define SDHC_PSR_CARDINS (_U_(0x1) << SDHC_PSR_CARDINS_Pos)
+#define SDHC_PSR_CARDINS_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) Reset or Debouncing or No Card */
+#define SDHC_PSR_CARDINS_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Card inserted */
+#define SDHC_PSR_CARDINS_NO (SDHC_PSR_CARDINS_NO_Val << SDHC_PSR_CARDINS_Pos)
+#define SDHC_PSR_CARDINS_YES (SDHC_PSR_CARDINS_YES_Val << SDHC_PSR_CARDINS_Pos)
+#define SDHC_PSR_CARDSS_Pos 17 /**< \brief (SDHC_PSR) Card State Stable */
+#define SDHC_PSR_CARDSS (_U_(0x1) << SDHC_PSR_CARDSS_Pos)
+#define SDHC_PSR_CARDSS_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) Reset or Debouncing */
+#define SDHC_PSR_CARDSS_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) No Card or Insered */
+#define SDHC_PSR_CARDSS_NO (SDHC_PSR_CARDSS_NO_Val << SDHC_PSR_CARDSS_Pos)
+#define SDHC_PSR_CARDSS_YES (SDHC_PSR_CARDSS_YES_Val << SDHC_PSR_CARDSS_Pos)
+#define SDHC_PSR_CARDDPL_Pos 18 /**< \brief (SDHC_PSR) Card Detect Pin Level */
+#define SDHC_PSR_CARDDPL (_U_(0x1) << SDHC_PSR_CARDDPL_Pos)
+#define SDHC_PSR_CARDDPL_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) No card present (SDCD#=1) */
+#define SDHC_PSR_CARDDPL_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Card present (SDCD#=0) */
+#define SDHC_PSR_CARDDPL_NO (SDHC_PSR_CARDDPL_NO_Val << SDHC_PSR_CARDDPL_Pos)
+#define SDHC_PSR_CARDDPL_YES (SDHC_PSR_CARDDPL_YES_Val << SDHC_PSR_CARDDPL_Pos)
+#define SDHC_PSR_WRPPL_Pos 19 /**< \brief (SDHC_PSR) Write Protect Pin Level */
+#define SDHC_PSR_WRPPL (_U_(0x1) << SDHC_PSR_WRPPL_Pos)
+#define SDHC_PSR_WRPPL_PROTECTED_Val _U_(0x0) /**< \brief (SDHC_PSR) Write protected (SDWP#=0) */
+#define SDHC_PSR_WRPPL_ENABLED_Val _U_(0x1) /**< \brief (SDHC_PSR) Write enabled (SDWP#=1) */
+#define SDHC_PSR_WRPPL_PROTECTED (SDHC_PSR_WRPPL_PROTECTED_Val << SDHC_PSR_WRPPL_Pos)
+#define SDHC_PSR_WRPPL_ENABLED (SDHC_PSR_WRPPL_ENABLED_Val << SDHC_PSR_WRPPL_Pos)
+#define SDHC_PSR_DATLL_Pos 20 /**< \brief (SDHC_PSR) DAT[3:0] Line Level */
+#define SDHC_PSR_DATLL_Msk (_U_(0xF) << SDHC_PSR_DATLL_Pos)
+#define SDHC_PSR_DATLL(value) (SDHC_PSR_DATLL_Msk & ((value) << SDHC_PSR_DATLL_Pos))
+#define SDHC_PSR_CMDLL_Pos 24 /**< \brief (SDHC_PSR) CMD Line Level */
+#define SDHC_PSR_CMDLL (_U_(0x1) << SDHC_PSR_CMDLL_Pos)
+#define SDHC_PSR_MASK _U_(0x01FF0F0F) /**< \brief (SDHC_PSR) MASK Register */
+
+/* -------- SDHC_HC1R : (SDHC Offset: 0x028) (R/W 8) Host Control 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t LEDCTRL:1; /*!< bit: 0 LED Control */
+ uint8_t DW:1; /*!< bit: 1 Data Width */
+ uint8_t HSEN:1; /*!< bit: 2 High Speed Enable */
+ uint8_t DMASEL:2; /*!< bit: 3.. 4 DMA Select */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t CARDDTL:1; /*!< bit: 6 Card Detect Test Level */
+ uint8_t CARDDSEL:1; /*!< bit: 7 Card Detect Signal Selection */
+ } bit; /*!< Structure used for bit access */
+ struct { // EMMC mode
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t DW:1; /*!< bit: 1 Data Width */
+ uint8_t HSEN:1; /*!< bit: 2 High Speed Enable */
+ uint8_t DMASEL:2; /*!< bit: 3.. 4 DMA Select */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } EMMC; /*!< Structure used for EMMC */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_HC1R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_HC1R_OFFSET 0x028 /**< \brief (SDHC_HC1R offset) Host Control 1 */
+#define SDHC_HC1R_RESETVALUE _U_(0xE00) /**< \brief (SDHC_HC1R reset_value) Host Control 1 */
+
+#define SDHC_HC1R_LEDCTRL_Pos 0 /**< \brief (SDHC_HC1R) LED Control */
+#define SDHC_HC1R_LEDCTRL (_U_(0x1) << SDHC_HC1R_LEDCTRL_Pos)
+#define SDHC_HC1R_LEDCTRL_OFF_Val _U_(0x0) /**< \brief (SDHC_HC1R) LED off */
+#define SDHC_HC1R_LEDCTRL_ON_Val _U_(0x1) /**< \brief (SDHC_HC1R) LED on */
+#define SDHC_HC1R_LEDCTRL_OFF (SDHC_HC1R_LEDCTRL_OFF_Val << SDHC_HC1R_LEDCTRL_Pos)
+#define SDHC_HC1R_LEDCTRL_ON (SDHC_HC1R_LEDCTRL_ON_Val << SDHC_HC1R_LEDCTRL_Pos)
+#define SDHC_HC1R_DW_Pos 1 /**< \brief (SDHC_HC1R) Data Width */
+#define SDHC_HC1R_DW (_U_(0x1) << SDHC_HC1R_DW_Pos)
+#define SDHC_HC1R_DW_1BIT_Val _U_(0x0) /**< \brief (SDHC_HC1R) 1-bit mode */
+#define SDHC_HC1R_DW_4BIT_Val _U_(0x1) /**< \brief (SDHC_HC1R) 4-bit mode */
+#define SDHC_HC1R_DW_1BIT (SDHC_HC1R_DW_1BIT_Val << SDHC_HC1R_DW_Pos)
+#define SDHC_HC1R_DW_4BIT (SDHC_HC1R_DW_4BIT_Val << SDHC_HC1R_DW_Pos)
+#define SDHC_HC1R_HSEN_Pos 2 /**< \brief (SDHC_HC1R) High Speed Enable */
+#define SDHC_HC1R_HSEN (_U_(0x1) << SDHC_HC1R_HSEN_Pos)
+#define SDHC_HC1R_HSEN_NORMAL_Val _U_(0x0) /**< \brief (SDHC_HC1R) Normal Speed mode */
+#define SDHC_HC1R_HSEN_HIGH_Val _U_(0x1) /**< \brief (SDHC_HC1R) High Speed mode */
+#define SDHC_HC1R_HSEN_NORMAL (SDHC_HC1R_HSEN_NORMAL_Val << SDHC_HC1R_HSEN_Pos)
+#define SDHC_HC1R_HSEN_HIGH (SDHC_HC1R_HSEN_HIGH_Val << SDHC_HC1R_HSEN_Pos)
+#define SDHC_HC1R_DMASEL_Pos 3 /**< \brief (SDHC_HC1R) DMA Select */
+#define SDHC_HC1R_DMASEL_Msk (_U_(0x3) << SDHC_HC1R_DMASEL_Pos)
+#define SDHC_HC1R_DMASEL(value) (SDHC_HC1R_DMASEL_Msk & ((value) << SDHC_HC1R_DMASEL_Pos))
+#define SDHC_HC1R_DMASEL_SDMA_Val _U_(0x0) /**< \brief (SDHC_HC1R) SDMA is selected */
+#define SDHC_HC1R_DMASEL_1_Val _U_(0x1) /**< \brief (SDHC_HC1R) Reserved */
+#define SDHC_HC1R_DMASEL_32BIT_Val _U_(0x2) /**< \brief (SDHC_HC1R) 32-bit Address ADMA2 is selected */
+#define SDHC_HC1R_DMASEL_SDMA (SDHC_HC1R_DMASEL_SDMA_Val << SDHC_HC1R_DMASEL_Pos)
+#define SDHC_HC1R_DMASEL_1 (SDHC_HC1R_DMASEL_1_Val << SDHC_HC1R_DMASEL_Pos)
+#define SDHC_HC1R_DMASEL_32BIT (SDHC_HC1R_DMASEL_32BIT_Val << SDHC_HC1R_DMASEL_Pos)
+#define SDHC_HC1R_CARDDTL_Pos 6 /**< \brief (SDHC_HC1R) Card Detect Test Level */
+#define SDHC_HC1R_CARDDTL (_U_(0x1) << SDHC_HC1R_CARDDTL_Pos)
+#define SDHC_HC1R_CARDDTL_NO_Val _U_(0x0) /**< \brief (SDHC_HC1R) No Card */
+#define SDHC_HC1R_CARDDTL_YES_Val _U_(0x1) /**< \brief (SDHC_HC1R) Card Inserted */
+#define SDHC_HC1R_CARDDTL_NO (SDHC_HC1R_CARDDTL_NO_Val << SDHC_HC1R_CARDDTL_Pos)
+#define SDHC_HC1R_CARDDTL_YES (SDHC_HC1R_CARDDTL_YES_Val << SDHC_HC1R_CARDDTL_Pos)
+#define SDHC_HC1R_CARDDSEL_Pos 7 /**< \brief (SDHC_HC1R) Card Detect Signal Selection */
+#define SDHC_HC1R_CARDDSEL (_U_(0x1) << SDHC_HC1R_CARDDSEL_Pos)
+#define SDHC_HC1R_CARDDSEL_NORMAL_Val _U_(0x0) /**< \brief (SDHC_HC1R) SDCD# is selected (for normal use) */
+#define SDHC_HC1R_CARDDSEL_TEST_Val _U_(0x1) /**< \brief (SDHC_HC1R) The Card Select Test Level is selected (for test purpose) */
+#define SDHC_HC1R_CARDDSEL_NORMAL (SDHC_HC1R_CARDDSEL_NORMAL_Val << SDHC_HC1R_CARDDSEL_Pos)
+#define SDHC_HC1R_CARDDSEL_TEST (SDHC_HC1R_CARDDSEL_TEST_Val << SDHC_HC1R_CARDDSEL_Pos)
+#define SDHC_HC1R_MASK _U_(0xDF) /**< \brief (SDHC_HC1R) MASK Register */
+
+// EMMC mode
+#define SDHC_HC1R_EMMC_DW_Pos 1 /**< \brief (SDHC_HC1R_EMMC) Data Width */
+#define SDHC_HC1R_EMMC_DW (_U_(0x1) << SDHC_HC1R_EMMC_DW_Pos)
+#define SDHC_HC1R_EMMC_DW_1BIT_Val _U_(0x0) /**< \brief (SDHC_HC1R_EMMC) 1-bit mode */
+#define SDHC_HC1R_EMMC_DW_4BIT_Val _U_(0x1) /**< \brief (SDHC_HC1R_EMMC) 4-bit mode */
+#define SDHC_HC1R_EMMC_DW_1BIT (SDHC_HC1R_EMMC_DW_1BIT_Val << SDHC_HC1R_EMMC_DW_Pos)
+#define SDHC_HC1R_EMMC_DW_4BIT (SDHC_HC1R_EMMC_DW_4BIT_Val << SDHC_HC1R_EMMC_DW_Pos)
+#define SDHC_HC1R_EMMC_HSEN_Pos 2 /**< \brief (SDHC_HC1R_EMMC) High Speed Enable */
+#define SDHC_HC1R_EMMC_HSEN (_U_(0x1) << SDHC_HC1R_EMMC_HSEN_Pos)
+#define SDHC_HC1R_EMMC_HSEN_NORMAL_Val _U_(0x0) /**< \brief (SDHC_HC1R_EMMC) Normal Speed mode */
+#define SDHC_HC1R_EMMC_HSEN_HIGH_Val _U_(0x1) /**< \brief (SDHC_HC1R_EMMC) High Speed mode */
+#define SDHC_HC1R_EMMC_HSEN_NORMAL (SDHC_HC1R_EMMC_HSEN_NORMAL_Val << SDHC_HC1R_EMMC_HSEN_Pos)
+#define SDHC_HC1R_EMMC_HSEN_HIGH (SDHC_HC1R_EMMC_HSEN_HIGH_Val << SDHC_HC1R_EMMC_HSEN_Pos)
+#define SDHC_HC1R_EMMC_DMASEL_Pos 3 /**< \brief (SDHC_HC1R_EMMC) DMA Select */
+#define SDHC_HC1R_EMMC_DMASEL_Msk (_U_(0x3) << SDHC_HC1R_EMMC_DMASEL_Pos)
+#define SDHC_HC1R_EMMC_DMASEL(value) (SDHC_HC1R_EMMC_DMASEL_Msk & ((value) << SDHC_HC1R_EMMC_DMASEL_Pos))
+#define SDHC_HC1R_EMMC_DMASEL_SDMA_Val _U_(0x0) /**< \brief (SDHC_HC1R_EMMC) SDMA is selected */
+#define SDHC_HC1R_EMMC_DMASEL_1_Val _U_(0x1) /**< \brief (SDHC_HC1R_EMMC) Reserved */
+#define SDHC_HC1R_EMMC_DMASEL_32BIT_Val _U_(0x2) /**< \brief (SDHC_HC1R_EMMC) 32-bit Address ADMA2 is selected */
+#define SDHC_HC1R_EMMC_DMASEL_SDMA (SDHC_HC1R_EMMC_DMASEL_SDMA_Val << SDHC_HC1R_EMMC_DMASEL_Pos)
+#define SDHC_HC1R_EMMC_DMASEL_1 (SDHC_HC1R_EMMC_DMASEL_1_Val << SDHC_HC1R_EMMC_DMASEL_Pos)
+#define SDHC_HC1R_EMMC_DMASEL_32BIT (SDHC_HC1R_EMMC_DMASEL_32BIT_Val << SDHC_HC1R_EMMC_DMASEL_Pos)
+#define SDHC_HC1R_EMMC_MASK _U_(0x1E) /**< \brief (SDHC_HC1R_EMMC) MASK Register */
+
+/* -------- SDHC_PCR : (SDHC Offset: 0x029) (R/W 8) Power Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SDBPWR:1; /*!< bit: 0 SD Bus Power */
+ uint8_t SDBVSEL:3; /*!< bit: 1.. 3 SD Bus Voltage Select */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_PCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_PCR_OFFSET 0x029 /**< \brief (SDHC_PCR offset) Power Control */
+#define SDHC_PCR_RESETVALUE _U_(0x0E) /**< \brief (SDHC_PCR reset_value) Power Control */
+
+#define SDHC_PCR_SDBPWR_Pos 0 /**< \brief (SDHC_PCR) SD Bus Power */
+#define SDHC_PCR_SDBPWR (_U_(0x1) << SDHC_PCR_SDBPWR_Pos)
+#define SDHC_PCR_SDBPWR_OFF_Val _U_(0x0) /**< \brief (SDHC_PCR) Power off */
+#define SDHC_PCR_SDBPWR_ON_Val _U_(0x1) /**< \brief (SDHC_PCR) Power on */
+#define SDHC_PCR_SDBPWR_OFF (SDHC_PCR_SDBPWR_OFF_Val << SDHC_PCR_SDBPWR_Pos)
+#define SDHC_PCR_SDBPWR_ON (SDHC_PCR_SDBPWR_ON_Val << SDHC_PCR_SDBPWR_Pos)
+#define SDHC_PCR_SDBVSEL_Pos 1 /**< \brief (SDHC_PCR) SD Bus Voltage Select */
+#define SDHC_PCR_SDBVSEL_Msk (_U_(0x7) << SDHC_PCR_SDBVSEL_Pos)
+#define SDHC_PCR_SDBVSEL(value) (SDHC_PCR_SDBVSEL_Msk & ((value) << SDHC_PCR_SDBVSEL_Pos))
+#define SDHC_PCR_SDBVSEL_1V8_Val _U_(0x5) /**< \brief (SDHC_PCR) 1.8V (Typ.) */
+#define SDHC_PCR_SDBVSEL_3V0_Val _U_(0x6) /**< \brief (SDHC_PCR) 3.0V (Typ.) */
+#define SDHC_PCR_SDBVSEL_3V3_Val _U_(0x7) /**< \brief (SDHC_PCR) 3.3V (Typ.) */
+#define SDHC_PCR_SDBVSEL_1V8 (SDHC_PCR_SDBVSEL_1V8_Val << SDHC_PCR_SDBVSEL_Pos)
+#define SDHC_PCR_SDBVSEL_3V0 (SDHC_PCR_SDBVSEL_3V0_Val << SDHC_PCR_SDBVSEL_Pos)
+#define SDHC_PCR_SDBVSEL_3V3 (SDHC_PCR_SDBVSEL_3V3_Val << SDHC_PCR_SDBVSEL_Pos)
+#define SDHC_PCR_MASK _U_(0x0F) /**< \brief (SDHC_PCR) MASK Register */
+
+/* -------- SDHC_BGCR : (SDHC Offset: 0x02A) (R/W 8) Block Gap Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STPBGR:1; /*!< bit: 0 Stop at Block Gap Request */
+ uint8_t CONTR:1; /*!< bit: 1 Continue Request */
+ uint8_t RWCTRL:1; /*!< bit: 2 Read Wait Control */
+ uint8_t INTBG:1; /*!< bit: 3 Interrupt at Block Gap */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct { // EMMC mode
+ uint8_t STPBGR:1; /*!< bit: 0 Stop at Block Gap Request */
+ uint8_t CONTR:1; /*!< bit: 1 Continue Request */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } EMMC; /*!< Structure used for EMMC */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_BGCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_BGCR_OFFSET 0x02A /**< \brief (SDHC_BGCR offset) Block Gap Control */
+#define SDHC_BGCR_RESETVALUE _U_(0x00) /**< \brief (SDHC_BGCR reset_value) Block Gap Control */
+
+#define SDHC_BGCR_STPBGR_Pos 0 /**< \brief (SDHC_BGCR) Stop at Block Gap Request */
+#define SDHC_BGCR_STPBGR (_U_(0x1) << SDHC_BGCR_STPBGR_Pos)
+#define SDHC_BGCR_STPBGR_TRANSFER_Val _U_(0x0) /**< \brief (SDHC_BGCR) Transfer */
+#define SDHC_BGCR_STPBGR_STOP_Val _U_(0x1) /**< \brief (SDHC_BGCR) Stop */
+#define SDHC_BGCR_STPBGR_TRANSFER (SDHC_BGCR_STPBGR_TRANSFER_Val << SDHC_BGCR_STPBGR_Pos)
+#define SDHC_BGCR_STPBGR_STOP (SDHC_BGCR_STPBGR_STOP_Val << SDHC_BGCR_STPBGR_Pos)
+#define SDHC_BGCR_CONTR_Pos 1 /**< \brief (SDHC_BGCR) Continue Request */
+#define SDHC_BGCR_CONTR (_U_(0x1) << SDHC_BGCR_CONTR_Pos)
+#define SDHC_BGCR_CONTR_GO_ON_Val _U_(0x0) /**< \brief (SDHC_BGCR) Not affected */
+#define SDHC_BGCR_CONTR_RESTART_Val _U_(0x1) /**< \brief (SDHC_BGCR) Restart */
+#define SDHC_BGCR_CONTR_GO_ON (SDHC_BGCR_CONTR_GO_ON_Val << SDHC_BGCR_CONTR_Pos)
+#define SDHC_BGCR_CONTR_RESTART (SDHC_BGCR_CONTR_RESTART_Val << SDHC_BGCR_CONTR_Pos)
+#define SDHC_BGCR_RWCTRL_Pos 2 /**< \brief (SDHC_BGCR) Read Wait Control */
+#define SDHC_BGCR_RWCTRL (_U_(0x1) << SDHC_BGCR_RWCTRL_Pos)
+#define SDHC_BGCR_RWCTRL_DISABLE_Val _U_(0x0) /**< \brief (SDHC_BGCR) Disable Read Wait Control */
+#define SDHC_BGCR_RWCTRL_ENABLE_Val _U_(0x1) /**< \brief (SDHC_BGCR) Enable Read Wait Control */
+#define SDHC_BGCR_RWCTRL_DISABLE (SDHC_BGCR_RWCTRL_DISABLE_Val << SDHC_BGCR_RWCTRL_Pos)
+#define SDHC_BGCR_RWCTRL_ENABLE (SDHC_BGCR_RWCTRL_ENABLE_Val << SDHC_BGCR_RWCTRL_Pos)
+#define SDHC_BGCR_INTBG_Pos 3 /**< \brief (SDHC_BGCR) Interrupt at Block Gap */
+#define SDHC_BGCR_INTBG (_U_(0x1) << SDHC_BGCR_INTBG_Pos)
+#define SDHC_BGCR_INTBG_DISABLED_Val _U_(0x0) /**< \brief (SDHC_BGCR) Disabled */
+#define SDHC_BGCR_INTBG_ENABLED_Val _U_(0x1) /**< \brief (SDHC_BGCR) Enabled */
+#define SDHC_BGCR_INTBG_DISABLED (SDHC_BGCR_INTBG_DISABLED_Val << SDHC_BGCR_INTBG_Pos)
+#define SDHC_BGCR_INTBG_ENABLED (SDHC_BGCR_INTBG_ENABLED_Val << SDHC_BGCR_INTBG_Pos)
+#define SDHC_BGCR_MASK _U_(0x0F) /**< \brief (SDHC_BGCR) MASK Register */
+
+// EMMC mode
+#define SDHC_BGCR_EMMC_STPBGR_Pos 0 /**< \brief (SDHC_BGCR_EMMC) Stop at Block Gap Request */
+#define SDHC_BGCR_EMMC_STPBGR (_U_(0x1) << SDHC_BGCR_EMMC_STPBGR_Pos)
+#define SDHC_BGCR_EMMC_STPBGR_TRANSFER_Val _U_(0x0) /**< \brief (SDHC_BGCR_EMMC) Transfer */
+#define SDHC_BGCR_EMMC_STPBGR_STOP_Val _U_(0x1) /**< \brief (SDHC_BGCR_EMMC) Stop */
+#define SDHC_BGCR_EMMC_STPBGR_TRANSFER (SDHC_BGCR_EMMC_STPBGR_TRANSFER_Val << SDHC_BGCR_EMMC_STPBGR_Pos)
+#define SDHC_BGCR_EMMC_STPBGR_STOP (SDHC_BGCR_EMMC_STPBGR_STOP_Val << SDHC_BGCR_EMMC_STPBGR_Pos)
+#define SDHC_BGCR_EMMC_CONTR_Pos 1 /**< \brief (SDHC_BGCR_EMMC) Continue Request */
+#define SDHC_BGCR_EMMC_CONTR (_U_(0x1) << SDHC_BGCR_EMMC_CONTR_Pos)
+#define SDHC_BGCR_EMMC_CONTR_GO_ON_Val _U_(0x0) /**< \brief (SDHC_BGCR_EMMC) Not affected */
+#define SDHC_BGCR_EMMC_CONTR_RESTART_Val _U_(0x1) /**< \brief (SDHC_BGCR_EMMC) Restart */
+#define SDHC_BGCR_EMMC_CONTR_GO_ON (SDHC_BGCR_EMMC_CONTR_GO_ON_Val << SDHC_BGCR_EMMC_CONTR_Pos)
+#define SDHC_BGCR_EMMC_CONTR_RESTART (SDHC_BGCR_EMMC_CONTR_RESTART_Val << SDHC_BGCR_EMMC_CONTR_Pos)
+#define SDHC_BGCR_EMMC_MASK _U_(0x03) /**< \brief (SDHC_BGCR_EMMC) MASK Register */
+
+/* -------- SDHC_WCR : (SDHC Offset: 0x02B) (R/W 8) Wakeup Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t WKENCINT:1; /*!< bit: 0 Wakeup Event Enable on Card Interrupt */
+ uint8_t WKENCINS:1; /*!< bit: 1 Wakeup Event Enable on Card Insertion */
+ uint8_t WKENCREM:1; /*!< bit: 2 Wakeup Event Enable on Card Removal */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_WCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_WCR_OFFSET 0x02B /**< \brief (SDHC_WCR offset) Wakeup Control */
+#define SDHC_WCR_RESETVALUE _U_(0x00) /**< \brief (SDHC_WCR reset_value) Wakeup Control */
+
+#define SDHC_WCR_WKENCINT_Pos 0 /**< \brief (SDHC_WCR) Wakeup Event Enable on Card Interrupt */
+#define SDHC_WCR_WKENCINT (_U_(0x1) << SDHC_WCR_WKENCINT_Pos)
+#define SDHC_WCR_WKENCINT_DISABLE_Val _U_(0x0) /**< \brief (SDHC_WCR) Disable */
+#define SDHC_WCR_WKENCINT_ENABLE_Val _U_(0x1) /**< \brief (SDHC_WCR) Enable */
+#define SDHC_WCR_WKENCINT_DISABLE (SDHC_WCR_WKENCINT_DISABLE_Val << SDHC_WCR_WKENCINT_Pos)
+#define SDHC_WCR_WKENCINT_ENABLE (SDHC_WCR_WKENCINT_ENABLE_Val << SDHC_WCR_WKENCINT_Pos)
+#define SDHC_WCR_WKENCINS_Pos 1 /**< \brief (SDHC_WCR) Wakeup Event Enable on Card Insertion */
+#define SDHC_WCR_WKENCINS (_U_(0x1) << SDHC_WCR_WKENCINS_Pos)
+#define SDHC_WCR_WKENCINS_DISABLE_Val _U_(0x0) /**< \brief (SDHC_WCR) Disable */
+#define SDHC_WCR_WKENCINS_ENABLE_Val _U_(0x1) /**< \brief (SDHC_WCR) Enable */
+#define SDHC_WCR_WKENCINS_DISABLE (SDHC_WCR_WKENCINS_DISABLE_Val << SDHC_WCR_WKENCINS_Pos)
+#define SDHC_WCR_WKENCINS_ENABLE (SDHC_WCR_WKENCINS_ENABLE_Val << SDHC_WCR_WKENCINS_Pos)
+#define SDHC_WCR_WKENCREM_Pos 2 /**< \brief (SDHC_WCR) Wakeup Event Enable on Card Removal */
+#define SDHC_WCR_WKENCREM (_U_(0x1) << SDHC_WCR_WKENCREM_Pos)
+#define SDHC_WCR_WKENCREM_DISABLE_Val _U_(0x0) /**< \brief (SDHC_WCR) Disable */
+#define SDHC_WCR_WKENCREM_ENABLE_Val _U_(0x1) /**< \brief (SDHC_WCR) Enable */
+#define SDHC_WCR_WKENCREM_DISABLE (SDHC_WCR_WKENCREM_DISABLE_Val << SDHC_WCR_WKENCREM_Pos)
+#define SDHC_WCR_WKENCREM_ENABLE (SDHC_WCR_WKENCREM_ENABLE_Val << SDHC_WCR_WKENCREM_Pos)
+#define SDHC_WCR_MASK _U_(0x07) /**< \brief (SDHC_WCR) MASK Register */
+
+/* -------- SDHC_CCR : (SDHC Offset: 0x02C) (R/W 16) Clock Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t INTCLKEN:1; /*!< bit: 0 Internal Clock Enable */
+ uint16_t INTCLKS:1; /*!< bit: 1 Internal Clock Stable */
+ uint16_t SDCLKEN:1; /*!< bit: 2 SD Clock Enable */
+ uint16_t :2; /*!< bit: 3.. 4 Reserved */
+ uint16_t CLKGSEL:1; /*!< bit: 5 Clock Generator Select */
+ uint16_t USDCLKFSEL:2; /*!< bit: 6.. 7 Upper Bits of SDCLK Frequency Select */
+ uint16_t SDCLKFSEL:8; /*!< bit: 8..15 SDCLK Frequency Select */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_CCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_CCR_OFFSET 0x02C /**< \brief (SDHC_CCR offset) Clock Control */
+#define SDHC_CCR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_CCR reset_value) Clock Control */
+
+#define SDHC_CCR_INTCLKEN_Pos 0 /**< \brief (SDHC_CCR) Internal Clock Enable */
+#define SDHC_CCR_INTCLKEN (_U_(0x1) << SDHC_CCR_INTCLKEN_Pos)
+#define SDHC_CCR_INTCLKEN_OFF_Val _U_(0x0) /**< \brief (SDHC_CCR) Stop */
+#define SDHC_CCR_INTCLKEN_ON_Val _U_(0x1) /**< \brief (SDHC_CCR) Oscillate */
+#define SDHC_CCR_INTCLKEN_OFF (SDHC_CCR_INTCLKEN_OFF_Val << SDHC_CCR_INTCLKEN_Pos)
+#define SDHC_CCR_INTCLKEN_ON (SDHC_CCR_INTCLKEN_ON_Val << SDHC_CCR_INTCLKEN_Pos)
+#define SDHC_CCR_INTCLKS_Pos 1 /**< \brief (SDHC_CCR) Internal Clock Stable */
+#define SDHC_CCR_INTCLKS (_U_(0x1) << SDHC_CCR_INTCLKS_Pos)
+#define SDHC_CCR_INTCLKS_NOT_READY_Val _U_(0x0) /**< \brief (SDHC_CCR) Not Ready */
+#define SDHC_CCR_INTCLKS_READY_Val _U_(0x1) /**< \brief (SDHC_CCR) Ready */
+#define SDHC_CCR_INTCLKS_NOT_READY (SDHC_CCR_INTCLKS_NOT_READY_Val << SDHC_CCR_INTCLKS_Pos)
+#define SDHC_CCR_INTCLKS_READY (SDHC_CCR_INTCLKS_READY_Val << SDHC_CCR_INTCLKS_Pos)
+#define SDHC_CCR_SDCLKEN_Pos 2 /**< \brief (SDHC_CCR) SD Clock Enable */
+#define SDHC_CCR_SDCLKEN (_U_(0x1) << SDHC_CCR_SDCLKEN_Pos)
+#define SDHC_CCR_SDCLKEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_CCR) Disable */
+#define SDHC_CCR_SDCLKEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_CCR) Enable */
+#define SDHC_CCR_SDCLKEN_DISABLE (SDHC_CCR_SDCLKEN_DISABLE_Val << SDHC_CCR_SDCLKEN_Pos)
+#define SDHC_CCR_SDCLKEN_ENABLE (SDHC_CCR_SDCLKEN_ENABLE_Val << SDHC_CCR_SDCLKEN_Pos)
+#define SDHC_CCR_CLKGSEL_Pos 5 /**< \brief (SDHC_CCR) Clock Generator Select */
+#define SDHC_CCR_CLKGSEL (_U_(0x1) << SDHC_CCR_CLKGSEL_Pos)
+#define SDHC_CCR_CLKGSEL_DIV_Val _U_(0x0) /**< \brief (SDHC_CCR) Divided Clock Mode */
+#define SDHC_CCR_CLKGSEL_PROG_Val _U_(0x1) /**< \brief (SDHC_CCR) Programmable Clock Mode */
+#define SDHC_CCR_CLKGSEL_DIV (SDHC_CCR_CLKGSEL_DIV_Val << SDHC_CCR_CLKGSEL_Pos)
+#define SDHC_CCR_CLKGSEL_PROG (SDHC_CCR_CLKGSEL_PROG_Val << SDHC_CCR_CLKGSEL_Pos)
+#define SDHC_CCR_USDCLKFSEL_Pos 6 /**< \brief (SDHC_CCR) Upper Bits of SDCLK Frequency Select */
+#define SDHC_CCR_USDCLKFSEL_Msk (_U_(0x3) << SDHC_CCR_USDCLKFSEL_Pos)
+#define SDHC_CCR_USDCLKFSEL(value) (SDHC_CCR_USDCLKFSEL_Msk & ((value) << SDHC_CCR_USDCLKFSEL_Pos))
+#define SDHC_CCR_SDCLKFSEL_Pos 8 /**< \brief (SDHC_CCR) SDCLK Frequency Select */
+#define SDHC_CCR_SDCLKFSEL_Msk (_U_(0xFF) << SDHC_CCR_SDCLKFSEL_Pos)
+#define SDHC_CCR_SDCLKFSEL(value) (SDHC_CCR_SDCLKFSEL_Msk & ((value) << SDHC_CCR_SDCLKFSEL_Pos))
+#define SDHC_CCR_MASK _U_(0xFFE7) /**< \brief (SDHC_CCR) MASK Register */
+
+/* -------- SDHC_TCR : (SDHC Offset: 0x02E) (R/W 8) Timeout Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTCVAL:4; /*!< bit: 0.. 3 Data Timeout Counter Value */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_TCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_TCR_OFFSET 0x02E /**< \brief (SDHC_TCR offset) Timeout Control */
+#define SDHC_TCR_RESETVALUE _U_(0x00) /**< \brief (SDHC_TCR reset_value) Timeout Control */
+
+#define SDHC_TCR_DTCVAL_Pos 0 /**< \brief (SDHC_TCR) Data Timeout Counter Value */
+#define SDHC_TCR_DTCVAL_Msk (_U_(0xF) << SDHC_TCR_DTCVAL_Pos)
+#define SDHC_TCR_DTCVAL(value) (SDHC_TCR_DTCVAL_Msk & ((value) << SDHC_TCR_DTCVAL_Pos))
+#define SDHC_TCR_MASK _U_(0x0F) /**< \brief (SDHC_TCR) MASK Register */
+
+/* -------- SDHC_SRR : (SDHC Offset: 0x02F) (R/W 8) Software Reset -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRSTALL:1; /*!< bit: 0 Software Reset For All */
+ uint8_t SWRSTCMD:1; /*!< bit: 1 Software Reset For CMD Line */
+ uint8_t SWRSTDAT:1; /*!< bit: 2 Software Reset For DAT Line */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_SRR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_SRR_OFFSET 0x02F /**< \brief (SDHC_SRR offset) Software Reset */
+#define SDHC_SRR_RESETVALUE _U_(0x00) /**< \brief (SDHC_SRR reset_value) Software Reset */
+
+#define SDHC_SRR_SWRSTALL_Pos 0 /**< \brief (SDHC_SRR) Software Reset For All */
+#define SDHC_SRR_SWRSTALL (_U_(0x1) << SDHC_SRR_SWRSTALL_Pos)
+#define SDHC_SRR_SWRSTALL_WORK_Val _U_(0x0) /**< \brief (SDHC_SRR) Work */
+#define SDHC_SRR_SWRSTALL_RESET_Val _U_(0x1) /**< \brief (SDHC_SRR) Reset */
+#define SDHC_SRR_SWRSTALL_WORK (SDHC_SRR_SWRSTALL_WORK_Val << SDHC_SRR_SWRSTALL_Pos)
+#define SDHC_SRR_SWRSTALL_RESET (SDHC_SRR_SWRSTALL_RESET_Val << SDHC_SRR_SWRSTALL_Pos)
+#define SDHC_SRR_SWRSTCMD_Pos 1 /**< \brief (SDHC_SRR) Software Reset For CMD Line */
+#define SDHC_SRR_SWRSTCMD (_U_(0x1) << SDHC_SRR_SWRSTCMD_Pos)
+#define SDHC_SRR_SWRSTCMD_WORK_Val _U_(0x0) /**< \brief (SDHC_SRR) Work */
+#define SDHC_SRR_SWRSTCMD_RESET_Val _U_(0x1) /**< \brief (SDHC_SRR) Reset */
+#define SDHC_SRR_SWRSTCMD_WORK (SDHC_SRR_SWRSTCMD_WORK_Val << SDHC_SRR_SWRSTCMD_Pos)
+#define SDHC_SRR_SWRSTCMD_RESET (SDHC_SRR_SWRSTCMD_RESET_Val << SDHC_SRR_SWRSTCMD_Pos)
+#define SDHC_SRR_SWRSTDAT_Pos 2 /**< \brief (SDHC_SRR) Software Reset For DAT Line */
+#define SDHC_SRR_SWRSTDAT (_U_(0x1) << SDHC_SRR_SWRSTDAT_Pos)
+#define SDHC_SRR_SWRSTDAT_WORK_Val _U_(0x0) /**< \brief (SDHC_SRR) Work */
+#define SDHC_SRR_SWRSTDAT_RESET_Val _U_(0x1) /**< \brief (SDHC_SRR) Reset */
+#define SDHC_SRR_SWRSTDAT_WORK (SDHC_SRR_SWRSTDAT_WORK_Val << SDHC_SRR_SWRSTDAT_Pos)
+#define SDHC_SRR_SWRSTDAT_RESET (SDHC_SRR_SWRSTDAT_RESET_Val << SDHC_SRR_SWRSTDAT_Pos)
+#define SDHC_SRR_MASK _U_(0x07) /**< \brief (SDHC_SRR) MASK Register */
+
+/* -------- SDHC_NISTR : (SDHC Offset: 0x030) (R/W 16) Normal Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CMDC:1; /*!< bit: 0 Command Complete */
+ uint16_t TRFC:1; /*!< bit: 1 Transfer Complete */
+ uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event */
+ uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt */
+ uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready */
+ uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready */
+ uint16_t CINS:1; /*!< bit: 6 Card Insertion */
+ uint16_t CREM:1; /*!< bit: 7 Card Removal */
+ uint16_t CINT:1; /*!< bit: 8 Card Interrupt */
+ uint16_t :6; /*!< bit: 9..14 Reserved */
+ uint16_t ERRINT:1; /*!< bit: 15 Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ struct { // EMMC mode
+ uint16_t CMDC:1; /*!< bit: 0 Command Complete */
+ uint16_t TRFC:1; /*!< bit: 1 Transfer Complete */
+ uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event */
+ uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt */
+ uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready */
+ uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready */
+ uint16_t :8; /*!< bit: 6..13 Reserved */
+ uint16_t BOOTAR:1; /*!< bit: 14 Boot Acknowledge Received */
+ uint16_t ERRINT:1; /*!< bit: 15 Error Interrupt */
+ } EMMC; /*!< Structure used for EMMC */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_NISTR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_NISTR_OFFSET 0x030 /**< \brief (SDHC_NISTR offset) Normal Interrupt Status */
+#define SDHC_NISTR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_NISTR reset_value) Normal Interrupt Status */
+
+#define SDHC_NISTR_CMDC_Pos 0 /**< \brief (SDHC_NISTR) Command Complete */
+#define SDHC_NISTR_CMDC (_U_(0x1) << SDHC_NISTR_CMDC_Pos)
+#define SDHC_NISTR_CMDC_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No command complete */
+#define SDHC_NISTR_CMDC_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Command complete */
+#define SDHC_NISTR_CMDC_NO (SDHC_NISTR_CMDC_NO_Val << SDHC_NISTR_CMDC_Pos)
+#define SDHC_NISTR_CMDC_YES (SDHC_NISTR_CMDC_YES_Val << SDHC_NISTR_CMDC_Pos)
+#define SDHC_NISTR_TRFC_Pos 1 /**< \brief (SDHC_NISTR) Transfer Complete */
+#define SDHC_NISTR_TRFC (_U_(0x1) << SDHC_NISTR_TRFC_Pos)
+#define SDHC_NISTR_TRFC_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Not complete */
+#define SDHC_NISTR_TRFC_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Command execution is completed */
+#define SDHC_NISTR_TRFC_NO (SDHC_NISTR_TRFC_NO_Val << SDHC_NISTR_TRFC_Pos)
+#define SDHC_NISTR_TRFC_YES (SDHC_NISTR_TRFC_YES_Val << SDHC_NISTR_TRFC_Pos)
+#define SDHC_NISTR_BLKGE_Pos 2 /**< \brief (SDHC_NISTR) Block Gap Event */
+#define SDHC_NISTR_BLKGE (_U_(0x1) << SDHC_NISTR_BLKGE_Pos)
+#define SDHC_NISTR_BLKGE_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No Block Gap Event */
+#define SDHC_NISTR_BLKGE_STOP_Val _U_(0x1) /**< \brief (SDHC_NISTR) Transaction stopped at block gap */
+#define SDHC_NISTR_BLKGE_NO (SDHC_NISTR_BLKGE_NO_Val << SDHC_NISTR_BLKGE_Pos)
+#define SDHC_NISTR_BLKGE_STOP (SDHC_NISTR_BLKGE_STOP_Val << SDHC_NISTR_BLKGE_Pos)
+#define SDHC_NISTR_DMAINT_Pos 3 /**< \brief (SDHC_NISTR) DMA Interrupt */
+#define SDHC_NISTR_DMAINT (_U_(0x1) << SDHC_NISTR_DMAINT_Pos)
+#define SDHC_NISTR_DMAINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No DMA Interrupt */
+#define SDHC_NISTR_DMAINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) DMA Interrupt is generated */
+#define SDHC_NISTR_DMAINT_NO (SDHC_NISTR_DMAINT_NO_Val << SDHC_NISTR_DMAINT_Pos)
+#define SDHC_NISTR_DMAINT_YES (SDHC_NISTR_DMAINT_YES_Val << SDHC_NISTR_DMAINT_Pos)
+#define SDHC_NISTR_BWRRDY_Pos 4 /**< \brief (SDHC_NISTR) Buffer Write Ready */
+#define SDHC_NISTR_BWRRDY (_U_(0x1) << SDHC_NISTR_BWRRDY_Pos)
+#define SDHC_NISTR_BWRRDY_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Not ready to write buffer */
+#define SDHC_NISTR_BWRRDY_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Ready to write buffer */
+#define SDHC_NISTR_BWRRDY_NO (SDHC_NISTR_BWRRDY_NO_Val << SDHC_NISTR_BWRRDY_Pos)
+#define SDHC_NISTR_BWRRDY_YES (SDHC_NISTR_BWRRDY_YES_Val << SDHC_NISTR_BWRRDY_Pos)
+#define SDHC_NISTR_BRDRDY_Pos 5 /**< \brief (SDHC_NISTR) Buffer Read Ready */
+#define SDHC_NISTR_BRDRDY (_U_(0x1) << SDHC_NISTR_BRDRDY_Pos)
+#define SDHC_NISTR_BRDRDY_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Not ready to read buffer */
+#define SDHC_NISTR_BRDRDY_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Ready to read buffer */
+#define SDHC_NISTR_BRDRDY_NO (SDHC_NISTR_BRDRDY_NO_Val << SDHC_NISTR_BRDRDY_Pos)
+#define SDHC_NISTR_BRDRDY_YES (SDHC_NISTR_BRDRDY_YES_Val << SDHC_NISTR_BRDRDY_Pos)
+#define SDHC_NISTR_CINS_Pos 6 /**< \brief (SDHC_NISTR) Card Insertion */
+#define SDHC_NISTR_CINS (_U_(0x1) << SDHC_NISTR_CINS_Pos)
+#define SDHC_NISTR_CINS_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Card state stable or Debouncing */
+#define SDHC_NISTR_CINS_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Card inserted */
+#define SDHC_NISTR_CINS_NO (SDHC_NISTR_CINS_NO_Val << SDHC_NISTR_CINS_Pos)
+#define SDHC_NISTR_CINS_YES (SDHC_NISTR_CINS_YES_Val << SDHC_NISTR_CINS_Pos)
+#define SDHC_NISTR_CREM_Pos 7 /**< \brief (SDHC_NISTR) Card Removal */
+#define SDHC_NISTR_CREM (_U_(0x1) << SDHC_NISTR_CREM_Pos)
+#define SDHC_NISTR_CREM_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Card state stable or Debouncing */
+#define SDHC_NISTR_CREM_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Card Removed */
+#define SDHC_NISTR_CREM_NO (SDHC_NISTR_CREM_NO_Val << SDHC_NISTR_CREM_Pos)
+#define SDHC_NISTR_CREM_YES (SDHC_NISTR_CREM_YES_Val << SDHC_NISTR_CREM_Pos)
+#define SDHC_NISTR_CINT_Pos 8 /**< \brief (SDHC_NISTR) Card Interrupt */
+#define SDHC_NISTR_CINT (_U_(0x1) << SDHC_NISTR_CINT_Pos)
+#define SDHC_NISTR_CINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No Card Interrupt */
+#define SDHC_NISTR_CINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Generate Card Interrupt */
+#define SDHC_NISTR_CINT_NO (SDHC_NISTR_CINT_NO_Val << SDHC_NISTR_CINT_Pos)
+#define SDHC_NISTR_CINT_YES (SDHC_NISTR_CINT_YES_Val << SDHC_NISTR_CINT_Pos)
+#define SDHC_NISTR_ERRINT_Pos 15 /**< \brief (SDHC_NISTR) Error Interrupt */
+#define SDHC_NISTR_ERRINT (_U_(0x1) << SDHC_NISTR_ERRINT_Pos)
+#define SDHC_NISTR_ERRINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No Error */
+#define SDHC_NISTR_ERRINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Error */
+#define SDHC_NISTR_ERRINT_NO (SDHC_NISTR_ERRINT_NO_Val << SDHC_NISTR_ERRINT_Pos)
+#define SDHC_NISTR_ERRINT_YES (SDHC_NISTR_ERRINT_YES_Val << SDHC_NISTR_ERRINT_Pos)
+#define SDHC_NISTR_MASK _U_(0x81FF) /**< \brief (SDHC_NISTR) MASK Register */
+
+// EMMC mode
+#define SDHC_NISTR_EMMC_CMDC_Pos 0 /**< \brief (SDHC_NISTR_EMMC) Command Complete */
+#define SDHC_NISTR_EMMC_CMDC (_U_(0x1) << SDHC_NISTR_EMMC_CMDC_Pos)
+#define SDHC_NISTR_EMMC_CMDC_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) No command complete */
+#define SDHC_NISTR_EMMC_CMDC_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Command complete */
+#define SDHC_NISTR_EMMC_CMDC_NO (SDHC_NISTR_EMMC_CMDC_NO_Val << SDHC_NISTR_EMMC_CMDC_Pos)
+#define SDHC_NISTR_EMMC_CMDC_YES (SDHC_NISTR_EMMC_CMDC_YES_Val << SDHC_NISTR_EMMC_CMDC_Pos)
+#define SDHC_NISTR_EMMC_TRFC_Pos 1 /**< \brief (SDHC_NISTR_EMMC) Transfer Complete */
+#define SDHC_NISTR_EMMC_TRFC (_U_(0x1) << SDHC_NISTR_EMMC_TRFC_Pos)
+#define SDHC_NISTR_EMMC_TRFC_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) Not complete */
+#define SDHC_NISTR_EMMC_TRFC_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Command execution is completed */
+#define SDHC_NISTR_EMMC_TRFC_NO (SDHC_NISTR_EMMC_TRFC_NO_Val << SDHC_NISTR_EMMC_TRFC_Pos)
+#define SDHC_NISTR_EMMC_TRFC_YES (SDHC_NISTR_EMMC_TRFC_YES_Val << SDHC_NISTR_EMMC_TRFC_Pos)
+#define SDHC_NISTR_EMMC_BLKGE_Pos 2 /**< \brief (SDHC_NISTR_EMMC) Block Gap Event */
+#define SDHC_NISTR_EMMC_BLKGE (_U_(0x1) << SDHC_NISTR_EMMC_BLKGE_Pos)
+#define SDHC_NISTR_EMMC_BLKGE_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) No Block Gap Event */
+#define SDHC_NISTR_EMMC_BLKGE_STOP_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Transaction stopped at block gap */
+#define SDHC_NISTR_EMMC_BLKGE_NO (SDHC_NISTR_EMMC_BLKGE_NO_Val << SDHC_NISTR_EMMC_BLKGE_Pos)
+#define SDHC_NISTR_EMMC_BLKGE_STOP (SDHC_NISTR_EMMC_BLKGE_STOP_Val << SDHC_NISTR_EMMC_BLKGE_Pos)
+#define SDHC_NISTR_EMMC_DMAINT_Pos 3 /**< \brief (SDHC_NISTR_EMMC) DMA Interrupt */
+#define SDHC_NISTR_EMMC_DMAINT (_U_(0x1) << SDHC_NISTR_EMMC_DMAINT_Pos)
+#define SDHC_NISTR_EMMC_DMAINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) No DMA Interrupt */
+#define SDHC_NISTR_EMMC_DMAINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) DMA Interrupt is generated */
+#define SDHC_NISTR_EMMC_DMAINT_NO (SDHC_NISTR_EMMC_DMAINT_NO_Val << SDHC_NISTR_EMMC_DMAINT_Pos)
+#define SDHC_NISTR_EMMC_DMAINT_YES (SDHC_NISTR_EMMC_DMAINT_YES_Val << SDHC_NISTR_EMMC_DMAINT_Pos)
+#define SDHC_NISTR_EMMC_BWRRDY_Pos 4 /**< \brief (SDHC_NISTR_EMMC) Buffer Write Ready */
+#define SDHC_NISTR_EMMC_BWRRDY (_U_(0x1) << SDHC_NISTR_EMMC_BWRRDY_Pos)
+#define SDHC_NISTR_EMMC_BWRRDY_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) Not ready to write buffer */
+#define SDHC_NISTR_EMMC_BWRRDY_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Ready to write buffer */
+#define SDHC_NISTR_EMMC_BWRRDY_NO (SDHC_NISTR_EMMC_BWRRDY_NO_Val << SDHC_NISTR_EMMC_BWRRDY_Pos)
+#define SDHC_NISTR_EMMC_BWRRDY_YES (SDHC_NISTR_EMMC_BWRRDY_YES_Val << SDHC_NISTR_EMMC_BWRRDY_Pos)
+#define SDHC_NISTR_EMMC_BRDRDY_Pos 5 /**< \brief (SDHC_NISTR_EMMC) Buffer Read Ready */
+#define SDHC_NISTR_EMMC_BRDRDY (_U_(0x1) << SDHC_NISTR_EMMC_BRDRDY_Pos)
+#define SDHC_NISTR_EMMC_BRDRDY_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) Not ready to read buffer */
+#define SDHC_NISTR_EMMC_BRDRDY_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Ready to read buffer */
+#define SDHC_NISTR_EMMC_BRDRDY_NO (SDHC_NISTR_EMMC_BRDRDY_NO_Val << SDHC_NISTR_EMMC_BRDRDY_Pos)
+#define SDHC_NISTR_EMMC_BRDRDY_YES (SDHC_NISTR_EMMC_BRDRDY_YES_Val << SDHC_NISTR_EMMC_BRDRDY_Pos)
+#define SDHC_NISTR_EMMC_BOOTAR_Pos 14 /**< \brief (SDHC_NISTR_EMMC) Boot Acknowledge Received */
+#define SDHC_NISTR_EMMC_BOOTAR (_U_(0x1) << SDHC_NISTR_EMMC_BOOTAR_Pos)
+#define SDHC_NISTR_EMMC_ERRINT_Pos 15 /**< \brief (SDHC_NISTR_EMMC) Error Interrupt */
+#define SDHC_NISTR_EMMC_ERRINT (_U_(0x1) << SDHC_NISTR_EMMC_ERRINT_Pos)
+#define SDHC_NISTR_EMMC_ERRINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) No Error */
+#define SDHC_NISTR_EMMC_ERRINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Error */
+#define SDHC_NISTR_EMMC_ERRINT_NO (SDHC_NISTR_EMMC_ERRINT_NO_Val << SDHC_NISTR_EMMC_ERRINT_Pos)
+#define SDHC_NISTR_EMMC_ERRINT_YES (SDHC_NISTR_EMMC_ERRINT_YES_Val << SDHC_NISTR_EMMC_ERRINT_Pos)
+#define SDHC_NISTR_EMMC_MASK _U_(0xC03F) /**< \brief (SDHC_NISTR_EMMC) MASK Register */
+
+/* -------- SDHC_EISTR : (SDHC Offset: 0x032) (R/W 16) Error Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error */
+ uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error */
+ uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error */
+ uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error */
+ uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error */
+ uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error */
+ uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error */
+ uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error */
+ uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error */
+ uint16_t ADMA:1; /*!< bit: 9 ADMA Error */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct { // EMMC mode
+ uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error */
+ uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error */
+ uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error */
+ uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error */
+ uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error */
+ uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error */
+ uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error */
+ uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error */
+ uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error */
+ uint16_t ADMA:1; /*!< bit: 9 ADMA Error */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t BOOTAE:1; /*!< bit: 12 Boot Acknowledge Error */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } EMMC; /*!< Structure used for EMMC */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_EISTR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_EISTR_OFFSET 0x032 /**< \brief (SDHC_EISTR offset) Error Interrupt Status */
+#define SDHC_EISTR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_EISTR reset_value) Error Interrupt Status */
+
+#define SDHC_EISTR_CMDTEO_Pos 0 /**< \brief (SDHC_EISTR) Command Timeout Error */
+#define SDHC_EISTR_CMDTEO (_U_(0x1) << SDHC_EISTR_CMDTEO_Pos)
+#define SDHC_EISTR_CMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
+#define SDHC_EISTR_CMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Timeout */
+#define SDHC_EISTR_CMDTEO_NO (SDHC_EISTR_CMDTEO_NO_Val << SDHC_EISTR_CMDTEO_Pos)
+#define SDHC_EISTR_CMDTEO_YES (SDHC_EISTR_CMDTEO_YES_Val << SDHC_EISTR_CMDTEO_Pos)
+#define SDHC_EISTR_CMDCRC_Pos 1 /**< \brief (SDHC_EISTR) Command CRC Error */
+#define SDHC_EISTR_CMDCRC (_U_(0x1) << SDHC_EISTR_CMDCRC_Pos)
+#define SDHC_EISTR_CMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
+#define SDHC_EISTR_CMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) CRC Error Generated */
+#define SDHC_EISTR_CMDCRC_NO (SDHC_EISTR_CMDCRC_NO_Val << SDHC_EISTR_CMDCRC_Pos)
+#define SDHC_EISTR_CMDCRC_YES (SDHC_EISTR_CMDCRC_YES_Val << SDHC_EISTR_CMDCRC_Pos)
+#define SDHC_EISTR_CMDEND_Pos 2 /**< \brief (SDHC_EISTR) Command End Bit Error */
+#define SDHC_EISTR_CMDEND (_U_(0x1) << SDHC_EISTR_CMDEND_Pos)
+#define SDHC_EISTR_CMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No error */
+#define SDHC_EISTR_CMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) End Bit Error Generated */
+#define SDHC_EISTR_CMDEND_NO (SDHC_EISTR_CMDEND_NO_Val << SDHC_EISTR_CMDEND_Pos)
+#define SDHC_EISTR_CMDEND_YES (SDHC_EISTR_CMDEND_YES_Val << SDHC_EISTR_CMDEND_Pos)
+#define SDHC_EISTR_CMDIDX_Pos 3 /**< \brief (SDHC_EISTR) Command Index Error */
+#define SDHC_EISTR_CMDIDX (_U_(0x1) << SDHC_EISTR_CMDIDX_Pos)
+#define SDHC_EISTR_CMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
+#define SDHC_EISTR_CMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */
+#define SDHC_EISTR_CMDIDX_NO (SDHC_EISTR_CMDIDX_NO_Val << SDHC_EISTR_CMDIDX_Pos)
+#define SDHC_EISTR_CMDIDX_YES (SDHC_EISTR_CMDIDX_YES_Val << SDHC_EISTR_CMDIDX_Pos)
+#define SDHC_EISTR_DATTEO_Pos 4 /**< \brief (SDHC_EISTR) Data Timeout Error */
+#define SDHC_EISTR_DATTEO (_U_(0x1) << SDHC_EISTR_DATTEO_Pos)
+#define SDHC_EISTR_DATTEO_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
+#define SDHC_EISTR_DATTEO_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Timeout */
+#define SDHC_EISTR_DATTEO_NO (SDHC_EISTR_DATTEO_NO_Val << SDHC_EISTR_DATTEO_Pos)
+#define SDHC_EISTR_DATTEO_YES (SDHC_EISTR_DATTEO_YES_Val << SDHC_EISTR_DATTEO_Pos)
+#define SDHC_EISTR_DATCRC_Pos 5 /**< \brief (SDHC_EISTR) Data CRC Error */
+#define SDHC_EISTR_DATCRC (_U_(0x1) << SDHC_EISTR_DATCRC_Pos)
+#define SDHC_EISTR_DATCRC_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
+#define SDHC_EISTR_DATCRC_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */
+#define SDHC_EISTR_DATCRC_NO (SDHC_EISTR_DATCRC_NO_Val << SDHC_EISTR_DATCRC_Pos)
+#define SDHC_EISTR_DATCRC_YES (SDHC_EISTR_DATCRC_YES_Val << SDHC_EISTR_DATCRC_Pos)
+#define SDHC_EISTR_DATEND_Pos 6 /**< \brief (SDHC_EISTR) Data End Bit Error */
+#define SDHC_EISTR_DATEND (_U_(0x1) << SDHC_EISTR_DATEND_Pos)
+#define SDHC_EISTR_DATEND_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
+#define SDHC_EISTR_DATEND_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */
+#define SDHC_EISTR_DATEND_NO (SDHC_EISTR_DATEND_NO_Val << SDHC_EISTR_DATEND_Pos)
+#define SDHC_EISTR_DATEND_YES (SDHC_EISTR_DATEND_YES_Val << SDHC_EISTR_DATEND_Pos)
+#define SDHC_EISTR_CURLIM_Pos 7 /**< \brief (SDHC_EISTR) Current Limit Error */
+#define SDHC_EISTR_CURLIM (_U_(0x1) << SDHC_EISTR_CURLIM_Pos)
+#define SDHC_EISTR_CURLIM_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
+#define SDHC_EISTR_CURLIM_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Power Fail */
+#define SDHC_EISTR_CURLIM_NO (SDHC_EISTR_CURLIM_NO_Val << SDHC_EISTR_CURLIM_Pos)
+#define SDHC_EISTR_CURLIM_YES (SDHC_EISTR_CURLIM_YES_Val << SDHC_EISTR_CURLIM_Pos)
+#define SDHC_EISTR_ACMD_Pos 8 /**< \brief (SDHC_EISTR) Auto CMD Error */
+#define SDHC_EISTR_ACMD (_U_(0x1) << SDHC_EISTR_ACMD_Pos)
+#define SDHC_EISTR_ACMD_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
+#define SDHC_EISTR_ACMD_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */
+#define SDHC_EISTR_ACMD_NO (SDHC_EISTR_ACMD_NO_Val << SDHC_EISTR_ACMD_Pos)
+#define SDHC_EISTR_ACMD_YES (SDHC_EISTR_ACMD_YES_Val << SDHC_EISTR_ACMD_Pos)
+#define SDHC_EISTR_ADMA_Pos 9 /**< \brief (SDHC_EISTR) ADMA Error */
+#define SDHC_EISTR_ADMA (_U_(0x1) << SDHC_EISTR_ADMA_Pos)
+#define SDHC_EISTR_ADMA_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
+#define SDHC_EISTR_ADMA_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */
+#define SDHC_EISTR_ADMA_NO (SDHC_EISTR_ADMA_NO_Val << SDHC_EISTR_ADMA_Pos)
+#define SDHC_EISTR_ADMA_YES (SDHC_EISTR_ADMA_YES_Val << SDHC_EISTR_ADMA_Pos)
+#define SDHC_EISTR_MASK _U_(0x03FF) /**< \brief (SDHC_EISTR) MASK Register */
+
+// EMMC mode
+#define SDHC_EISTR_EMMC_CMDTEO_Pos 0 /**< \brief (SDHC_EISTR_EMMC) Command Timeout Error */
+#define SDHC_EISTR_EMMC_CMDTEO (_U_(0x1) << SDHC_EISTR_EMMC_CMDTEO_Pos)
+#define SDHC_EISTR_EMMC_CMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define SDHC_EISTR_EMMC_CMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Timeout */
+#define SDHC_EISTR_EMMC_CMDTEO_NO (SDHC_EISTR_EMMC_CMDTEO_NO_Val << SDHC_EISTR_EMMC_CMDTEO_Pos)
+#define SDHC_EISTR_EMMC_CMDTEO_YES (SDHC_EISTR_EMMC_CMDTEO_YES_Val << SDHC_EISTR_EMMC_CMDTEO_Pos)
+#define SDHC_EISTR_EMMC_CMDCRC_Pos 1 /**< \brief (SDHC_EISTR_EMMC) Command CRC Error */
+#define SDHC_EISTR_EMMC_CMDCRC (_U_(0x1) << SDHC_EISTR_EMMC_CMDCRC_Pos)
+#define SDHC_EISTR_EMMC_CMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define SDHC_EISTR_EMMC_CMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) CRC Error Generated */
+#define SDHC_EISTR_EMMC_CMDCRC_NO (SDHC_EISTR_EMMC_CMDCRC_NO_Val << SDHC_EISTR_EMMC_CMDCRC_Pos)
+#define SDHC_EISTR_EMMC_CMDCRC_YES (SDHC_EISTR_EMMC_CMDCRC_YES_Val << SDHC_EISTR_EMMC_CMDCRC_Pos)
+#define SDHC_EISTR_EMMC_CMDEND_Pos 2 /**< \brief (SDHC_EISTR_EMMC) Command End Bit Error */
+#define SDHC_EISTR_EMMC_CMDEND (_U_(0x1) << SDHC_EISTR_EMMC_CMDEND_Pos)
+#define SDHC_EISTR_EMMC_CMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No error */
+#define SDHC_EISTR_EMMC_CMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) End Bit Error Generated */
+#define SDHC_EISTR_EMMC_CMDEND_NO (SDHC_EISTR_EMMC_CMDEND_NO_Val << SDHC_EISTR_EMMC_CMDEND_Pos)
+#define SDHC_EISTR_EMMC_CMDEND_YES (SDHC_EISTR_EMMC_CMDEND_YES_Val << SDHC_EISTR_EMMC_CMDEND_Pos)
+#define SDHC_EISTR_EMMC_CMDIDX_Pos 3 /**< \brief (SDHC_EISTR_EMMC) Command Index Error */
+#define SDHC_EISTR_EMMC_CMDIDX (_U_(0x1) << SDHC_EISTR_EMMC_CMDIDX_Pos)
+#define SDHC_EISTR_EMMC_CMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define SDHC_EISTR_EMMC_CMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */
+#define SDHC_EISTR_EMMC_CMDIDX_NO (SDHC_EISTR_EMMC_CMDIDX_NO_Val << SDHC_EISTR_EMMC_CMDIDX_Pos)
+#define SDHC_EISTR_EMMC_CMDIDX_YES (SDHC_EISTR_EMMC_CMDIDX_YES_Val << SDHC_EISTR_EMMC_CMDIDX_Pos)
+#define SDHC_EISTR_EMMC_DATTEO_Pos 4 /**< \brief (SDHC_EISTR_EMMC) Data Timeout Error */
+#define SDHC_EISTR_EMMC_DATTEO (_U_(0x1) << SDHC_EISTR_EMMC_DATTEO_Pos)
+#define SDHC_EISTR_EMMC_DATTEO_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define SDHC_EISTR_EMMC_DATTEO_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Timeout */
+#define SDHC_EISTR_EMMC_DATTEO_NO (SDHC_EISTR_EMMC_DATTEO_NO_Val << SDHC_EISTR_EMMC_DATTEO_Pos)
+#define SDHC_EISTR_EMMC_DATTEO_YES (SDHC_EISTR_EMMC_DATTEO_YES_Val << SDHC_EISTR_EMMC_DATTEO_Pos)
+#define SDHC_EISTR_EMMC_DATCRC_Pos 5 /**< \brief (SDHC_EISTR_EMMC) Data CRC Error */
+#define SDHC_EISTR_EMMC_DATCRC (_U_(0x1) << SDHC_EISTR_EMMC_DATCRC_Pos)
+#define SDHC_EISTR_EMMC_DATCRC_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define SDHC_EISTR_EMMC_DATCRC_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */
+#define SDHC_EISTR_EMMC_DATCRC_NO (SDHC_EISTR_EMMC_DATCRC_NO_Val << SDHC_EISTR_EMMC_DATCRC_Pos)
+#define SDHC_EISTR_EMMC_DATCRC_YES (SDHC_EISTR_EMMC_DATCRC_YES_Val << SDHC_EISTR_EMMC_DATCRC_Pos)
+#define SDHC_EISTR_EMMC_DATEND_Pos 6 /**< \brief (SDHC_EISTR_EMMC) Data End Bit Error */
+#define SDHC_EISTR_EMMC_DATEND (_U_(0x1) << SDHC_EISTR_EMMC_DATEND_Pos)
+#define SDHC_EISTR_EMMC_DATEND_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define SDHC_EISTR_EMMC_DATEND_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */
+#define SDHC_EISTR_EMMC_DATEND_NO (SDHC_EISTR_EMMC_DATEND_NO_Val << SDHC_EISTR_EMMC_DATEND_Pos)
+#define SDHC_EISTR_EMMC_DATEND_YES (SDHC_EISTR_EMMC_DATEND_YES_Val << SDHC_EISTR_EMMC_DATEND_Pos)
+#define SDHC_EISTR_EMMC_CURLIM_Pos 7 /**< \brief (SDHC_EISTR_EMMC) Current Limit Error */
+#define SDHC_EISTR_EMMC_CURLIM (_U_(0x1) << SDHC_EISTR_EMMC_CURLIM_Pos)
+#define SDHC_EISTR_EMMC_CURLIM_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define SDHC_EISTR_EMMC_CURLIM_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Power Fail */
+#define SDHC_EISTR_EMMC_CURLIM_NO (SDHC_EISTR_EMMC_CURLIM_NO_Val << SDHC_EISTR_EMMC_CURLIM_Pos)
+#define SDHC_EISTR_EMMC_CURLIM_YES (SDHC_EISTR_EMMC_CURLIM_YES_Val << SDHC_EISTR_EMMC_CURLIM_Pos)
+#define SDHC_EISTR_EMMC_ACMD_Pos 8 /**< \brief (SDHC_EISTR_EMMC) Auto CMD Error */
+#define SDHC_EISTR_EMMC_ACMD (_U_(0x1) << SDHC_EISTR_EMMC_ACMD_Pos)
+#define SDHC_EISTR_EMMC_ACMD_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define SDHC_EISTR_EMMC_ACMD_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */
+#define SDHC_EISTR_EMMC_ACMD_NO (SDHC_EISTR_EMMC_ACMD_NO_Val << SDHC_EISTR_EMMC_ACMD_Pos)
+#define SDHC_EISTR_EMMC_ACMD_YES (SDHC_EISTR_EMMC_ACMD_YES_Val << SDHC_EISTR_EMMC_ACMD_Pos)
+#define SDHC_EISTR_EMMC_ADMA_Pos 9 /**< \brief (SDHC_EISTR_EMMC) ADMA Error */
+#define SDHC_EISTR_EMMC_ADMA (_U_(0x1) << SDHC_EISTR_EMMC_ADMA_Pos)
+#define SDHC_EISTR_EMMC_ADMA_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define SDHC_EISTR_EMMC_ADMA_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */
+#define SDHC_EISTR_EMMC_ADMA_NO (SDHC_EISTR_EMMC_ADMA_NO_Val << SDHC_EISTR_EMMC_ADMA_Pos)
+#define SDHC_EISTR_EMMC_ADMA_YES (SDHC_EISTR_EMMC_ADMA_YES_Val << SDHC_EISTR_EMMC_ADMA_Pos)
+#define SDHC_EISTR_EMMC_BOOTAE_Pos 12 /**< \brief (SDHC_EISTR_EMMC) Boot Acknowledge Error */
+#define SDHC_EISTR_EMMC_BOOTAE (_U_(0x1) << SDHC_EISTR_EMMC_BOOTAE_Pos)
+#define SDHC_EISTR_EMMC_BOOTAE_0_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) FIFO contains at least one byte */
+#define SDHC_EISTR_EMMC_BOOTAE_1_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) FIFO is empty */
+#define SDHC_EISTR_EMMC_BOOTAE_0 (SDHC_EISTR_EMMC_BOOTAE_0_Val << SDHC_EISTR_EMMC_BOOTAE_Pos)
+#define SDHC_EISTR_EMMC_BOOTAE_1 (SDHC_EISTR_EMMC_BOOTAE_1_Val << SDHC_EISTR_EMMC_BOOTAE_Pos)
+#define SDHC_EISTR_EMMC_MASK _U_(0x13FF) /**< \brief (SDHC_EISTR_EMMC) MASK Register */
+
+/* -------- SDHC_NISTER : (SDHC Offset: 0x034) (R/W 16) Normal Interrupt Status Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CMDC:1; /*!< bit: 0 Command Complete Status Enable */
+ uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Status Enable */
+ uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Status Enable */
+ uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Status Enable */
+ uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Status Enable */
+ uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Status Enable */
+ uint16_t CINS:1; /*!< bit: 6 Card Insertion Status Enable */
+ uint16_t CREM:1; /*!< bit: 7 Card Removal Status Enable */
+ uint16_t CINT:1; /*!< bit: 8 Card Interrupt Status Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct { // EMMC mode
+ uint16_t CMDC:1; /*!< bit: 0 Command Complete Status Enable */
+ uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Status Enable */
+ uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Status Enable */
+ uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Status Enable */
+ uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Status Enable */
+ uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Status Enable */
+ uint16_t :8; /*!< bit: 6..13 Reserved */
+ uint16_t BOOTAR:1; /*!< bit: 14 Boot Acknowledge Received Status Enable */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } EMMC; /*!< Structure used for EMMC */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_NISTER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_NISTER_OFFSET 0x034 /**< \brief (SDHC_NISTER offset) Normal Interrupt Status Enable */
+#define SDHC_NISTER_RESETVALUE _U_(0x0000) /**< \brief (SDHC_NISTER reset_value) Normal Interrupt Status Enable */
+
+#define SDHC_NISTER_CMDC_Pos 0 /**< \brief (SDHC_NISTER) Command Complete Status Enable */
+#define SDHC_NISTER_CMDC (_U_(0x1) << SDHC_NISTER_CMDC_Pos)
+#define SDHC_NISTER_CMDC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
+#define SDHC_NISTER_CMDC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_CMDC_MASKED (SDHC_NISTER_CMDC_MASKED_Val << SDHC_NISTER_CMDC_Pos)
+#define SDHC_NISTER_CMDC_ENABLED (SDHC_NISTER_CMDC_ENABLED_Val << SDHC_NISTER_CMDC_Pos)
+#define SDHC_NISTER_TRFC_Pos 1 /**< \brief (SDHC_NISTER) Transfer Complete Status Enable */
+#define SDHC_NISTER_TRFC (_U_(0x1) << SDHC_NISTER_TRFC_Pos)
+#define SDHC_NISTER_TRFC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
+#define SDHC_NISTER_TRFC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_TRFC_MASKED (SDHC_NISTER_TRFC_MASKED_Val << SDHC_NISTER_TRFC_Pos)
+#define SDHC_NISTER_TRFC_ENABLED (SDHC_NISTER_TRFC_ENABLED_Val << SDHC_NISTER_TRFC_Pos)
+#define SDHC_NISTER_BLKGE_Pos 2 /**< \brief (SDHC_NISTER) Block Gap Event Status Enable */
+#define SDHC_NISTER_BLKGE (_U_(0x1) << SDHC_NISTER_BLKGE_Pos)
+#define SDHC_NISTER_BLKGE_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
+#define SDHC_NISTER_BLKGE_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_BLKGE_MASKED (SDHC_NISTER_BLKGE_MASKED_Val << SDHC_NISTER_BLKGE_Pos)
+#define SDHC_NISTER_BLKGE_ENABLED (SDHC_NISTER_BLKGE_ENABLED_Val << SDHC_NISTER_BLKGE_Pos)
+#define SDHC_NISTER_DMAINT_Pos 3 /**< \brief (SDHC_NISTER) DMA Interrupt Status Enable */
+#define SDHC_NISTER_DMAINT (_U_(0x1) << SDHC_NISTER_DMAINT_Pos)
+#define SDHC_NISTER_DMAINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
+#define SDHC_NISTER_DMAINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_DMAINT_MASKED (SDHC_NISTER_DMAINT_MASKED_Val << SDHC_NISTER_DMAINT_Pos)
+#define SDHC_NISTER_DMAINT_ENABLED (SDHC_NISTER_DMAINT_ENABLED_Val << SDHC_NISTER_DMAINT_Pos)
+#define SDHC_NISTER_BWRRDY_Pos 4 /**< \brief (SDHC_NISTER) Buffer Write Ready Status Enable */
+#define SDHC_NISTER_BWRRDY (_U_(0x1) << SDHC_NISTER_BWRRDY_Pos)
+#define SDHC_NISTER_BWRRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
+#define SDHC_NISTER_BWRRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_BWRRDY_MASKED (SDHC_NISTER_BWRRDY_MASKED_Val << SDHC_NISTER_BWRRDY_Pos)
+#define SDHC_NISTER_BWRRDY_ENABLED (SDHC_NISTER_BWRRDY_ENABLED_Val << SDHC_NISTER_BWRRDY_Pos)
+#define SDHC_NISTER_BRDRDY_Pos 5 /**< \brief (SDHC_NISTER) Buffer Read Ready Status Enable */
+#define SDHC_NISTER_BRDRDY (_U_(0x1) << SDHC_NISTER_BRDRDY_Pos)
+#define SDHC_NISTER_BRDRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
+#define SDHC_NISTER_BRDRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_BRDRDY_MASKED (SDHC_NISTER_BRDRDY_MASKED_Val << SDHC_NISTER_BRDRDY_Pos)
+#define SDHC_NISTER_BRDRDY_ENABLED (SDHC_NISTER_BRDRDY_ENABLED_Val << SDHC_NISTER_BRDRDY_Pos)
+#define SDHC_NISTER_CINS_Pos 6 /**< \brief (SDHC_NISTER) Card Insertion Status Enable */
+#define SDHC_NISTER_CINS (_U_(0x1) << SDHC_NISTER_CINS_Pos)
+#define SDHC_NISTER_CINS_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
+#define SDHC_NISTER_CINS_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_CINS_MASKED (SDHC_NISTER_CINS_MASKED_Val << SDHC_NISTER_CINS_Pos)
+#define SDHC_NISTER_CINS_ENABLED (SDHC_NISTER_CINS_ENABLED_Val << SDHC_NISTER_CINS_Pos)
+#define SDHC_NISTER_CREM_Pos 7 /**< \brief (SDHC_NISTER) Card Removal Status Enable */
+#define SDHC_NISTER_CREM (_U_(0x1) << SDHC_NISTER_CREM_Pos)
+#define SDHC_NISTER_CREM_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
+#define SDHC_NISTER_CREM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_CREM_MASKED (SDHC_NISTER_CREM_MASKED_Val << SDHC_NISTER_CREM_Pos)
+#define SDHC_NISTER_CREM_ENABLED (SDHC_NISTER_CREM_ENABLED_Val << SDHC_NISTER_CREM_Pos)
+#define SDHC_NISTER_CINT_Pos 8 /**< \brief (SDHC_NISTER) Card Interrupt Status Enable */
+#define SDHC_NISTER_CINT (_U_(0x1) << SDHC_NISTER_CINT_Pos)
+#define SDHC_NISTER_CINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
+#define SDHC_NISTER_CINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_CINT_MASKED (SDHC_NISTER_CINT_MASKED_Val << SDHC_NISTER_CINT_Pos)
+#define SDHC_NISTER_CINT_ENABLED (SDHC_NISTER_CINT_ENABLED_Val << SDHC_NISTER_CINT_Pos)
+#define SDHC_NISTER_MASK _U_(0x01FF) /**< \brief (SDHC_NISTER) MASK Register */
+
+// EMMC mode
+#define SDHC_NISTER_EMMC_CMDC_Pos 0 /**< \brief (SDHC_NISTER_EMMC) Command Complete Status Enable */
+#define SDHC_NISTER_EMMC_CMDC (_U_(0x1) << SDHC_NISTER_EMMC_CMDC_Pos)
+#define SDHC_NISTER_EMMC_CMDC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */
+#define SDHC_NISTER_EMMC_CMDC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */
+#define SDHC_NISTER_EMMC_CMDC_MASKED (SDHC_NISTER_EMMC_CMDC_MASKED_Val << SDHC_NISTER_EMMC_CMDC_Pos)
+#define SDHC_NISTER_EMMC_CMDC_ENABLED (SDHC_NISTER_EMMC_CMDC_ENABLED_Val << SDHC_NISTER_EMMC_CMDC_Pos)
+#define SDHC_NISTER_EMMC_TRFC_Pos 1 /**< \brief (SDHC_NISTER_EMMC) Transfer Complete Status Enable */
+#define SDHC_NISTER_EMMC_TRFC (_U_(0x1) << SDHC_NISTER_EMMC_TRFC_Pos)
+#define SDHC_NISTER_EMMC_TRFC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */
+#define SDHC_NISTER_EMMC_TRFC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */
+#define SDHC_NISTER_EMMC_TRFC_MASKED (SDHC_NISTER_EMMC_TRFC_MASKED_Val << SDHC_NISTER_EMMC_TRFC_Pos)
+#define SDHC_NISTER_EMMC_TRFC_ENABLED (SDHC_NISTER_EMMC_TRFC_ENABLED_Val << SDHC_NISTER_EMMC_TRFC_Pos)
+#define SDHC_NISTER_EMMC_BLKGE_Pos 2 /**< \brief (SDHC_NISTER_EMMC) Block Gap Event Status Enable */
+#define SDHC_NISTER_EMMC_BLKGE (_U_(0x1) << SDHC_NISTER_EMMC_BLKGE_Pos)
+#define SDHC_NISTER_EMMC_BLKGE_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */
+#define SDHC_NISTER_EMMC_BLKGE_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */
+#define SDHC_NISTER_EMMC_BLKGE_MASKED (SDHC_NISTER_EMMC_BLKGE_MASKED_Val << SDHC_NISTER_EMMC_BLKGE_Pos)
+#define SDHC_NISTER_EMMC_BLKGE_ENABLED (SDHC_NISTER_EMMC_BLKGE_ENABLED_Val << SDHC_NISTER_EMMC_BLKGE_Pos)
+#define SDHC_NISTER_EMMC_DMAINT_Pos 3 /**< \brief (SDHC_NISTER_EMMC) DMA Interrupt Status Enable */
+#define SDHC_NISTER_EMMC_DMAINT (_U_(0x1) << SDHC_NISTER_EMMC_DMAINT_Pos)
+#define SDHC_NISTER_EMMC_DMAINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */
+#define SDHC_NISTER_EMMC_DMAINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */
+#define SDHC_NISTER_EMMC_DMAINT_MASKED (SDHC_NISTER_EMMC_DMAINT_MASKED_Val << SDHC_NISTER_EMMC_DMAINT_Pos)
+#define SDHC_NISTER_EMMC_DMAINT_ENABLED (SDHC_NISTER_EMMC_DMAINT_ENABLED_Val << SDHC_NISTER_EMMC_DMAINT_Pos)
+#define SDHC_NISTER_EMMC_BWRRDY_Pos 4 /**< \brief (SDHC_NISTER_EMMC) Buffer Write Ready Status Enable */
+#define SDHC_NISTER_EMMC_BWRRDY (_U_(0x1) << SDHC_NISTER_EMMC_BWRRDY_Pos)
+#define SDHC_NISTER_EMMC_BWRRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */
+#define SDHC_NISTER_EMMC_BWRRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */
+#define SDHC_NISTER_EMMC_BWRRDY_MASKED (SDHC_NISTER_EMMC_BWRRDY_MASKED_Val << SDHC_NISTER_EMMC_BWRRDY_Pos)
+#define SDHC_NISTER_EMMC_BWRRDY_ENABLED (SDHC_NISTER_EMMC_BWRRDY_ENABLED_Val << SDHC_NISTER_EMMC_BWRRDY_Pos)
+#define SDHC_NISTER_EMMC_BRDRDY_Pos 5 /**< \brief (SDHC_NISTER_EMMC) Buffer Read Ready Status Enable */
+#define SDHC_NISTER_EMMC_BRDRDY (_U_(0x1) << SDHC_NISTER_EMMC_BRDRDY_Pos)
+#define SDHC_NISTER_EMMC_BRDRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */
+#define SDHC_NISTER_EMMC_BRDRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */
+#define SDHC_NISTER_EMMC_BRDRDY_MASKED (SDHC_NISTER_EMMC_BRDRDY_MASKED_Val << SDHC_NISTER_EMMC_BRDRDY_Pos)
+#define SDHC_NISTER_EMMC_BRDRDY_ENABLED (SDHC_NISTER_EMMC_BRDRDY_ENABLED_Val << SDHC_NISTER_EMMC_BRDRDY_Pos)
+#define SDHC_NISTER_EMMC_BOOTAR_Pos 14 /**< \brief (SDHC_NISTER_EMMC) Boot Acknowledge Received Status Enable */
+#define SDHC_NISTER_EMMC_BOOTAR (_U_(0x1) << SDHC_NISTER_EMMC_BOOTAR_Pos)
+#define SDHC_NISTER_EMMC_MASK _U_(0x403F) /**< \brief (SDHC_NISTER_EMMC) MASK Register */
+
+/* -------- SDHC_EISTER : (SDHC Offset: 0x036) (R/W 16) Error Interrupt Status Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Status Enable */
+ uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Status Enable */
+ uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Status Enable */
+ uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Status Enable */
+ uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Status Enable */
+ uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Status Enable */
+ uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Status Enable */
+ uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Status Enable */
+ uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Status Enable */
+ uint16_t ADMA:1; /*!< bit: 9 ADMA Error Status Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct { // EMMC mode
+ uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Status Enable */
+ uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Status Enable */
+ uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Status Enable */
+ uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Status Enable */
+ uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Status Enable */
+ uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Status Enable */
+ uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Status Enable */
+ uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Status Enable */
+ uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Status Enable */
+ uint16_t ADMA:1; /*!< bit: 9 ADMA Error Status Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t BOOTAE:1; /*!< bit: 12 Boot Acknowledge Error Status Enable */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } EMMC; /*!< Structure used for EMMC */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_EISTER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_EISTER_OFFSET 0x036 /**< \brief (SDHC_EISTER offset) Error Interrupt Status Enable */
+#define SDHC_EISTER_RESETVALUE _U_(0x0000) /**< \brief (SDHC_EISTER reset_value) Error Interrupt Status Enable */
+
+#define SDHC_EISTER_CMDTEO_Pos 0 /**< \brief (SDHC_EISTER) Command Timeout Error Status Enable */
+#define SDHC_EISTER_CMDTEO (_U_(0x1) << SDHC_EISTER_CMDTEO_Pos)
+#define SDHC_EISTER_CMDTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_CMDTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_CMDTEO_MASKED (SDHC_EISTER_CMDTEO_MASKED_Val << SDHC_EISTER_CMDTEO_Pos)
+#define SDHC_EISTER_CMDTEO_ENABLED (SDHC_EISTER_CMDTEO_ENABLED_Val << SDHC_EISTER_CMDTEO_Pos)
+#define SDHC_EISTER_CMDCRC_Pos 1 /**< \brief (SDHC_EISTER) Command CRC Error Status Enable */
+#define SDHC_EISTER_CMDCRC (_U_(0x1) << SDHC_EISTER_CMDCRC_Pos)
+#define SDHC_EISTER_CMDCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_CMDCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_CMDCRC_MASKED (SDHC_EISTER_CMDCRC_MASKED_Val << SDHC_EISTER_CMDCRC_Pos)
+#define SDHC_EISTER_CMDCRC_ENABLED (SDHC_EISTER_CMDCRC_ENABLED_Val << SDHC_EISTER_CMDCRC_Pos)
+#define SDHC_EISTER_CMDEND_Pos 2 /**< \brief (SDHC_EISTER) Command End Bit Error Status Enable */
+#define SDHC_EISTER_CMDEND (_U_(0x1) << SDHC_EISTER_CMDEND_Pos)
+#define SDHC_EISTER_CMDEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_CMDEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_CMDEND_MASKED (SDHC_EISTER_CMDEND_MASKED_Val << SDHC_EISTER_CMDEND_Pos)
+#define SDHC_EISTER_CMDEND_ENABLED (SDHC_EISTER_CMDEND_ENABLED_Val << SDHC_EISTER_CMDEND_Pos)
+#define SDHC_EISTER_CMDIDX_Pos 3 /**< \brief (SDHC_EISTER) Command Index Error Status Enable */
+#define SDHC_EISTER_CMDIDX (_U_(0x1) << SDHC_EISTER_CMDIDX_Pos)
+#define SDHC_EISTER_CMDIDX_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_CMDIDX_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_CMDIDX_MASKED (SDHC_EISTER_CMDIDX_MASKED_Val << SDHC_EISTER_CMDIDX_Pos)
+#define SDHC_EISTER_CMDIDX_ENABLED (SDHC_EISTER_CMDIDX_ENABLED_Val << SDHC_EISTER_CMDIDX_Pos)
+#define SDHC_EISTER_DATTEO_Pos 4 /**< \brief (SDHC_EISTER) Data Timeout Error Status Enable */
+#define SDHC_EISTER_DATTEO (_U_(0x1) << SDHC_EISTER_DATTEO_Pos)
+#define SDHC_EISTER_DATTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_DATTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_DATTEO_MASKED (SDHC_EISTER_DATTEO_MASKED_Val << SDHC_EISTER_DATTEO_Pos)
+#define SDHC_EISTER_DATTEO_ENABLED (SDHC_EISTER_DATTEO_ENABLED_Val << SDHC_EISTER_DATTEO_Pos)
+#define SDHC_EISTER_DATCRC_Pos 5 /**< \brief (SDHC_EISTER) Data CRC Error Status Enable */
+#define SDHC_EISTER_DATCRC (_U_(0x1) << SDHC_EISTER_DATCRC_Pos)
+#define SDHC_EISTER_DATCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_DATCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_DATCRC_MASKED (SDHC_EISTER_DATCRC_MASKED_Val << SDHC_EISTER_DATCRC_Pos)
+#define SDHC_EISTER_DATCRC_ENABLED (SDHC_EISTER_DATCRC_ENABLED_Val << SDHC_EISTER_DATCRC_Pos)
+#define SDHC_EISTER_DATEND_Pos 6 /**< \brief (SDHC_EISTER) Data End Bit Error Status Enable */
+#define SDHC_EISTER_DATEND (_U_(0x1) << SDHC_EISTER_DATEND_Pos)
+#define SDHC_EISTER_DATEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_DATEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_DATEND_MASKED (SDHC_EISTER_DATEND_MASKED_Val << SDHC_EISTER_DATEND_Pos)
+#define SDHC_EISTER_DATEND_ENABLED (SDHC_EISTER_DATEND_ENABLED_Val << SDHC_EISTER_DATEND_Pos)
+#define SDHC_EISTER_CURLIM_Pos 7 /**< \brief (SDHC_EISTER) Current Limit Error Status Enable */
+#define SDHC_EISTER_CURLIM (_U_(0x1) << SDHC_EISTER_CURLIM_Pos)
+#define SDHC_EISTER_CURLIM_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_CURLIM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_CURLIM_MASKED (SDHC_EISTER_CURLIM_MASKED_Val << SDHC_EISTER_CURLIM_Pos)
+#define SDHC_EISTER_CURLIM_ENABLED (SDHC_EISTER_CURLIM_ENABLED_Val << SDHC_EISTER_CURLIM_Pos)
+#define SDHC_EISTER_ACMD_Pos 8 /**< \brief (SDHC_EISTER) Auto CMD Error Status Enable */
+#define SDHC_EISTER_ACMD (_U_(0x1) << SDHC_EISTER_ACMD_Pos)
+#define SDHC_EISTER_ACMD_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_ACMD_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_ACMD_MASKED (SDHC_EISTER_ACMD_MASKED_Val << SDHC_EISTER_ACMD_Pos)
+#define SDHC_EISTER_ACMD_ENABLED (SDHC_EISTER_ACMD_ENABLED_Val << SDHC_EISTER_ACMD_Pos)
+#define SDHC_EISTER_ADMA_Pos 9 /**< \brief (SDHC_EISTER) ADMA Error Status Enable */
+#define SDHC_EISTER_ADMA (_U_(0x1) << SDHC_EISTER_ADMA_Pos)
+#define SDHC_EISTER_ADMA_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_ADMA_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_ADMA_MASKED (SDHC_EISTER_ADMA_MASKED_Val << SDHC_EISTER_ADMA_Pos)
+#define SDHC_EISTER_ADMA_ENABLED (SDHC_EISTER_ADMA_ENABLED_Val << SDHC_EISTER_ADMA_Pos)
+#define SDHC_EISTER_MASK _U_(0x03FF) /**< \brief (SDHC_EISTER) MASK Register */
+
+// EMMC mode
+#define SDHC_EISTER_EMMC_CMDTEO_Pos 0 /**< \brief (SDHC_EISTER_EMMC) Command Timeout Error Status Enable */
+#define SDHC_EISTER_EMMC_CMDTEO (_U_(0x1) << SDHC_EISTER_EMMC_CMDTEO_Pos)
+#define SDHC_EISTER_EMMC_CMDTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_CMDTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_CMDTEO_MASKED (SDHC_EISTER_EMMC_CMDTEO_MASKED_Val << SDHC_EISTER_EMMC_CMDTEO_Pos)
+#define SDHC_EISTER_EMMC_CMDTEO_ENABLED (SDHC_EISTER_EMMC_CMDTEO_ENABLED_Val << SDHC_EISTER_EMMC_CMDTEO_Pos)
+#define SDHC_EISTER_EMMC_CMDCRC_Pos 1 /**< \brief (SDHC_EISTER_EMMC) Command CRC Error Status Enable */
+#define SDHC_EISTER_EMMC_CMDCRC (_U_(0x1) << SDHC_EISTER_EMMC_CMDCRC_Pos)
+#define SDHC_EISTER_EMMC_CMDCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_CMDCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_CMDCRC_MASKED (SDHC_EISTER_EMMC_CMDCRC_MASKED_Val << SDHC_EISTER_EMMC_CMDCRC_Pos)
+#define SDHC_EISTER_EMMC_CMDCRC_ENABLED (SDHC_EISTER_EMMC_CMDCRC_ENABLED_Val << SDHC_EISTER_EMMC_CMDCRC_Pos)
+#define SDHC_EISTER_EMMC_CMDEND_Pos 2 /**< \brief (SDHC_EISTER_EMMC) Command End Bit Error Status Enable */
+#define SDHC_EISTER_EMMC_CMDEND (_U_(0x1) << SDHC_EISTER_EMMC_CMDEND_Pos)
+#define SDHC_EISTER_EMMC_CMDEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_CMDEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_CMDEND_MASKED (SDHC_EISTER_EMMC_CMDEND_MASKED_Val << SDHC_EISTER_EMMC_CMDEND_Pos)
+#define SDHC_EISTER_EMMC_CMDEND_ENABLED (SDHC_EISTER_EMMC_CMDEND_ENABLED_Val << SDHC_EISTER_EMMC_CMDEND_Pos)
+#define SDHC_EISTER_EMMC_CMDIDX_Pos 3 /**< \brief (SDHC_EISTER_EMMC) Command Index Error Status Enable */
+#define SDHC_EISTER_EMMC_CMDIDX (_U_(0x1) << SDHC_EISTER_EMMC_CMDIDX_Pos)
+#define SDHC_EISTER_EMMC_CMDIDX_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_CMDIDX_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_CMDIDX_MASKED (SDHC_EISTER_EMMC_CMDIDX_MASKED_Val << SDHC_EISTER_EMMC_CMDIDX_Pos)
+#define SDHC_EISTER_EMMC_CMDIDX_ENABLED (SDHC_EISTER_EMMC_CMDIDX_ENABLED_Val << SDHC_EISTER_EMMC_CMDIDX_Pos)
+#define SDHC_EISTER_EMMC_DATTEO_Pos 4 /**< \brief (SDHC_EISTER_EMMC) Data Timeout Error Status Enable */
+#define SDHC_EISTER_EMMC_DATTEO (_U_(0x1) << SDHC_EISTER_EMMC_DATTEO_Pos)
+#define SDHC_EISTER_EMMC_DATTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_DATTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_DATTEO_MASKED (SDHC_EISTER_EMMC_DATTEO_MASKED_Val << SDHC_EISTER_EMMC_DATTEO_Pos)
+#define SDHC_EISTER_EMMC_DATTEO_ENABLED (SDHC_EISTER_EMMC_DATTEO_ENABLED_Val << SDHC_EISTER_EMMC_DATTEO_Pos)
+#define SDHC_EISTER_EMMC_DATCRC_Pos 5 /**< \brief (SDHC_EISTER_EMMC) Data CRC Error Status Enable */
+#define SDHC_EISTER_EMMC_DATCRC (_U_(0x1) << SDHC_EISTER_EMMC_DATCRC_Pos)
+#define SDHC_EISTER_EMMC_DATCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_DATCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_DATCRC_MASKED (SDHC_EISTER_EMMC_DATCRC_MASKED_Val << SDHC_EISTER_EMMC_DATCRC_Pos)
+#define SDHC_EISTER_EMMC_DATCRC_ENABLED (SDHC_EISTER_EMMC_DATCRC_ENABLED_Val << SDHC_EISTER_EMMC_DATCRC_Pos)
+#define SDHC_EISTER_EMMC_DATEND_Pos 6 /**< \brief (SDHC_EISTER_EMMC) Data End Bit Error Status Enable */
+#define SDHC_EISTER_EMMC_DATEND (_U_(0x1) << SDHC_EISTER_EMMC_DATEND_Pos)
+#define SDHC_EISTER_EMMC_DATEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_DATEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_DATEND_MASKED (SDHC_EISTER_EMMC_DATEND_MASKED_Val << SDHC_EISTER_EMMC_DATEND_Pos)
+#define SDHC_EISTER_EMMC_DATEND_ENABLED (SDHC_EISTER_EMMC_DATEND_ENABLED_Val << SDHC_EISTER_EMMC_DATEND_Pos)
+#define SDHC_EISTER_EMMC_CURLIM_Pos 7 /**< \brief (SDHC_EISTER_EMMC) Current Limit Error Status Enable */
+#define SDHC_EISTER_EMMC_CURLIM (_U_(0x1) << SDHC_EISTER_EMMC_CURLIM_Pos)
+#define SDHC_EISTER_EMMC_CURLIM_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_CURLIM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_CURLIM_MASKED (SDHC_EISTER_EMMC_CURLIM_MASKED_Val << SDHC_EISTER_EMMC_CURLIM_Pos)
+#define SDHC_EISTER_EMMC_CURLIM_ENABLED (SDHC_EISTER_EMMC_CURLIM_ENABLED_Val << SDHC_EISTER_EMMC_CURLIM_Pos)
+#define SDHC_EISTER_EMMC_ACMD_Pos 8 /**< \brief (SDHC_EISTER_EMMC) Auto CMD Error Status Enable */
+#define SDHC_EISTER_EMMC_ACMD (_U_(0x1) << SDHC_EISTER_EMMC_ACMD_Pos)
+#define SDHC_EISTER_EMMC_ACMD_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_ACMD_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_ACMD_MASKED (SDHC_EISTER_EMMC_ACMD_MASKED_Val << SDHC_EISTER_EMMC_ACMD_Pos)
+#define SDHC_EISTER_EMMC_ACMD_ENABLED (SDHC_EISTER_EMMC_ACMD_ENABLED_Val << SDHC_EISTER_EMMC_ACMD_Pos)
+#define SDHC_EISTER_EMMC_ADMA_Pos 9 /**< \brief (SDHC_EISTER_EMMC) ADMA Error Status Enable */
+#define SDHC_EISTER_EMMC_ADMA (_U_(0x1) << SDHC_EISTER_EMMC_ADMA_Pos)
+#define SDHC_EISTER_EMMC_ADMA_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_ADMA_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_ADMA_MASKED (SDHC_EISTER_EMMC_ADMA_MASKED_Val << SDHC_EISTER_EMMC_ADMA_Pos)
+#define SDHC_EISTER_EMMC_ADMA_ENABLED (SDHC_EISTER_EMMC_ADMA_ENABLED_Val << SDHC_EISTER_EMMC_ADMA_Pos)
+#define SDHC_EISTER_EMMC_BOOTAE_Pos 12 /**< \brief (SDHC_EISTER_EMMC) Boot Acknowledge Error Status Enable */
+#define SDHC_EISTER_EMMC_BOOTAE (_U_(0x1) << SDHC_EISTER_EMMC_BOOTAE_Pos)
+#define SDHC_EISTER_EMMC_MASK _U_(0x13FF) /**< \brief (SDHC_EISTER_EMMC) MASK Register */
+
+/* -------- SDHC_NISIER : (SDHC Offset: 0x038) (R/W 16) Normal Interrupt Signal Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CMDC:1; /*!< bit: 0 Command Complete Signal Enable */
+ uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Signal Enable */
+ uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Signal Enable */
+ uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Signal Enable */
+ uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Signal Enable */
+ uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Signal Enable */
+ uint16_t CINS:1; /*!< bit: 6 Card Insertion Signal Enable */
+ uint16_t CREM:1; /*!< bit: 7 Card Removal Signal Enable */
+ uint16_t CINT:1; /*!< bit: 8 Card Interrupt Signal Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct { // EMMC mode
+ uint16_t CMDC:1; /*!< bit: 0 Command Complete Signal Enable */
+ uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Signal Enable */
+ uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Signal Enable */
+ uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Signal Enable */
+ uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Signal Enable */
+ uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Signal Enable */
+ uint16_t :8; /*!< bit: 6..13 Reserved */
+ uint16_t BOOTAR:1; /*!< bit: 14 Boot Acknowledge Received Signal Enable */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } EMMC; /*!< Structure used for EMMC */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_NISIER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_NISIER_OFFSET 0x038 /**< \brief (SDHC_NISIER offset) Normal Interrupt Signal Enable */
+#define SDHC_NISIER_RESETVALUE _U_(0x0000) /**< \brief (SDHC_NISIER reset_value) Normal Interrupt Signal Enable */
+
+#define SDHC_NISIER_CMDC_Pos 0 /**< \brief (SDHC_NISIER) Command Complete Signal Enable */
+#define SDHC_NISIER_CMDC (_U_(0x1) << SDHC_NISIER_CMDC_Pos)
+#define SDHC_NISIER_CMDC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
+#define SDHC_NISIER_CMDC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_CMDC_MASKED (SDHC_NISIER_CMDC_MASKED_Val << SDHC_NISIER_CMDC_Pos)
+#define SDHC_NISIER_CMDC_ENABLED (SDHC_NISIER_CMDC_ENABLED_Val << SDHC_NISIER_CMDC_Pos)
+#define SDHC_NISIER_TRFC_Pos 1 /**< \brief (SDHC_NISIER) Transfer Complete Signal Enable */
+#define SDHC_NISIER_TRFC (_U_(0x1) << SDHC_NISIER_TRFC_Pos)
+#define SDHC_NISIER_TRFC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
+#define SDHC_NISIER_TRFC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_TRFC_MASKED (SDHC_NISIER_TRFC_MASKED_Val << SDHC_NISIER_TRFC_Pos)
+#define SDHC_NISIER_TRFC_ENABLED (SDHC_NISIER_TRFC_ENABLED_Val << SDHC_NISIER_TRFC_Pos)
+#define SDHC_NISIER_BLKGE_Pos 2 /**< \brief (SDHC_NISIER) Block Gap Event Signal Enable */
+#define SDHC_NISIER_BLKGE (_U_(0x1) << SDHC_NISIER_BLKGE_Pos)
+#define SDHC_NISIER_BLKGE_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
+#define SDHC_NISIER_BLKGE_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_BLKGE_MASKED (SDHC_NISIER_BLKGE_MASKED_Val << SDHC_NISIER_BLKGE_Pos)
+#define SDHC_NISIER_BLKGE_ENABLED (SDHC_NISIER_BLKGE_ENABLED_Val << SDHC_NISIER_BLKGE_Pos)
+#define SDHC_NISIER_DMAINT_Pos 3 /**< \brief (SDHC_NISIER) DMA Interrupt Signal Enable */
+#define SDHC_NISIER_DMAINT (_U_(0x1) << SDHC_NISIER_DMAINT_Pos)
+#define SDHC_NISIER_DMAINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
+#define SDHC_NISIER_DMAINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_DMAINT_MASKED (SDHC_NISIER_DMAINT_MASKED_Val << SDHC_NISIER_DMAINT_Pos)
+#define SDHC_NISIER_DMAINT_ENABLED (SDHC_NISIER_DMAINT_ENABLED_Val << SDHC_NISIER_DMAINT_Pos)
+#define SDHC_NISIER_BWRRDY_Pos 4 /**< \brief (SDHC_NISIER) Buffer Write Ready Signal Enable */
+#define SDHC_NISIER_BWRRDY (_U_(0x1) << SDHC_NISIER_BWRRDY_Pos)
+#define SDHC_NISIER_BWRRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
+#define SDHC_NISIER_BWRRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_BWRRDY_MASKED (SDHC_NISIER_BWRRDY_MASKED_Val << SDHC_NISIER_BWRRDY_Pos)
+#define SDHC_NISIER_BWRRDY_ENABLED (SDHC_NISIER_BWRRDY_ENABLED_Val << SDHC_NISIER_BWRRDY_Pos)
+#define SDHC_NISIER_BRDRDY_Pos 5 /**< \brief (SDHC_NISIER) Buffer Read Ready Signal Enable */
+#define SDHC_NISIER_BRDRDY (_U_(0x1) << SDHC_NISIER_BRDRDY_Pos)
+#define SDHC_NISIER_BRDRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
+#define SDHC_NISIER_BRDRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_BRDRDY_MASKED (SDHC_NISIER_BRDRDY_MASKED_Val << SDHC_NISIER_BRDRDY_Pos)
+#define SDHC_NISIER_BRDRDY_ENABLED (SDHC_NISIER_BRDRDY_ENABLED_Val << SDHC_NISIER_BRDRDY_Pos)
+#define SDHC_NISIER_CINS_Pos 6 /**< \brief (SDHC_NISIER) Card Insertion Signal Enable */
+#define SDHC_NISIER_CINS (_U_(0x1) << SDHC_NISIER_CINS_Pos)
+#define SDHC_NISIER_CINS_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
+#define SDHC_NISIER_CINS_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_CINS_MASKED (SDHC_NISIER_CINS_MASKED_Val << SDHC_NISIER_CINS_Pos)
+#define SDHC_NISIER_CINS_ENABLED (SDHC_NISIER_CINS_ENABLED_Val << SDHC_NISIER_CINS_Pos)
+#define SDHC_NISIER_CREM_Pos 7 /**< \brief (SDHC_NISIER) Card Removal Signal Enable */
+#define SDHC_NISIER_CREM (_U_(0x1) << SDHC_NISIER_CREM_Pos)
+#define SDHC_NISIER_CREM_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
+#define SDHC_NISIER_CREM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_CREM_MASKED (SDHC_NISIER_CREM_MASKED_Val << SDHC_NISIER_CREM_Pos)
+#define SDHC_NISIER_CREM_ENABLED (SDHC_NISIER_CREM_ENABLED_Val << SDHC_NISIER_CREM_Pos)
+#define SDHC_NISIER_CINT_Pos 8 /**< \brief (SDHC_NISIER) Card Interrupt Signal Enable */
+#define SDHC_NISIER_CINT (_U_(0x1) << SDHC_NISIER_CINT_Pos)
+#define SDHC_NISIER_CINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
+#define SDHC_NISIER_CINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_CINT_MASKED (SDHC_NISIER_CINT_MASKED_Val << SDHC_NISIER_CINT_Pos)
+#define SDHC_NISIER_CINT_ENABLED (SDHC_NISIER_CINT_ENABLED_Val << SDHC_NISIER_CINT_Pos)
+#define SDHC_NISIER_MASK _U_(0x01FF) /**< \brief (SDHC_NISIER) MASK Register */
+
+// EMMC mode
+#define SDHC_NISIER_EMMC_CMDC_Pos 0 /**< \brief (SDHC_NISIER_EMMC) Command Complete Signal Enable */
+#define SDHC_NISIER_EMMC_CMDC (_U_(0x1) << SDHC_NISIER_EMMC_CMDC_Pos)
+#define SDHC_NISIER_EMMC_CMDC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */
+#define SDHC_NISIER_EMMC_CMDC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */
+#define SDHC_NISIER_EMMC_CMDC_MASKED (SDHC_NISIER_EMMC_CMDC_MASKED_Val << SDHC_NISIER_EMMC_CMDC_Pos)
+#define SDHC_NISIER_EMMC_CMDC_ENABLED (SDHC_NISIER_EMMC_CMDC_ENABLED_Val << SDHC_NISIER_EMMC_CMDC_Pos)
+#define SDHC_NISIER_EMMC_TRFC_Pos 1 /**< \brief (SDHC_NISIER_EMMC) Transfer Complete Signal Enable */
+#define SDHC_NISIER_EMMC_TRFC (_U_(0x1) << SDHC_NISIER_EMMC_TRFC_Pos)
+#define SDHC_NISIER_EMMC_TRFC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */
+#define SDHC_NISIER_EMMC_TRFC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */
+#define SDHC_NISIER_EMMC_TRFC_MASKED (SDHC_NISIER_EMMC_TRFC_MASKED_Val << SDHC_NISIER_EMMC_TRFC_Pos)
+#define SDHC_NISIER_EMMC_TRFC_ENABLED (SDHC_NISIER_EMMC_TRFC_ENABLED_Val << SDHC_NISIER_EMMC_TRFC_Pos)
+#define SDHC_NISIER_EMMC_BLKGE_Pos 2 /**< \brief (SDHC_NISIER_EMMC) Block Gap Event Signal Enable */
+#define SDHC_NISIER_EMMC_BLKGE (_U_(0x1) << SDHC_NISIER_EMMC_BLKGE_Pos)
+#define SDHC_NISIER_EMMC_BLKGE_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */
+#define SDHC_NISIER_EMMC_BLKGE_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */
+#define SDHC_NISIER_EMMC_BLKGE_MASKED (SDHC_NISIER_EMMC_BLKGE_MASKED_Val << SDHC_NISIER_EMMC_BLKGE_Pos)
+#define SDHC_NISIER_EMMC_BLKGE_ENABLED (SDHC_NISIER_EMMC_BLKGE_ENABLED_Val << SDHC_NISIER_EMMC_BLKGE_Pos)
+#define SDHC_NISIER_EMMC_DMAINT_Pos 3 /**< \brief (SDHC_NISIER_EMMC) DMA Interrupt Signal Enable */
+#define SDHC_NISIER_EMMC_DMAINT (_U_(0x1) << SDHC_NISIER_EMMC_DMAINT_Pos)
+#define SDHC_NISIER_EMMC_DMAINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */
+#define SDHC_NISIER_EMMC_DMAINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */
+#define SDHC_NISIER_EMMC_DMAINT_MASKED (SDHC_NISIER_EMMC_DMAINT_MASKED_Val << SDHC_NISIER_EMMC_DMAINT_Pos)
+#define SDHC_NISIER_EMMC_DMAINT_ENABLED (SDHC_NISIER_EMMC_DMAINT_ENABLED_Val << SDHC_NISIER_EMMC_DMAINT_Pos)
+#define SDHC_NISIER_EMMC_BWRRDY_Pos 4 /**< \brief (SDHC_NISIER_EMMC) Buffer Write Ready Signal Enable */
+#define SDHC_NISIER_EMMC_BWRRDY (_U_(0x1) << SDHC_NISIER_EMMC_BWRRDY_Pos)
+#define SDHC_NISIER_EMMC_BWRRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */
+#define SDHC_NISIER_EMMC_BWRRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */
+#define SDHC_NISIER_EMMC_BWRRDY_MASKED (SDHC_NISIER_EMMC_BWRRDY_MASKED_Val << SDHC_NISIER_EMMC_BWRRDY_Pos)
+#define SDHC_NISIER_EMMC_BWRRDY_ENABLED (SDHC_NISIER_EMMC_BWRRDY_ENABLED_Val << SDHC_NISIER_EMMC_BWRRDY_Pos)
+#define SDHC_NISIER_EMMC_BRDRDY_Pos 5 /**< \brief (SDHC_NISIER_EMMC) Buffer Read Ready Signal Enable */
+#define SDHC_NISIER_EMMC_BRDRDY (_U_(0x1) << SDHC_NISIER_EMMC_BRDRDY_Pos)
+#define SDHC_NISIER_EMMC_BRDRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */
+#define SDHC_NISIER_EMMC_BRDRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */
+#define SDHC_NISIER_EMMC_BRDRDY_MASKED (SDHC_NISIER_EMMC_BRDRDY_MASKED_Val << SDHC_NISIER_EMMC_BRDRDY_Pos)
+#define SDHC_NISIER_EMMC_BRDRDY_ENABLED (SDHC_NISIER_EMMC_BRDRDY_ENABLED_Val << SDHC_NISIER_EMMC_BRDRDY_Pos)
+#define SDHC_NISIER_EMMC_BOOTAR_Pos 14 /**< \brief (SDHC_NISIER_EMMC) Boot Acknowledge Received Signal Enable */
+#define SDHC_NISIER_EMMC_BOOTAR (_U_(0x1) << SDHC_NISIER_EMMC_BOOTAR_Pos)
+#define SDHC_NISIER_EMMC_MASK _U_(0x403F) /**< \brief (SDHC_NISIER_EMMC) MASK Register */
+
+/* -------- SDHC_EISIER : (SDHC Offset: 0x03A) (R/W 16) Error Interrupt Signal Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Signal Enable */
+ uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Signal Enable */
+ uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Signal Enable */
+ uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Signal Enable */
+ uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Signal Enable */
+ uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Signal Enable */
+ uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Signal Enable */
+ uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Signal Enable */
+ uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Signal Enable */
+ uint16_t ADMA:1; /*!< bit: 9 ADMA Error Signal Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct { // EMMC mode
+ uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Signal Enable */
+ uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Signal Enable */
+ uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Signal Enable */
+ uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Signal Enable */
+ uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Signal Enable */
+ uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Signal Enable */
+ uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Signal Enable */
+ uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Signal Enable */
+ uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Signal Enable */
+ uint16_t ADMA:1; /*!< bit: 9 ADMA Error Signal Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t BOOTAE:1; /*!< bit: 12 Boot Acknowledge Error Signal Enable */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } EMMC; /*!< Structure used for EMMC */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_EISIER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_EISIER_OFFSET 0x03A /**< \brief (SDHC_EISIER offset) Error Interrupt Signal Enable */
+#define SDHC_EISIER_RESETVALUE _U_(0x0000) /**< \brief (SDHC_EISIER reset_value) Error Interrupt Signal Enable */
+
+#define SDHC_EISIER_CMDTEO_Pos 0 /**< \brief (SDHC_EISIER) Command Timeout Error Signal Enable */
+#define SDHC_EISIER_CMDTEO (_U_(0x1) << SDHC_EISIER_CMDTEO_Pos)
+#define SDHC_EISIER_CMDTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_CMDTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_CMDTEO_MASKED (SDHC_EISIER_CMDTEO_MASKED_Val << SDHC_EISIER_CMDTEO_Pos)
+#define SDHC_EISIER_CMDTEO_ENABLED (SDHC_EISIER_CMDTEO_ENABLED_Val << SDHC_EISIER_CMDTEO_Pos)
+#define SDHC_EISIER_CMDCRC_Pos 1 /**< \brief (SDHC_EISIER) Command CRC Error Signal Enable */
+#define SDHC_EISIER_CMDCRC (_U_(0x1) << SDHC_EISIER_CMDCRC_Pos)
+#define SDHC_EISIER_CMDCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_CMDCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_CMDCRC_MASKED (SDHC_EISIER_CMDCRC_MASKED_Val << SDHC_EISIER_CMDCRC_Pos)
+#define SDHC_EISIER_CMDCRC_ENABLED (SDHC_EISIER_CMDCRC_ENABLED_Val << SDHC_EISIER_CMDCRC_Pos)
+#define SDHC_EISIER_CMDEND_Pos 2 /**< \brief (SDHC_EISIER) Command End Bit Error Signal Enable */
+#define SDHC_EISIER_CMDEND (_U_(0x1) << SDHC_EISIER_CMDEND_Pos)
+#define SDHC_EISIER_CMDEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_CMDEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_CMDEND_MASKED (SDHC_EISIER_CMDEND_MASKED_Val << SDHC_EISIER_CMDEND_Pos)
+#define SDHC_EISIER_CMDEND_ENABLED (SDHC_EISIER_CMDEND_ENABLED_Val << SDHC_EISIER_CMDEND_Pos)
+#define SDHC_EISIER_CMDIDX_Pos 3 /**< \brief (SDHC_EISIER) Command Index Error Signal Enable */
+#define SDHC_EISIER_CMDIDX (_U_(0x1) << SDHC_EISIER_CMDIDX_Pos)
+#define SDHC_EISIER_CMDIDX_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_CMDIDX_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_CMDIDX_MASKED (SDHC_EISIER_CMDIDX_MASKED_Val << SDHC_EISIER_CMDIDX_Pos)
+#define SDHC_EISIER_CMDIDX_ENABLED (SDHC_EISIER_CMDIDX_ENABLED_Val << SDHC_EISIER_CMDIDX_Pos)
+#define SDHC_EISIER_DATTEO_Pos 4 /**< \brief (SDHC_EISIER) Data Timeout Error Signal Enable */
+#define SDHC_EISIER_DATTEO (_U_(0x1) << SDHC_EISIER_DATTEO_Pos)
+#define SDHC_EISIER_DATTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_DATTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_DATTEO_MASKED (SDHC_EISIER_DATTEO_MASKED_Val << SDHC_EISIER_DATTEO_Pos)
+#define SDHC_EISIER_DATTEO_ENABLED (SDHC_EISIER_DATTEO_ENABLED_Val << SDHC_EISIER_DATTEO_Pos)
+#define SDHC_EISIER_DATCRC_Pos 5 /**< \brief (SDHC_EISIER) Data CRC Error Signal Enable */
+#define SDHC_EISIER_DATCRC (_U_(0x1) << SDHC_EISIER_DATCRC_Pos)
+#define SDHC_EISIER_DATCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_DATCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_DATCRC_MASKED (SDHC_EISIER_DATCRC_MASKED_Val << SDHC_EISIER_DATCRC_Pos)
+#define SDHC_EISIER_DATCRC_ENABLED (SDHC_EISIER_DATCRC_ENABLED_Val << SDHC_EISIER_DATCRC_Pos)
+#define SDHC_EISIER_DATEND_Pos 6 /**< \brief (SDHC_EISIER) Data End Bit Error Signal Enable */
+#define SDHC_EISIER_DATEND (_U_(0x1) << SDHC_EISIER_DATEND_Pos)
+#define SDHC_EISIER_DATEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_DATEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_DATEND_MASKED (SDHC_EISIER_DATEND_MASKED_Val << SDHC_EISIER_DATEND_Pos)
+#define SDHC_EISIER_DATEND_ENABLED (SDHC_EISIER_DATEND_ENABLED_Val << SDHC_EISIER_DATEND_Pos)
+#define SDHC_EISIER_CURLIM_Pos 7 /**< \brief (SDHC_EISIER) Current Limit Error Signal Enable */
+#define SDHC_EISIER_CURLIM (_U_(0x1) << SDHC_EISIER_CURLIM_Pos)
+#define SDHC_EISIER_CURLIM_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_CURLIM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_CURLIM_MASKED (SDHC_EISIER_CURLIM_MASKED_Val << SDHC_EISIER_CURLIM_Pos)
+#define SDHC_EISIER_CURLIM_ENABLED (SDHC_EISIER_CURLIM_ENABLED_Val << SDHC_EISIER_CURLIM_Pos)
+#define SDHC_EISIER_ACMD_Pos 8 /**< \brief (SDHC_EISIER) Auto CMD Error Signal Enable */
+#define SDHC_EISIER_ACMD (_U_(0x1) << SDHC_EISIER_ACMD_Pos)
+#define SDHC_EISIER_ACMD_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_ACMD_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_ACMD_MASKED (SDHC_EISIER_ACMD_MASKED_Val << SDHC_EISIER_ACMD_Pos)
+#define SDHC_EISIER_ACMD_ENABLED (SDHC_EISIER_ACMD_ENABLED_Val << SDHC_EISIER_ACMD_Pos)
+#define SDHC_EISIER_ADMA_Pos 9 /**< \brief (SDHC_EISIER) ADMA Error Signal Enable */
+#define SDHC_EISIER_ADMA (_U_(0x1) << SDHC_EISIER_ADMA_Pos)
+#define SDHC_EISIER_ADMA_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_ADMA_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_ADMA_MASKED (SDHC_EISIER_ADMA_MASKED_Val << SDHC_EISIER_ADMA_Pos)
+#define SDHC_EISIER_ADMA_ENABLED (SDHC_EISIER_ADMA_ENABLED_Val << SDHC_EISIER_ADMA_Pos)
+#define SDHC_EISIER_MASK _U_(0x03FF) /**< \brief (SDHC_EISIER) MASK Register */
+
+// EMMC mode
+#define SDHC_EISIER_EMMC_CMDTEO_Pos 0 /**< \brief (SDHC_EISIER_EMMC) Command Timeout Error Signal Enable */
+#define SDHC_EISIER_EMMC_CMDTEO (_U_(0x1) << SDHC_EISIER_EMMC_CMDTEO_Pos)
+#define SDHC_EISIER_EMMC_CMDTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_CMDTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_CMDTEO_MASKED (SDHC_EISIER_EMMC_CMDTEO_MASKED_Val << SDHC_EISIER_EMMC_CMDTEO_Pos)
+#define SDHC_EISIER_EMMC_CMDTEO_ENABLED (SDHC_EISIER_EMMC_CMDTEO_ENABLED_Val << SDHC_EISIER_EMMC_CMDTEO_Pos)
+#define SDHC_EISIER_EMMC_CMDCRC_Pos 1 /**< \brief (SDHC_EISIER_EMMC) Command CRC Error Signal Enable */
+#define SDHC_EISIER_EMMC_CMDCRC (_U_(0x1) << SDHC_EISIER_EMMC_CMDCRC_Pos)
+#define SDHC_EISIER_EMMC_CMDCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_CMDCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_CMDCRC_MASKED (SDHC_EISIER_EMMC_CMDCRC_MASKED_Val << SDHC_EISIER_EMMC_CMDCRC_Pos)
+#define SDHC_EISIER_EMMC_CMDCRC_ENABLED (SDHC_EISIER_EMMC_CMDCRC_ENABLED_Val << SDHC_EISIER_EMMC_CMDCRC_Pos)
+#define SDHC_EISIER_EMMC_CMDEND_Pos 2 /**< \brief (SDHC_EISIER_EMMC) Command End Bit Error Signal Enable */
+#define SDHC_EISIER_EMMC_CMDEND (_U_(0x1) << SDHC_EISIER_EMMC_CMDEND_Pos)
+#define SDHC_EISIER_EMMC_CMDEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_CMDEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_CMDEND_MASKED (SDHC_EISIER_EMMC_CMDEND_MASKED_Val << SDHC_EISIER_EMMC_CMDEND_Pos)
+#define SDHC_EISIER_EMMC_CMDEND_ENABLED (SDHC_EISIER_EMMC_CMDEND_ENABLED_Val << SDHC_EISIER_EMMC_CMDEND_Pos)
+#define SDHC_EISIER_EMMC_CMDIDX_Pos 3 /**< \brief (SDHC_EISIER_EMMC) Command Index Error Signal Enable */
+#define SDHC_EISIER_EMMC_CMDIDX (_U_(0x1) << SDHC_EISIER_EMMC_CMDIDX_Pos)
+#define SDHC_EISIER_EMMC_CMDIDX_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_CMDIDX_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_CMDIDX_MASKED (SDHC_EISIER_EMMC_CMDIDX_MASKED_Val << SDHC_EISIER_EMMC_CMDIDX_Pos)
+#define SDHC_EISIER_EMMC_CMDIDX_ENABLED (SDHC_EISIER_EMMC_CMDIDX_ENABLED_Val << SDHC_EISIER_EMMC_CMDIDX_Pos)
+#define SDHC_EISIER_EMMC_DATTEO_Pos 4 /**< \brief (SDHC_EISIER_EMMC) Data Timeout Error Signal Enable */
+#define SDHC_EISIER_EMMC_DATTEO (_U_(0x1) << SDHC_EISIER_EMMC_DATTEO_Pos)
+#define SDHC_EISIER_EMMC_DATTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_DATTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_DATTEO_MASKED (SDHC_EISIER_EMMC_DATTEO_MASKED_Val << SDHC_EISIER_EMMC_DATTEO_Pos)
+#define SDHC_EISIER_EMMC_DATTEO_ENABLED (SDHC_EISIER_EMMC_DATTEO_ENABLED_Val << SDHC_EISIER_EMMC_DATTEO_Pos)
+#define SDHC_EISIER_EMMC_DATCRC_Pos 5 /**< \brief (SDHC_EISIER_EMMC) Data CRC Error Signal Enable */
+#define SDHC_EISIER_EMMC_DATCRC (_U_(0x1) << SDHC_EISIER_EMMC_DATCRC_Pos)
+#define SDHC_EISIER_EMMC_DATCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_DATCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_DATCRC_MASKED (SDHC_EISIER_EMMC_DATCRC_MASKED_Val << SDHC_EISIER_EMMC_DATCRC_Pos)
+#define SDHC_EISIER_EMMC_DATCRC_ENABLED (SDHC_EISIER_EMMC_DATCRC_ENABLED_Val << SDHC_EISIER_EMMC_DATCRC_Pos)
+#define SDHC_EISIER_EMMC_DATEND_Pos 6 /**< \brief (SDHC_EISIER_EMMC) Data End Bit Error Signal Enable */
+#define SDHC_EISIER_EMMC_DATEND (_U_(0x1) << SDHC_EISIER_EMMC_DATEND_Pos)
+#define SDHC_EISIER_EMMC_DATEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_DATEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_DATEND_MASKED (SDHC_EISIER_EMMC_DATEND_MASKED_Val << SDHC_EISIER_EMMC_DATEND_Pos)
+#define SDHC_EISIER_EMMC_DATEND_ENABLED (SDHC_EISIER_EMMC_DATEND_ENABLED_Val << SDHC_EISIER_EMMC_DATEND_Pos)
+#define SDHC_EISIER_EMMC_CURLIM_Pos 7 /**< \brief (SDHC_EISIER_EMMC) Current Limit Error Signal Enable */
+#define SDHC_EISIER_EMMC_CURLIM (_U_(0x1) << SDHC_EISIER_EMMC_CURLIM_Pos)
+#define SDHC_EISIER_EMMC_CURLIM_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_CURLIM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_CURLIM_MASKED (SDHC_EISIER_EMMC_CURLIM_MASKED_Val << SDHC_EISIER_EMMC_CURLIM_Pos)
+#define SDHC_EISIER_EMMC_CURLIM_ENABLED (SDHC_EISIER_EMMC_CURLIM_ENABLED_Val << SDHC_EISIER_EMMC_CURLIM_Pos)
+#define SDHC_EISIER_EMMC_ACMD_Pos 8 /**< \brief (SDHC_EISIER_EMMC) Auto CMD Error Signal Enable */
+#define SDHC_EISIER_EMMC_ACMD (_U_(0x1) << SDHC_EISIER_EMMC_ACMD_Pos)
+#define SDHC_EISIER_EMMC_ACMD_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_ACMD_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_ACMD_MASKED (SDHC_EISIER_EMMC_ACMD_MASKED_Val << SDHC_EISIER_EMMC_ACMD_Pos)
+#define SDHC_EISIER_EMMC_ACMD_ENABLED (SDHC_EISIER_EMMC_ACMD_ENABLED_Val << SDHC_EISIER_EMMC_ACMD_Pos)
+#define SDHC_EISIER_EMMC_ADMA_Pos 9 /**< \brief (SDHC_EISIER_EMMC) ADMA Error Signal Enable */
+#define SDHC_EISIER_EMMC_ADMA (_U_(0x1) << SDHC_EISIER_EMMC_ADMA_Pos)
+#define SDHC_EISIER_EMMC_ADMA_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_ADMA_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_ADMA_MASKED (SDHC_EISIER_EMMC_ADMA_MASKED_Val << SDHC_EISIER_EMMC_ADMA_Pos)
+#define SDHC_EISIER_EMMC_ADMA_ENABLED (SDHC_EISIER_EMMC_ADMA_ENABLED_Val << SDHC_EISIER_EMMC_ADMA_Pos)
+#define SDHC_EISIER_EMMC_BOOTAE_Pos 12 /**< \brief (SDHC_EISIER_EMMC) Boot Acknowledge Error Signal Enable */
+#define SDHC_EISIER_EMMC_BOOTAE (_U_(0x1) << SDHC_EISIER_EMMC_BOOTAE_Pos)
+#define SDHC_EISIER_EMMC_MASK _U_(0x13FF) /**< \brief (SDHC_EISIER_EMMC) MASK Register */
+
+/* -------- SDHC_ACESR : (SDHC Offset: 0x03C) (R/ 16) Auto CMD Error Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ACMD12NE:1; /*!< bit: 0 Auto CMD12 Not Executed */
+ uint16_t ACMDTEO:1; /*!< bit: 1 Auto CMD Timeout Error */
+ uint16_t ACMDCRC:1; /*!< bit: 2 Auto CMD CRC Error */
+ uint16_t ACMDEND:1; /*!< bit: 3 Auto CMD End Bit Error */
+ uint16_t ACMDIDX:1; /*!< bit: 4 Auto CMD Index Error */
+ uint16_t :2; /*!< bit: 5.. 6 Reserved */
+ uint16_t CMDNI:1; /*!< bit: 7 Command not Issued By Auto CMD12 Error */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_ACESR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_ACESR_OFFSET 0x03C /**< \brief (SDHC_ACESR offset) Auto CMD Error Status */
+#define SDHC_ACESR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_ACESR reset_value) Auto CMD Error Status */
+
+#define SDHC_ACESR_ACMD12NE_Pos 0 /**< \brief (SDHC_ACESR) Auto CMD12 Not Executed */
+#define SDHC_ACESR_ACMD12NE (_U_(0x1) << SDHC_ACESR_ACMD12NE_Pos)
+#define SDHC_ACESR_ACMD12NE_EXEC_Val _U_(0x0) /**< \brief (SDHC_ACESR) Executed */
+#define SDHC_ACESR_ACMD12NE_NOT_EXEC_Val _U_(0x1) /**< \brief (SDHC_ACESR) Not executed */
+#define SDHC_ACESR_ACMD12NE_EXEC (SDHC_ACESR_ACMD12NE_EXEC_Val << SDHC_ACESR_ACMD12NE_Pos)
+#define SDHC_ACESR_ACMD12NE_NOT_EXEC (SDHC_ACESR_ACMD12NE_NOT_EXEC_Val << SDHC_ACESR_ACMD12NE_Pos)
+#define SDHC_ACESR_ACMDTEO_Pos 1 /**< \brief (SDHC_ACESR) Auto CMD Timeout Error */
+#define SDHC_ACESR_ACMDTEO (_U_(0x1) << SDHC_ACESR_ACMDTEO_Pos)
+#define SDHC_ACESR_ACMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */
+#define SDHC_ACESR_ACMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_ACESR) Timeout */
+#define SDHC_ACESR_ACMDTEO_NO (SDHC_ACESR_ACMDTEO_NO_Val << SDHC_ACESR_ACMDTEO_Pos)
+#define SDHC_ACESR_ACMDTEO_YES (SDHC_ACESR_ACMDTEO_YES_Val << SDHC_ACESR_ACMDTEO_Pos)
+#define SDHC_ACESR_ACMDCRC_Pos 2 /**< \brief (SDHC_ACESR) Auto CMD CRC Error */
+#define SDHC_ACESR_ACMDCRC (_U_(0x1) << SDHC_ACESR_ACMDCRC_Pos)
+#define SDHC_ACESR_ACMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */
+#define SDHC_ACESR_ACMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_ACESR) CRC Error Generated */
+#define SDHC_ACESR_ACMDCRC_NO (SDHC_ACESR_ACMDCRC_NO_Val << SDHC_ACESR_ACMDCRC_Pos)
+#define SDHC_ACESR_ACMDCRC_YES (SDHC_ACESR_ACMDCRC_YES_Val << SDHC_ACESR_ACMDCRC_Pos)
+#define SDHC_ACESR_ACMDEND_Pos 3 /**< \brief (SDHC_ACESR) Auto CMD End Bit Error */
+#define SDHC_ACESR_ACMDEND (_U_(0x1) << SDHC_ACESR_ACMDEND_Pos)
+#define SDHC_ACESR_ACMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */
+#define SDHC_ACESR_ACMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_ACESR) End Bit Error Generated */
+#define SDHC_ACESR_ACMDEND_NO (SDHC_ACESR_ACMDEND_NO_Val << SDHC_ACESR_ACMDEND_Pos)
+#define SDHC_ACESR_ACMDEND_YES (SDHC_ACESR_ACMDEND_YES_Val << SDHC_ACESR_ACMDEND_Pos)
+#define SDHC_ACESR_ACMDIDX_Pos 4 /**< \brief (SDHC_ACESR) Auto CMD Index Error */
+#define SDHC_ACESR_ACMDIDX (_U_(0x1) << SDHC_ACESR_ACMDIDX_Pos)
+#define SDHC_ACESR_ACMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */
+#define SDHC_ACESR_ACMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_ACESR) Error */
+#define SDHC_ACESR_ACMDIDX_NO (SDHC_ACESR_ACMDIDX_NO_Val << SDHC_ACESR_ACMDIDX_Pos)
+#define SDHC_ACESR_ACMDIDX_YES (SDHC_ACESR_ACMDIDX_YES_Val << SDHC_ACESR_ACMDIDX_Pos)
+#define SDHC_ACESR_CMDNI_Pos 7 /**< \brief (SDHC_ACESR) Command not Issued By Auto CMD12 Error */
+#define SDHC_ACESR_CMDNI (_U_(0x1) << SDHC_ACESR_CMDNI_Pos)
+#define SDHC_ACESR_CMDNI_OK_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */
+#define SDHC_ACESR_CMDNI_NOT_ISSUED_Val _U_(0x1) /**< \brief (SDHC_ACESR) Not Issued */
+#define SDHC_ACESR_CMDNI_OK (SDHC_ACESR_CMDNI_OK_Val << SDHC_ACESR_CMDNI_Pos)
+#define SDHC_ACESR_CMDNI_NOT_ISSUED (SDHC_ACESR_CMDNI_NOT_ISSUED_Val << SDHC_ACESR_CMDNI_Pos)
+#define SDHC_ACESR_MASK _U_(0x009F) /**< \brief (SDHC_ACESR) MASK Register */
+
+/* -------- SDHC_HC2R : (SDHC Offset: 0x03E) (R/W 16) Host Control 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t UHSMS:3; /*!< bit: 0.. 2 UHS Mode Select */
+ uint16_t VS18EN:1; /*!< bit: 3 1.8V Signaling Enable */
+ uint16_t DRVSEL:2; /*!< bit: 4.. 5 Driver Strength Select */
+ uint16_t EXTUN:1; /*!< bit: 6 Execute Tuning */
+ uint16_t SLCKSEL:1; /*!< bit: 7 Sampling Clock Select */
+ uint16_t :6; /*!< bit: 8..13 Reserved */
+ uint16_t ASINTEN:1; /*!< bit: 14 Asynchronous Interrupt Enable */
+ uint16_t PVALEN:1; /*!< bit: 15 Preset Value Enable */
+ } bit; /*!< Structure used for bit access */
+ struct { // EMMC mode
+ uint16_t HS200EN:4; /*!< bit: 0.. 3 HS200 Mode Enable */
+ uint16_t DRVSEL:2; /*!< bit: 4.. 5 Driver Strength Select */
+ uint16_t EXTUN:1; /*!< bit: 6 Execute Tuning */
+ uint16_t SLCKSEL:1; /*!< bit: 7 Sampling Clock Select */
+ uint16_t :7; /*!< bit: 8..14 Reserved */
+ uint16_t PVALEN:1; /*!< bit: 15 Preset Value Enable */
+ } EMMC; /*!< Structure used for EMMC */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_HC2R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_HC2R_OFFSET 0x03E /**< \brief (SDHC_HC2R offset) Host Control 2 */
+#define SDHC_HC2R_RESETVALUE _U_(0x0000) /**< \brief (SDHC_HC2R reset_value) Host Control 2 */
+
+#define SDHC_HC2R_UHSMS_Pos 0 /**< \brief (SDHC_HC2R) UHS Mode Select */
+#define SDHC_HC2R_UHSMS_Msk (_U_(0x7) << SDHC_HC2R_UHSMS_Pos)
+#define SDHC_HC2R_UHSMS(value) (SDHC_HC2R_UHSMS_Msk & ((value) << SDHC_HC2R_UHSMS_Pos))
+#define SDHC_HC2R_UHSMS_SDR12_Val _U_(0x0) /**< \brief (SDHC_HC2R) SDR12 */
+#define SDHC_HC2R_UHSMS_SDR25_Val _U_(0x1) /**< \brief (SDHC_HC2R) SDR25 */
+#define SDHC_HC2R_UHSMS_SDR50_Val _U_(0x2) /**< \brief (SDHC_HC2R) SDR50 */
+#define SDHC_HC2R_UHSMS_SDR104_Val _U_(0x3) /**< \brief (SDHC_HC2R) SDR104 */
+#define SDHC_HC2R_UHSMS_DDR50_Val _U_(0x4) /**< \brief (SDHC_HC2R) DDR50 */
+#define SDHC_HC2R_UHSMS_SDR12 (SDHC_HC2R_UHSMS_SDR12_Val << SDHC_HC2R_UHSMS_Pos)
+#define SDHC_HC2R_UHSMS_SDR25 (SDHC_HC2R_UHSMS_SDR25_Val << SDHC_HC2R_UHSMS_Pos)
+#define SDHC_HC2R_UHSMS_SDR50 (SDHC_HC2R_UHSMS_SDR50_Val << SDHC_HC2R_UHSMS_Pos)
+#define SDHC_HC2R_UHSMS_SDR104 (SDHC_HC2R_UHSMS_SDR104_Val << SDHC_HC2R_UHSMS_Pos)
+#define SDHC_HC2R_UHSMS_DDR50 (SDHC_HC2R_UHSMS_DDR50_Val << SDHC_HC2R_UHSMS_Pos)
+#define SDHC_HC2R_VS18EN_Pos 3 /**< \brief (SDHC_HC2R) 1.8V Signaling Enable */
+#define SDHC_HC2R_VS18EN (_U_(0x1) << SDHC_HC2R_VS18EN_Pos)
+#define SDHC_HC2R_VS18EN_S33V_Val _U_(0x0) /**< \brief (SDHC_HC2R) 3.3V Signaling */
+#define SDHC_HC2R_VS18EN_S18V_Val _U_(0x1) /**< \brief (SDHC_HC2R) 1.8V Signaling */
+#define SDHC_HC2R_VS18EN_S33V (SDHC_HC2R_VS18EN_S33V_Val << SDHC_HC2R_VS18EN_Pos)
+#define SDHC_HC2R_VS18EN_S18V (SDHC_HC2R_VS18EN_S18V_Val << SDHC_HC2R_VS18EN_Pos)
+#define SDHC_HC2R_DRVSEL_Pos 4 /**< \brief (SDHC_HC2R) Driver Strength Select */
+#define SDHC_HC2R_DRVSEL_Msk (_U_(0x3) << SDHC_HC2R_DRVSEL_Pos)
+#define SDHC_HC2R_DRVSEL(value) (SDHC_HC2R_DRVSEL_Msk & ((value) << SDHC_HC2R_DRVSEL_Pos))
+#define SDHC_HC2R_DRVSEL_B_Val _U_(0x0) /**< \brief (SDHC_HC2R) Driver Type B is Selected (Default) */
+#define SDHC_HC2R_DRVSEL_A_Val _U_(0x1) /**< \brief (SDHC_HC2R) Driver Type A is Selected */
+#define SDHC_HC2R_DRVSEL_C_Val _U_(0x2) /**< \brief (SDHC_HC2R) Driver Type C is Selected */
+#define SDHC_HC2R_DRVSEL_D_Val _U_(0x3) /**< \brief (SDHC_HC2R) Driver Type D is Selected */
+#define SDHC_HC2R_DRVSEL_B (SDHC_HC2R_DRVSEL_B_Val << SDHC_HC2R_DRVSEL_Pos)
+#define SDHC_HC2R_DRVSEL_A (SDHC_HC2R_DRVSEL_A_Val << SDHC_HC2R_DRVSEL_Pos)
+#define SDHC_HC2R_DRVSEL_C (SDHC_HC2R_DRVSEL_C_Val << SDHC_HC2R_DRVSEL_Pos)
+#define SDHC_HC2R_DRVSEL_D (SDHC_HC2R_DRVSEL_D_Val << SDHC_HC2R_DRVSEL_Pos)
+#define SDHC_HC2R_EXTUN_Pos 6 /**< \brief (SDHC_HC2R) Execute Tuning */
+#define SDHC_HC2R_EXTUN (_U_(0x1) << SDHC_HC2R_EXTUN_Pos)
+#define SDHC_HC2R_EXTUN_NO_Val _U_(0x0) /**< \brief (SDHC_HC2R) Not Tuned or Tuning Completed */
+#define SDHC_HC2R_EXTUN_REQUESTED_Val _U_(0x1) /**< \brief (SDHC_HC2R) Execute Tuning */
+#define SDHC_HC2R_EXTUN_NO (SDHC_HC2R_EXTUN_NO_Val << SDHC_HC2R_EXTUN_Pos)
+#define SDHC_HC2R_EXTUN_REQUESTED (SDHC_HC2R_EXTUN_REQUESTED_Val << SDHC_HC2R_EXTUN_Pos)
+#define SDHC_HC2R_SLCKSEL_Pos 7 /**< \brief (SDHC_HC2R) Sampling Clock Select */
+#define SDHC_HC2R_SLCKSEL (_U_(0x1) << SDHC_HC2R_SLCKSEL_Pos)
+#define SDHC_HC2R_SLCKSEL_FIXED_Val _U_(0x0) /**< \brief (SDHC_HC2R) Fixed clock is used to sample data */
+#define SDHC_HC2R_SLCKSEL_TUNED_Val _U_(0x1) /**< \brief (SDHC_HC2R) Tuned clock is used to sample data */
+#define SDHC_HC2R_SLCKSEL_FIXED (SDHC_HC2R_SLCKSEL_FIXED_Val << SDHC_HC2R_SLCKSEL_Pos)
+#define SDHC_HC2R_SLCKSEL_TUNED (SDHC_HC2R_SLCKSEL_TUNED_Val << SDHC_HC2R_SLCKSEL_Pos)
+#define SDHC_HC2R_ASINTEN_Pos 14 /**< \brief (SDHC_HC2R) Asynchronous Interrupt Enable */
+#define SDHC_HC2R_ASINTEN (_U_(0x1) << SDHC_HC2R_ASINTEN_Pos)
+#define SDHC_HC2R_ASINTEN_DISABLED_Val _U_(0x0) /**< \brief (SDHC_HC2R) Disabled */
+#define SDHC_HC2R_ASINTEN_ENABLED_Val _U_(0x1) /**< \brief (SDHC_HC2R) Enabled */
+#define SDHC_HC2R_ASINTEN_DISABLED (SDHC_HC2R_ASINTEN_DISABLED_Val << SDHC_HC2R_ASINTEN_Pos)
+#define SDHC_HC2R_ASINTEN_ENABLED (SDHC_HC2R_ASINTEN_ENABLED_Val << SDHC_HC2R_ASINTEN_Pos)
+#define SDHC_HC2R_PVALEN_Pos 15 /**< \brief (SDHC_HC2R) Preset Value Enable */
+#define SDHC_HC2R_PVALEN (_U_(0x1) << SDHC_HC2R_PVALEN_Pos)
+#define SDHC_HC2R_PVALEN_HOST_Val _U_(0x0) /**< \brief (SDHC_HC2R) SDCLK and Driver Strength are controlled by Host Controller */
+#define SDHC_HC2R_PVALEN_AUTO_Val _U_(0x1) /**< \brief (SDHC_HC2R) Automatic Selection by Preset Value is Enabled */
+#define SDHC_HC2R_PVALEN_HOST (SDHC_HC2R_PVALEN_HOST_Val << SDHC_HC2R_PVALEN_Pos)
+#define SDHC_HC2R_PVALEN_AUTO (SDHC_HC2R_PVALEN_AUTO_Val << SDHC_HC2R_PVALEN_Pos)
+#define SDHC_HC2R_MASK _U_(0xC0FF) /**< \brief (SDHC_HC2R) MASK Register */
+
+// EMMC mode
+#define SDHC_HC2R_EMMC_HS200EN_Pos 0 /**< \brief (SDHC_HC2R_EMMC) HS200 Mode Enable */
+#define SDHC_HC2R_EMMC_HS200EN_Msk (_U_(0xF) << SDHC_HC2R_EMMC_HS200EN_Pos)
+#define SDHC_HC2R_EMMC_HS200EN(value) (SDHC_HC2R_EMMC_HS200EN_Msk & ((value) << SDHC_HC2R_EMMC_HS200EN_Pos))
+#define SDHC_HC2R_EMMC_HS200EN_SDR12_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) SDR12 */
+#define SDHC_HC2R_EMMC_HS200EN_SDR25_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) SDR25 */
+#define SDHC_HC2R_EMMC_HS200EN_SDR50_Val _U_(0x2) /**< \brief (SDHC_HC2R_EMMC) SDR50 */
+#define SDHC_HC2R_EMMC_HS200EN_SDR104_Val _U_(0x3) /**< \brief (SDHC_HC2R_EMMC) SDR104 */
+#define SDHC_HC2R_EMMC_HS200EN_DDR50_Val _U_(0x4) /**< \brief (SDHC_HC2R_EMMC) DDR50 */
+#define SDHC_HC2R_EMMC_HS200EN_SDR12 (SDHC_HC2R_EMMC_HS200EN_SDR12_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
+#define SDHC_HC2R_EMMC_HS200EN_SDR25 (SDHC_HC2R_EMMC_HS200EN_SDR25_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
+#define SDHC_HC2R_EMMC_HS200EN_SDR50 (SDHC_HC2R_EMMC_HS200EN_SDR50_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
+#define SDHC_HC2R_EMMC_HS200EN_SDR104 (SDHC_HC2R_EMMC_HS200EN_SDR104_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
+#define SDHC_HC2R_EMMC_HS200EN_DDR50 (SDHC_HC2R_EMMC_HS200EN_DDR50_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
+#define SDHC_HC2R_EMMC_DRVSEL_Pos 4 /**< \brief (SDHC_HC2R_EMMC) Driver Strength Select */
+#define SDHC_HC2R_EMMC_DRVSEL_Msk (_U_(0x3) << SDHC_HC2R_EMMC_DRVSEL_Pos)
+#define SDHC_HC2R_EMMC_DRVSEL(value) (SDHC_HC2R_EMMC_DRVSEL_Msk & ((value) << SDHC_HC2R_EMMC_DRVSEL_Pos))
+#define SDHC_HC2R_EMMC_DRVSEL_B_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) Driver Type B is Selected (Default) */
+#define SDHC_HC2R_EMMC_DRVSEL_A_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) Driver Type A is Selected */
+#define SDHC_HC2R_EMMC_DRVSEL_C_Val _U_(0x2) /**< \brief (SDHC_HC2R_EMMC) Driver Type C is Selected */
+#define SDHC_HC2R_EMMC_DRVSEL_D_Val _U_(0x3) /**< \brief (SDHC_HC2R_EMMC) Driver Type D is Selected */
+#define SDHC_HC2R_EMMC_DRVSEL_B (SDHC_HC2R_EMMC_DRVSEL_B_Val << SDHC_HC2R_EMMC_DRVSEL_Pos)
+#define SDHC_HC2R_EMMC_DRVSEL_A (SDHC_HC2R_EMMC_DRVSEL_A_Val << SDHC_HC2R_EMMC_DRVSEL_Pos)
+#define SDHC_HC2R_EMMC_DRVSEL_C (SDHC_HC2R_EMMC_DRVSEL_C_Val << SDHC_HC2R_EMMC_DRVSEL_Pos)
+#define SDHC_HC2R_EMMC_DRVSEL_D (SDHC_HC2R_EMMC_DRVSEL_D_Val << SDHC_HC2R_EMMC_DRVSEL_Pos)
+#define SDHC_HC2R_EMMC_EXTUN_Pos 6 /**< \brief (SDHC_HC2R_EMMC) Execute Tuning */
+#define SDHC_HC2R_EMMC_EXTUN (_U_(0x1) << SDHC_HC2R_EMMC_EXTUN_Pos)
+#define SDHC_HC2R_EMMC_EXTUN_NO_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) Not Tuned or Tuning Completed */
+#define SDHC_HC2R_EMMC_EXTUN_REQUESTED_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) Execute Tuning */
+#define SDHC_HC2R_EMMC_EXTUN_NO (SDHC_HC2R_EMMC_EXTUN_NO_Val << SDHC_HC2R_EMMC_EXTUN_Pos)
+#define SDHC_HC2R_EMMC_EXTUN_REQUESTED (SDHC_HC2R_EMMC_EXTUN_REQUESTED_Val << SDHC_HC2R_EMMC_EXTUN_Pos)
+#define SDHC_HC2R_EMMC_SLCKSEL_Pos 7 /**< \brief (SDHC_HC2R_EMMC) Sampling Clock Select */
+#define SDHC_HC2R_EMMC_SLCKSEL (_U_(0x1) << SDHC_HC2R_EMMC_SLCKSEL_Pos)
+#define SDHC_HC2R_EMMC_SLCKSEL_FIXED_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) Fixed clock is used to sample data */
+#define SDHC_HC2R_EMMC_SLCKSEL_TUNED_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) Tuned clock is used to sample data */
+#define SDHC_HC2R_EMMC_SLCKSEL_FIXED (SDHC_HC2R_EMMC_SLCKSEL_FIXED_Val << SDHC_HC2R_EMMC_SLCKSEL_Pos)
+#define SDHC_HC2R_EMMC_SLCKSEL_TUNED (SDHC_HC2R_EMMC_SLCKSEL_TUNED_Val << SDHC_HC2R_EMMC_SLCKSEL_Pos)
+#define SDHC_HC2R_EMMC_PVALEN_Pos 15 /**< \brief (SDHC_HC2R_EMMC) Preset Value Enable */
+#define SDHC_HC2R_EMMC_PVALEN (_U_(0x1) << SDHC_HC2R_EMMC_PVALEN_Pos)
+#define SDHC_HC2R_EMMC_PVALEN_HOST_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) SDCLK and Driver Strength are controlled by Host Controller */
+#define SDHC_HC2R_EMMC_PVALEN_AUTO_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) Automatic Selection by Preset Value is Enabled */
+#define SDHC_HC2R_EMMC_PVALEN_HOST (SDHC_HC2R_EMMC_PVALEN_HOST_Val << SDHC_HC2R_EMMC_PVALEN_Pos)
+#define SDHC_HC2R_EMMC_PVALEN_AUTO (SDHC_HC2R_EMMC_PVALEN_AUTO_Val << SDHC_HC2R_EMMC_PVALEN_Pos)
+#define SDHC_HC2R_EMMC_MASK _U_(0x80FF) /**< \brief (SDHC_HC2R_EMMC) MASK Register */
+
+/* -------- SDHC_CA0R : (SDHC Offset: 0x040) (R/ 32) Capabilities 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TEOCLKF:6; /*!< bit: 0.. 5 Timeout Clock Frequency */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t TEOCLKU:1; /*!< bit: 7 Timeout Clock Unit */
+ uint32_t BASECLKF:8; /*!< bit: 8..15 Base Clock Frequency */
+ uint32_t MAXBLKL:2; /*!< bit: 16..17 Max Block Length */
+ uint32_t ED8SUP:1; /*!< bit: 18 8-bit Support for Embedded Device */
+ uint32_t ADMA2SUP:1; /*!< bit: 19 ADMA2 Support */
+ uint32_t :1; /*!< bit: 20 Reserved */
+ uint32_t HSSUP:1; /*!< bit: 21 High Speed Support */
+ uint32_t SDMASUP:1; /*!< bit: 22 SDMA Support */
+ uint32_t SRSUP:1; /*!< bit: 23 Suspend/Resume Support */
+ uint32_t V33VSUP:1; /*!< bit: 24 Voltage Support 3.3V */
+ uint32_t V30VSUP:1; /*!< bit: 25 Voltage Support 3.0V */
+ uint32_t V18VSUP:1; /*!< bit: 26 Voltage Support 1.8V */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t SB64SUP:1; /*!< bit: 28 64-Bit System Bus Support */
+ uint32_t ASINTSUP:1; /*!< bit: 29 Asynchronous Interrupt Support */
+ uint32_t SLTYPE:2; /*!< bit: 30..31 Slot Type */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_CA0R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_CA0R_OFFSET 0x040 /**< \brief (SDHC_CA0R offset) Capabilities 0 */
+#define SDHC_CA0R_RESETVALUE _U_(0x27E80080) /**< \brief (SDHC_CA0R reset_value) Capabilities 0 */
+
+#define SDHC_CA0R_TEOCLKF_Pos 0 /**< \brief (SDHC_CA0R) Timeout Clock Frequency */
+#define SDHC_CA0R_TEOCLKF_Msk (_U_(0x3F) << SDHC_CA0R_TEOCLKF_Pos)
+#define SDHC_CA0R_TEOCLKF(value) (SDHC_CA0R_TEOCLKF_Msk & ((value) << SDHC_CA0R_TEOCLKF_Pos))
+#define SDHC_CA0R_TEOCLKF_OTHER_Val _U_(0x0) /**< \brief (SDHC_CA0R) Get information via another method */
+#define SDHC_CA0R_TEOCLKF_OTHER (SDHC_CA0R_TEOCLKF_OTHER_Val << SDHC_CA0R_TEOCLKF_Pos)
+#define SDHC_CA0R_TEOCLKU_Pos 7 /**< \brief (SDHC_CA0R) Timeout Clock Unit */
+#define SDHC_CA0R_TEOCLKU (_U_(0x1) << SDHC_CA0R_TEOCLKU_Pos)
+#define SDHC_CA0R_TEOCLKU_KHZ_Val _U_(0x0) /**< \brief (SDHC_CA0R) kHz */
+#define SDHC_CA0R_TEOCLKU_MHZ_Val _U_(0x1) /**< \brief (SDHC_CA0R) MHz */
+#define SDHC_CA0R_TEOCLKU_KHZ (SDHC_CA0R_TEOCLKU_KHZ_Val << SDHC_CA0R_TEOCLKU_Pos)
+#define SDHC_CA0R_TEOCLKU_MHZ (SDHC_CA0R_TEOCLKU_MHZ_Val << SDHC_CA0R_TEOCLKU_Pos)
+#define SDHC_CA0R_BASECLKF_Pos 8 /**< \brief (SDHC_CA0R) Base Clock Frequency */
+#define SDHC_CA0R_BASECLKF_Msk (_U_(0xFF) << SDHC_CA0R_BASECLKF_Pos)
+#define SDHC_CA0R_BASECLKF(value) (SDHC_CA0R_BASECLKF_Msk & ((value) << SDHC_CA0R_BASECLKF_Pos))
+#define SDHC_CA0R_BASECLKF_OTHER_Val _U_(0x0) /**< \brief (SDHC_CA0R) Get information via another method */
+#define SDHC_CA0R_BASECLKF_OTHER (SDHC_CA0R_BASECLKF_OTHER_Val << SDHC_CA0R_BASECLKF_Pos)
+#define SDHC_CA0R_MAXBLKL_Pos 16 /**< \brief (SDHC_CA0R) Max Block Length */
+#define SDHC_CA0R_MAXBLKL_Msk (_U_(0x3) << SDHC_CA0R_MAXBLKL_Pos)
+#define SDHC_CA0R_MAXBLKL(value) (SDHC_CA0R_MAXBLKL_Msk & ((value) << SDHC_CA0R_MAXBLKL_Pos))
+#define SDHC_CA0R_MAXBLKL_512_Val _U_(0x0) /**< \brief (SDHC_CA0R) 512 bytes */
+#define SDHC_CA0R_MAXBLKL_1024_Val _U_(0x1) /**< \brief (SDHC_CA0R) 1024 bytes */
+#define SDHC_CA0R_MAXBLKL_2048_Val _U_(0x2) /**< \brief (SDHC_CA0R) 2048 bytes */
+#define SDHC_CA0R_MAXBLKL_512 (SDHC_CA0R_MAXBLKL_512_Val << SDHC_CA0R_MAXBLKL_Pos)
+#define SDHC_CA0R_MAXBLKL_1024 (SDHC_CA0R_MAXBLKL_1024_Val << SDHC_CA0R_MAXBLKL_Pos)
+#define SDHC_CA0R_MAXBLKL_2048 (SDHC_CA0R_MAXBLKL_2048_Val << SDHC_CA0R_MAXBLKL_Pos)
+#define SDHC_CA0R_ED8SUP_Pos 18 /**< \brief (SDHC_CA0R) 8-bit Support for Embedded Device */
+#define SDHC_CA0R_ED8SUP (_U_(0x1) << SDHC_CA0R_ED8SUP_Pos)
+#define SDHC_CA0R_ED8SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 8-bit Bus Width not Supported */
+#define SDHC_CA0R_ED8SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 8-bit Bus Width Supported */
+#define SDHC_CA0R_ED8SUP_NO (SDHC_CA0R_ED8SUP_NO_Val << SDHC_CA0R_ED8SUP_Pos)
+#define SDHC_CA0R_ED8SUP_YES (SDHC_CA0R_ED8SUP_YES_Val << SDHC_CA0R_ED8SUP_Pos)
+#define SDHC_CA0R_ADMA2SUP_Pos 19 /**< \brief (SDHC_CA0R) ADMA2 Support */
+#define SDHC_CA0R_ADMA2SUP (_U_(0x1) << SDHC_CA0R_ADMA2SUP_Pos)
+#define SDHC_CA0R_ADMA2SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) ADMA2 not Supported */
+#define SDHC_CA0R_ADMA2SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) ADMA2 Supported */
+#define SDHC_CA0R_ADMA2SUP_NO (SDHC_CA0R_ADMA2SUP_NO_Val << SDHC_CA0R_ADMA2SUP_Pos)
+#define SDHC_CA0R_ADMA2SUP_YES (SDHC_CA0R_ADMA2SUP_YES_Val << SDHC_CA0R_ADMA2SUP_Pos)
+#define SDHC_CA0R_HSSUP_Pos 21 /**< \brief (SDHC_CA0R) High Speed Support */
+#define SDHC_CA0R_HSSUP (_U_(0x1) << SDHC_CA0R_HSSUP_Pos)
+#define SDHC_CA0R_HSSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) High Speed not Supported */
+#define SDHC_CA0R_HSSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) High Speed Supported */
+#define SDHC_CA0R_HSSUP_NO (SDHC_CA0R_HSSUP_NO_Val << SDHC_CA0R_HSSUP_Pos)
+#define SDHC_CA0R_HSSUP_YES (SDHC_CA0R_HSSUP_YES_Val << SDHC_CA0R_HSSUP_Pos)
+#define SDHC_CA0R_SDMASUP_Pos 22 /**< \brief (SDHC_CA0R) SDMA Support */
+#define SDHC_CA0R_SDMASUP (_U_(0x1) << SDHC_CA0R_SDMASUP_Pos)
+#define SDHC_CA0R_SDMASUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) SDMA not Supported */
+#define SDHC_CA0R_SDMASUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) SDMA Supported */
+#define SDHC_CA0R_SDMASUP_NO (SDHC_CA0R_SDMASUP_NO_Val << SDHC_CA0R_SDMASUP_Pos)
+#define SDHC_CA0R_SDMASUP_YES (SDHC_CA0R_SDMASUP_YES_Val << SDHC_CA0R_SDMASUP_Pos)
+#define SDHC_CA0R_SRSUP_Pos 23 /**< \brief (SDHC_CA0R) Suspend/Resume Support */
+#define SDHC_CA0R_SRSUP (_U_(0x1) << SDHC_CA0R_SRSUP_Pos)
+#define SDHC_CA0R_SRSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) Suspend/Resume not Supported */
+#define SDHC_CA0R_SRSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) Suspend/Resume Supported */
+#define SDHC_CA0R_SRSUP_NO (SDHC_CA0R_SRSUP_NO_Val << SDHC_CA0R_SRSUP_Pos)
+#define SDHC_CA0R_SRSUP_YES (SDHC_CA0R_SRSUP_YES_Val << SDHC_CA0R_SRSUP_Pos)
+#define SDHC_CA0R_V33VSUP_Pos 24 /**< \brief (SDHC_CA0R) Voltage Support 3.3V */
+#define SDHC_CA0R_V33VSUP (_U_(0x1) << SDHC_CA0R_V33VSUP_Pos)
+#define SDHC_CA0R_V33VSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 3.3V Not Supported */
+#define SDHC_CA0R_V33VSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 3.3V Supported */
+#define SDHC_CA0R_V33VSUP_NO (SDHC_CA0R_V33VSUP_NO_Val << SDHC_CA0R_V33VSUP_Pos)
+#define SDHC_CA0R_V33VSUP_YES (SDHC_CA0R_V33VSUP_YES_Val << SDHC_CA0R_V33VSUP_Pos)
+#define SDHC_CA0R_V30VSUP_Pos 25 /**< \brief (SDHC_CA0R) Voltage Support 3.0V */
+#define SDHC_CA0R_V30VSUP (_U_(0x1) << SDHC_CA0R_V30VSUP_Pos)
+#define SDHC_CA0R_V30VSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 3.0V Not Supported */
+#define SDHC_CA0R_V30VSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 3.0V Supported */
+#define SDHC_CA0R_V30VSUP_NO (SDHC_CA0R_V30VSUP_NO_Val << SDHC_CA0R_V30VSUP_Pos)
+#define SDHC_CA0R_V30VSUP_YES (SDHC_CA0R_V30VSUP_YES_Val << SDHC_CA0R_V30VSUP_Pos)
+#define SDHC_CA0R_V18VSUP_Pos 26 /**< \brief (SDHC_CA0R) Voltage Support 1.8V */
+#define SDHC_CA0R_V18VSUP (_U_(0x1) << SDHC_CA0R_V18VSUP_Pos)
+#define SDHC_CA0R_V18VSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 1.8V Not Supported */
+#define SDHC_CA0R_V18VSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 1.8V Supported */
+#define SDHC_CA0R_V18VSUP_NO (SDHC_CA0R_V18VSUP_NO_Val << SDHC_CA0R_V18VSUP_Pos)
+#define SDHC_CA0R_V18VSUP_YES (SDHC_CA0R_V18VSUP_YES_Val << SDHC_CA0R_V18VSUP_Pos)
+#define SDHC_CA0R_SB64SUP_Pos 28 /**< \brief (SDHC_CA0R) 64-Bit System Bus Support */
+#define SDHC_CA0R_SB64SUP (_U_(0x1) << SDHC_CA0R_SB64SUP_Pos)
+#define SDHC_CA0R_SB64SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 32-bit Address Descriptors and System Bus */
+#define SDHC_CA0R_SB64SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 64-bit Address Descriptors and System Bus */
+#define SDHC_CA0R_SB64SUP_NO (SDHC_CA0R_SB64SUP_NO_Val << SDHC_CA0R_SB64SUP_Pos)
+#define SDHC_CA0R_SB64SUP_YES (SDHC_CA0R_SB64SUP_YES_Val << SDHC_CA0R_SB64SUP_Pos)
+#define SDHC_CA0R_ASINTSUP_Pos 29 /**< \brief (SDHC_CA0R) Asynchronous Interrupt Support */
+#define SDHC_CA0R_ASINTSUP (_U_(0x1) << SDHC_CA0R_ASINTSUP_Pos)
+#define SDHC_CA0R_ASINTSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) Asynchronous Interrupt not Supported */
+#define SDHC_CA0R_ASINTSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) Asynchronous Interrupt supported */
+#define SDHC_CA0R_ASINTSUP_NO (SDHC_CA0R_ASINTSUP_NO_Val << SDHC_CA0R_ASINTSUP_Pos)
+#define SDHC_CA0R_ASINTSUP_YES (SDHC_CA0R_ASINTSUP_YES_Val << SDHC_CA0R_ASINTSUP_Pos)
+#define SDHC_CA0R_SLTYPE_Pos 30 /**< \brief (SDHC_CA0R) Slot Type */
+#define SDHC_CA0R_SLTYPE_Msk (_U_(0x3) << SDHC_CA0R_SLTYPE_Pos)
+#define SDHC_CA0R_SLTYPE(value) (SDHC_CA0R_SLTYPE_Msk & ((value) << SDHC_CA0R_SLTYPE_Pos))
+#define SDHC_CA0R_SLTYPE_REMOVABLE_Val _U_(0x0) /**< \brief (SDHC_CA0R) Removable Card Slot */
+#define SDHC_CA0R_SLTYPE_EMBEDDED_Val _U_(0x1) /**< \brief (SDHC_CA0R) Embedded Slot for One Device */
+#define SDHC_CA0R_SLTYPE_REMOVABLE (SDHC_CA0R_SLTYPE_REMOVABLE_Val << SDHC_CA0R_SLTYPE_Pos)
+#define SDHC_CA0R_SLTYPE_EMBEDDED (SDHC_CA0R_SLTYPE_EMBEDDED_Val << SDHC_CA0R_SLTYPE_Pos)
+#define SDHC_CA0R_MASK _U_(0xF7EFFFBF) /**< \brief (SDHC_CA0R) MASK Register */
+
+/* -------- SDHC_CA1R : (SDHC Offset: 0x044) (R/ 32) Capabilities 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SDR50SUP:1; /*!< bit: 0 SDR50 Support */
+ uint32_t SDR104SUP:1; /*!< bit: 1 SDR104 Support */
+ uint32_t DDR50SUP:1; /*!< bit: 2 DDR50 Support */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t DRVASUP:1; /*!< bit: 4 Driver Type A Support */
+ uint32_t DRVCSUP:1; /*!< bit: 5 Driver Type C Support */
+ uint32_t DRVDSUP:1; /*!< bit: 6 Driver Type D Support */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t TCNTRT:4; /*!< bit: 8..11 Timer Count for Re-Tuning */
+ uint32_t :1; /*!< bit: 12 Reserved */
+ uint32_t TSDR50:1; /*!< bit: 13 Use Tuning for SDR50 */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t CLKMULT:8; /*!< bit: 16..23 Clock Multiplier */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_CA1R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_CA1R_OFFSET 0x044 /**< \brief (SDHC_CA1R offset) Capabilities 1 */
+#define SDHC_CA1R_RESETVALUE _U_(0x00000070) /**< \brief (SDHC_CA1R reset_value) Capabilities 1 */
+
+#define SDHC_CA1R_SDR50SUP_Pos 0 /**< \brief (SDHC_CA1R) SDR50 Support */
+#define SDHC_CA1R_SDR50SUP (_U_(0x1) << SDHC_CA1R_SDR50SUP_Pos)
+#define SDHC_CA1R_SDR50SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) SDR50 is Not Supported */
+#define SDHC_CA1R_SDR50SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) SDR50 is Supported */
+#define SDHC_CA1R_SDR50SUP_NO (SDHC_CA1R_SDR50SUP_NO_Val << SDHC_CA1R_SDR50SUP_Pos)
+#define SDHC_CA1R_SDR50SUP_YES (SDHC_CA1R_SDR50SUP_YES_Val << SDHC_CA1R_SDR50SUP_Pos)
+#define SDHC_CA1R_SDR104SUP_Pos 1 /**< \brief (SDHC_CA1R) SDR104 Support */
+#define SDHC_CA1R_SDR104SUP (_U_(0x1) << SDHC_CA1R_SDR104SUP_Pos)
+#define SDHC_CA1R_SDR104SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) SDR104 is Not Supported */
+#define SDHC_CA1R_SDR104SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) SDR104 is Supported */
+#define SDHC_CA1R_SDR104SUP_NO (SDHC_CA1R_SDR104SUP_NO_Val << SDHC_CA1R_SDR104SUP_Pos)
+#define SDHC_CA1R_SDR104SUP_YES (SDHC_CA1R_SDR104SUP_YES_Val << SDHC_CA1R_SDR104SUP_Pos)
+#define SDHC_CA1R_DDR50SUP_Pos 2 /**< \brief (SDHC_CA1R) DDR50 Support */
+#define SDHC_CA1R_DDR50SUP (_U_(0x1) << SDHC_CA1R_DDR50SUP_Pos)
+#define SDHC_CA1R_DDR50SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) DDR50 is Not Supported */
+#define SDHC_CA1R_DDR50SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) DDR50 is Supported */
+#define SDHC_CA1R_DDR50SUP_NO (SDHC_CA1R_DDR50SUP_NO_Val << SDHC_CA1R_DDR50SUP_Pos)
+#define SDHC_CA1R_DDR50SUP_YES (SDHC_CA1R_DDR50SUP_YES_Val << SDHC_CA1R_DDR50SUP_Pos)
+#define SDHC_CA1R_DRVASUP_Pos 4 /**< \brief (SDHC_CA1R) Driver Type A Support */
+#define SDHC_CA1R_DRVASUP (_U_(0x1) << SDHC_CA1R_DRVASUP_Pos)
+#define SDHC_CA1R_DRVASUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) Driver Type A is Not Supported */
+#define SDHC_CA1R_DRVASUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) Driver Type A is Supported */
+#define SDHC_CA1R_DRVASUP_NO (SDHC_CA1R_DRVASUP_NO_Val << SDHC_CA1R_DRVASUP_Pos)
+#define SDHC_CA1R_DRVASUP_YES (SDHC_CA1R_DRVASUP_YES_Val << SDHC_CA1R_DRVASUP_Pos)
+#define SDHC_CA1R_DRVCSUP_Pos 5 /**< \brief (SDHC_CA1R) Driver Type C Support */
+#define SDHC_CA1R_DRVCSUP (_U_(0x1) << SDHC_CA1R_DRVCSUP_Pos)
+#define SDHC_CA1R_DRVCSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) Driver Type C is Not Supported */
+#define SDHC_CA1R_DRVCSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) Driver Type C is Supported */
+#define SDHC_CA1R_DRVCSUP_NO (SDHC_CA1R_DRVCSUP_NO_Val << SDHC_CA1R_DRVCSUP_Pos)
+#define SDHC_CA1R_DRVCSUP_YES (SDHC_CA1R_DRVCSUP_YES_Val << SDHC_CA1R_DRVCSUP_Pos)
+#define SDHC_CA1R_DRVDSUP_Pos 6 /**< \brief (SDHC_CA1R) Driver Type D Support */
+#define SDHC_CA1R_DRVDSUP (_U_(0x1) << SDHC_CA1R_DRVDSUP_Pos)
+#define SDHC_CA1R_DRVDSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) Driver Type D is Not Supported */
+#define SDHC_CA1R_DRVDSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) Driver Type D is Supported */
+#define SDHC_CA1R_DRVDSUP_NO (SDHC_CA1R_DRVDSUP_NO_Val << SDHC_CA1R_DRVDSUP_Pos)
+#define SDHC_CA1R_DRVDSUP_YES (SDHC_CA1R_DRVDSUP_YES_Val << SDHC_CA1R_DRVDSUP_Pos)
+#define SDHC_CA1R_TCNTRT_Pos 8 /**< \brief (SDHC_CA1R) Timer Count for Re-Tuning */
+#define SDHC_CA1R_TCNTRT_Msk (_U_(0xF) << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT(value) (SDHC_CA1R_TCNTRT_Msk & ((value) << SDHC_CA1R_TCNTRT_Pos))
+#define SDHC_CA1R_TCNTRT_DISABLED_Val _U_(0x0) /**< \brief (SDHC_CA1R) Re-Tuning Timer disabled */
+#define SDHC_CA1R_TCNTRT_1S_Val _U_(0x1) /**< \brief (SDHC_CA1R) 1 second */
+#define SDHC_CA1R_TCNTRT_2S_Val _U_(0x2) /**< \brief (SDHC_CA1R) 2 seconds */
+#define SDHC_CA1R_TCNTRT_4S_Val _U_(0x3) /**< \brief (SDHC_CA1R) 4 seconds */
+#define SDHC_CA1R_TCNTRT_8S_Val _U_(0x4) /**< \brief (SDHC_CA1R) 8 seconds */
+#define SDHC_CA1R_TCNTRT_16S_Val _U_(0x5) /**< \brief (SDHC_CA1R) 16 seconds */
+#define SDHC_CA1R_TCNTRT_32S_Val _U_(0x6) /**< \brief (SDHC_CA1R) 32 seconds */
+#define SDHC_CA1R_TCNTRT_64S_Val _U_(0x7) /**< \brief (SDHC_CA1R) 64 seconds */
+#define SDHC_CA1R_TCNTRT_128S_Val _U_(0x8) /**< \brief (SDHC_CA1R) 128 seconds */
+#define SDHC_CA1R_TCNTRT_256S_Val _U_(0x9) /**< \brief (SDHC_CA1R) 256 seconds */
+#define SDHC_CA1R_TCNTRT_512S_Val _U_(0xA) /**< \brief (SDHC_CA1R) 512 seconds */
+#define SDHC_CA1R_TCNTRT_1024S_Val _U_(0xB) /**< \brief (SDHC_CA1R) 1024 seconds */
+#define SDHC_CA1R_TCNTRT_OTHER_Val _U_(0xF) /**< \brief (SDHC_CA1R) Get information from other source */
+#define SDHC_CA1R_TCNTRT_DISABLED (SDHC_CA1R_TCNTRT_DISABLED_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_1S (SDHC_CA1R_TCNTRT_1S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_2S (SDHC_CA1R_TCNTRT_2S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_4S (SDHC_CA1R_TCNTRT_4S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_8S (SDHC_CA1R_TCNTRT_8S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_16S (SDHC_CA1R_TCNTRT_16S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_32S (SDHC_CA1R_TCNTRT_32S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_64S (SDHC_CA1R_TCNTRT_64S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_128S (SDHC_CA1R_TCNTRT_128S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_256S (SDHC_CA1R_TCNTRT_256S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_512S (SDHC_CA1R_TCNTRT_512S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_1024S (SDHC_CA1R_TCNTRT_1024S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_OTHER (SDHC_CA1R_TCNTRT_OTHER_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TSDR50_Pos 13 /**< \brief (SDHC_CA1R) Use Tuning for SDR50 */
+#define SDHC_CA1R_TSDR50 (_U_(0x1) << SDHC_CA1R_TSDR50_Pos)
+#define SDHC_CA1R_TSDR50_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) SDR50 does not require tuning */
+#define SDHC_CA1R_TSDR50_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) SDR50 requires tuning */
+#define SDHC_CA1R_TSDR50_NO (SDHC_CA1R_TSDR50_NO_Val << SDHC_CA1R_TSDR50_Pos)
+#define SDHC_CA1R_TSDR50_YES (SDHC_CA1R_TSDR50_YES_Val << SDHC_CA1R_TSDR50_Pos)
+#define SDHC_CA1R_CLKMULT_Pos 16 /**< \brief (SDHC_CA1R) Clock Multiplier */
+#define SDHC_CA1R_CLKMULT_Msk (_U_(0xFF) << SDHC_CA1R_CLKMULT_Pos)
+#define SDHC_CA1R_CLKMULT(value) (SDHC_CA1R_CLKMULT_Msk & ((value) << SDHC_CA1R_CLKMULT_Pos))
+#define SDHC_CA1R_CLKMULT_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) Clock Multiplier is Not Supported */
+#define SDHC_CA1R_CLKMULT_NO (SDHC_CA1R_CLKMULT_NO_Val << SDHC_CA1R_CLKMULT_Pos)
+#define SDHC_CA1R_MASK _U_(0x00FF2F77) /**< \brief (SDHC_CA1R) MASK Register */
+
+/* -------- SDHC_MCCAR : (SDHC Offset: 0x048) (R/ 32) Maximum Current Capabilities -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MAXCUR33V:8; /*!< bit: 0.. 7 Maximum Current for 3.3V */
+ uint32_t MAXCUR30V:8; /*!< bit: 8..15 Maximum Current for 3.0V */
+ uint32_t MAXCUR18V:8; /*!< bit: 16..23 Maximum Current for 1.8V */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_MCCAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_MCCAR_OFFSET 0x048 /**< \brief (SDHC_MCCAR offset) Maximum Current Capabilities */
+#define SDHC_MCCAR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_MCCAR reset_value) Maximum Current Capabilities */
+
+#define SDHC_MCCAR_MAXCUR33V_Pos 0 /**< \brief (SDHC_MCCAR) Maximum Current for 3.3V */
+#define SDHC_MCCAR_MAXCUR33V_Msk (_U_(0xFF) << SDHC_MCCAR_MAXCUR33V_Pos)
+#define SDHC_MCCAR_MAXCUR33V(value) (SDHC_MCCAR_MAXCUR33V_Msk & ((value) << SDHC_MCCAR_MAXCUR33V_Pos))
+#define SDHC_MCCAR_MAXCUR33V_OTHER_Val _U_(0x0) /**< \brief (SDHC_MCCAR) Get information via another method */
+#define SDHC_MCCAR_MAXCUR33V_4MA_Val _U_(0x1) /**< \brief (SDHC_MCCAR) 4mA */
+#define SDHC_MCCAR_MAXCUR33V_8MA_Val _U_(0x2) /**< \brief (SDHC_MCCAR) 8mA */
+#define SDHC_MCCAR_MAXCUR33V_12MA_Val _U_(0x3) /**< \brief (SDHC_MCCAR) 12mA */
+#define SDHC_MCCAR_MAXCUR33V_OTHER (SDHC_MCCAR_MAXCUR33V_OTHER_Val << SDHC_MCCAR_MAXCUR33V_Pos)
+#define SDHC_MCCAR_MAXCUR33V_4MA (SDHC_MCCAR_MAXCUR33V_4MA_Val << SDHC_MCCAR_MAXCUR33V_Pos)
+#define SDHC_MCCAR_MAXCUR33V_8MA (SDHC_MCCAR_MAXCUR33V_8MA_Val << SDHC_MCCAR_MAXCUR33V_Pos)
+#define SDHC_MCCAR_MAXCUR33V_12MA (SDHC_MCCAR_MAXCUR33V_12MA_Val << SDHC_MCCAR_MAXCUR33V_Pos)
+#define SDHC_MCCAR_MAXCUR30V_Pos 8 /**< \brief (SDHC_MCCAR) Maximum Current for 3.0V */
+#define SDHC_MCCAR_MAXCUR30V_Msk (_U_(0xFF) << SDHC_MCCAR_MAXCUR30V_Pos)
+#define SDHC_MCCAR_MAXCUR30V(value) (SDHC_MCCAR_MAXCUR30V_Msk & ((value) << SDHC_MCCAR_MAXCUR30V_Pos))
+#define SDHC_MCCAR_MAXCUR30V_OTHER_Val _U_(0x0) /**< \brief (SDHC_MCCAR) Get information via another method */
+#define SDHC_MCCAR_MAXCUR30V_4MA_Val _U_(0x1) /**< \brief (SDHC_MCCAR) 4mA */
+#define SDHC_MCCAR_MAXCUR30V_8MA_Val _U_(0x2) /**< \brief (SDHC_MCCAR) 8mA */
+#define SDHC_MCCAR_MAXCUR30V_12MA_Val _U_(0x3) /**< \brief (SDHC_MCCAR) 12mA */
+#define SDHC_MCCAR_MAXCUR30V_OTHER (SDHC_MCCAR_MAXCUR30V_OTHER_Val << SDHC_MCCAR_MAXCUR30V_Pos)
+#define SDHC_MCCAR_MAXCUR30V_4MA (SDHC_MCCAR_MAXCUR30V_4MA_Val << SDHC_MCCAR_MAXCUR30V_Pos)
+#define SDHC_MCCAR_MAXCUR30V_8MA (SDHC_MCCAR_MAXCUR30V_8MA_Val << SDHC_MCCAR_MAXCUR30V_Pos)
+#define SDHC_MCCAR_MAXCUR30V_12MA (SDHC_MCCAR_MAXCUR30V_12MA_Val << SDHC_MCCAR_MAXCUR30V_Pos)
+#define SDHC_MCCAR_MAXCUR18V_Pos 16 /**< \brief (SDHC_MCCAR) Maximum Current for 1.8V */
+#define SDHC_MCCAR_MAXCUR18V_Msk (_U_(0xFF) << SDHC_MCCAR_MAXCUR18V_Pos)
+#define SDHC_MCCAR_MAXCUR18V(value) (SDHC_MCCAR_MAXCUR18V_Msk & ((value) << SDHC_MCCAR_MAXCUR18V_Pos))
+#define SDHC_MCCAR_MAXCUR18V_OTHER_Val _U_(0x0) /**< \brief (SDHC_MCCAR) Get information via another method */
+#define SDHC_MCCAR_MAXCUR18V_4MA_Val _U_(0x1) /**< \brief (SDHC_MCCAR) 4mA */
+#define SDHC_MCCAR_MAXCUR18V_8MA_Val _U_(0x2) /**< \brief (SDHC_MCCAR) 8mA */
+#define SDHC_MCCAR_MAXCUR18V_12MA_Val _U_(0x3) /**< \brief (SDHC_MCCAR) 12mA */
+#define SDHC_MCCAR_MAXCUR18V_OTHER (SDHC_MCCAR_MAXCUR18V_OTHER_Val << SDHC_MCCAR_MAXCUR18V_Pos)
+#define SDHC_MCCAR_MAXCUR18V_4MA (SDHC_MCCAR_MAXCUR18V_4MA_Val << SDHC_MCCAR_MAXCUR18V_Pos)
+#define SDHC_MCCAR_MAXCUR18V_8MA (SDHC_MCCAR_MAXCUR18V_8MA_Val << SDHC_MCCAR_MAXCUR18V_Pos)
+#define SDHC_MCCAR_MAXCUR18V_12MA (SDHC_MCCAR_MAXCUR18V_12MA_Val << SDHC_MCCAR_MAXCUR18V_Pos)
+#define SDHC_MCCAR_MASK _U_(0x00FFFFFF) /**< \brief (SDHC_MCCAR) MASK Register */
+
+/* -------- SDHC_FERACES : (SDHC Offset: 0x050) ( /W 16) Force Event for Auto CMD Error Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ACMD12NE:1; /*!< bit: 0 Force Event for Auto CMD12 Not Executed */
+ uint16_t ACMDTEO:1; /*!< bit: 1 Force Event for Auto CMD Timeout Error */
+ uint16_t ACMDCRC:1; /*!< bit: 2 Force Event for Auto CMD CRC Error */
+ uint16_t ACMDEND:1; /*!< bit: 3 Force Event for Auto CMD End Bit Error */
+ uint16_t ACMDIDX:1; /*!< bit: 4 Force Event for Auto CMD Index Error */
+ uint16_t :2; /*!< bit: 5.. 6 Reserved */
+ uint16_t CMDNI:1; /*!< bit: 7 Force Event for Command Not Issued By Auto CMD12 Error */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_FERACES_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_FERACES_OFFSET 0x050 /**< \brief (SDHC_FERACES offset) Force Event for Auto CMD Error Status */
+#define SDHC_FERACES_RESETVALUE _U_(0x0000) /**< \brief (SDHC_FERACES reset_value) Force Event for Auto CMD Error Status */
+
+#define SDHC_FERACES_ACMD12NE_Pos 0 /**< \brief (SDHC_FERACES) Force Event for Auto CMD12 Not Executed */
+#define SDHC_FERACES_ACMD12NE (_U_(0x1) << SDHC_FERACES_ACMD12NE_Pos)
+#define SDHC_FERACES_ACMD12NE_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */
+#define SDHC_FERACES_ACMD12NE_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */
+#define SDHC_FERACES_ACMD12NE_NO (SDHC_FERACES_ACMD12NE_NO_Val << SDHC_FERACES_ACMD12NE_Pos)
+#define SDHC_FERACES_ACMD12NE_YES (SDHC_FERACES_ACMD12NE_YES_Val << SDHC_FERACES_ACMD12NE_Pos)
+#define SDHC_FERACES_ACMDTEO_Pos 1 /**< \brief (SDHC_FERACES) Force Event for Auto CMD Timeout Error */
+#define SDHC_FERACES_ACMDTEO (_U_(0x1) << SDHC_FERACES_ACMDTEO_Pos)
+#define SDHC_FERACES_ACMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */
+#define SDHC_FERACES_ACMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */
+#define SDHC_FERACES_ACMDTEO_NO (SDHC_FERACES_ACMDTEO_NO_Val << SDHC_FERACES_ACMDTEO_Pos)
+#define SDHC_FERACES_ACMDTEO_YES (SDHC_FERACES_ACMDTEO_YES_Val << SDHC_FERACES_ACMDTEO_Pos)
+#define SDHC_FERACES_ACMDCRC_Pos 2 /**< \brief (SDHC_FERACES) Force Event for Auto CMD CRC Error */
+#define SDHC_FERACES_ACMDCRC (_U_(0x1) << SDHC_FERACES_ACMDCRC_Pos)
+#define SDHC_FERACES_ACMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */
+#define SDHC_FERACES_ACMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */
+#define SDHC_FERACES_ACMDCRC_NO (SDHC_FERACES_ACMDCRC_NO_Val << SDHC_FERACES_ACMDCRC_Pos)
+#define SDHC_FERACES_ACMDCRC_YES (SDHC_FERACES_ACMDCRC_YES_Val << SDHC_FERACES_ACMDCRC_Pos)
+#define SDHC_FERACES_ACMDEND_Pos 3 /**< \brief (SDHC_FERACES) Force Event for Auto CMD End Bit Error */
+#define SDHC_FERACES_ACMDEND (_U_(0x1) << SDHC_FERACES_ACMDEND_Pos)
+#define SDHC_FERACES_ACMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */
+#define SDHC_FERACES_ACMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */
+#define SDHC_FERACES_ACMDEND_NO (SDHC_FERACES_ACMDEND_NO_Val << SDHC_FERACES_ACMDEND_Pos)
+#define SDHC_FERACES_ACMDEND_YES (SDHC_FERACES_ACMDEND_YES_Val << SDHC_FERACES_ACMDEND_Pos)
+#define SDHC_FERACES_ACMDIDX_Pos 4 /**< \brief (SDHC_FERACES) Force Event for Auto CMD Index Error */
+#define SDHC_FERACES_ACMDIDX (_U_(0x1) << SDHC_FERACES_ACMDIDX_Pos)
+#define SDHC_FERACES_ACMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */
+#define SDHC_FERACES_ACMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */
+#define SDHC_FERACES_ACMDIDX_NO (SDHC_FERACES_ACMDIDX_NO_Val << SDHC_FERACES_ACMDIDX_Pos)
+#define SDHC_FERACES_ACMDIDX_YES (SDHC_FERACES_ACMDIDX_YES_Val << SDHC_FERACES_ACMDIDX_Pos)
+#define SDHC_FERACES_CMDNI_Pos 7 /**< \brief (SDHC_FERACES) Force Event for Command Not Issued By Auto CMD12 Error */
+#define SDHC_FERACES_CMDNI (_U_(0x1) << SDHC_FERACES_CMDNI_Pos)
+#define SDHC_FERACES_CMDNI_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */
+#define SDHC_FERACES_CMDNI_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */
+#define SDHC_FERACES_CMDNI_NO (SDHC_FERACES_CMDNI_NO_Val << SDHC_FERACES_CMDNI_Pos)
+#define SDHC_FERACES_CMDNI_YES (SDHC_FERACES_CMDNI_YES_Val << SDHC_FERACES_CMDNI_Pos)
+#define SDHC_FERACES_MASK _U_(0x009F) /**< \brief (SDHC_FERACES) MASK Register */
+
+/* -------- SDHC_FEREIS : (SDHC Offset: 0x052) ( /W 16) Force Event for Error Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CMDTEO:1; /*!< bit: 0 Force Event for Command Timeout Error */
+ uint16_t CMDCRC:1; /*!< bit: 1 Force Event for Command CRC Error */
+ uint16_t CMDEND:1; /*!< bit: 2 Force Event for Command End Bit Error */
+ uint16_t CMDIDX:1; /*!< bit: 3 Force Event for Command Index Error */
+ uint16_t DATTEO:1; /*!< bit: 4 Force Event for Data Timeout Error */
+ uint16_t DATCRC:1; /*!< bit: 5 Force Event for Data CRC Error */
+ uint16_t DATEND:1; /*!< bit: 6 Force Event for Data End Bit Error */
+ uint16_t CURLIM:1; /*!< bit: 7 Force Event for Current Limit Error */
+ uint16_t ACMD:1; /*!< bit: 8 Force Event for Auto CMD Error */
+ uint16_t ADMA:1; /*!< bit: 9 Force Event for ADMA Error */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t BOOTAE:1; /*!< bit: 12 Force Event for Boot Acknowledge Error */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_FEREIS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_FEREIS_OFFSET 0x052 /**< \brief (SDHC_FEREIS offset) Force Event for Error Interrupt Status */
+#define SDHC_FEREIS_RESETVALUE _U_(0x0000) /**< \brief (SDHC_FEREIS reset_value) Force Event for Error Interrupt Status */
+
+#define SDHC_FEREIS_CMDTEO_Pos 0 /**< \brief (SDHC_FEREIS) Force Event for Command Timeout Error */
+#define SDHC_FEREIS_CMDTEO (_U_(0x1) << SDHC_FEREIS_CMDTEO_Pos)
+#define SDHC_FEREIS_CMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_CMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_CMDTEO_NO (SDHC_FEREIS_CMDTEO_NO_Val << SDHC_FEREIS_CMDTEO_Pos)
+#define SDHC_FEREIS_CMDTEO_YES (SDHC_FEREIS_CMDTEO_YES_Val << SDHC_FEREIS_CMDTEO_Pos)
+#define SDHC_FEREIS_CMDCRC_Pos 1 /**< \brief (SDHC_FEREIS) Force Event for Command CRC Error */
+#define SDHC_FEREIS_CMDCRC (_U_(0x1) << SDHC_FEREIS_CMDCRC_Pos)
+#define SDHC_FEREIS_CMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_CMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_CMDCRC_NO (SDHC_FEREIS_CMDCRC_NO_Val << SDHC_FEREIS_CMDCRC_Pos)
+#define SDHC_FEREIS_CMDCRC_YES (SDHC_FEREIS_CMDCRC_YES_Val << SDHC_FEREIS_CMDCRC_Pos)
+#define SDHC_FEREIS_CMDEND_Pos 2 /**< \brief (SDHC_FEREIS) Force Event for Command End Bit Error */
+#define SDHC_FEREIS_CMDEND (_U_(0x1) << SDHC_FEREIS_CMDEND_Pos)
+#define SDHC_FEREIS_CMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_CMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_CMDEND_NO (SDHC_FEREIS_CMDEND_NO_Val << SDHC_FEREIS_CMDEND_Pos)
+#define SDHC_FEREIS_CMDEND_YES (SDHC_FEREIS_CMDEND_YES_Val << SDHC_FEREIS_CMDEND_Pos)
+#define SDHC_FEREIS_CMDIDX_Pos 3 /**< \brief (SDHC_FEREIS) Force Event for Command Index Error */
+#define SDHC_FEREIS_CMDIDX (_U_(0x1) << SDHC_FEREIS_CMDIDX_Pos)
+#define SDHC_FEREIS_CMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_CMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_CMDIDX_NO (SDHC_FEREIS_CMDIDX_NO_Val << SDHC_FEREIS_CMDIDX_Pos)
+#define SDHC_FEREIS_CMDIDX_YES (SDHC_FEREIS_CMDIDX_YES_Val << SDHC_FEREIS_CMDIDX_Pos)
+#define SDHC_FEREIS_DATTEO_Pos 4 /**< \brief (SDHC_FEREIS) Force Event for Data Timeout Error */
+#define SDHC_FEREIS_DATTEO (_U_(0x1) << SDHC_FEREIS_DATTEO_Pos)
+#define SDHC_FEREIS_DATTEO_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_DATTEO_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_DATTEO_NO (SDHC_FEREIS_DATTEO_NO_Val << SDHC_FEREIS_DATTEO_Pos)
+#define SDHC_FEREIS_DATTEO_YES (SDHC_FEREIS_DATTEO_YES_Val << SDHC_FEREIS_DATTEO_Pos)
+#define SDHC_FEREIS_DATCRC_Pos 5 /**< \brief (SDHC_FEREIS) Force Event for Data CRC Error */
+#define SDHC_FEREIS_DATCRC (_U_(0x1) << SDHC_FEREIS_DATCRC_Pos)
+#define SDHC_FEREIS_DATCRC_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_DATCRC_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_DATCRC_NO (SDHC_FEREIS_DATCRC_NO_Val << SDHC_FEREIS_DATCRC_Pos)
+#define SDHC_FEREIS_DATCRC_YES (SDHC_FEREIS_DATCRC_YES_Val << SDHC_FEREIS_DATCRC_Pos)
+#define SDHC_FEREIS_DATEND_Pos 6 /**< \brief (SDHC_FEREIS) Force Event for Data End Bit Error */
+#define SDHC_FEREIS_DATEND (_U_(0x1) << SDHC_FEREIS_DATEND_Pos)
+#define SDHC_FEREIS_DATEND_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_DATEND_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_DATEND_NO (SDHC_FEREIS_DATEND_NO_Val << SDHC_FEREIS_DATEND_Pos)
+#define SDHC_FEREIS_DATEND_YES (SDHC_FEREIS_DATEND_YES_Val << SDHC_FEREIS_DATEND_Pos)
+#define SDHC_FEREIS_CURLIM_Pos 7 /**< \brief (SDHC_FEREIS) Force Event for Current Limit Error */
+#define SDHC_FEREIS_CURLIM (_U_(0x1) << SDHC_FEREIS_CURLIM_Pos)
+#define SDHC_FEREIS_CURLIM_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_CURLIM_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_CURLIM_NO (SDHC_FEREIS_CURLIM_NO_Val << SDHC_FEREIS_CURLIM_Pos)
+#define SDHC_FEREIS_CURLIM_YES (SDHC_FEREIS_CURLIM_YES_Val << SDHC_FEREIS_CURLIM_Pos)
+#define SDHC_FEREIS_ACMD_Pos 8 /**< \brief (SDHC_FEREIS) Force Event for Auto CMD Error */
+#define SDHC_FEREIS_ACMD (_U_(0x1) << SDHC_FEREIS_ACMD_Pos)
+#define SDHC_FEREIS_ACMD_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_ACMD_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_ACMD_NO (SDHC_FEREIS_ACMD_NO_Val << SDHC_FEREIS_ACMD_Pos)
+#define SDHC_FEREIS_ACMD_YES (SDHC_FEREIS_ACMD_YES_Val << SDHC_FEREIS_ACMD_Pos)
+#define SDHC_FEREIS_ADMA_Pos 9 /**< \brief (SDHC_FEREIS) Force Event for ADMA Error */
+#define SDHC_FEREIS_ADMA (_U_(0x1) << SDHC_FEREIS_ADMA_Pos)
+#define SDHC_FEREIS_ADMA_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_ADMA_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_ADMA_NO (SDHC_FEREIS_ADMA_NO_Val << SDHC_FEREIS_ADMA_Pos)
+#define SDHC_FEREIS_ADMA_YES (SDHC_FEREIS_ADMA_YES_Val << SDHC_FEREIS_ADMA_Pos)
+#define SDHC_FEREIS_BOOTAE_Pos 12 /**< \brief (SDHC_FEREIS) Force Event for Boot Acknowledge Error */
+#define SDHC_FEREIS_BOOTAE (_U_(0x1) << SDHC_FEREIS_BOOTAE_Pos)
+#define SDHC_FEREIS_BOOTAE_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_BOOTAE_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_BOOTAE_NO (SDHC_FEREIS_BOOTAE_NO_Val << SDHC_FEREIS_BOOTAE_Pos)
+#define SDHC_FEREIS_BOOTAE_YES (SDHC_FEREIS_BOOTAE_YES_Val << SDHC_FEREIS_BOOTAE_Pos)
+#define SDHC_FEREIS_MASK _U_(0x13FF) /**< \brief (SDHC_FEREIS) MASK Register */
+
+/* -------- SDHC_AESR : (SDHC Offset: 0x054) (R/ 8) ADMA Error Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ERRST:2; /*!< bit: 0.. 1 ADMA Error State */
+ uint8_t LMIS:1; /*!< bit: 2 ADMA Length Mismatch Error */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_AESR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_AESR_OFFSET 0x054 /**< \brief (SDHC_AESR offset) ADMA Error Status */
+#define SDHC_AESR_RESETVALUE _U_(0x00) /**< \brief (SDHC_AESR reset_value) ADMA Error Status */
+
+#define SDHC_AESR_ERRST_Pos 0 /**< \brief (SDHC_AESR) ADMA Error State */
+#define SDHC_AESR_ERRST_Msk (_U_(0x3) << SDHC_AESR_ERRST_Pos)
+#define SDHC_AESR_ERRST(value) (SDHC_AESR_ERRST_Msk & ((value) << SDHC_AESR_ERRST_Pos))
+#define SDHC_AESR_ERRST_STOP_Val _U_(0x0) /**< \brief (SDHC_AESR) ST_STOP (Stop DMA) */
+#define SDHC_AESR_ERRST_FDS_Val _U_(0x1) /**< \brief (SDHC_AESR) ST_FDS (Fetch Descriptor) */
+#define SDHC_AESR_ERRST_2_Val _U_(0x2) /**< \brief (SDHC_AESR) Reserved */
+#define SDHC_AESR_ERRST_TFR_Val _U_(0x3) /**< \brief (SDHC_AESR) ST_TFR (Transfer Data) */
+#define SDHC_AESR_ERRST_STOP (SDHC_AESR_ERRST_STOP_Val << SDHC_AESR_ERRST_Pos)
+#define SDHC_AESR_ERRST_FDS (SDHC_AESR_ERRST_FDS_Val << SDHC_AESR_ERRST_Pos)
+#define SDHC_AESR_ERRST_2 (SDHC_AESR_ERRST_2_Val << SDHC_AESR_ERRST_Pos)
+#define SDHC_AESR_ERRST_TFR (SDHC_AESR_ERRST_TFR_Val << SDHC_AESR_ERRST_Pos)
+#define SDHC_AESR_LMIS_Pos 2 /**< \brief (SDHC_AESR) ADMA Length Mismatch Error */
+#define SDHC_AESR_LMIS (_U_(0x1) << SDHC_AESR_LMIS_Pos)
+#define SDHC_AESR_LMIS_NO_Val _U_(0x0) /**< \brief (SDHC_AESR) No Error */
+#define SDHC_AESR_LMIS_YES_Val _U_(0x1) /**< \brief (SDHC_AESR) Error */
+#define SDHC_AESR_LMIS_NO (SDHC_AESR_LMIS_NO_Val << SDHC_AESR_LMIS_Pos)
+#define SDHC_AESR_LMIS_YES (SDHC_AESR_LMIS_YES_Val << SDHC_AESR_LMIS_Pos)
+#define SDHC_AESR_MASK _U_(0x07) /**< \brief (SDHC_AESR) MASK Register */
+
+/* -------- SDHC_ASAR : (SDHC Offset: 0x058) (R/W 32) ADMA System Address n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADMASA:32; /*!< bit: 0..31 ADMA System Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_ASAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_ASAR_OFFSET 0x058 /**< \brief (SDHC_ASAR offset) ADMA System Address n */
+#define SDHC_ASAR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_ASAR reset_value) ADMA System Address n */
+
+#define SDHC_ASAR_ADMASA_Pos 0 /**< \brief (SDHC_ASAR) ADMA System Address */
+#define SDHC_ASAR_ADMASA_Msk (_U_(0xFFFFFFFF) << SDHC_ASAR_ADMASA_Pos)
+#define SDHC_ASAR_ADMASA(value) (SDHC_ASAR_ADMASA_Msk & ((value) << SDHC_ASAR_ADMASA_Pos))
+#define SDHC_ASAR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_ASAR) MASK Register */
+
+/* -------- SDHC_PVR : (SDHC Offset: 0x060) (R/W 16) Preset Value n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SDCLKFSEL:10; /*!< bit: 0.. 9 SDCLK Frequency Select Value for Initialization */
+ uint16_t CLKGSEL:1; /*!< bit: 10 Clock Generator Select Value for Initialization */
+ uint16_t :3; /*!< bit: 11..13 Reserved */
+ uint16_t DRVSEL:2; /*!< bit: 14..15 Driver Strength Select Value for Initialization */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_PVR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_PVR_OFFSET 0x060 /**< \brief (SDHC_PVR offset) Preset Value n */
+#define SDHC_PVR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_PVR reset_value) Preset Value n */
+
+#define SDHC_PVR_SDCLKFSEL_Pos 0 /**< \brief (SDHC_PVR) SDCLK Frequency Select Value for Initialization */
+#define SDHC_PVR_SDCLKFSEL_Msk (_U_(0x3FF) << SDHC_PVR_SDCLKFSEL_Pos)
+#define SDHC_PVR_SDCLKFSEL(value) (SDHC_PVR_SDCLKFSEL_Msk & ((value) << SDHC_PVR_SDCLKFSEL_Pos))
+#define SDHC_PVR_CLKGSEL_Pos 10 /**< \brief (SDHC_PVR) Clock Generator Select Value for Initialization */
+#define SDHC_PVR_CLKGSEL (_U_(0x1) << SDHC_PVR_CLKGSEL_Pos)
+#define SDHC_PVR_CLKGSEL_DIV_Val _U_(0x0) /**< \brief (SDHC_PVR) Host Controller Ver2.00 Compatible Clock Generator (Divider) */
+#define SDHC_PVR_CLKGSEL_PROG_Val _U_(0x1) /**< \brief (SDHC_PVR) Programmable Clock Generator */
+#define SDHC_PVR_CLKGSEL_DIV (SDHC_PVR_CLKGSEL_DIV_Val << SDHC_PVR_CLKGSEL_Pos)
+#define SDHC_PVR_CLKGSEL_PROG (SDHC_PVR_CLKGSEL_PROG_Val << SDHC_PVR_CLKGSEL_Pos)
+#define SDHC_PVR_DRVSEL_Pos 14 /**< \brief (SDHC_PVR) Driver Strength Select Value for Initialization */
+#define SDHC_PVR_DRVSEL_Msk (_U_(0x3) << SDHC_PVR_DRVSEL_Pos)
+#define SDHC_PVR_DRVSEL(value) (SDHC_PVR_DRVSEL_Msk & ((value) << SDHC_PVR_DRVSEL_Pos))
+#define SDHC_PVR_DRVSEL_B_Val _U_(0x0) /**< \brief (SDHC_PVR) Driver Type B is Selected */
+#define SDHC_PVR_DRVSEL_A_Val _U_(0x1) /**< \brief (SDHC_PVR) Driver Type A is Selected */
+#define SDHC_PVR_DRVSEL_C_Val _U_(0x2) /**< \brief (SDHC_PVR) Driver Type C is Selected */
+#define SDHC_PVR_DRVSEL_D_Val _U_(0x3) /**< \brief (SDHC_PVR) Driver Type D is Selected */
+#define SDHC_PVR_DRVSEL_B (SDHC_PVR_DRVSEL_B_Val << SDHC_PVR_DRVSEL_Pos)
+#define SDHC_PVR_DRVSEL_A (SDHC_PVR_DRVSEL_A_Val << SDHC_PVR_DRVSEL_Pos)
+#define SDHC_PVR_DRVSEL_C (SDHC_PVR_DRVSEL_C_Val << SDHC_PVR_DRVSEL_Pos)
+#define SDHC_PVR_DRVSEL_D (SDHC_PVR_DRVSEL_D_Val << SDHC_PVR_DRVSEL_Pos)
+#define SDHC_PVR_MASK _U_(0xC7FF) /**< \brief (SDHC_PVR) MASK Register */
+
+/* -------- SDHC_SISR : (SDHC Offset: 0x0FC) (R/ 16) Slot Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t INTSSL:1; /*!< bit: 0 Interrupt Signal for Each Slot */
+ uint16_t :15; /*!< bit: 1..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_SISR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_SISR_OFFSET 0x0FC /**< \brief (SDHC_SISR offset) Slot Interrupt Status */
+#define SDHC_SISR_RESETVALUE _U_(0x20000) /**< \brief (SDHC_SISR reset_value) Slot Interrupt Status */
+
+#define SDHC_SISR_INTSSL_Pos 0 /**< \brief (SDHC_SISR) Interrupt Signal for Each Slot */
+#define SDHC_SISR_INTSSL_Msk (_U_(0x1) << SDHC_SISR_INTSSL_Pos)
+#define SDHC_SISR_INTSSL(value) (SDHC_SISR_INTSSL_Msk & ((value) << SDHC_SISR_INTSSL_Pos))
+#define SDHC_SISR_MASK _U_(0x0001) /**< \brief (SDHC_SISR) MASK Register */
+
+/* -------- SDHC_HCVR : (SDHC Offset: 0x0FE) (R/ 16) Host Controller Version -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SVER:8; /*!< bit: 0.. 7 Spec Version */
+ uint16_t VVER:8; /*!< bit: 8..15 Vendor Version */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_HCVR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_HCVR_OFFSET 0x0FE /**< \brief (SDHC_HCVR offset) Host Controller Version */
+#define SDHC_HCVR_RESETVALUE _U_(0x1802) /**< \brief (SDHC_HCVR reset_value) Host Controller Version */
+
+#define SDHC_HCVR_SVER_Pos 0 /**< \brief (SDHC_HCVR) Spec Version */
+#define SDHC_HCVR_SVER_Msk (_U_(0xFF) << SDHC_HCVR_SVER_Pos)
+#define SDHC_HCVR_SVER(value) (SDHC_HCVR_SVER_Msk & ((value) << SDHC_HCVR_SVER_Pos))
+#define SDHC_HCVR_VVER_Pos 8 /**< \brief (SDHC_HCVR) Vendor Version */
+#define SDHC_HCVR_VVER_Msk (_U_(0xFF) << SDHC_HCVR_VVER_Pos)
+#define SDHC_HCVR_VVER(value) (SDHC_HCVR_VVER_Msk & ((value) << SDHC_HCVR_VVER_Pos))
+#define SDHC_HCVR_MASK _U_(0xFFFF) /**< \brief (SDHC_HCVR) MASK Register */
+
+/* -------- SDHC_MC1R : (SDHC Offset: 0x204) (R/W 8) MMC Control 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMDTYP:2; /*!< bit: 0.. 1 e.MMC Command Type */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t DDR:1; /*!< bit: 3 e.MMC HSDDR Mode */
+ uint8_t OPD:1; /*!< bit: 4 e.MMC Open Drain Mode */
+ uint8_t BOOTA:1; /*!< bit: 5 e.MMC Boot Acknowledge Enable */
+ uint8_t RSTN:1; /*!< bit: 6 e.MMC Reset Signal */
+ uint8_t FCD:1; /*!< bit: 7 e.MMC Force Card Detect */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_MC1R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_MC1R_OFFSET 0x204 /**< \brief (SDHC_MC1R offset) MMC Control 1 */
+#define SDHC_MC1R_RESETVALUE _U_(0x00) /**< \brief (SDHC_MC1R reset_value) MMC Control 1 */
+
+#define SDHC_MC1R_CMDTYP_Pos 0 /**< \brief (SDHC_MC1R) e.MMC Command Type */
+#define SDHC_MC1R_CMDTYP_Msk (_U_(0x3) << SDHC_MC1R_CMDTYP_Pos)
+#define SDHC_MC1R_CMDTYP(value) (SDHC_MC1R_CMDTYP_Msk & ((value) << SDHC_MC1R_CMDTYP_Pos))
+#define SDHC_MC1R_CMDTYP_NORMAL_Val _U_(0x0) /**< \brief (SDHC_MC1R) Not a MMC specific command */
+#define SDHC_MC1R_CMDTYP_WAITIRQ_Val _U_(0x1) /**< \brief (SDHC_MC1R) Wait IRQ Command */
+#define SDHC_MC1R_CMDTYP_STREAM_Val _U_(0x2) /**< \brief (SDHC_MC1R) Stream Command */
+#define SDHC_MC1R_CMDTYP_BOOT_Val _U_(0x3) /**< \brief (SDHC_MC1R) Boot Command */
+#define SDHC_MC1R_CMDTYP_NORMAL (SDHC_MC1R_CMDTYP_NORMAL_Val << SDHC_MC1R_CMDTYP_Pos)
+#define SDHC_MC1R_CMDTYP_WAITIRQ (SDHC_MC1R_CMDTYP_WAITIRQ_Val << SDHC_MC1R_CMDTYP_Pos)
+#define SDHC_MC1R_CMDTYP_STREAM (SDHC_MC1R_CMDTYP_STREAM_Val << SDHC_MC1R_CMDTYP_Pos)
+#define SDHC_MC1R_CMDTYP_BOOT (SDHC_MC1R_CMDTYP_BOOT_Val << SDHC_MC1R_CMDTYP_Pos)
+#define SDHC_MC1R_DDR_Pos 3 /**< \brief (SDHC_MC1R) e.MMC HSDDR Mode */
+#define SDHC_MC1R_DDR (_U_(0x1) << SDHC_MC1R_DDR_Pos)
+#define SDHC_MC1R_OPD_Pos 4 /**< \brief (SDHC_MC1R) e.MMC Open Drain Mode */
+#define SDHC_MC1R_OPD (_U_(0x1) << SDHC_MC1R_OPD_Pos)
+#define SDHC_MC1R_BOOTA_Pos 5 /**< \brief (SDHC_MC1R) e.MMC Boot Acknowledge Enable */
+#define SDHC_MC1R_BOOTA (_U_(0x1) << SDHC_MC1R_BOOTA_Pos)
+#define SDHC_MC1R_RSTN_Pos 6 /**< \brief (SDHC_MC1R) e.MMC Reset Signal */
+#define SDHC_MC1R_RSTN (_U_(0x1) << SDHC_MC1R_RSTN_Pos)
+#define SDHC_MC1R_FCD_Pos 7 /**< \brief (SDHC_MC1R) e.MMC Force Card Detect */
+#define SDHC_MC1R_FCD (_U_(0x1) << SDHC_MC1R_FCD_Pos)
+#define SDHC_MC1R_MASK _U_(0xFB) /**< \brief (SDHC_MC1R) MASK Register */
+
+/* -------- SDHC_MC2R : (SDHC Offset: 0x205) ( /W 8) MMC Control 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SRESP:1; /*!< bit: 0 e.MMC Abort Wait IRQ */
+ uint8_t ABOOT:1; /*!< bit: 1 e.MMC Abort Boot */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_MC2R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_MC2R_OFFSET 0x205 /**< \brief (SDHC_MC2R offset) MMC Control 2 */
+#define SDHC_MC2R_RESETVALUE _U_(0x00) /**< \brief (SDHC_MC2R reset_value) MMC Control 2 */
+
+#define SDHC_MC2R_SRESP_Pos 0 /**< \brief (SDHC_MC2R) e.MMC Abort Wait IRQ */
+#define SDHC_MC2R_SRESP (_U_(0x1) << SDHC_MC2R_SRESP_Pos)
+#define SDHC_MC2R_ABOOT_Pos 1 /**< \brief (SDHC_MC2R) e.MMC Abort Boot */
+#define SDHC_MC2R_ABOOT (_U_(0x1) << SDHC_MC2R_ABOOT_Pos)
+#define SDHC_MC2R_MASK _U_(0x03) /**< \brief (SDHC_MC2R) MASK Register */
+
+/* -------- SDHC_ACR : (SDHC Offset: 0x208) (R/W 32) AHB Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BMAX:2; /*!< bit: 0.. 1 AHB Maximum Burst */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_ACR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_ACR_OFFSET 0x208 /**< \brief (SDHC_ACR offset) AHB Control */
+#define SDHC_ACR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_ACR reset_value) AHB Control */
+
+#define SDHC_ACR_BMAX_Pos 0 /**< \brief (SDHC_ACR) AHB Maximum Burst */
+#define SDHC_ACR_BMAX_Msk (_U_(0x3) << SDHC_ACR_BMAX_Pos)
+#define SDHC_ACR_BMAX(value) (SDHC_ACR_BMAX_Msk & ((value) << SDHC_ACR_BMAX_Pos))
+#define SDHC_ACR_BMAX_INCR16_Val _U_(0x0) /**< \brief (SDHC_ACR) */
+#define SDHC_ACR_BMAX_INCR8_Val _U_(0x1) /**< \brief (SDHC_ACR) */
+#define SDHC_ACR_BMAX_INCR4_Val _U_(0x2) /**< \brief (SDHC_ACR) */
+#define SDHC_ACR_BMAX_SINGLE_Val _U_(0x3) /**< \brief (SDHC_ACR) */
+#define SDHC_ACR_BMAX_INCR16 (SDHC_ACR_BMAX_INCR16_Val << SDHC_ACR_BMAX_Pos)
+#define SDHC_ACR_BMAX_INCR8 (SDHC_ACR_BMAX_INCR8_Val << SDHC_ACR_BMAX_Pos)
+#define SDHC_ACR_BMAX_INCR4 (SDHC_ACR_BMAX_INCR4_Val << SDHC_ACR_BMAX_Pos)
+#define SDHC_ACR_BMAX_SINGLE (SDHC_ACR_BMAX_SINGLE_Val << SDHC_ACR_BMAX_Pos)
+#define SDHC_ACR_MASK _U_(0x00000003) /**< \brief (SDHC_ACR) MASK Register */
+
+/* -------- SDHC_CC2R : (SDHC Offset: 0x20C) (R/W 32) Clock Control 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FSDCLKD:1; /*!< bit: 0 Force SDCK Disabled */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_CC2R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_CC2R_OFFSET 0x20C /**< \brief (SDHC_CC2R offset) Clock Control 2 */
+#define SDHC_CC2R_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_CC2R reset_value) Clock Control 2 */
+
+#define SDHC_CC2R_FSDCLKD_Pos 0 /**< \brief (SDHC_CC2R) Force SDCK Disabled */
+#define SDHC_CC2R_FSDCLKD (_U_(0x1) << SDHC_CC2R_FSDCLKD_Pos)
+#define SDHC_CC2R_FSDCLKD_NOEFFECT_Val _U_(0x0) /**< \brief (SDHC_CC2R) No effect */
+#define SDHC_CC2R_FSDCLKD_DISABLE_Val _U_(0x1) /**< \brief (SDHC_CC2R) SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled */
+#define SDHC_CC2R_FSDCLKD_NOEFFECT (SDHC_CC2R_FSDCLKD_NOEFFECT_Val << SDHC_CC2R_FSDCLKD_Pos)
+#define SDHC_CC2R_FSDCLKD_DISABLE (SDHC_CC2R_FSDCLKD_DISABLE_Val << SDHC_CC2R_FSDCLKD_Pos)
+#define SDHC_CC2R_MASK _U_(0x00000001) /**< \brief (SDHC_CC2R) MASK Register */
+
+/* -------- SDHC_CACR : (SDHC Offset: 0x230) (R/W 32) Capabilities Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CAPWREN:1; /*!< bit: 0 Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) */
+ uint32_t :7; /*!< bit: 1.. 7 Reserved */
+ uint32_t KEY:8; /*!< bit: 8..15 Key (0x46) */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_CACR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_CACR_OFFSET 0x230 /**< \brief (SDHC_CACR offset) Capabilities Control */
+#define SDHC_CACR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_CACR reset_value) Capabilities Control */
+
+#define SDHC_CACR_CAPWREN_Pos 0 /**< \brief (SDHC_CACR) Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) */
+#define SDHC_CACR_CAPWREN (_U_(0x1) << SDHC_CACR_CAPWREN_Pos)
+#define SDHC_CACR_KEY_Pos 8 /**< \brief (SDHC_CACR) Key (0x46) */
+#define SDHC_CACR_KEY_Msk (_U_(0xFF) << SDHC_CACR_KEY_Pos)
+#define SDHC_CACR_KEY(value) (SDHC_CACR_KEY_Msk & ((value) << SDHC_CACR_KEY_Pos))
+#define SDHC_CACR_MASK _U_(0x0000FF01) /**< \brief (SDHC_CACR) MASK Register */
+
+/* -------- SDHC_DBGR : (SDHC Offset: 0x234) (R/W 8) Debug -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t NIDBG:1; /*!< bit: 0 Non-intrusive debug enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_DBGR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_DBGR_OFFSET 0x234 /**< \brief (SDHC_DBGR offset) Debug */
+#define SDHC_DBGR_RESETVALUE _U_(0x00) /**< \brief (SDHC_DBGR reset_value) Debug */
+
+#define SDHC_DBGR_NIDBG_Pos 0 /**< \brief (SDHC_DBGR) Non-intrusive debug enable */
+#define SDHC_DBGR_NIDBG (_U_(0x1) << SDHC_DBGR_NIDBG_Pos)
+#define SDHC_DBGR_NIDBG_IDBG_Val _U_(0x0) /**< \brief (SDHC_DBGR) Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer) */
+#define SDHC_DBGR_NIDBG_NIDBG_Val _U_(0x1) /**< \brief (SDHC_DBGR) Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer) */
+#define SDHC_DBGR_NIDBG_IDBG (SDHC_DBGR_NIDBG_IDBG_Val << SDHC_DBGR_NIDBG_Pos)
+#define SDHC_DBGR_NIDBG_NIDBG (SDHC_DBGR_NIDBG_NIDBG_Val << SDHC_DBGR_NIDBG_Pos)
+#define SDHC_DBGR_MASK _U_(0x01) /**< \brief (SDHC_DBGR) MASK Register */
+
+/** \brief SDHC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO SDHC_SSAR_Type SSAR; /**< \brief Offset: 0x000 (R/W 32) SDMA System Address / Argument 2 */
+ __IO SDHC_BSR_Type BSR; /**< \brief Offset: 0x004 (R/W 16) Block Size */
+ __IO SDHC_BCR_Type BCR; /**< \brief Offset: 0x006 (R/W 16) Block Count */
+ __IO SDHC_ARG1R_Type ARG1R; /**< \brief Offset: 0x008 (R/W 32) Argument 1 */
+ __IO SDHC_TMR_Type TMR; /**< \brief Offset: 0x00C (R/W 16) Transfer Mode */
+ __IO SDHC_CR_Type CR; /**< \brief Offset: 0x00E (R/W 16) Command */
+ __I SDHC_RR_Type RR[4]; /**< \brief Offset: 0x010 (R/ 32) Response */
+ __IO SDHC_BDPR_Type BDPR; /**< \brief Offset: 0x020 (R/W 32) Buffer Data Port */
+ __I SDHC_PSR_Type PSR; /**< \brief Offset: 0x024 (R/ 32) Present State */
+ __IO SDHC_HC1R_Type HC1R; /**< \brief Offset: 0x028 (R/W 8) Host Control 1 */
+ __IO SDHC_PCR_Type PCR; /**< \brief Offset: 0x029 (R/W 8) Power Control */
+ __IO SDHC_BGCR_Type BGCR; /**< \brief Offset: 0x02A (R/W 8) Block Gap Control */
+ __IO SDHC_WCR_Type WCR; /**< \brief Offset: 0x02B (R/W 8) Wakeup Control */
+ __IO SDHC_CCR_Type CCR; /**< \brief Offset: 0x02C (R/W 16) Clock Control */
+ __IO SDHC_TCR_Type TCR; /**< \brief Offset: 0x02E (R/W 8) Timeout Control */
+ __IO SDHC_SRR_Type SRR; /**< \brief Offset: 0x02F (R/W 8) Software Reset */
+ __IO SDHC_NISTR_Type NISTR; /**< \brief Offset: 0x030 (R/W 16) Normal Interrupt Status */
+ __IO SDHC_EISTR_Type EISTR; /**< \brief Offset: 0x032 (R/W 16) Error Interrupt Status */
+ __IO SDHC_NISTER_Type NISTER; /**< \brief Offset: 0x034 (R/W 16) Normal Interrupt Status Enable */
+ __IO SDHC_EISTER_Type EISTER; /**< \brief Offset: 0x036 (R/W 16) Error Interrupt Status Enable */
+ __IO SDHC_NISIER_Type NISIER; /**< \brief Offset: 0x038 (R/W 16) Normal Interrupt Signal Enable */
+ __IO SDHC_EISIER_Type EISIER; /**< \brief Offset: 0x03A (R/W 16) Error Interrupt Signal Enable */
+ __I SDHC_ACESR_Type ACESR; /**< \brief Offset: 0x03C (R/ 16) Auto CMD Error Status */
+ __IO SDHC_HC2R_Type HC2R; /**< \brief Offset: 0x03E (R/W 16) Host Control 2 */
+ __I SDHC_CA0R_Type CA0R; /**< \brief Offset: 0x040 (R/ 32) Capabilities 0 */
+ __I SDHC_CA1R_Type CA1R; /**< \brief Offset: 0x044 (R/ 32) Capabilities 1 */
+ __I SDHC_MCCAR_Type MCCAR; /**< \brief Offset: 0x048 (R/ 32) Maximum Current Capabilities */
+ RoReg8 Reserved1[0x4];
+ __O SDHC_FERACES_Type FERACES; /**< \brief Offset: 0x050 ( /W 16) Force Event for Auto CMD Error Status */
+ __O SDHC_FEREIS_Type FEREIS; /**< \brief Offset: 0x052 ( /W 16) Force Event for Error Interrupt Status */
+ __I SDHC_AESR_Type AESR; /**< \brief Offset: 0x054 (R/ 8) ADMA Error Status */
+ RoReg8 Reserved2[0x3];
+ __IO SDHC_ASAR_Type ASAR[1]; /**< \brief Offset: 0x058 (R/W 32) ADMA System Address n */
+ RoReg8 Reserved3[0x4];
+ __IO SDHC_PVR_Type PVR[8]; /**< \brief Offset: 0x060 (R/W 16) Preset Value n */
+ RoReg8 Reserved4[0x8C];
+ __I SDHC_SISR_Type SISR; /**< \brief Offset: 0x0FC (R/ 16) Slot Interrupt Status */
+ __I SDHC_HCVR_Type HCVR; /**< \brief Offset: 0x0FE (R/ 16) Host Controller Version */
+ RoReg8 Reserved5[0x104];
+ __IO SDHC_MC1R_Type MC1R; /**< \brief Offset: 0x204 (R/W 8) MMC Control 1 */
+ __O SDHC_MC2R_Type MC2R; /**< \brief Offset: 0x205 ( /W 8) MMC Control 2 */
+ RoReg8 Reserved6[0x2];
+ __IO SDHC_ACR_Type ACR; /**< \brief Offset: 0x208 (R/W 32) AHB Control */
+ __IO SDHC_CC2R_Type CC2R; /**< \brief Offset: 0x20C (R/W 32) Clock Control 2 */
+ RoReg8 Reserved7[0x20];
+ __IO SDHC_CACR_Type CACR; /**< \brief Offset: 0x230 (R/W 32) Capabilities Control */
+ __IO SDHC_DBGR_Type DBGR; /**< \brief Offset: 0x234 (R/W 8) Debug */
+} Sdhc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_SDHC_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/sercom.h b/sysmoOCTSIM/include/component/sercom.h
index 24f0915..a90f9c4 100644
--- a/sysmoOCTSIM/include/component/sercom.h
+++ b/sysmoOCTSIM/include/component/sercom.h
@@ -1,1680 +1,1680 @@
-/**
- * \file
- *
- * \brief Component description for SERCOM
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_SERCOM_COMPONENT_
-#define _SAME54_SERCOM_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR SERCOM */
-/* ========================================================================== */
-/** \addtogroup SAME54_SERCOM Serial Communication Interface */
-/*@{*/
-
-#define SERCOM_U2201
-#define REV_SERCOM 0x500
-
-/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
- uint32_t :8; /*!< bit: 8..15 Reserved */
- uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
- uint32_t :3; /*!< bit: 17..19 Reserved */
- uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
- uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
- uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
- uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
- uint32_t :1; /*!< bit: 26 Reserved */
- uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
- uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
- uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_I2CM_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */
-#define SERCOM_I2CM_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */
-
-#define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */
-#define SERCOM_I2CM_CTRLA_SWRST (_U_(0x1) << SERCOM_I2CM_CTRLA_SWRST_Pos)
-#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */
-#define SERCOM_I2CM_CTRLA_ENABLE (_U_(0x1) << SERCOM_I2CM_CTRLA_ENABLE_Pos)
-#define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
-#define SERCOM_I2CM_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_I2CM_CTRLA_MODE_Pos)
-#define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))
-#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */
-#define SERCOM_I2CM_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)
-#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */
-#define SERCOM_I2CM_CTRLA_PINOUT (_U_(0x1) << SERCOM_I2CM_CTRLA_PINOUT_Pos)
-#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
-#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
-#define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))
-#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
-#define SERCOM_I2CM_CTRLA_MEXTTOEN (_U_(0x1) << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
-#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
-#define SERCOM_I2CM_CTRLA_SEXTTOEN (_U_(0x1) << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
-#define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
-#define SERCOM_I2CM_CTRLA_SPEED_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_SPEED_Pos)
-#define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))
-#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
-#define SERCOM_I2CM_CTRLA_SCLSM (_U_(0x1) << SERCOM_I2CM_CTRLA_SCLSM_Pos)
-#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
-#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
-#define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))
-#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
-#define SERCOM_I2CM_CTRLA_LOWTOUTEN (_U_(0x1) << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
-#define SERCOM_I2CM_CTRLA_MASK _U_(0x7BF1009F) /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
-
-/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
- uint32_t :8; /*!< bit: 8..15 Reserved */
- uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
- uint32_t :3; /*!< bit: 17..19 Reserved */
- uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
- uint32_t :1; /*!< bit: 22 Reserved */
- uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
- uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
- uint32_t :1; /*!< bit: 26 Reserved */
- uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
- uint32_t :2; /*!< bit: 28..29 Reserved */
- uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_I2CS_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */
-#define SERCOM_I2CS_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */
-
-#define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */
-#define SERCOM_I2CS_CTRLA_SWRST (_U_(0x1) << SERCOM_I2CS_CTRLA_SWRST_Pos)
-#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */
-#define SERCOM_I2CS_CTRLA_ENABLE (_U_(0x1) << SERCOM_I2CS_CTRLA_ENABLE_Pos)
-#define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
-#define SERCOM_I2CS_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_I2CS_CTRLA_MODE_Pos)
-#define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))
-#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */
-#define SERCOM_I2CS_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)
-#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */
-#define SERCOM_I2CS_CTRLA_PINOUT (_U_(0x1) << SERCOM_I2CS_CTRLA_PINOUT_Pos)
-#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
-#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (_U_(0x3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
-#define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))
-#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
-#define SERCOM_I2CS_CTRLA_SEXTTOEN (_U_(0x1) << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
-#define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
-#define SERCOM_I2CS_CTRLA_SPEED_Msk (_U_(0x3) << SERCOM_I2CS_CTRLA_SPEED_Pos)
-#define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))
-#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
-#define SERCOM_I2CS_CTRLA_SCLSM (_U_(0x1) << SERCOM_I2CS_CTRLA_SCLSM_Pos)
-#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
-#define SERCOM_I2CS_CTRLA_LOWTOUTEN (_U_(0x1) << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)
-#define SERCOM_I2CS_CTRLA_MASK _U_(0x4BB1009F) /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */
-
-/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
- uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
- uint32_t :7; /*!< bit: 9..15 Reserved */
- uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
- uint32_t :2; /*!< bit: 18..19 Reserved */
- uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
- uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
- uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
- uint32_t DORD:1; /*!< bit: 30 Data Order */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_SPI_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
-#define SERCOM_SPI_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
-
-#define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
-#define SERCOM_SPI_CTRLA_SWRST (_U_(0x1) << SERCOM_SPI_CTRLA_SWRST_Pos)
-#define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */
-#define SERCOM_SPI_CTRLA_ENABLE (_U_(0x1) << SERCOM_SPI_CTRLA_ENABLE_Pos)
-#define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
-#define SERCOM_SPI_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_SPI_CTRLA_MODE_Pos)
-#define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))
-#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */
-#define SERCOM_SPI_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
-#define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
-#define SERCOM_SPI_CTRLA_IBON (_U_(0x1) << SERCOM_SPI_CTRLA_IBON_Pos)
-#define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
-#define SERCOM_SPI_CTRLA_DOPO_Msk (_U_(0x3) << SERCOM_SPI_CTRLA_DOPO_Pos)
-#define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))
-#define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
-#define SERCOM_SPI_CTRLA_DIPO_Msk (_U_(0x3) << SERCOM_SPI_CTRLA_DIPO_Pos)
-#define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))
-#define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
-#define SERCOM_SPI_CTRLA_FORM_Msk (_U_(0xF) << SERCOM_SPI_CTRLA_FORM_Pos)
-#define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))
-#define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
-#define SERCOM_SPI_CTRLA_CPHA (_U_(0x1) << SERCOM_SPI_CTRLA_CPHA_Pos)
-#define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
-#define SERCOM_SPI_CTRLA_CPOL (_U_(0x1) << SERCOM_SPI_CTRLA_CPOL_Pos)
-#define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */
-#define SERCOM_SPI_CTRLA_DORD (_U_(0x1) << SERCOM_SPI_CTRLA_DORD_Pos)
-#define SERCOM_SPI_CTRLA_MASK _U_(0x7F33019F) /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
-
-/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
- uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
- uint32_t TXINV:1; /*!< bit: 9 Transmit Data Invert */
- uint32_t RXINV:1; /*!< bit: 10 Receive Data Invert */
- uint32_t :2; /*!< bit: 11..12 Reserved */
- uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
- uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
- uint32_t :2; /*!< bit: 18..19 Reserved */
- uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
- uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
- uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
- uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
- uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
- uint32_t DORD:1; /*!< bit: 30 Data Order */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_USART_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
-#define SERCOM_USART_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
-
-#define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */
-#define SERCOM_USART_CTRLA_SWRST (_U_(0x1) << SERCOM_USART_CTRLA_SWRST_Pos)
-#define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */
-#define SERCOM_USART_CTRLA_ENABLE (_U_(0x1) << SERCOM_USART_CTRLA_ENABLE_Pos)
-#define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
-#define SERCOM_USART_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_USART_CTRLA_MODE_Pos)
-#define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))
-#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */
-#define SERCOM_USART_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
-#define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
-#define SERCOM_USART_CTRLA_IBON (_U_(0x1) << SERCOM_USART_CTRLA_IBON_Pos)
-#define SERCOM_USART_CTRLA_TXINV_Pos 9 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Invert */
-#define SERCOM_USART_CTRLA_TXINV (_U_(0x1) << SERCOM_USART_CTRLA_TXINV_Pos)
-#define SERCOM_USART_CTRLA_RXINV_Pos 10 /**< \brief (SERCOM_USART_CTRLA) Receive Data Invert */
-#define SERCOM_USART_CTRLA_RXINV (_U_(0x1) << SERCOM_USART_CTRLA_RXINV_Pos)
-#define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */
-#define SERCOM_USART_CTRLA_SAMPR_Msk (_U_(0x7) << SERCOM_USART_CTRLA_SAMPR_Pos)
-#define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))
-#define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
-#define SERCOM_USART_CTRLA_TXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_TXPO_Pos)
-#define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))
-#define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
-#define SERCOM_USART_CTRLA_RXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_RXPO_Pos)
-#define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))
-#define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
-#define SERCOM_USART_CTRLA_SAMPA_Msk (_U_(0x3) << SERCOM_USART_CTRLA_SAMPA_Pos)
-#define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))
-#define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */
-#define SERCOM_USART_CTRLA_FORM_Msk (_U_(0xF) << SERCOM_USART_CTRLA_FORM_Pos)
-#define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))
-#define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
-#define SERCOM_USART_CTRLA_CMODE (_U_(0x1) << SERCOM_USART_CTRLA_CMODE_Pos)
-#define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
-#define SERCOM_USART_CTRLA_CPOL (_U_(0x1) << SERCOM_USART_CTRLA_CPOL_Pos)
-#define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */
-#define SERCOM_USART_CTRLA_DORD (_U_(0x1) << SERCOM_USART_CTRLA_DORD_Pos)
-#define SERCOM_USART_CTRLA_MASK _U_(0x7FF3E79F) /**< \brief (SERCOM_USART_CTRLA) MASK Register */
-
-/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
- uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
- uint32_t :6; /*!< bit: 10..15 Reserved */
- uint32_t CMD:2; /*!< bit: 16..17 Command */
- uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
- uint32_t :13; /*!< bit: 19..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_I2CM_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */
-#define SERCOM_I2CM_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */
-
-#define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */
-#define SERCOM_I2CM_CTRLB_SMEN (_U_(0x1) << SERCOM_I2CM_CTRLB_SMEN_Pos)
-#define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */
-#define SERCOM_I2CM_CTRLB_QCEN (_U_(0x1) << SERCOM_I2CM_CTRLB_QCEN_Pos)
-#define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */
-#define SERCOM_I2CM_CTRLB_CMD_Msk (_U_(0x3) << SERCOM_I2CM_CTRLB_CMD_Pos)
-#define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))
-#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
-#define SERCOM_I2CM_CTRLB_ACKACT (_U_(0x1) << SERCOM_I2CM_CTRLB_ACKACT_Pos)
-#define SERCOM_I2CM_CTRLB_MASK _U_(0x00070300) /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
-
-/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
- uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
- uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
- uint32_t :3; /*!< bit: 11..13 Reserved */
- uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
- uint32_t CMD:2; /*!< bit: 16..17 Command */
- uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
- uint32_t :13; /*!< bit: 19..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_I2CS_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */
-#define SERCOM_I2CS_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */
-
-#define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */
-#define SERCOM_I2CS_CTRLB_SMEN (_U_(0x1) << SERCOM_I2CS_CTRLB_SMEN_Pos)
-#define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */
-#define SERCOM_I2CS_CTRLB_GCMD (_U_(0x1) << SERCOM_I2CS_CTRLB_GCMD_Pos)
-#define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */
-#define SERCOM_I2CS_CTRLB_AACKEN (_U_(0x1) << SERCOM_I2CS_CTRLB_AACKEN_Pos)
-#define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
-#define SERCOM_I2CS_CTRLB_AMODE_Msk (_U_(0x3) << SERCOM_I2CS_CTRLB_AMODE_Pos)
-#define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))
-#define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */
-#define SERCOM_I2CS_CTRLB_CMD_Msk (_U_(0x3) << SERCOM_I2CS_CTRLB_CMD_Pos)
-#define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))
-#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
-#define SERCOM_I2CS_CTRLB_ACKACT (_U_(0x1) << SERCOM_I2CS_CTRLB_ACKACT_Pos)
-#define SERCOM_I2CS_CTRLB_MASK _U_(0x0007C700) /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
-
-/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
- uint32_t :3; /*!< bit: 3.. 5 Reserved */
- uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
- uint32_t :2; /*!< bit: 7.. 8 Reserved */
- uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
- uint32_t :3; /*!< bit: 10..12 Reserved */
- uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
- uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
- uint32_t :1; /*!< bit: 16 Reserved */
- uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_SPI_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
-#define SERCOM_SPI_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
-
-#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */
-#define SERCOM_SPI_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_SPI_CTRLB_CHSIZE_Pos)
-#define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))
-#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
-#define SERCOM_SPI_CTRLB_PLOADEN (_U_(0x1) << SERCOM_SPI_CTRLB_PLOADEN_Pos)
-#define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
-#define SERCOM_SPI_CTRLB_SSDE (_U_(0x1) << SERCOM_SPI_CTRLB_SSDE_Pos)
-#define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */
-#define SERCOM_SPI_CTRLB_MSSEN (_U_(0x1) << SERCOM_SPI_CTRLB_MSSEN_Pos)
-#define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
-#define SERCOM_SPI_CTRLB_AMODE_Msk (_U_(0x3) << SERCOM_SPI_CTRLB_AMODE_Pos)
-#define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))
-#define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
-#define SERCOM_SPI_CTRLB_RXEN (_U_(0x1) << SERCOM_SPI_CTRLB_RXEN_Pos)
-#define SERCOM_SPI_CTRLB_MASK _U_(0x0002E247) /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
-
-/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
- uint32_t :3; /*!< bit: 3.. 5 Reserved */
- uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
- uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
- uint32_t ENC:1; /*!< bit: 10 Encoding Format */
- uint32_t :2; /*!< bit: 11..12 Reserved */
- uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
- uint32_t :2; /*!< bit: 14..15 Reserved */
- uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
- uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
- uint32_t :6; /*!< bit: 18..23 Reserved */
- uint32_t LINCMD:2; /*!< bit: 24..25 LIN Command */
- uint32_t :6; /*!< bit: 26..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_USART_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
-#define SERCOM_USART_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
-
-#define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */
-#define SERCOM_USART_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_USART_CTRLB_CHSIZE_Pos)
-#define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))
-#define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
-#define SERCOM_USART_CTRLB_SBMODE (_U_(0x1) << SERCOM_USART_CTRLB_SBMODE_Pos)
-#define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
-#define SERCOM_USART_CTRLB_COLDEN (_U_(0x1) << SERCOM_USART_CTRLB_COLDEN_Pos)
-#define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
-#define SERCOM_USART_CTRLB_SFDE (_U_(0x1) << SERCOM_USART_CTRLB_SFDE_Pos)
-#define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */
-#define SERCOM_USART_CTRLB_ENC (_U_(0x1) << SERCOM_USART_CTRLB_ENC_Pos)
-#define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
-#define SERCOM_USART_CTRLB_PMODE (_U_(0x1) << SERCOM_USART_CTRLB_PMODE_Pos)
-#define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
-#define SERCOM_USART_CTRLB_TXEN (_U_(0x1) << SERCOM_USART_CTRLB_TXEN_Pos)
-#define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
-#define SERCOM_USART_CTRLB_RXEN (_U_(0x1) << SERCOM_USART_CTRLB_RXEN_Pos)
-#define SERCOM_USART_CTRLB_LINCMD_Pos 24 /**< \brief (SERCOM_USART_CTRLB) LIN Command */
-#define SERCOM_USART_CTRLB_LINCMD_Msk (_U_(0x3) << SERCOM_USART_CTRLB_LINCMD_Pos)
-#define SERCOM_USART_CTRLB_LINCMD(value) (SERCOM_USART_CTRLB_LINCMD_Msk & ((value) << SERCOM_USART_CTRLB_LINCMD_Pos))
-#define SERCOM_USART_CTRLB_MASK _U_(0x03032747) /**< \brief (SERCOM_USART_CTRLB) MASK Register */
-
-/* -------- SERCOM_I2CM_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CM I2CM Control C -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :24; /*!< bit: 0..23 Reserved */
- uint32_t DATA32B:1; /*!< bit: 24 Data 32 Bit */
- uint32_t :7; /*!< bit: 25..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_I2CM_CTRLC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_CTRLC_OFFSET 0x08 /**< \brief (SERCOM_I2CM_CTRLC offset) I2CM Control C */
-#define SERCOM_I2CM_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLC reset_value) I2CM Control C */
-
-#define SERCOM_I2CM_CTRLC_DATA32B_Pos 24 /**< \brief (SERCOM_I2CM_CTRLC) Data 32 Bit */
-#define SERCOM_I2CM_CTRLC_DATA32B (_U_(0x1) << SERCOM_I2CM_CTRLC_DATA32B_Pos)
-#define SERCOM_I2CM_CTRLC_MASK _U_(0x01000000) /**< \brief (SERCOM_I2CM_CTRLC) MASK Register */
-
-/* -------- SERCOM_I2CS_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CS I2CS Control C -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SDASETUP:4; /*!< bit: 0.. 3 SDA Setup Time */
- uint32_t :20; /*!< bit: 4..23 Reserved */
- uint32_t DATA32B:1; /*!< bit: 24 Data 32 Bit */
- uint32_t :7; /*!< bit: 25..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_I2CS_CTRLC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_CTRLC_OFFSET 0x08 /**< \brief (SERCOM_I2CS_CTRLC offset) I2CS Control C */
-#define SERCOM_I2CS_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLC reset_value) I2CS Control C */
-
-#define SERCOM_I2CS_CTRLC_SDASETUP_Pos 0 /**< \brief (SERCOM_I2CS_CTRLC) SDA Setup Time */
-#define SERCOM_I2CS_CTRLC_SDASETUP_Msk (_U_(0xF) << SERCOM_I2CS_CTRLC_SDASETUP_Pos)
-#define SERCOM_I2CS_CTRLC_SDASETUP(value) (SERCOM_I2CS_CTRLC_SDASETUP_Msk & ((value) << SERCOM_I2CS_CTRLC_SDASETUP_Pos))
-#define SERCOM_I2CS_CTRLC_DATA32B_Pos 24 /**< \brief (SERCOM_I2CS_CTRLC) Data 32 Bit */
-#define SERCOM_I2CS_CTRLC_DATA32B (_U_(0x1) << SERCOM_I2CS_CTRLC_DATA32B_Pos)
-#define SERCOM_I2CS_CTRLC_MASK _U_(0x0100000F) /**< \brief (SERCOM_I2CS_CTRLC) MASK Register */
-
-/* -------- SERCOM_SPI_CTRLC : (SERCOM Offset: 0x08) (R/W 32) SPI SPI Control C -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ICSPACE:6; /*!< bit: 0.. 5 Inter-Character Spacing */
- uint32_t :18; /*!< bit: 6..23 Reserved */
- uint32_t DATA32B:1; /*!< bit: 24 Data 32 Bit */
- uint32_t :7; /*!< bit: 25..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_SPI_CTRLC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_CTRLC_OFFSET 0x08 /**< \brief (SERCOM_SPI_CTRLC offset) SPI Control C */
-#define SERCOM_SPI_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLC reset_value) SPI Control C */
-
-#define SERCOM_SPI_CTRLC_ICSPACE_Pos 0 /**< \brief (SERCOM_SPI_CTRLC) Inter-Character Spacing */
-#define SERCOM_SPI_CTRLC_ICSPACE_Msk (_U_(0x3F) << SERCOM_SPI_CTRLC_ICSPACE_Pos)
-#define SERCOM_SPI_CTRLC_ICSPACE(value) (SERCOM_SPI_CTRLC_ICSPACE_Msk & ((value) << SERCOM_SPI_CTRLC_ICSPACE_Pos))
-#define SERCOM_SPI_CTRLC_DATA32B_Pos 24 /**< \brief (SERCOM_SPI_CTRLC) Data 32 Bit */
-#define SERCOM_SPI_CTRLC_DATA32B (_U_(0x1) << SERCOM_SPI_CTRLC_DATA32B_Pos)
-#define SERCOM_SPI_CTRLC_MASK _U_(0x0100003F) /**< \brief (SERCOM_SPI_CTRLC) MASK Register */
-
-/* -------- SERCOM_USART_CTRLC : (SERCOM Offset: 0x08) (R/W 32) USART USART Control C -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t GTIME:3; /*!< bit: 0.. 2 Guard Time */
- uint32_t :5; /*!< bit: 3.. 7 Reserved */
- uint32_t BRKLEN:2; /*!< bit: 8.. 9 LIN Master Break Length */
- uint32_t HDRDLY:2; /*!< bit: 10..11 LIN Master Header Delay */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t INACK:1; /*!< bit: 16 Inhibit Not Acknowledge */
- uint32_t DSNACK:1; /*!< bit: 17 Disable Successive NACK */
- uint32_t :2; /*!< bit: 18..19 Reserved */
- uint32_t MAXITER:3; /*!< bit: 20..22 Maximum Iterations */
- uint32_t :1; /*!< bit: 23 Reserved */
- uint32_t DATA32B:2; /*!< bit: 24..25 Data 32 Bit */
- uint32_t :6; /*!< bit: 26..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_USART_CTRLC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_CTRLC_OFFSET 0x08 /**< \brief (SERCOM_USART_CTRLC offset) USART Control C */
-#define SERCOM_USART_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLC reset_value) USART Control C */
-
-#define SERCOM_USART_CTRLC_GTIME_Pos 0 /**< \brief (SERCOM_USART_CTRLC) Guard Time */
-#define SERCOM_USART_CTRLC_GTIME_Msk (_U_(0x7) << SERCOM_USART_CTRLC_GTIME_Pos)
-#define SERCOM_USART_CTRLC_GTIME(value) (SERCOM_USART_CTRLC_GTIME_Msk & ((value) << SERCOM_USART_CTRLC_GTIME_Pos))
-#define SERCOM_USART_CTRLC_BRKLEN_Pos 8 /**< \brief (SERCOM_USART_CTRLC) LIN Master Break Length */
-#define SERCOM_USART_CTRLC_BRKLEN_Msk (_U_(0x3) << SERCOM_USART_CTRLC_BRKLEN_Pos)
-#define SERCOM_USART_CTRLC_BRKLEN(value) (SERCOM_USART_CTRLC_BRKLEN_Msk & ((value) << SERCOM_USART_CTRLC_BRKLEN_Pos))
-#define SERCOM_USART_CTRLC_HDRDLY_Pos 10 /**< \brief (SERCOM_USART_CTRLC) LIN Master Header Delay */
-#define SERCOM_USART_CTRLC_HDRDLY_Msk (_U_(0x3) << SERCOM_USART_CTRLC_HDRDLY_Pos)
-#define SERCOM_USART_CTRLC_HDRDLY(value) (SERCOM_USART_CTRLC_HDRDLY_Msk & ((value) << SERCOM_USART_CTRLC_HDRDLY_Pos))
-#define SERCOM_USART_CTRLC_INACK_Pos 16 /**< \brief (SERCOM_USART_CTRLC) Inhibit Not Acknowledge */
-#define SERCOM_USART_CTRLC_INACK (_U_(0x1) << SERCOM_USART_CTRLC_INACK_Pos)
-#define SERCOM_USART_CTRLC_DSNACK_Pos 17 /**< \brief (SERCOM_USART_CTRLC) Disable Successive NACK */
-#define SERCOM_USART_CTRLC_DSNACK (_U_(0x1) << SERCOM_USART_CTRLC_DSNACK_Pos)
-#define SERCOM_USART_CTRLC_MAXITER_Pos 20 /**< \brief (SERCOM_USART_CTRLC) Maximum Iterations */
-#define SERCOM_USART_CTRLC_MAXITER_Msk (_U_(0x7) << SERCOM_USART_CTRLC_MAXITER_Pos)
-#define SERCOM_USART_CTRLC_MAXITER(value) (SERCOM_USART_CTRLC_MAXITER_Msk & ((value) << SERCOM_USART_CTRLC_MAXITER_Pos))
-#define SERCOM_USART_CTRLC_DATA32B_Pos 24 /**< \brief (SERCOM_USART_CTRLC) Data 32 Bit */
-#define SERCOM_USART_CTRLC_DATA32B_Msk (_U_(0x3) << SERCOM_USART_CTRLC_DATA32B_Pos)
-#define SERCOM_USART_CTRLC_DATA32B(value) (SERCOM_USART_CTRLC_DATA32B_Msk & ((value) << SERCOM_USART_CTRLC_DATA32B_Pos))
-#define SERCOM_USART_CTRLC_MASK _U_(0x03730F07) /**< \brief (SERCOM_USART_CTRLC) MASK Register */
-
-/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
- uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
- uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
- uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_I2CM_BAUD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */
-#define SERCOM_I2CM_BAUD_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */
-
-#define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
-#define SERCOM_I2CM_BAUD_BAUD_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUD_Pos)
-#define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))
-#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
-#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
-#define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))
-#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
-#define SERCOM_I2CM_BAUD_HSBAUD_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUD_Pos)
-#define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))
-#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
-#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
-#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))
-#define SERCOM_I2CM_BAUD_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
-
-/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SERCOM_SPI_BAUD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
-#define SERCOM_SPI_BAUD_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
-
-#define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
-#define SERCOM_SPI_BAUD_BAUD_Msk (_U_(0xFF) << SERCOM_SPI_BAUD_BAUD_Pos)
-#define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))
-#define SERCOM_SPI_BAUD_MASK _U_(0xFF) /**< \brief (SERCOM_SPI_BAUD) MASK Register */
-
-/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
- } bit; /*!< Structure used for bit access */
- struct { // FRAC mode
- uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
- uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
- } FRAC; /*!< Structure used for FRAC */
- struct { // FRACFP mode
- uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
- uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
- } FRACFP; /*!< Structure used for FRACFP */
- struct { // USARTFP mode
- uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
- } USARTFP; /*!< Structure used for USARTFP */
- uint16_t reg; /*!< Type used for register access */
-} SERCOM_USART_BAUD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */
-#define SERCOM_USART_BAUD_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */
-
-#define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
-#define SERCOM_USART_BAUD_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_BAUD_BAUD_Pos)
-#define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))
-#define SERCOM_USART_BAUD_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD) MASK Register */
-
-// FRAC mode
-#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
-#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
-#define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))
-#define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
-#define SERCOM_USART_BAUD_FRAC_FP_Msk (_U_(0x7) << SERCOM_USART_BAUD_FRAC_FP_Pos)
-#define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))
-#define SERCOM_USART_BAUD_FRAC_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
-
-// FRACFP mode
-#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
-#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
-#define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))
-#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
-#define SERCOM_USART_BAUD_FRACFP_FP_Msk (_U_(0x7) << SERCOM_USART_BAUD_FRACFP_FP_Pos)
-#define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))
-#define SERCOM_USART_BAUD_FRACFP_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
-
-// USARTFP mode
-#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
-#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
-#define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))
-#define SERCOM_USART_BAUD_USARTFP_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
-
-/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SERCOM_USART_RXPL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */
-#define SERCOM_USART_RXPL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */
-
-#define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
-#define SERCOM_USART_RXPL_RXPL_Msk (_U_(0xFF) << SERCOM_USART_RXPL_RXPL_Pos)
-#define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))
-#define SERCOM_USART_RXPL_MASK _U_(0xFF) /**< \brief (SERCOM_USART_RXPL) MASK Register */
-
-/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
- uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
- uint8_t :5; /*!< bit: 2.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SERCOM_I2CM_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */
-#define SERCOM_I2CM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */
-
-#define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */
-#define SERCOM_I2CM_INTENCLR_MB (_U_(0x1) << SERCOM_I2CM_INTENCLR_MB_Pos)
-#define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */
-#define SERCOM_I2CM_INTENCLR_SB (_U_(0x1) << SERCOM_I2CM_INTENCLR_SB_Pos)
-#define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */
-#define SERCOM_I2CM_INTENCLR_ERROR (_U_(0x1) << SERCOM_I2CM_INTENCLR_ERROR_Pos)
-#define SERCOM_I2CM_INTENCLR_MASK _U_(0x83) /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */
-
-/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
- uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
- uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SERCOM_I2CS_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */
-#define SERCOM_I2CS_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */
-
-#define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */
-#define SERCOM_I2CS_INTENCLR_PREC (_U_(0x1) << SERCOM_I2CS_INTENCLR_PREC_Pos)
-#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */
-#define SERCOM_I2CS_INTENCLR_AMATCH (_U_(0x1) << SERCOM_I2CS_INTENCLR_AMATCH_Pos)
-#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */
-#define SERCOM_I2CS_INTENCLR_DRDY (_U_(0x1) << SERCOM_I2CS_INTENCLR_DRDY_Pos)
-#define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */
-#define SERCOM_I2CS_INTENCLR_ERROR (_U_(0x1) << SERCOM_I2CS_INTENCLR_ERROR_Pos)
-#define SERCOM_I2CS_INTENCLR_MASK _U_(0x87) /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */
-
-/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
- uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SERCOM_SPI_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
-#define SERCOM_SPI_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
-
-#define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */
-#define SERCOM_SPI_INTENCLR_DRE (_U_(0x1) << SERCOM_SPI_INTENCLR_DRE_Pos)
-#define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */
-#define SERCOM_SPI_INTENCLR_TXC (_U_(0x1) << SERCOM_SPI_INTENCLR_TXC_Pos)
-#define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */
-#define SERCOM_SPI_INTENCLR_RXC (_U_(0x1) << SERCOM_SPI_INTENCLR_RXC_Pos)
-#define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */
-#define SERCOM_SPI_INTENCLR_SSL (_U_(0x1) << SERCOM_SPI_INTENCLR_SSL_Pos)
-#define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */
-#define SERCOM_SPI_INTENCLR_ERROR (_U_(0x1) << SERCOM_SPI_INTENCLR_ERROR_Pos)
-#define SERCOM_SPI_INTENCLR_MASK _U_(0x8F) /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
-
-/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
- uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
- uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
- uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
- uint8_t :1; /*!< bit: 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SERCOM_USART_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
-#define SERCOM_USART_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
-
-#define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */
-#define SERCOM_USART_INTENCLR_DRE (_U_(0x1) << SERCOM_USART_INTENCLR_DRE_Pos)
-#define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */
-#define SERCOM_USART_INTENCLR_TXC (_U_(0x1) << SERCOM_USART_INTENCLR_TXC_Pos)
-#define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */
-#define SERCOM_USART_INTENCLR_RXC (_U_(0x1) << SERCOM_USART_INTENCLR_RXC_Pos)
-#define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
-#define SERCOM_USART_INTENCLR_RXS (_U_(0x1) << SERCOM_USART_INTENCLR_RXS_Pos)
-#define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */
-#define SERCOM_USART_INTENCLR_CTSIC (_U_(0x1) << SERCOM_USART_INTENCLR_CTSIC_Pos)
-#define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */
-#define SERCOM_USART_INTENCLR_RXBRK (_U_(0x1) << SERCOM_USART_INTENCLR_RXBRK_Pos)
-#define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */
-#define SERCOM_USART_INTENCLR_ERROR (_U_(0x1) << SERCOM_USART_INTENCLR_ERROR_Pos)
-#define SERCOM_USART_INTENCLR_MASK _U_(0xBF) /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
-
-/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
- uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
- uint8_t :5; /*!< bit: 2.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SERCOM_I2CM_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */
-#define SERCOM_I2CM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */
-
-#define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */
-#define SERCOM_I2CM_INTENSET_MB (_U_(0x1) << SERCOM_I2CM_INTENSET_MB_Pos)
-#define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */
-#define SERCOM_I2CM_INTENSET_SB (_U_(0x1) << SERCOM_I2CM_INTENSET_SB_Pos)
-#define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */
-#define SERCOM_I2CM_INTENSET_ERROR (_U_(0x1) << SERCOM_I2CM_INTENSET_ERROR_Pos)
-#define SERCOM_I2CM_INTENSET_MASK _U_(0x83) /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */
-
-/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
- uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
- uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SERCOM_I2CS_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */
-#define SERCOM_I2CS_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */
-
-#define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */
-#define SERCOM_I2CS_INTENSET_PREC (_U_(0x1) << SERCOM_I2CS_INTENSET_PREC_Pos)
-#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */
-#define SERCOM_I2CS_INTENSET_AMATCH (_U_(0x1) << SERCOM_I2CS_INTENSET_AMATCH_Pos)
-#define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */
-#define SERCOM_I2CS_INTENSET_DRDY (_U_(0x1) << SERCOM_I2CS_INTENSET_DRDY_Pos)
-#define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */
-#define SERCOM_I2CS_INTENSET_ERROR (_U_(0x1) << SERCOM_I2CS_INTENSET_ERROR_Pos)
-#define SERCOM_I2CS_INTENSET_MASK _U_(0x87) /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */
-
-/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
- uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SERCOM_SPI_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
-#define SERCOM_SPI_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
-
-#define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
-#define SERCOM_SPI_INTENSET_DRE (_U_(0x1) << SERCOM_SPI_INTENSET_DRE_Pos)
-#define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
-#define SERCOM_SPI_INTENSET_TXC (_U_(0x1) << SERCOM_SPI_INTENSET_TXC_Pos)
-#define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
-#define SERCOM_SPI_INTENSET_RXC (_U_(0x1) << SERCOM_SPI_INTENSET_RXC_Pos)
-#define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */
-#define SERCOM_SPI_INTENSET_SSL (_U_(0x1) << SERCOM_SPI_INTENSET_SSL_Pos)
-#define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */
-#define SERCOM_SPI_INTENSET_ERROR (_U_(0x1) << SERCOM_SPI_INTENSET_ERROR_Pos)
-#define SERCOM_SPI_INTENSET_MASK _U_(0x8F) /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
-
-/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
- uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
- uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
- uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
- uint8_t :1; /*!< bit: 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SERCOM_USART_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
-#define SERCOM_USART_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
-
-#define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
-#define SERCOM_USART_INTENSET_DRE (_U_(0x1) << SERCOM_USART_INTENSET_DRE_Pos)
-#define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
-#define SERCOM_USART_INTENSET_TXC (_U_(0x1) << SERCOM_USART_INTENSET_TXC_Pos)
-#define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
-#define SERCOM_USART_INTENSET_RXC (_U_(0x1) << SERCOM_USART_INTENSET_RXC_Pos)
-#define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
-#define SERCOM_USART_INTENSET_RXS (_U_(0x1) << SERCOM_USART_INTENSET_RXS_Pos)
-#define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */
-#define SERCOM_USART_INTENSET_CTSIC (_U_(0x1) << SERCOM_USART_INTENSET_CTSIC_Pos)
-#define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */
-#define SERCOM_USART_INTENSET_RXBRK (_U_(0x1) << SERCOM_USART_INTENSET_RXBRK_Pos)
-#define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */
-#define SERCOM_USART_INTENSET_ERROR (_U_(0x1) << SERCOM_USART_INTENSET_ERROR_Pos)
-#define SERCOM_USART_INTENSET_MASK _U_(0xBF) /**< \brief (SERCOM_USART_INTENSET) MASK Register */
-
-/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
- __I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
- __I uint8_t :5; /*!< bit: 2.. 6 Reserved */
- __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SERCOM_I2CM_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */
-#define SERCOM_I2CM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */
-
-#define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */
-#define SERCOM_I2CM_INTFLAG_MB (_U_(0x1) << SERCOM_I2CM_INTFLAG_MB_Pos)
-#define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */
-#define SERCOM_I2CM_INTFLAG_SB (_U_(0x1) << SERCOM_I2CM_INTFLAG_SB_Pos)
-#define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */
-#define SERCOM_I2CM_INTFLAG_ERROR (_U_(0x1) << SERCOM_I2CM_INTFLAG_ERROR_Pos)
-#define SERCOM_I2CM_INTFLAG_MASK _U_(0x83) /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */
-
-/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
- __I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
- __I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
- __I uint8_t :4; /*!< bit: 3.. 6 Reserved */
- __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SERCOM_I2CS_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */
-#define SERCOM_I2CS_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */
-
-#define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */
-#define SERCOM_I2CS_INTFLAG_PREC (_U_(0x1) << SERCOM_I2CS_INTFLAG_PREC_Pos)
-#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */
-#define SERCOM_I2CS_INTFLAG_AMATCH (_U_(0x1) << SERCOM_I2CS_INTFLAG_AMATCH_Pos)
-#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */
-#define SERCOM_I2CS_INTFLAG_DRDY (_U_(0x1) << SERCOM_I2CS_INTFLAG_DRDY_Pos)
-#define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */
-#define SERCOM_I2CS_INTFLAG_ERROR (_U_(0x1) << SERCOM_I2CS_INTFLAG_ERROR_Pos)
-#define SERCOM_I2CS_INTFLAG_MASK _U_(0x87) /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */
-
-/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
- __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
- __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
- __I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
- __I uint8_t :3; /*!< bit: 4.. 6 Reserved */
- __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SERCOM_SPI_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
-#define SERCOM_SPI_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
-
-#define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */
-#define SERCOM_SPI_INTFLAG_DRE (_U_(0x1) << SERCOM_SPI_INTFLAG_DRE_Pos)
-#define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */
-#define SERCOM_SPI_INTFLAG_TXC (_U_(0x1) << SERCOM_SPI_INTFLAG_TXC_Pos)
-#define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */
-#define SERCOM_SPI_INTFLAG_RXC (_U_(0x1) << SERCOM_SPI_INTFLAG_RXC_Pos)
-#define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */
-#define SERCOM_SPI_INTFLAG_SSL (_U_(0x1) << SERCOM_SPI_INTFLAG_SSL_Pos)
-#define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */
-#define SERCOM_SPI_INTFLAG_ERROR (_U_(0x1) << SERCOM_SPI_INTFLAG_ERROR_Pos)
-#define SERCOM_SPI_INTFLAG_MASK _U_(0x8F) /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
-
-/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
- __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
- __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
- __I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
- __I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
- __I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
- __I uint8_t :1; /*!< bit: 6 Reserved */
- __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SERCOM_USART_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
-#define SERCOM_USART_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
-
-#define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */
-#define SERCOM_USART_INTFLAG_DRE (_U_(0x1) << SERCOM_USART_INTFLAG_DRE_Pos)
-#define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */
-#define SERCOM_USART_INTFLAG_TXC (_U_(0x1) << SERCOM_USART_INTFLAG_TXC_Pos)
-#define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */
-#define SERCOM_USART_INTFLAG_RXC (_U_(0x1) << SERCOM_USART_INTFLAG_RXC_Pos)
-#define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
-#define SERCOM_USART_INTFLAG_RXS (_U_(0x1) << SERCOM_USART_INTFLAG_RXS_Pos)
-#define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */
-#define SERCOM_USART_INTFLAG_CTSIC (_U_(0x1) << SERCOM_USART_INTFLAG_CTSIC_Pos)
-#define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */
-#define SERCOM_USART_INTFLAG_RXBRK (_U_(0x1) << SERCOM_USART_INTFLAG_RXBRK_Pos)
-#define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */
-#define SERCOM_USART_INTFLAG_ERROR (_U_(0x1) << SERCOM_USART_INTFLAG_ERROR_Pos)
-#define SERCOM_USART_INTFLAG_MASK _U_(0xBF) /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
-
-/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
- uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
- uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
- uint16_t :1; /*!< bit: 3 Reserved */
- uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
- uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
- uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
- uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
- uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
- uint16_t LENERR:1; /*!< bit: 10 Length Error */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} SERCOM_I2CM_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */
-#define SERCOM_I2CM_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */
-
-#define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */
-#define SERCOM_I2CM_STATUS_BUSERR (_U_(0x1) << SERCOM_I2CM_STATUS_BUSERR_Pos)
-#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */
-#define SERCOM_I2CM_STATUS_ARBLOST (_U_(0x1) << SERCOM_I2CM_STATUS_ARBLOST_Pos)
-#define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */
-#define SERCOM_I2CM_STATUS_RXNACK (_U_(0x1) << SERCOM_I2CM_STATUS_RXNACK_Pos)
-#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */
-#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (_U_(0x3) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
-#define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))
-#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
-#define SERCOM_I2CM_STATUS_LOWTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
-#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
-#define SERCOM_I2CM_STATUS_CLKHOLD (_U_(0x1) << SERCOM_I2CM_STATUS_CLKHOLD_Pos)
-#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */
-#define SERCOM_I2CM_STATUS_MEXTTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)
-#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */
-#define SERCOM_I2CM_STATUS_SEXTTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)
-#define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */
-#define SERCOM_I2CM_STATUS_LENERR (_U_(0x1) << SERCOM_I2CM_STATUS_LENERR_Pos)
-#define SERCOM_I2CM_STATUS_MASK _U_(0x07F7) /**< \brief (SERCOM_I2CM_STATUS) MASK Register */
-
-/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
- uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
- uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
- uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
- uint16_t SR:1; /*!< bit: 4 Repeated Start */
- uint16_t :1; /*!< bit: 5 Reserved */
- uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
- uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
- uint16_t :1; /*!< bit: 8 Reserved */
- uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
- uint16_t HS:1; /*!< bit: 10 High Speed */
- uint16_t LENERR:1; /*!< bit: 11 Transaction Length Error */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} SERCOM_I2CS_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */
-#define SERCOM_I2CS_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */
-
-#define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */
-#define SERCOM_I2CS_STATUS_BUSERR (_U_(0x1) << SERCOM_I2CS_STATUS_BUSERR_Pos)
-#define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */
-#define SERCOM_I2CS_STATUS_COLL (_U_(0x1) << SERCOM_I2CS_STATUS_COLL_Pos)
-#define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */
-#define SERCOM_I2CS_STATUS_RXNACK (_U_(0x1) << SERCOM_I2CS_STATUS_RXNACK_Pos)
-#define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */
-#define SERCOM_I2CS_STATUS_DIR (_U_(0x1) << SERCOM_I2CS_STATUS_DIR_Pos)
-#define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */
-#define SERCOM_I2CS_STATUS_SR (_U_(0x1) << SERCOM_I2CS_STATUS_SR_Pos)
-#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */
-#define SERCOM_I2CS_STATUS_LOWTOUT (_U_(0x1) << SERCOM_I2CS_STATUS_LOWTOUT_Pos)
-#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */
-#define SERCOM_I2CS_STATUS_CLKHOLD (_U_(0x1) << SERCOM_I2CS_STATUS_CLKHOLD_Pos)
-#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */
-#define SERCOM_I2CS_STATUS_SEXTTOUT (_U_(0x1) << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)
-#define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */
-#define SERCOM_I2CS_STATUS_HS (_U_(0x1) << SERCOM_I2CS_STATUS_HS_Pos)
-#define SERCOM_I2CS_STATUS_LENERR_Pos 11 /**< \brief (SERCOM_I2CS_STATUS) Transaction Length Error */
-#define SERCOM_I2CS_STATUS_LENERR (_U_(0x1) << SERCOM_I2CS_STATUS_LENERR_Pos)
-#define SERCOM_I2CS_STATUS_MASK _U_(0x0EDF) /**< \brief (SERCOM_I2CS_STATUS) MASK Register */
-
-/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
- uint16_t :8; /*!< bit: 3..10 Reserved */
- uint16_t LENERR:1; /*!< bit: 11 Transaction Length Error */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} SERCOM_SPI_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
-#define SERCOM_SPI_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
-
-#define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
-#define SERCOM_SPI_STATUS_BUFOVF (_U_(0x1) << SERCOM_SPI_STATUS_BUFOVF_Pos)
-#define SERCOM_SPI_STATUS_LENERR_Pos 11 /**< \brief (SERCOM_SPI_STATUS) Transaction Length Error */
-#define SERCOM_SPI_STATUS_LENERR (_U_(0x1) << SERCOM_SPI_STATUS_LENERR_Pos)
-#define SERCOM_SPI_STATUS_MASK _U_(0x0804) /**< \brief (SERCOM_SPI_STATUS) MASK Register */
-
-/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t PERR:1; /*!< bit: 0 Parity Error */
- uint16_t FERR:1; /*!< bit: 1 Frame Error */
- uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
- uint16_t CTS:1; /*!< bit: 3 Clear To Send */
- uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
- uint16_t COLL:1; /*!< bit: 5 Collision Detected */
- uint16_t TXE:1; /*!< bit: 6 Transmitter Empty */
- uint16_t ITER:1; /*!< bit: 7 Maximum Number of Repetitions Reached */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} SERCOM_USART_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */
-#define SERCOM_USART_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
-
-#define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */
-#define SERCOM_USART_STATUS_PERR (_U_(0x1) << SERCOM_USART_STATUS_PERR_Pos)
-#define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */
-#define SERCOM_USART_STATUS_FERR (_U_(0x1) << SERCOM_USART_STATUS_FERR_Pos)
-#define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
-#define SERCOM_USART_STATUS_BUFOVF (_U_(0x1) << SERCOM_USART_STATUS_BUFOVF_Pos)
-#define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */
-#define SERCOM_USART_STATUS_CTS (_U_(0x1) << SERCOM_USART_STATUS_CTS_Pos)
-#define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */
-#define SERCOM_USART_STATUS_ISF (_U_(0x1) << SERCOM_USART_STATUS_ISF_Pos)
-#define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */
-#define SERCOM_USART_STATUS_COLL (_U_(0x1) << SERCOM_USART_STATUS_COLL_Pos)
-#define SERCOM_USART_STATUS_TXE_Pos 6 /**< \brief (SERCOM_USART_STATUS) Transmitter Empty */
-#define SERCOM_USART_STATUS_TXE (_U_(0x1) << SERCOM_USART_STATUS_TXE_Pos)
-#define SERCOM_USART_STATUS_ITER_Pos 7 /**< \brief (SERCOM_USART_STATUS) Maximum Number of Repetitions Reached */
-#define SERCOM_USART_STATUS_ITER (_U_(0x1) << SERCOM_USART_STATUS_ITER_Pos)
-#define SERCOM_USART_STATUS_MASK _U_(0x00FF) /**< \brief (SERCOM_USART_STATUS) MASK Register */
-
-/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t LENGTH:1; /*!< bit: 4 Length Synchronization Busy */
- uint32_t :27; /*!< bit: 5..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_I2CM_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Synchronization Busy */
-#define SERCOM_I2CM_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Synchronization Busy */
-
-#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */
-#define SERCOM_I2CM_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)
-#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */
-#define SERCOM_I2CM_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)
-#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */
-#define SERCOM_I2CM_SYNCBUSY_SYSOP (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)
-#define SERCOM_I2CM_SYNCBUSY_LENGTH_Pos 4 /**< \brief (SERCOM_I2CM_SYNCBUSY) Length Synchronization Busy */
-#define SERCOM_I2CM_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_LENGTH_Pos)
-#define SERCOM_I2CM_SYNCBUSY_MASK _U_(0x00000017) /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */
-
-/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t :2; /*!< bit: 2.. 3 Reserved */
- uint32_t LENGTH:1; /*!< bit: 4 Length Synchronization Busy */
- uint32_t :27; /*!< bit: 5..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_I2CS_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Synchronization Busy */
-#define SERCOM_I2CS_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Synchronization Busy */
-
-#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */
-#define SERCOM_I2CS_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)
-#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */
-#define SERCOM_I2CS_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)
-#define SERCOM_I2CS_SYNCBUSY_LENGTH_Pos 4 /**< \brief (SERCOM_I2CS_SYNCBUSY) Length Synchronization Busy */
-#define SERCOM_I2CS_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_LENGTH_Pos)
-#define SERCOM_I2CS_SYNCBUSY_MASK _U_(0x00000013) /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */
-
-/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t LENGTH:1; /*!< bit: 4 LENGTH Synchronization Busy */
- uint32_t :27; /*!< bit: 5..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_SPI_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Synchronization Busy */
-#define SERCOM_SPI_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Synchronization Busy */
-
-#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
-#define SERCOM_SPI_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
-#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */
-#define SERCOM_SPI_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)
-#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */
-#define SERCOM_SPI_SYNCBUSY_CTRLB (_U_(0x1) << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
-#define SERCOM_SPI_SYNCBUSY_LENGTH_Pos 4 /**< \brief (SERCOM_SPI_SYNCBUSY) LENGTH Synchronization Busy */
-#define SERCOM_SPI_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_SPI_SYNCBUSY_LENGTH_Pos)
-#define SERCOM_SPI_SYNCBUSY_MASK _U_(0x00000017) /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
-
-/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
- uint32_t RXERRCNT:1; /*!< bit: 3 RXERRCNT Synchronization Busy */
- uint32_t LENGTH:1; /*!< bit: 4 LENGTH Synchronization Busy */
- uint32_t :27; /*!< bit: 5..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_USART_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Synchronization Busy */
-#define SERCOM_USART_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Synchronization Busy */
-
-#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
-#define SERCOM_USART_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_USART_SYNCBUSY_SWRST_Pos)
-#define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */
-#define SERCOM_USART_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_USART_SYNCBUSY_ENABLE_Pos)
-#define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */
-#define SERCOM_USART_SYNCBUSY_CTRLB (_U_(0x1) << SERCOM_USART_SYNCBUSY_CTRLB_Pos)
-#define SERCOM_USART_SYNCBUSY_RXERRCNT_Pos 3 /**< \brief (SERCOM_USART_SYNCBUSY) RXERRCNT Synchronization Busy */
-#define SERCOM_USART_SYNCBUSY_RXERRCNT (_U_(0x1) << SERCOM_USART_SYNCBUSY_RXERRCNT_Pos)
-#define SERCOM_USART_SYNCBUSY_LENGTH_Pos 4 /**< \brief (SERCOM_USART_SYNCBUSY) LENGTH Synchronization Busy */
-#define SERCOM_USART_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_USART_SYNCBUSY_LENGTH_Pos)
-#define SERCOM_USART_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */
-
-/* -------- SERCOM_USART_RXERRCNT : (SERCOM Offset: 0x20) (R/ 8) USART USART Receive Error Count -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint8_t reg; /*!< Type used for register access */
-} SERCOM_USART_RXERRCNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_RXERRCNT_OFFSET 0x20 /**< \brief (SERCOM_USART_RXERRCNT offset) USART Receive Error Count */
-#define SERCOM_USART_RXERRCNT_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_RXERRCNT reset_value) USART Receive Error Count */
-#define SERCOM_USART_RXERRCNT_MASK _U_(0xFF) /**< \brief (SERCOM_USART_RXERRCNT) MASK Register */
-
-/* -------- SERCOM_I2CS_LENGTH : (SERCOM Offset: 0x22) (R/W 16) I2CS I2CS Length -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t LEN:8; /*!< bit: 0.. 7 Data Length */
- uint16_t LENEN:1; /*!< bit: 8 Data Length Enable */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} SERCOM_I2CS_LENGTH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_LENGTH_OFFSET 0x22 /**< \brief (SERCOM_I2CS_LENGTH offset) I2CS Length */
-#define SERCOM_I2CS_LENGTH_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CS_LENGTH reset_value) I2CS Length */
-
-#define SERCOM_I2CS_LENGTH_LEN_Pos 0 /**< \brief (SERCOM_I2CS_LENGTH) Data Length */
-#define SERCOM_I2CS_LENGTH_LEN_Msk (_U_(0xFF) << SERCOM_I2CS_LENGTH_LEN_Pos)
-#define SERCOM_I2CS_LENGTH_LEN(value) (SERCOM_I2CS_LENGTH_LEN_Msk & ((value) << SERCOM_I2CS_LENGTH_LEN_Pos))
-#define SERCOM_I2CS_LENGTH_LENEN_Pos 8 /**< \brief (SERCOM_I2CS_LENGTH) Data Length Enable */
-#define SERCOM_I2CS_LENGTH_LENEN (_U_(0x1) << SERCOM_I2CS_LENGTH_LENEN_Pos)
-#define SERCOM_I2CS_LENGTH_MASK _U_(0x01FF) /**< \brief (SERCOM_I2CS_LENGTH) MASK Register */
-
-/* -------- SERCOM_SPI_LENGTH : (SERCOM Offset: 0x22) (R/W 16) SPI SPI Length -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t LEN:8; /*!< bit: 0.. 7 Data Length */
- uint16_t LENEN:1; /*!< bit: 8 Data Length Enable */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} SERCOM_SPI_LENGTH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_LENGTH_OFFSET 0x22 /**< \brief (SERCOM_SPI_LENGTH offset) SPI Length */
-#define SERCOM_SPI_LENGTH_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_SPI_LENGTH reset_value) SPI Length */
-
-#define SERCOM_SPI_LENGTH_LEN_Pos 0 /**< \brief (SERCOM_SPI_LENGTH) Data Length */
-#define SERCOM_SPI_LENGTH_LEN_Msk (_U_(0xFF) << SERCOM_SPI_LENGTH_LEN_Pos)
-#define SERCOM_SPI_LENGTH_LEN(value) (SERCOM_SPI_LENGTH_LEN_Msk & ((value) << SERCOM_SPI_LENGTH_LEN_Pos))
-#define SERCOM_SPI_LENGTH_LENEN_Pos 8 /**< \brief (SERCOM_SPI_LENGTH) Data Length Enable */
-#define SERCOM_SPI_LENGTH_LENEN (_U_(0x1) << SERCOM_SPI_LENGTH_LENEN_Pos)
-#define SERCOM_SPI_LENGTH_MASK _U_(0x01FF) /**< \brief (SERCOM_SPI_LENGTH) MASK Register */
-
-/* -------- SERCOM_USART_LENGTH : (SERCOM Offset: 0x22) (R/W 16) USART USART Length -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t LEN:8; /*!< bit: 0.. 7 Data Length */
- uint16_t LENEN:2; /*!< bit: 8.. 9 Data Length Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} SERCOM_USART_LENGTH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_LENGTH_OFFSET 0x22 /**< \brief (SERCOM_USART_LENGTH offset) USART Length */
-#define SERCOM_USART_LENGTH_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_LENGTH reset_value) USART Length */
-
-#define SERCOM_USART_LENGTH_LEN_Pos 0 /**< \brief (SERCOM_USART_LENGTH) Data Length */
-#define SERCOM_USART_LENGTH_LEN_Msk (_U_(0xFF) << SERCOM_USART_LENGTH_LEN_Pos)
-#define SERCOM_USART_LENGTH_LEN(value) (SERCOM_USART_LENGTH_LEN_Msk & ((value) << SERCOM_USART_LENGTH_LEN_Pos))
-#define SERCOM_USART_LENGTH_LENEN_Pos 8 /**< \brief (SERCOM_USART_LENGTH) Data Length Enable */
-#define SERCOM_USART_LENGTH_LENEN_Msk (_U_(0x3) << SERCOM_USART_LENGTH_LENEN_Pos)
-#define SERCOM_USART_LENGTH_LENEN(value) (SERCOM_USART_LENGTH_LENEN_Msk & ((value) << SERCOM_USART_LENGTH_LENEN_Pos))
-#define SERCOM_USART_LENGTH_MASK _U_(0x03FF) /**< \brief (SERCOM_USART_LENGTH) MASK Register */
-
-/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
- uint32_t :2; /*!< bit: 11..12 Reserved */
- uint32_t LENEN:1; /*!< bit: 13 Length Enable */
- uint32_t HS:1; /*!< bit: 14 High Speed Mode */
- uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
- uint32_t LEN:8; /*!< bit: 16..23 Length */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_I2CM_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */
-#define SERCOM_I2CM_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */
-
-#define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */
-#define SERCOM_I2CM_ADDR_ADDR_Msk (_U_(0x7FF) << SERCOM_I2CM_ADDR_ADDR_Pos)
-#define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))
-#define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
-#define SERCOM_I2CM_ADDR_LENEN (_U_(0x1) << SERCOM_I2CM_ADDR_LENEN_Pos)
-#define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
-#define SERCOM_I2CM_ADDR_HS (_U_(0x1) << SERCOM_I2CM_ADDR_HS_Pos)
-#define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */
-#define SERCOM_I2CM_ADDR_TENBITEN (_U_(0x1) << SERCOM_I2CM_ADDR_TENBITEN_Pos)
-#define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */
-#define SERCOM_I2CM_ADDR_LEN_Msk (_U_(0xFF) << SERCOM_I2CM_ADDR_LEN_Pos)
-#define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))
-#define SERCOM_I2CM_ADDR_MASK _U_(0x00FFE7FF) /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
-
-/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
- uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
- uint32_t :4; /*!< bit: 11..14 Reserved */
- uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
- uint32_t :1; /*!< bit: 16 Reserved */
- uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_I2CS_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */
-#define SERCOM_I2CS_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */
-
-#define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */
-#define SERCOM_I2CS_ADDR_GENCEN (_U_(0x1) << SERCOM_I2CS_ADDR_GENCEN_Pos)
-#define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */
-#define SERCOM_I2CS_ADDR_ADDR_Msk (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDR_Pos)
-#define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))
-#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
-#define SERCOM_I2CS_ADDR_TENBITEN (_U_(0x1) << SERCOM_I2CS_ADDR_TENBITEN_Pos)
-#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
-#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
-#define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))
-#define SERCOM_I2CS_ADDR_MASK _U_(0x07FE87FF) /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
-
-/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
- uint32_t :8; /*!< bit: 8..15 Reserved */
- uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_SPI_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
-#define SERCOM_SPI_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
-
-#define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */
-#define SERCOM_SPI_ADDR_ADDR_Msk (_U_(0xFF) << SERCOM_SPI_ADDR_ADDR_Pos)
-#define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))
-#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */
-#define SERCOM_SPI_ADDR_ADDRMASK_Msk (_U_(0xFF) << SERCOM_SPI_ADDR_ADDRMASK_Pos)
-#define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))
-#define SERCOM_SPI_ADDR_MASK _U_(0x00FF00FF) /**< \brief (SERCOM_SPI_ADDR) MASK Register */
-
-/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CM I2CM Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 Data Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_I2CM_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */
-#define SERCOM_I2CM_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */
-
-#define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */
-#define SERCOM_I2CM_DATA_DATA_Msk (_U_(0xFFFFFFFF) << SERCOM_I2CM_DATA_DATA_Pos)
-#define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))
-#define SERCOM_I2CM_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CM_DATA) MASK Register */
-
-/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CS I2CS Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 Data Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_I2CS_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */
-#define SERCOM_I2CS_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */
-
-#define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */
-#define SERCOM_I2CS_DATA_DATA_Msk (_U_(0xFFFFFFFF) << SERCOM_I2CS_DATA_DATA_Pos)
-#define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))
-#define SERCOM_I2CS_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CS_DATA) MASK Register */
-
-/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 Data Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_SPI_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
-#define SERCOM_SPI_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
-
-#define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */
-#define SERCOM_SPI_DATA_DATA_Msk (_U_(0xFFFFFFFF) << SERCOM_SPI_DATA_DATA_Pos)
-#define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))
-#define SERCOM_SPI_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_SPI_DATA) MASK Register */
-
-/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 32) USART USART Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 Data Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SERCOM_USART_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */
-#define SERCOM_USART_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
-
-#define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */
-#define SERCOM_USART_DATA_DATA_Msk (_U_(0xFFFFFFFF) << SERCOM_USART_DATA_DATA_Pos)
-#define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))
-#define SERCOM_USART_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_USART_DATA) MASK Register */
-
-/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SERCOM_I2CM_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */
-#define SERCOM_I2CM_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */
-
-#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */
-#define SERCOM_I2CM_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)
-#define SERCOM_I2CM_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */
-
-/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SERCOM_SPI_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
-#define SERCOM_SPI_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
-
-#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */
-#define SERCOM_SPI_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
-#define SERCOM_SPI_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
-
-/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} SERCOM_USART_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
-#define SERCOM_USART_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
-
-#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */
-#define SERCOM_USART_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
-#define SERCOM_USART_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
-
-/** \brief SERCOM_I2CM hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* I2C Master Mode */
- __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
- __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
- __IO SERCOM_I2CM_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) I2CM Control C */
- __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
- RoReg8 Reserved1[0x4];
- __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
- RoReg8 Reserved2[0x1];
- __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
- __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Synchronization Busy */
- RoReg8 Reserved5[0x4];
- __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
- __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) I2CM Data */
- RoReg8 Reserved6[0x4];
- __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
-} SercomI2cm;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief SERCOM_I2CS hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* I2C Slave Mode */
- __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
- __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
- __IO SERCOM_I2CS_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) I2CS Control C */
- RoReg8 Reserved1[0x8];
- __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
- RoReg8 Reserved2[0x1];
- __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
- __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Synchronization Busy */
- RoReg8 Reserved5[0x2];
- __IO SERCOM_I2CS_LENGTH_Type LENGTH; /**< \brief Offset: 0x22 (R/W 16) I2CS Length */
- __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
- __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) I2CS Data */
-} SercomI2cs;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief SERCOM_SPI hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* SPI Mode */
- __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
- __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
- __IO SERCOM_SPI_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) SPI Control C */
- __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
- RoReg8 Reserved1[0x7];
- __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
- RoReg8 Reserved2[0x1];
- __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
- __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Synchronization Busy */
- RoReg8 Reserved5[0x2];
- __IO SERCOM_SPI_LENGTH_Type LENGTH; /**< \brief Offset: 0x22 (R/W 16) SPI Length */
- __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
- __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
- RoReg8 Reserved6[0x4];
- __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
-} SercomSpi;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief SERCOM_USART hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* USART Mode */
- __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
- __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
- __IO SERCOM_USART_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) USART Control C */
- __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
- __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
- RoReg8 Reserved1[0x5];
- __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
- RoReg8 Reserved2[0x1];
- __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
- __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Synchronization Busy */
- __I SERCOM_USART_RXERRCNT_Type RXERRCNT; /**< \brief Offset: 0x20 (R/ 8) USART Receive Error Count */
- RoReg8 Reserved5[0x1];
- __IO SERCOM_USART_LENGTH_Type LENGTH; /**< \brief Offset: 0x22 (R/W 16) USART Length */
- RoReg8 Reserved6[0x4];
- __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) USART Data */
- RoReg8 Reserved7[0x4];
- __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
-} SercomUsart;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
- SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
- SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
- SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
-} Sercom;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_SERCOM_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for SERCOM
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_SERCOM_COMPONENT_
+#define _SAME54_SERCOM_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR SERCOM */
+/* ========================================================================== */
+/** \addtogroup SAME54_SERCOM Serial Communication Interface */
+/*@{*/
+
+#define SERCOM_U2201
+#define REV_SERCOM 0x500
+
+/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
+ uint32_t :3; /*!< bit: 17..19 Reserved */
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
+ uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
+ uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
+ uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
+ uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
+ uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */
+#define SERCOM_I2CM_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */
+
+#define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */
+#define SERCOM_I2CM_CTRLA_SWRST (_U_(0x1) << SERCOM_I2CM_CTRLA_SWRST_Pos)
+#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */
+#define SERCOM_I2CM_CTRLA_ENABLE (_U_(0x1) << SERCOM_I2CM_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
+#define SERCOM_I2CM_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))
+#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */
+#define SERCOM_I2CM_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */
+#define SERCOM_I2CM_CTRLA_PINOUT (_U_(0x1) << SERCOM_I2CM_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))
+#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
+#define SERCOM_I2CM_CTRLA_MEXTTOEN (_U_(0x1) << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
+#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CM_CTRLA_SEXTTOEN (_U_(0x1) << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
+#define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
+#define SERCOM_I2CM_CTRLA_SPEED_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_SPEED_Pos)
+#define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))
+#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
+#define SERCOM_I2CM_CTRLA_SCLSM (_U_(0x1) << SERCOM_I2CM_CTRLA_SCLSM_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
+#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN (_U_(0x1) << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
+#define SERCOM_I2CM_CTRLA_MASK _U_(0x7BF1009F) /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
+ uint32_t :3; /*!< bit: 17..19 Reserved */
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
+ uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
+ uint32_t :2; /*!< bit: 28..29 Reserved */
+ uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */
+#define SERCOM_I2CS_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */
+
+#define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */
+#define SERCOM_I2CS_CTRLA_SWRST (_U_(0x1) << SERCOM_I2CS_CTRLA_SWRST_Pos)
+#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */
+#define SERCOM_I2CS_CTRLA_ENABLE (_U_(0x1) << SERCOM_I2CS_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
+#define SERCOM_I2CS_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))
+#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */
+#define SERCOM_I2CS_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */
+#define SERCOM_I2CS_CTRLA_PINOUT (_U_(0x1) << SERCOM_I2CS_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (_U_(0x3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))
+#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CS_CTRLA_SEXTTOEN (_U_(0x1) << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
+#define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
+#define SERCOM_I2CS_CTRLA_SPEED_Msk (_U_(0x3) << SERCOM_I2CS_CTRLA_SPEED_Pos)
+#define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))
+#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
+#define SERCOM_I2CS_CTRLA_SCLSM (_U_(0x1) << SERCOM_I2CS_CTRLA_SCLSM_Pos)
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN (_U_(0x1) << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)
+#define SERCOM_I2CS_CTRLA_MASK _U_(0x4BB1009F) /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
+ uint32_t :7; /*!< bit: 9..15 Reserved */
+ uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
+ uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
+ uint32_t DORD:1; /*!< bit: 30 Data Order */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
+#define SERCOM_SPI_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
+
+#define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
+#define SERCOM_SPI_CTRLA_SWRST (_U_(0x1) << SERCOM_SPI_CTRLA_SWRST_Pos)
+#define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */
+#define SERCOM_SPI_CTRLA_ENABLE (_U_(0x1) << SERCOM_SPI_CTRLA_ENABLE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
+#define SERCOM_SPI_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))
+#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */
+#define SERCOM_SPI_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_SPI_CTRLA_IBON (_U_(0x1) << SERCOM_SPI_CTRLA_IBON_Pos)
+#define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
+#define SERCOM_SPI_CTRLA_DOPO_Msk (_U_(0x3) << SERCOM_SPI_CTRLA_DOPO_Pos)
+#define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))
+#define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
+#define SERCOM_SPI_CTRLA_DIPO_Msk (_U_(0x3) << SERCOM_SPI_CTRLA_DIPO_Pos)
+#define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))
+#define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
+#define SERCOM_SPI_CTRLA_FORM_Msk (_U_(0xF) << SERCOM_SPI_CTRLA_FORM_Pos)
+#define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))
+#define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
+#define SERCOM_SPI_CTRLA_CPHA (_U_(0x1) << SERCOM_SPI_CTRLA_CPHA_Pos)
+#define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
+#define SERCOM_SPI_CTRLA_CPOL (_U_(0x1) << SERCOM_SPI_CTRLA_CPOL_Pos)
+#define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */
+#define SERCOM_SPI_CTRLA_DORD (_U_(0x1) << SERCOM_SPI_CTRLA_DORD_Pos)
+#define SERCOM_SPI_CTRLA_MASK _U_(0x7F33019F) /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
+
+/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
+ uint32_t TXINV:1; /*!< bit: 9 Transmit Data Invert */
+ uint32_t RXINV:1; /*!< bit: 10 Receive Data Invert */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
+ uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
+ uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
+ uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
+ uint32_t DORD:1; /*!< bit: 30 Data Order */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
+#define SERCOM_USART_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
+
+#define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */
+#define SERCOM_USART_CTRLA_SWRST (_U_(0x1) << SERCOM_USART_CTRLA_SWRST_Pos)
+#define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */
+#define SERCOM_USART_CTRLA_ENABLE (_U_(0x1) << SERCOM_USART_CTRLA_ENABLE_Pos)
+#define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
+#define SERCOM_USART_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))
+#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */
+#define SERCOM_USART_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_USART_CTRLA_IBON (_U_(0x1) << SERCOM_USART_CTRLA_IBON_Pos)
+#define SERCOM_USART_CTRLA_TXINV_Pos 9 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Invert */
+#define SERCOM_USART_CTRLA_TXINV (_U_(0x1) << SERCOM_USART_CTRLA_TXINV_Pos)
+#define SERCOM_USART_CTRLA_RXINV_Pos 10 /**< \brief (SERCOM_USART_CTRLA) Receive Data Invert */
+#define SERCOM_USART_CTRLA_RXINV (_U_(0x1) << SERCOM_USART_CTRLA_RXINV_Pos)
+#define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */
+#define SERCOM_USART_CTRLA_SAMPR_Msk (_U_(0x7) << SERCOM_USART_CTRLA_SAMPR_Pos)
+#define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))
+#define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
+#define SERCOM_USART_CTRLA_TXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_TXPO_Pos)
+#define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))
+#define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
+#define SERCOM_USART_CTRLA_RXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_RXPO_Pos)
+#define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))
+#define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
+#define SERCOM_USART_CTRLA_SAMPA_Msk (_U_(0x3) << SERCOM_USART_CTRLA_SAMPA_Pos)
+#define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))
+#define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */
+#define SERCOM_USART_CTRLA_FORM_Msk (_U_(0xF) << SERCOM_USART_CTRLA_FORM_Pos)
+#define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))
+#define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
+#define SERCOM_USART_CTRLA_CMODE (_U_(0x1) << SERCOM_USART_CTRLA_CMODE_Pos)
+#define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
+#define SERCOM_USART_CTRLA_CPOL (_U_(0x1) << SERCOM_USART_CTRLA_CPOL_Pos)
+#define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */
+#define SERCOM_USART_CTRLA_DORD (_U_(0x1) << SERCOM_USART_CTRLA_DORD_Pos)
+#define SERCOM_USART_CTRLA_MASK _U_(0x7FF3E79F) /**< \brief (SERCOM_USART_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
+ uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t CMD:2; /*!< bit: 16..17 Command */
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */
+#define SERCOM_I2CM_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */
+
+#define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CM_CTRLB_SMEN (_U_(0x1) << SERCOM_I2CM_CTRLB_SMEN_Pos)
+#define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */
+#define SERCOM_I2CM_CTRLB_QCEN (_U_(0x1) << SERCOM_I2CM_CTRLB_QCEN_Pos)
+#define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */
+#define SERCOM_I2CM_CTRLB_CMD_Msk (_U_(0x3) << SERCOM_I2CM_CTRLB_CMD_Pos)
+#define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))
+#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
+#define SERCOM_I2CM_CTRLB_ACKACT (_U_(0x1) << SERCOM_I2CM_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CM_CTRLB_MASK _U_(0x00070300) /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
+ uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
+ uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
+ uint32_t :3; /*!< bit: 11..13 Reserved */
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
+ uint32_t CMD:2; /*!< bit: 16..17 Command */
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */
+#define SERCOM_I2CS_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */
+
+#define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CS_CTRLB_SMEN (_U_(0x1) << SERCOM_I2CS_CTRLB_SMEN_Pos)
+#define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */
+#define SERCOM_I2CS_CTRLB_GCMD (_U_(0x1) << SERCOM_I2CS_CTRLB_GCMD_Pos)
+#define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */
+#define SERCOM_I2CS_CTRLB_AACKEN (_U_(0x1) << SERCOM_I2CS_CTRLB_AACKEN_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
+#define SERCOM_I2CS_CTRLB_AMODE_Msk (_U_(0x3) << SERCOM_I2CS_CTRLB_AMODE_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))
+#define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */
+#define SERCOM_I2CS_CTRLB_CMD_Msk (_U_(0x3) << SERCOM_I2CS_CTRLB_CMD_Pos)
+#define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))
+#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
+#define SERCOM_I2CS_CTRLB_ACKACT (_U_(0x1) << SERCOM_I2CS_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CS_CTRLB_MASK _U_(0x0007C700) /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
+ uint32_t :2; /*!< bit: 7.. 8 Reserved */
+ uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
+ uint32_t :3; /*!< bit: 10..12 Reserved */
+ uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
+ uint32_t :1; /*!< bit: 16 Reserved */
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
+#define SERCOM_SPI_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
+
+#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */
+#define SERCOM_SPI_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_SPI_CTRLB_CHSIZE_Pos)
+#define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))
+#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
+#define SERCOM_SPI_CTRLB_PLOADEN (_U_(0x1) << SERCOM_SPI_CTRLB_PLOADEN_Pos)
+#define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
+#define SERCOM_SPI_CTRLB_SSDE (_U_(0x1) << SERCOM_SPI_CTRLB_SSDE_Pos)
+#define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */
+#define SERCOM_SPI_CTRLB_MSSEN (_U_(0x1) << SERCOM_SPI_CTRLB_MSSEN_Pos)
+#define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
+#define SERCOM_SPI_CTRLB_AMODE_Msk (_U_(0x3) << SERCOM_SPI_CTRLB_AMODE_Pos)
+#define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))
+#define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
+#define SERCOM_SPI_CTRLB_RXEN (_U_(0x1) << SERCOM_SPI_CTRLB_RXEN_Pos)
+#define SERCOM_SPI_CTRLB_MASK _U_(0x0002E247) /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
+
+/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
+ uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
+ uint32_t ENC:1; /*!< bit: 10 Encoding Format */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
+ uint32_t :6; /*!< bit: 18..23 Reserved */
+ uint32_t LINCMD:2; /*!< bit: 24..25 LIN Command */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
+#define SERCOM_USART_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
+
+#define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */
+#define SERCOM_USART_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_USART_CTRLB_CHSIZE_Pos)
+#define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))
+#define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
+#define SERCOM_USART_CTRLB_SBMODE (_U_(0x1) << SERCOM_USART_CTRLB_SBMODE_Pos)
+#define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
+#define SERCOM_USART_CTRLB_COLDEN (_U_(0x1) << SERCOM_USART_CTRLB_COLDEN_Pos)
+#define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
+#define SERCOM_USART_CTRLB_SFDE (_U_(0x1) << SERCOM_USART_CTRLB_SFDE_Pos)
+#define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */
+#define SERCOM_USART_CTRLB_ENC (_U_(0x1) << SERCOM_USART_CTRLB_ENC_Pos)
+#define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
+#define SERCOM_USART_CTRLB_PMODE (_U_(0x1) << SERCOM_USART_CTRLB_PMODE_Pos)
+#define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
+#define SERCOM_USART_CTRLB_TXEN (_U_(0x1) << SERCOM_USART_CTRLB_TXEN_Pos)
+#define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
+#define SERCOM_USART_CTRLB_RXEN (_U_(0x1) << SERCOM_USART_CTRLB_RXEN_Pos)
+#define SERCOM_USART_CTRLB_LINCMD_Pos 24 /**< \brief (SERCOM_USART_CTRLB) LIN Command */
+#define SERCOM_USART_CTRLB_LINCMD_Msk (_U_(0x3) << SERCOM_USART_CTRLB_LINCMD_Pos)
+#define SERCOM_USART_CTRLB_LINCMD(value) (SERCOM_USART_CTRLB_LINCMD_Msk & ((value) << SERCOM_USART_CTRLB_LINCMD_Pos))
+#define SERCOM_USART_CTRLB_MASK _U_(0x03032747) /**< \brief (SERCOM_USART_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CM_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CM I2CM Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :24; /*!< bit: 0..23 Reserved */
+ uint32_t DATA32B:1; /*!< bit: 24 Data 32 Bit */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLC_OFFSET 0x08 /**< \brief (SERCOM_I2CM_CTRLC offset) I2CM Control C */
+#define SERCOM_I2CM_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLC reset_value) I2CM Control C */
+
+#define SERCOM_I2CM_CTRLC_DATA32B_Pos 24 /**< \brief (SERCOM_I2CM_CTRLC) Data 32 Bit */
+#define SERCOM_I2CM_CTRLC_DATA32B (_U_(0x1) << SERCOM_I2CM_CTRLC_DATA32B_Pos)
+#define SERCOM_I2CM_CTRLC_MASK _U_(0x01000000) /**< \brief (SERCOM_I2CM_CTRLC) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CS I2CS Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SDASETUP:4; /*!< bit: 0.. 3 SDA Setup Time */
+ uint32_t :20; /*!< bit: 4..23 Reserved */
+ uint32_t DATA32B:1; /*!< bit: 24 Data 32 Bit */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLC_OFFSET 0x08 /**< \brief (SERCOM_I2CS_CTRLC offset) I2CS Control C */
+#define SERCOM_I2CS_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLC reset_value) I2CS Control C */
+
+#define SERCOM_I2CS_CTRLC_SDASETUP_Pos 0 /**< \brief (SERCOM_I2CS_CTRLC) SDA Setup Time */
+#define SERCOM_I2CS_CTRLC_SDASETUP_Msk (_U_(0xF) << SERCOM_I2CS_CTRLC_SDASETUP_Pos)
+#define SERCOM_I2CS_CTRLC_SDASETUP(value) (SERCOM_I2CS_CTRLC_SDASETUP_Msk & ((value) << SERCOM_I2CS_CTRLC_SDASETUP_Pos))
+#define SERCOM_I2CS_CTRLC_DATA32B_Pos 24 /**< \brief (SERCOM_I2CS_CTRLC) Data 32 Bit */
+#define SERCOM_I2CS_CTRLC_DATA32B (_U_(0x1) << SERCOM_I2CS_CTRLC_DATA32B_Pos)
+#define SERCOM_I2CS_CTRLC_MASK _U_(0x0100000F) /**< \brief (SERCOM_I2CS_CTRLC) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLC : (SERCOM Offset: 0x08) (R/W 32) SPI SPI Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ICSPACE:6; /*!< bit: 0.. 5 Inter-Character Spacing */
+ uint32_t :18; /*!< bit: 6..23 Reserved */
+ uint32_t DATA32B:1; /*!< bit: 24 Data 32 Bit */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLC_OFFSET 0x08 /**< \brief (SERCOM_SPI_CTRLC offset) SPI Control C */
+#define SERCOM_SPI_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLC reset_value) SPI Control C */
+
+#define SERCOM_SPI_CTRLC_ICSPACE_Pos 0 /**< \brief (SERCOM_SPI_CTRLC) Inter-Character Spacing */
+#define SERCOM_SPI_CTRLC_ICSPACE_Msk (_U_(0x3F) << SERCOM_SPI_CTRLC_ICSPACE_Pos)
+#define SERCOM_SPI_CTRLC_ICSPACE(value) (SERCOM_SPI_CTRLC_ICSPACE_Msk & ((value) << SERCOM_SPI_CTRLC_ICSPACE_Pos))
+#define SERCOM_SPI_CTRLC_DATA32B_Pos 24 /**< \brief (SERCOM_SPI_CTRLC) Data 32 Bit */
+#define SERCOM_SPI_CTRLC_DATA32B (_U_(0x1) << SERCOM_SPI_CTRLC_DATA32B_Pos)
+#define SERCOM_SPI_CTRLC_MASK _U_(0x0100003F) /**< \brief (SERCOM_SPI_CTRLC) MASK Register */
+
+/* -------- SERCOM_USART_CTRLC : (SERCOM Offset: 0x08) (R/W 32) USART USART Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t GTIME:3; /*!< bit: 0.. 2 Guard Time */
+ uint32_t :5; /*!< bit: 3.. 7 Reserved */
+ uint32_t BRKLEN:2; /*!< bit: 8.. 9 LIN Master Break Length */
+ uint32_t HDRDLY:2; /*!< bit: 10..11 LIN Master Header Delay */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t INACK:1; /*!< bit: 16 Inhibit Not Acknowledge */
+ uint32_t DSNACK:1; /*!< bit: 17 Disable Successive NACK */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t MAXITER:3; /*!< bit: 20..22 Maximum Iterations */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t DATA32B:2; /*!< bit: 24..25 Data 32 Bit */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLC_OFFSET 0x08 /**< \brief (SERCOM_USART_CTRLC offset) USART Control C */
+#define SERCOM_USART_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLC reset_value) USART Control C */
+
+#define SERCOM_USART_CTRLC_GTIME_Pos 0 /**< \brief (SERCOM_USART_CTRLC) Guard Time */
+#define SERCOM_USART_CTRLC_GTIME_Msk (_U_(0x7) << SERCOM_USART_CTRLC_GTIME_Pos)
+#define SERCOM_USART_CTRLC_GTIME(value) (SERCOM_USART_CTRLC_GTIME_Msk & ((value) << SERCOM_USART_CTRLC_GTIME_Pos))
+#define SERCOM_USART_CTRLC_BRKLEN_Pos 8 /**< \brief (SERCOM_USART_CTRLC) LIN Master Break Length */
+#define SERCOM_USART_CTRLC_BRKLEN_Msk (_U_(0x3) << SERCOM_USART_CTRLC_BRKLEN_Pos)
+#define SERCOM_USART_CTRLC_BRKLEN(value) (SERCOM_USART_CTRLC_BRKLEN_Msk & ((value) << SERCOM_USART_CTRLC_BRKLEN_Pos))
+#define SERCOM_USART_CTRLC_HDRDLY_Pos 10 /**< \brief (SERCOM_USART_CTRLC) LIN Master Header Delay */
+#define SERCOM_USART_CTRLC_HDRDLY_Msk (_U_(0x3) << SERCOM_USART_CTRLC_HDRDLY_Pos)
+#define SERCOM_USART_CTRLC_HDRDLY(value) (SERCOM_USART_CTRLC_HDRDLY_Msk & ((value) << SERCOM_USART_CTRLC_HDRDLY_Pos))
+#define SERCOM_USART_CTRLC_INACK_Pos 16 /**< \brief (SERCOM_USART_CTRLC) Inhibit Not Acknowledge */
+#define SERCOM_USART_CTRLC_INACK (_U_(0x1) << SERCOM_USART_CTRLC_INACK_Pos)
+#define SERCOM_USART_CTRLC_DSNACK_Pos 17 /**< \brief (SERCOM_USART_CTRLC) Disable Successive NACK */
+#define SERCOM_USART_CTRLC_DSNACK (_U_(0x1) << SERCOM_USART_CTRLC_DSNACK_Pos)
+#define SERCOM_USART_CTRLC_MAXITER_Pos 20 /**< \brief (SERCOM_USART_CTRLC) Maximum Iterations */
+#define SERCOM_USART_CTRLC_MAXITER_Msk (_U_(0x7) << SERCOM_USART_CTRLC_MAXITER_Pos)
+#define SERCOM_USART_CTRLC_MAXITER(value) (SERCOM_USART_CTRLC_MAXITER_Msk & ((value) << SERCOM_USART_CTRLC_MAXITER_Pos))
+#define SERCOM_USART_CTRLC_DATA32B_Pos 24 /**< \brief (SERCOM_USART_CTRLC) Data 32 Bit */
+#define SERCOM_USART_CTRLC_DATA32B_Msk (_U_(0x3) << SERCOM_USART_CTRLC_DATA32B_Pos)
+#define SERCOM_USART_CTRLC_DATA32B(value) (SERCOM_USART_CTRLC_DATA32B_Msk & ((value) << SERCOM_USART_CTRLC_DATA32B_Pos))
+#define SERCOM_USART_CTRLC_MASK _U_(0x03730F07) /**< \brief (SERCOM_USART_CTRLC) MASK Register */
+
+/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
+ uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
+ uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
+ uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */
+#define SERCOM_I2CM_BAUD_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */
+
+#define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
+#define SERCOM_I2CM_BAUD_BAUD_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUD_Pos)
+#define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))
+#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
+#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))
+#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
+#define SERCOM_I2CM_BAUD_HSBAUD_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUD_Pos)
+#define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))
+#define SERCOM_I2CM_BAUD_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
+
+/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
+#define SERCOM_SPI_BAUD_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
+
+#define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
+#define SERCOM_SPI_BAUD_BAUD_Msk (_U_(0xFF) << SERCOM_SPI_BAUD_BAUD_Pos)
+#define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))
+#define SERCOM_SPI_BAUD_MASK _U_(0xFF) /**< \brief (SERCOM_SPI_BAUD) MASK Register */
+
+/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
+ } bit; /*!< Structure used for bit access */
+ struct { // FRAC mode
+ uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
+ uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
+ } FRAC; /*!< Structure used for FRAC */
+ struct { // FRACFP mode
+ uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
+ uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
+ } FRACFP; /*!< Structure used for FRACFP */
+ struct { // USARTFP mode
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
+ } USARTFP; /*!< Structure used for USARTFP */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_USART_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */
+#define SERCOM_USART_BAUD_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */
+
+#define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
+#define SERCOM_USART_BAUD_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_BAUD_BAUD_Pos)
+#define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))
+#define SERCOM_USART_BAUD_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD) MASK Register */
+
+// FRAC mode
+#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
+#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
+#define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))
+#define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
+#define SERCOM_USART_BAUD_FRAC_FP_Msk (_U_(0x7) << SERCOM_USART_BAUD_FRAC_FP_Pos)
+#define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))
+#define SERCOM_USART_BAUD_FRAC_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
+
+// FRACFP mode
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
+#define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))
+#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
+#define SERCOM_USART_BAUD_FRACFP_FP_Msk (_U_(0x7) << SERCOM_USART_BAUD_FRACFP_FP_Pos)
+#define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))
+#define SERCOM_USART_BAUD_FRACFP_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
+
+// USARTFP mode
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
+#define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))
+#define SERCOM_USART_BAUD_USARTFP_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
+
+/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_RXPL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */
+#define SERCOM_USART_RXPL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */
+
+#define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
+#define SERCOM_USART_RXPL_RXPL_Msk (_U_(0xFF) << SERCOM_USART_RXPL_RXPL_Pos)
+#define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))
+#define SERCOM_USART_RXPL_MASK _U_(0xFF) /**< \brief (SERCOM_USART_RXPL) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */
+#define SERCOM_I2CM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */
+
+#define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_MB (_U_(0x1) << SERCOM_I2CM_INTENCLR_MB_Pos)
+#define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_SB (_U_(0x1) << SERCOM_I2CM_INTENCLR_SB_Pos)
+#define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_ERROR (_U_(0x1) << SERCOM_I2CM_INTENCLR_ERROR_Pos)
+#define SERCOM_I2CM_INTENCLR_MASK _U_(0x83) /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */
+#define SERCOM_I2CS_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */
+
+#define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_PREC (_U_(0x1) << SERCOM_I2CS_INTENCLR_PREC_Pos)
+#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_AMATCH (_U_(0x1) << SERCOM_I2CS_INTENCLR_AMATCH_Pos)
+#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_DRDY (_U_(0x1) << SERCOM_I2CS_INTENCLR_DRDY_Pos)
+#define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_ERROR (_U_(0x1) << SERCOM_I2CS_INTENCLR_ERROR_Pos)
+#define SERCOM_I2CS_INTENCLR_MASK _U_(0x87) /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */
+
+/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
+#define SERCOM_SPI_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
+
+#define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_DRE (_U_(0x1) << SERCOM_SPI_INTENCLR_DRE_Pos)
+#define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_TXC (_U_(0x1) << SERCOM_SPI_INTENCLR_TXC_Pos)
+#define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_RXC (_U_(0x1) << SERCOM_SPI_INTENCLR_RXC_Pos)
+#define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_SSL (_U_(0x1) << SERCOM_SPI_INTENCLR_SSL_Pos)
+#define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_ERROR (_U_(0x1) << SERCOM_SPI_INTENCLR_ERROR_Pos)
+#define SERCOM_SPI_INTENCLR_MASK _U_(0x8F) /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
+
+/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
+#define SERCOM_USART_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
+
+#define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */
+#define SERCOM_USART_INTENCLR_DRE (_U_(0x1) << SERCOM_USART_INTENCLR_DRE_Pos)
+#define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */
+#define SERCOM_USART_INTENCLR_TXC (_U_(0x1) << SERCOM_USART_INTENCLR_TXC_Pos)
+#define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXC (_U_(0x1) << SERCOM_USART_INTENCLR_RXC_Pos)
+#define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXS (_U_(0x1) << SERCOM_USART_INTENCLR_RXS_Pos)
+#define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */
+#define SERCOM_USART_INTENCLR_CTSIC (_U_(0x1) << SERCOM_USART_INTENCLR_CTSIC_Pos)
+#define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXBRK (_U_(0x1) << SERCOM_USART_INTENCLR_RXBRK_Pos)
+#define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_USART_INTENCLR_ERROR (_U_(0x1) << SERCOM_USART_INTENCLR_ERROR_Pos)
+#define SERCOM_USART_INTENCLR_MASK _U_(0xBF) /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */
+#define SERCOM_I2CM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */
+
+#define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_MB (_U_(0x1) << SERCOM_I2CM_INTENSET_MB_Pos)
+#define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_SB (_U_(0x1) << SERCOM_I2CM_INTENSET_SB_Pos)
+#define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_ERROR (_U_(0x1) << SERCOM_I2CM_INTENSET_ERROR_Pos)
+#define SERCOM_I2CM_INTENSET_MASK _U_(0x83) /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */
+#define SERCOM_I2CS_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */
+
+#define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_PREC (_U_(0x1) << SERCOM_I2CS_INTENSET_PREC_Pos)
+#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_AMATCH (_U_(0x1) << SERCOM_I2CS_INTENSET_AMATCH_Pos)
+#define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_DRDY (_U_(0x1) << SERCOM_I2CS_INTENSET_DRDY_Pos)
+#define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_ERROR (_U_(0x1) << SERCOM_I2CS_INTENSET_ERROR_Pos)
+#define SERCOM_I2CS_INTENSET_MASK _U_(0x87) /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */
+
+/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
+#define SERCOM_SPI_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
+
+#define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_SPI_INTENSET_DRE (_U_(0x1) << SERCOM_SPI_INTENSET_DRE_Pos)
+#define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_TXC (_U_(0x1) << SERCOM_SPI_INTENSET_TXC_Pos)
+#define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_RXC (_U_(0x1) << SERCOM_SPI_INTENSET_RXC_Pos)
+#define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */
+#define SERCOM_SPI_INTENSET_SSL (_U_(0x1) << SERCOM_SPI_INTENSET_SSL_Pos)
+#define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_SPI_INTENSET_ERROR (_U_(0x1) << SERCOM_SPI_INTENSET_ERROR_Pos)
+#define SERCOM_SPI_INTENSET_MASK _U_(0x8F) /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
+
+/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
+#define SERCOM_USART_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
+
+#define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_USART_INTENSET_DRE (_U_(0x1) << SERCOM_USART_INTENSET_DRE_Pos)
+#define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_TXC (_U_(0x1) << SERCOM_USART_INTENSET_TXC_Pos)
+#define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXC (_U_(0x1) << SERCOM_USART_INTENSET_RXC_Pos)
+#define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXS (_U_(0x1) << SERCOM_USART_INTENSET_RXS_Pos)
+#define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */
+#define SERCOM_USART_INTENSET_CTSIC (_U_(0x1) << SERCOM_USART_INTENSET_CTSIC_Pos)
+#define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXBRK (_U_(0x1) << SERCOM_USART_INTENSET_RXBRK_Pos)
+#define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_USART_INTENSET_ERROR (_U_(0x1) << SERCOM_USART_INTENSET_ERROR_Pos)
+#define SERCOM_USART_INTENSET_MASK _U_(0xBF) /**< \brief (SERCOM_USART_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
+ __I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
+ __I uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */
+#define SERCOM_I2CM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */
+#define SERCOM_I2CM_INTFLAG_MB (_U_(0x1) << SERCOM_I2CM_INTFLAG_MB_Pos)
+#define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */
+#define SERCOM_I2CM_INTFLAG_SB (_U_(0x1) << SERCOM_I2CM_INTFLAG_SB_Pos)
+#define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */
+#define SERCOM_I2CM_INTFLAG_ERROR (_U_(0x1) << SERCOM_I2CM_INTFLAG_ERROR_Pos)
+#define SERCOM_I2CM_INTFLAG_MASK _U_(0x83) /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
+ __I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
+ __I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
+ __I uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */
+#define SERCOM_I2CS_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */
+#define SERCOM_I2CS_INTFLAG_PREC (_U_(0x1) << SERCOM_I2CS_INTFLAG_PREC_Pos)
+#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */
+#define SERCOM_I2CS_INTFLAG_AMATCH (_U_(0x1) << SERCOM_I2CS_INTFLAG_AMATCH_Pos)
+#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */
+#define SERCOM_I2CS_INTFLAG_DRDY (_U_(0x1) << SERCOM_I2CS_INTFLAG_DRDY_Pos)
+#define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */
+#define SERCOM_I2CS_INTFLAG_ERROR (_U_(0x1) << SERCOM_I2CS_INTFLAG_ERROR_Pos)
+#define SERCOM_I2CS_INTFLAG_MASK _U_(0x87) /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */
+
+/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
+ __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
+ __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
+ __I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
+ __I uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
+#define SERCOM_SPI_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
+
+#define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */
+#define SERCOM_SPI_INTFLAG_DRE (_U_(0x1) << SERCOM_SPI_INTFLAG_DRE_Pos)
+#define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */
+#define SERCOM_SPI_INTFLAG_TXC (_U_(0x1) << SERCOM_SPI_INTFLAG_TXC_Pos)
+#define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */
+#define SERCOM_SPI_INTFLAG_RXC (_U_(0x1) << SERCOM_SPI_INTFLAG_RXC_Pos)
+#define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */
+#define SERCOM_SPI_INTFLAG_SSL (_U_(0x1) << SERCOM_SPI_INTFLAG_SSL_Pos)
+#define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */
+#define SERCOM_SPI_INTFLAG_ERROR (_U_(0x1) << SERCOM_SPI_INTFLAG_ERROR_Pos)
+#define SERCOM_SPI_INTFLAG_MASK _U_(0x8F) /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
+
+/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
+ __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
+ __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
+ __I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
+ __I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
+ __I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
+ __I uint8_t :1; /*!< bit: 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
+#define SERCOM_USART_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
+
+#define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */
+#define SERCOM_USART_INTFLAG_DRE (_U_(0x1) << SERCOM_USART_INTFLAG_DRE_Pos)
+#define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */
+#define SERCOM_USART_INTFLAG_TXC (_U_(0x1) << SERCOM_USART_INTFLAG_TXC_Pos)
+#define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */
+#define SERCOM_USART_INTFLAG_RXC (_U_(0x1) << SERCOM_USART_INTFLAG_RXC_Pos)
+#define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
+#define SERCOM_USART_INTFLAG_RXS (_U_(0x1) << SERCOM_USART_INTFLAG_RXS_Pos)
+#define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */
+#define SERCOM_USART_INTFLAG_CTSIC (_U_(0x1) << SERCOM_USART_INTFLAG_CTSIC_Pos)
+#define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */
+#define SERCOM_USART_INTFLAG_RXBRK (_U_(0x1) << SERCOM_USART_INTFLAG_RXBRK_Pos)
+#define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */
+#define SERCOM_USART_INTFLAG_ERROR (_U_(0x1) << SERCOM_USART_INTFLAG_ERROR_Pos)
+#define SERCOM_USART_INTFLAG_MASK _U_(0xBF) /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
+ uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
+ uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
+ uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
+ uint16_t LENERR:1; /*!< bit: 10 Length Error */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */
+#define SERCOM_I2CM_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */
+
+#define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */
+#define SERCOM_I2CM_STATUS_BUSERR (_U_(0x1) << SERCOM_I2CM_STATUS_BUSERR_Pos)
+#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */
+#define SERCOM_I2CM_STATUS_ARBLOST (_U_(0x1) << SERCOM_I2CM_STATUS_ARBLOST_Pos)
+#define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CM_STATUS_RXNACK (_U_(0x1) << SERCOM_I2CM_STATUS_RXNACK_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */
+#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (_U_(0x3) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))
+#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
+#define SERCOM_I2CM_STATUS_LOWTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
+#define SERCOM_I2CM_STATUS_CLKHOLD (_U_(0x1) << SERCOM_I2CM_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */
+#define SERCOM_I2CM_STATUS_MEXTTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)
+#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CM_STATUS_SEXTTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)
+#define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */
+#define SERCOM_I2CM_STATUS_LENERR (_U_(0x1) << SERCOM_I2CM_STATUS_LENERR_Pos)
+#define SERCOM_I2CM_STATUS_MASK _U_(0x07F7) /**< \brief (SERCOM_I2CM_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
+ uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
+ uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
+ uint16_t SR:1; /*!< bit: 4 Repeated Start */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
+ uint16_t :1; /*!< bit: 8 Reserved */
+ uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
+ uint16_t HS:1; /*!< bit: 10 High Speed */
+ uint16_t LENERR:1; /*!< bit: 11 Transaction Length Error */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */
+#define SERCOM_I2CS_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */
+
+#define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */
+#define SERCOM_I2CS_STATUS_BUSERR (_U_(0x1) << SERCOM_I2CS_STATUS_BUSERR_Pos)
+#define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */
+#define SERCOM_I2CS_STATUS_COLL (_U_(0x1) << SERCOM_I2CS_STATUS_COLL_Pos)
+#define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CS_STATUS_RXNACK (_U_(0x1) << SERCOM_I2CS_STATUS_RXNACK_Pos)
+#define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */
+#define SERCOM_I2CS_STATUS_DIR (_U_(0x1) << SERCOM_I2CS_STATUS_DIR_Pos)
+#define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */
+#define SERCOM_I2CS_STATUS_SR (_U_(0x1) << SERCOM_I2CS_STATUS_SR_Pos)
+#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */
+#define SERCOM_I2CS_STATUS_LOWTOUT (_U_(0x1) << SERCOM_I2CS_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */
+#define SERCOM_I2CS_STATUS_CLKHOLD (_U_(0x1) << SERCOM_I2CS_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CS_STATUS_SEXTTOUT (_U_(0x1) << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)
+#define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */
+#define SERCOM_I2CS_STATUS_HS (_U_(0x1) << SERCOM_I2CS_STATUS_HS_Pos)
+#define SERCOM_I2CS_STATUS_LENERR_Pos 11 /**< \brief (SERCOM_I2CS_STATUS) Transaction Length Error */
+#define SERCOM_I2CS_STATUS_LENERR (_U_(0x1) << SERCOM_I2CS_STATUS_LENERR_Pos)
+#define SERCOM_I2CS_STATUS_MASK _U_(0x0EDF) /**< \brief (SERCOM_I2CS_STATUS) MASK Register */
+
+/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
+ uint16_t :8; /*!< bit: 3..10 Reserved */
+ uint16_t LENERR:1; /*!< bit: 11 Transaction Length Error */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_SPI_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
+#define SERCOM_SPI_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
+
+#define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
+#define SERCOM_SPI_STATUS_BUFOVF (_U_(0x1) << SERCOM_SPI_STATUS_BUFOVF_Pos)
+#define SERCOM_SPI_STATUS_LENERR_Pos 11 /**< \brief (SERCOM_SPI_STATUS) Transaction Length Error */
+#define SERCOM_SPI_STATUS_LENERR (_U_(0x1) << SERCOM_SPI_STATUS_LENERR_Pos)
+#define SERCOM_SPI_STATUS_MASK _U_(0x0804) /**< \brief (SERCOM_SPI_STATUS) MASK Register */
+
+/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PERR:1; /*!< bit: 0 Parity Error */
+ uint16_t FERR:1; /*!< bit: 1 Frame Error */
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
+ uint16_t CTS:1; /*!< bit: 3 Clear To Send */
+ uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
+ uint16_t COLL:1; /*!< bit: 5 Collision Detected */
+ uint16_t TXE:1; /*!< bit: 6 Transmitter Empty */
+ uint16_t ITER:1; /*!< bit: 7 Maximum Number of Repetitions Reached */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_USART_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */
+#define SERCOM_USART_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
+
+#define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */
+#define SERCOM_USART_STATUS_PERR (_U_(0x1) << SERCOM_USART_STATUS_PERR_Pos)
+#define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */
+#define SERCOM_USART_STATUS_FERR (_U_(0x1) << SERCOM_USART_STATUS_FERR_Pos)
+#define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
+#define SERCOM_USART_STATUS_BUFOVF (_U_(0x1) << SERCOM_USART_STATUS_BUFOVF_Pos)
+#define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */
+#define SERCOM_USART_STATUS_CTS (_U_(0x1) << SERCOM_USART_STATUS_CTS_Pos)
+#define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */
+#define SERCOM_USART_STATUS_ISF (_U_(0x1) << SERCOM_USART_STATUS_ISF_Pos)
+#define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */
+#define SERCOM_USART_STATUS_COLL (_U_(0x1) << SERCOM_USART_STATUS_COLL_Pos)
+#define SERCOM_USART_STATUS_TXE_Pos 6 /**< \brief (SERCOM_USART_STATUS) Transmitter Empty */
+#define SERCOM_USART_STATUS_TXE (_U_(0x1) << SERCOM_USART_STATUS_TXE_Pos)
+#define SERCOM_USART_STATUS_ITER_Pos 7 /**< \brief (SERCOM_USART_STATUS) Maximum Number of Repetitions Reached */
+#define SERCOM_USART_STATUS_ITER (_U_(0x1) << SERCOM_USART_STATUS_ITER_Pos)
+#define SERCOM_USART_STATUS_MASK _U_(0x00FF) /**< \brief (SERCOM_USART_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t LENGTH:1; /*!< bit: 4 Length Synchronization Busy */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Synchronization Busy */
+
+#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)
+#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_SYSOP (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)
+#define SERCOM_I2CM_SYNCBUSY_LENGTH_Pos 4 /**< \brief (SERCOM_I2CM_SYNCBUSY) Length Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_LENGTH_Pos)
+#define SERCOM_I2CM_SYNCBUSY_MASK _U_(0x00000017) /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t :2; /*!< bit: 2.. 3 Reserved */
+ uint32_t LENGTH:1; /*!< bit: 4 Length Synchronization Busy */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Synchronization Busy */
+
+#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)
+#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_I2CS_SYNCBUSY_LENGTH_Pos 4 /**< \brief (SERCOM_I2CS_SYNCBUSY) Length Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_LENGTH_Pos)
+#define SERCOM_I2CS_SYNCBUSY_MASK _U_(0x00000013) /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t LENGTH:1; /*!< bit: 4 LENGTH Synchronization Busy */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Synchronization Busy */
+
+#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
+#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_CTRLB (_U_(0x1) << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
+#define SERCOM_SPI_SYNCBUSY_LENGTH_Pos 4 /**< \brief (SERCOM_SPI_SYNCBUSY) LENGTH Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_SPI_SYNCBUSY_LENGTH_Pos)
+#define SERCOM_SPI_SYNCBUSY_MASK _U_(0x00000017) /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
+ uint32_t RXERRCNT:1; /*!< bit: 3 RXERRCNT Synchronization Busy */
+ uint32_t LENGTH:1; /*!< bit: 4 LENGTH Synchronization Busy */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Synchronization Busy */
+
+#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_USART_SYNCBUSY_SWRST_Pos)
+#define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_USART_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_CTRLB (_U_(0x1) << SERCOM_USART_SYNCBUSY_CTRLB_Pos)
+#define SERCOM_USART_SYNCBUSY_RXERRCNT_Pos 3 /**< \brief (SERCOM_USART_SYNCBUSY) RXERRCNT Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_RXERRCNT (_U_(0x1) << SERCOM_USART_SYNCBUSY_RXERRCNT_Pos)
+#define SERCOM_USART_SYNCBUSY_LENGTH_Pos 4 /**< \brief (SERCOM_USART_SYNCBUSY) LENGTH Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_USART_SYNCBUSY_LENGTH_Pos)
+#define SERCOM_USART_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_USART_RXERRCNT : (SERCOM Offset: 0x20) (R/ 8) USART USART Receive Error Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_RXERRCNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_RXERRCNT_OFFSET 0x20 /**< \brief (SERCOM_USART_RXERRCNT offset) USART Receive Error Count */
+#define SERCOM_USART_RXERRCNT_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_RXERRCNT reset_value) USART Receive Error Count */
+#define SERCOM_USART_RXERRCNT_MASK _U_(0xFF) /**< \brief (SERCOM_USART_RXERRCNT) MASK Register */
+
+/* -------- SERCOM_I2CS_LENGTH : (SERCOM Offset: 0x22) (R/W 16) I2CS I2CS Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t LEN:8; /*!< bit: 0.. 7 Data Length */
+ uint16_t LENEN:1; /*!< bit: 8 Data Length Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_LENGTH_OFFSET 0x22 /**< \brief (SERCOM_I2CS_LENGTH offset) I2CS Length */
+#define SERCOM_I2CS_LENGTH_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CS_LENGTH reset_value) I2CS Length */
+
+#define SERCOM_I2CS_LENGTH_LEN_Pos 0 /**< \brief (SERCOM_I2CS_LENGTH) Data Length */
+#define SERCOM_I2CS_LENGTH_LEN_Msk (_U_(0xFF) << SERCOM_I2CS_LENGTH_LEN_Pos)
+#define SERCOM_I2CS_LENGTH_LEN(value) (SERCOM_I2CS_LENGTH_LEN_Msk & ((value) << SERCOM_I2CS_LENGTH_LEN_Pos))
+#define SERCOM_I2CS_LENGTH_LENEN_Pos 8 /**< \brief (SERCOM_I2CS_LENGTH) Data Length Enable */
+#define SERCOM_I2CS_LENGTH_LENEN (_U_(0x1) << SERCOM_I2CS_LENGTH_LENEN_Pos)
+#define SERCOM_I2CS_LENGTH_MASK _U_(0x01FF) /**< \brief (SERCOM_I2CS_LENGTH) MASK Register */
+
+/* -------- SERCOM_SPI_LENGTH : (SERCOM Offset: 0x22) (R/W 16) SPI SPI Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t LEN:8; /*!< bit: 0.. 7 Data Length */
+ uint16_t LENEN:1; /*!< bit: 8 Data Length Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_SPI_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_LENGTH_OFFSET 0x22 /**< \brief (SERCOM_SPI_LENGTH offset) SPI Length */
+#define SERCOM_SPI_LENGTH_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_SPI_LENGTH reset_value) SPI Length */
+
+#define SERCOM_SPI_LENGTH_LEN_Pos 0 /**< \brief (SERCOM_SPI_LENGTH) Data Length */
+#define SERCOM_SPI_LENGTH_LEN_Msk (_U_(0xFF) << SERCOM_SPI_LENGTH_LEN_Pos)
+#define SERCOM_SPI_LENGTH_LEN(value) (SERCOM_SPI_LENGTH_LEN_Msk & ((value) << SERCOM_SPI_LENGTH_LEN_Pos))
+#define SERCOM_SPI_LENGTH_LENEN_Pos 8 /**< \brief (SERCOM_SPI_LENGTH) Data Length Enable */
+#define SERCOM_SPI_LENGTH_LENEN (_U_(0x1) << SERCOM_SPI_LENGTH_LENEN_Pos)
+#define SERCOM_SPI_LENGTH_MASK _U_(0x01FF) /**< \brief (SERCOM_SPI_LENGTH) MASK Register */
+
+/* -------- SERCOM_USART_LENGTH : (SERCOM Offset: 0x22) (R/W 16) USART USART Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t LEN:8; /*!< bit: 0.. 7 Data Length */
+ uint16_t LENEN:2; /*!< bit: 8.. 9 Data Length Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_USART_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_LENGTH_OFFSET 0x22 /**< \brief (SERCOM_USART_LENGTH offset) USART Length */
+#define SERCOM_USART_LENGTH_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_LENGTH reset_value) USART Length */
+
+#define SERCOM_USART_LENGTH_LEN_Pos 0 /**< \brief (SERCOM_USART_LENGTH) Data Length */
+#define SERCOM_USART_LENGTH_LEN_Msk (_U_(0xFF) << SERCOM_USART_LENGTH_LEN_Pos)
+#define SERCOM_USART_LENGTH_LEN(value) (SERCOM_USART_LENGTH_LEN_Msk & ((value) << SERCOM_USART_LENGTH_LEN_Pos))
+#define SERCOM_USART_LENGTH_LENEN_Pos 8 /**< \brief (SERCOM_USART_LENGTH) Data Length Enable */
+#define SERCOM_USART_LENGTH_LENEN_Msk (_U_(0x3) << SERCOM_USART_LENGTH_LENEN_Pos)
+#define SERCOM_USART_LENGTH_LENEN(value) (SERCOM_USART_LENGTH_LENEN_Msk & ((value) << SERCOM_USART_LENGTH_LENEN_Pos))
+#define SERCOM_USART_LENGTH_MASK _U_(0x03FF) /**< \brief (SERCOM_USART_LENGTH) MASK Register */
+
+/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t LENEN:1; /*!< bit: 13 Length Enable */
+ uint32_t HS:1; /*!< bit: 14 High Speed Mode */
+ uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
+ uint32_t LEN:8; /*!< bit: 16..23 Length */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */
+#define SERCOM_I2CM_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */
+
+#define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */
+#define SERCOM_I2CM_ADDR_ADDR_Msk (_U_(0x7FF) << SERCOM_I2CM_ADDR_ADDR_Pos)
+#define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))
+#define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
+#define SERCOM_I2CM_ADDR_LENEN (_U_(0x1) << SERCOM_I2CM_ADDR_LENEN_Pos)
+#define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
+#define SERCOM_I2CM_ADDR_HS (_U_(0x1) << SERCOM_I2CM_ADDR_HS_Pos)
+#define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */
+#define SERCOM_I2CM_ADDR_TENBITEN (_U_(0x1) << SERCOM_I2CM_ADDR_TENBITEN_Pos)
+#define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */
+#define SERCOM_I2CM_ADDR_LEN_Msk (_U_(0xFF) << SERCOM_I2CM_ADDR_LEN_Pos)
+#define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))
+#define SERCOM_I2CM_ADDR_MASK _U_(0x00FFE7FF) /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
+ uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
+ uint32_t :4; /*!< bit: 11..14 Reserved */
+ uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
+ uint32_t :1; /*!< bit: 16 Reserved */
+ uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */
+#define SERCOM_I2CS_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */
+
+#define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */
+#define SERCOM_I2CS_ADDR_GENCEN (_U_(0x1) << SERCOM_I2CS_ADDR_GENCEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */
+#define SERCOM_I2CS_ADDR_ADDR_Msk (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDR_Pos)
+#define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))
+#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
+#define SERCOM_I2CS_ADDR_TENBITEN (_U_(0x1) << SERCOM_I2CS_ADDR_TENBITEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
+#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))
+#define SERCOM_I2CS_ADDR_MASK _U_(0x07FE87FF) /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
+
+/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
+#define SERCOM_SPI_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
+
+#define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */
+#define SERCOM_SPI_ADDR_ADDR_Msk (_U_(0xFF) << SERCOM_SPI_ADDR_ADDR_Pos)
+#define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))
+#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */
+#define SERCOM_SPI_ADDR_ADDRMASK_Msk (_U_(0xFF) << SERCOM_SPI_ADDR_ADDRMASK_Pos)
+#define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))
+#define SERCOM_SPI_ADDR_MASK _U_(0x00FF00FF) /**< \brief (SERCOM_SPI_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CM I2CM Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */
+#define SERCOM_I2CM_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */
+
+#define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */
+#define SERCOM_I2CM_DATA_DATA_Msk (_U_(0xFFFFFFFF) << SERCOM_I2CM_DATA_DATA_Pos)
+#define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))
+#define SERCOM_I2CM_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CM_DATA) MASK Register */
+
+/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CS I2CS Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */
+#define SERCOM_I2CS_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */
+
+#define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */
+#define SERCOM_I2CS_DATA_DATA_Msk (_U_(0xFFFFFFFF) << SERCOM_I2CS_DATA_DATA_Pos)
+#define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))
+#define SERCOM_I2CS_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CS_DATA) MASK Register */
+
+/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
+#define SERCOM_SPI_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
+
+#define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */
+#define SERCOM_SPI_DATA_DATA_Msk (_U_(0xFFFFFFFF) << SERCOM_SPI_DATA_DATA_Pos)
+#define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))
+#define SERCOM_SPI_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_SPI_DATA) MASK Register */
+
+/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 32) USART USART Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */
+#define SERCOM_USART_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
+
+#define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */
+#define SERCOM_USART_DATA_DATA_Msk (_U_(0xFFFFFFFF) << SERCOM_USART_DATA_DATA_Pos)
+#define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))
+#define SERCOM_USART_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_USART_DATA) MASK Register */
+
+/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */
+#define SERCOM_I2CM_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */
+
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_I2CM_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
+#define SERCOM_SPI_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
+
+#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */
+#define SERCOM_SPI_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_SPI_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
+#define SERCOM_USART_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
+
+#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */
+#define SERCOM_USART_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_USART_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
+
+/** \brief SERCOM_I2CM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Master Mode */
+ __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
+ __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
+ __IO SERCOM_I2CM_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) I2CM Control C */
+ __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
+ RoReg8 Reserved2[0x1];
+ __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
+ __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Synchronization Busy */
+ RoReg8 Reserved5[0x4];
+ __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
+ __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) I2CM Data */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
+} SercomI2cm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_I2CS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Slave Mode */
+ __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
+ __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
+ __IO SERCOM_I2CS_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) I2CS Control C */
+ RoReg8 Reserved1[0x8];
+ __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
+ RoReg8 Reserved2[0x1];
+ __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
+ __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Synchronization Busy */
+ RoReg8 Reserved5[0x2];
+ __IO SERCOM_I2CS_LENGTH_Type LENGTH; /**< \brief Offset: 0x22 (R/W 16) I2CS Length */
+ __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
+ __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) I2CS Data */
+} SercomI2cs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_SPI hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* SPI Mode */
+ __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
+ __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
+ __IO SERCOM_SPI_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) SPI Control C */
+ __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
+ RoReg8 Reserved1[0x7];
+ __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
+ RoReg8 Reserved2[0x1];
+ __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
+ __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Synchronization Busy */
+ RoReg8 Reserved5[0x2];
+ __IO SERCOM_SPI_LENGTH_Type LENGTH; /**< \brief Offset: 0x22 (R/W 16) SPI Length */
+ __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
+ __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
+} SercomSpi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_USART hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USART Mode */
+ __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
+ __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
+ __IO SERCOM_USART_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) USART Control C */
+ __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
+ __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
+ RoReg8 Reserved1[0x5];
+ __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
+ RoReg8 Reserved2[0x1];
+ __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
+ __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Synchronization Busy */
+ __I SERCOM_USART_RXERRCNT_Type RXERRCNT; /**< \brief Offset: 0x20 (R/ 8) USART Receive Error Count */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_USART_LENGTH_Type LENGTH; /**< \brief Offset: 0x22 (R/W 16) USART Length */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) USART Data */
+ RoReg8 Reserved7[0x4];
+ __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
+} SercomUsart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
+ SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
+ SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
+ SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
+} Sercom;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_SERCOM_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/tc.h b/sysmoOCTSIM/include/component/tc.h
index 953416f..aca1e53 100644
--- a/sysmoOCTSIM/include/component/tc.h
+++ b/sysmoOCTSIM/include/component/tc.h
@@ -1,851 +1,851 @@
-/**
- * \file
- *
- * \brief Component description for TC
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_TC_COMPONENT_
-#define _SAME54_TC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR TC */
-/* ========================================================================== */
-/** \addtogroup SAME54_TC Basic Timer Counter */
-/*@{*/
-
-#define TC_U2249
-#define REV_TC 0x300
-
-/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 32) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:2; /*!< bit: 2.. 3 Timer Counter Mode */
- uint32_t PRESCSYNC:2; /*!< bit: 4.. 5 Prescaler and Counter Synchronization */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
- uint32_t ONDEMAND:1; /*!< bit: 7 Clock On Demand */
- uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
- uint32_t ALOCK:1; /*!< bit: 11 Auto Lock */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t CAPTEN0:1; /*!< bit: 16 Capture Channel 0 Enable */
- uint32_t CAPTEN1:1; /*!< bit: 17 Capture Channel 1 Enable */
- uint32_t :2; /*!< bit: 18..19 Reserved */
- uint32_t COPEN0:1; /*!< bit: 20 Capture On Pin 0 Enable */
- uint32_t COPEN1:1; /*!< bit: 21 Capture On Pin 1 Enable */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t CAPTMODE0:2; /*!< bit: 24..25 Capture Mode Channel 0 */
- uint32_t :1; /*!< bit: 26 Reserved */
- uint32_t CAPTMODE1:2; /*!< bit: 27..28 Capture mode Channel 1 */
- uint32_t :3; /*!< bit: 29..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t CAPTEN:2; /*!< bit: 16..17 Capture Channel x Enable */
- uint32_t :2; /*!< bit: 18..19 Reserved */
- uint32_t COPEN:2; /*!< bit: 20..21 Capture On Pin x Enable */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} TC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */
-#define TC_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (TC_CTRLA reset_value) Control A */
-
-#define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */
-#define TC_CTRLA_SWRST (_U_(0x1) << TC_CTRLA_SWRST_Pos)
-#define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */
-#define TC_CTRLA_ENABLE (_U_(0x1) << TC_CTRLA_ENABLE_Pos)
-#define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) Timer Counter Mode */
-#define TC_CTRLA_MODE_Msk (_U_(0x3) << TC_CTRLA_MODE_Pos)
-#define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
-#define TC_CTRLA_MODE_COUNT16_Val _U_(0x0) /**< \brief (TC_CTRLA) Counter in 16-bit mode */
-#define TC_CTRLA_MODE_COUNT8_Val _U_(0x1) /**< \brief (TC_CTRLA) Counter in 8-bit mode */
-#define TC_CTRLA_MODE_COUNT32_Val _U_(0x2) /**< \brief (TC_CTRLA) Counter in 32-bit mode */
-#define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos)
-#define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos)
-#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)
-#define TC_CTRLA_PRESCSYNC_Pos 4 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
-#define TC_CTRLA_PRESCSYNC_Msk (_U_(0x3) << TC_CTRLA_PRESCSYNC_Pos)
-#define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
-#define TC_CTRLA_PRESCSYNC_GCLK_Val _U_(0x0) /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
-#define TC_CTRLA_PRESCSYNC_PRESC_Val _U_(0x1) /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
-#define TC_CTRLA_PRESCSYNC_RESYNC_Val _U_(0x2) /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock and reset the prescaler counter */
-#define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos)
-#define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos)
-#define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
-#define TC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TC_CTRLA) Run during Standby */
-#define TC_CTRLA_RUNSTDBY (_U_(0x1) << TC_CTRLA_RUNSTDBY_Pos)
-#define TC_CTRLA_ONDEMAND_Pos 7 /**< \brief (TC_CTRLA) Clock On Demand */
-#define TC_CTRLA_ONDEMAND (_U_(0x1) << TC_CTRLA_ONDEMAND_Pos)
-#define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */
-#define TC_CTRLA_PRESCALER_Msk (_U_(0x7) << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
-#define TC_CTRLA_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
-#define TC_CTRLA_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
-#define TC_CTRLA_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
-#define TC_CTRLA_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
-#define TC_CTRLA_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
-#define TC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
-#define TC_CTRLA_PRESCALER_DIV256_Val _U_(0x6) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
-#define TC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
-#define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_ALOCK_Pos 11 /**< \brief (TC_CTRLA) Auto Lock */
-#define TC_CTRLA_ALOCK (_U_(0x1) << TC_CTRLA_ALOCK_Pos)
-#define TC_CTRLA_CAPTEN0_Pos 16 /**< \brief (TC_CTRLA) Capture Channel 0 Enable */
-#define TC_CTRLA_CAPTEN0 (_U_(1) << TC_CTRLA_CAPTEN0_Pos)
-#define TC_CTRLA_CAPTEN1_Pos 17 /**< \brief (TC_CTRLA) Capture Channel 1 Enable */
-#define TC_CTRLA_CAPTEN1 (_U_(1) << TC_CTRLA_CAPTEN1_Pos)
-#define TC_CTRLA_CAPTEN_Pos 16 /**< \brief (TC_CTRLA) Capture Channel x Enable */
-#define TC_CTRLA_CAPTEN_Msk (_U_(0x3) << TC_CTRLA_CAPTEN_Pos)
-#define TC_CTRLA_CAPTEN(value) (TC_CTRLA_CAPTEN_Msk & ((value) << TC_CTRLA_CAPTEN_Pos))
-#define TC_CTRLA_COPEN0_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin 0 Enable */
-#define TC_CTRLA_COPEN0 (_U_(1) << TC_CTRLA_COPEN0_Pos)
-#define TC_CTRLA_COPEN1_Pos 21 /**< \brief (TC_CTRLA) Capture On Pin 1 Enable */
-#define TC_CTRLA_COPEN1 (_U_(1) << TC_CTRLA_COPEN1_Pos)
-#define TC_CTRLA_COPEN_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin x Enable */
-#define TC_CTRLA_COPEN_Msk (_U_(0x3) << TC_CTRLA_COPEN_Pos)
-#define TC_CTRLA_COPEN(value) (TC_CTRLA_COPEN_Msk & ((value) << TC_CTRLA_COPEN_Pos))
-#define TC_CTRLA_CAPTMODE0_Pos 24 /**< \brief (TC_CTRLA) Capture Mode Channel 0 */
-#define TC_CTRLA_CAPTMODE0_Msk (_U_(0x3) << TC_CTRLA_CAPTMODE0_Pos)
-#define TC_CTRLA_CAPTMODE0(value) (TC_CTRLA_CAPTMODE0_Msk & ((value) << TC_CTRLA_CAPTMODE0_Pos))
-#define TC_CTRLA_CAPTMODE0_DEFAULT_Val _U_(0x0) /**< \brief (TC_CTRLA) Default capture */
-#define TC_CTRLA_CAPTMODE0_CAPTMIN_Val _U_(0x1) /**< \brief (TC_CTRLA) Minimum capture */
-#define TC_CTRLA_CAPTMODE0_CAPTMAX_Val _U_(0x2) /**< \brief (TC_CTRLA) Maximum capture */
-#define TC_CTRLA_CAPTMODE0_DEFAULT (TC_CTRLA_CAPTMODE0_DEFAULT_Val << TC_CTRLA_CAPTMODE0_Pos)
-#define TC_CTRLA_CAPTMODE0_CAPTMIN (TC_CTRLA_CAPTMODE0_CAPTMIN_Val << TC_CTRLA_CAPTMODE0_Pos)
-#define TC_CTRLA_CAPTMODE0_CAPTMAX (TC_CTRLA_CAPTMODE0_CAPTMAX_Val << TC_CTRLA_CAPTMODE0_Pos)
-#define TC_CTRLA_CAPTMODE1_Pos 27 /**< \brief (TC_CTRLA) Capture mode Channel 1 */
-#define TC_CTRLA_CAPTMODE1_Msk (_U_(0x3) << TC_CTRLA_CAPTMODE1_Pos)
-#define TC_CTRLA_CAPTMODE1(value) (TC_CTRLA_CAPTMODE1_Msk & ((value) << TC_CTRLA_CAPTMODE1_Pos))
-#define TC_CTRLA_CAPTMODE1_DEFAULT_Val _U_(0x0) /**< \brief (TC_CTRLA) Default capture */
-#define TC_CTRLA_CAPTMODE1_CAPTMIN_Val _U_(0x1) /**< \brief (TC_CTRLA) Minimum capture */
-#define TC_CTRLA_CAPTMODE1_CAPTMAX_Val _U_(0x2) /**< \brief (TC_CTRLA) Maximum capture */
-#define TC_CTRLA_CAPTMODE1_DEFAULT (TC_CTRLA_CAPTMODE1_DEFAULT_Val << TC_CTRLA_CAPTMODE1_Pos)
-#define TC_CTRLA_CAPTMODE1_CAPTMIN (TC_CTRLA_CAPTMODE1_CAPTMIN_Val << TC_CTRLA_CAPTMODE1_Pos)
-#define TC_CTRLA_CAPTMODE1_CAPTMAX (TC_CTRLA_CAPTMODE1_CAPTMAX_Val << TC_CTRLA_CAPTMODE1_Pos)
-#define TC_CTRLA_MASK _U_(0x1B330FFF) /**< \brief (TC_CTRLA) MASK Register */
-
-/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t LUPD:1; /*!< bit: 1 Lock Update */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */
- uint8_t :2; /*!< bit: 3.. 4 Reserved */
- uint8_t CMD:3; /*!< bit: 5.. 7 Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} TC_CTRLBCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */
-#define TC_CTRLBCLR_RESETVALUE _U_(0x00) /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
-
-#define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */
-#define TC_CTRLBCLR_DIR (_U_(0x1) << TC_CTRLBCLR_DIR_Pos)
-#define TC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TC_CTRLBCLR) Lock Update */
-#define TC_CTRLBCLR_LUPD (_U_(0x1) << TC_CTRLBCLR_LUPD_Pos)
-#define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot on Counter */
-#define TC_CTRLBCLR_ONESHOT (_U_(0x1) << TC_CTRLBCLR_ONESHOT_Pos)
-#define TC_CTRLBCLR_CMD_Pos 5 /**< \brief (TC_CTRLBCLR) Command */
-#define TC_CTRLBCLR_CMD_Msk (_U_(0x7) << TC_CTRLBCLR_CMD_Pos)
-#define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
-#define TC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< \brief (TC_CTRLBCLR) No action */
-#define TC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
-#define TC_CTRLBCLR_CMD_STOP_Val _U_(0x2) /**< \brief (TC_CTRLBCLR) Force a stop */
-#define TC_CTRLBCLR_CMD_UPDATE_Val _U_(0x3) /**< \brief (TC_CTRLBCLR) Force update of double-buffered register */
-#define TC_CTRLBCLR_CMD_READSYNC_Val _U_(0x4) /**< \brief (TC_CTRLBCLR) Force a read synchronization of COUNT */
-#define TC_CTRLBCLR_CMD_DMAOS_Val _U_(0x5) /**< \brief (TC_CTRLBCLR) One-shot DMA trigger */
-#define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos)
-#define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
-#define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos)
-#define TC_CTRLBCLR_CMD_UPDATE (TC_CTRLBCLR_CMD_UPDATE_Val << TC_CTRLBCLR_CMD_Pos)
-#define TC_CTRLBCLR_CMD_READSYNC (TC_CTRLBCLR_CMD_READSYNC_Val << TC_CTRLBCLR_CMD_Pos)
-#define TC_CTRLBCLR_CMD_DMAOS (TC_CTRLBCLR_CMD_DMAOS_Val << TC_CTRLBCLR_CMD_Pos)
-#define TC_CTRLBCLR_MASK _U_(0xE7) /**< \brief (TC_CTRLBCLR) MASK Register */
-
-/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t LUPD:1; /*!< bit: 1 Lock Update */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */
- uint8_t :2; /*!< bit: 3.. 4 Reserved */
- uint8_t CMD:3; /*!< bit: 5.. 7 Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} TC_CTRLBSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */
-#define TC_CTRLBSET_RESETVALUE _U_(0x00) /**< \brief (TC_CTRLBSET reset_value) Control B Set */
-
-#define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */
-#define TC_CTRLBSET_DIR (_U_(0x1) << TC_CTRLBSET_DIR_Pos)
-#define TC_CTRLBSET_LUPD_Pos 1 /**< \brief (TC_CTRLBSET) Lock Update */
-#define TC_CTRLBSET_LUPD (_U_(0x1) << TC_CTRLBSET_LUPD_Pos)
-#define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot on Counter */
-#define TC_CTRLBSET_ONESHOT (_U_(0x1) << TC_CTRLBSET_ONESHOT_Pos)
-#define TC_CTRLBSET_CMD_Pos 5 /**< \brief (TC_CTRLBSET) Command */
-#define TC_CTRLBSET_CMD_Msk (_U_(0x7) << TC_CTRLBSET_CMD_Pos)
-#define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
-#define TC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< \brief (TC_CTRLBSET) No action */
-#define TC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
-#define TC_CTRLBSET_CMD_STOP_Val _U_(0x2) /**< \brief (TC_CTRLBSET) Force a stop */
-#define TC_CTRLBSET_CMD_UPDATE_Val _U_(0x3) /**< \brief (TC_CTRLBSET) Force update of double-buffered register */
-#define TC_CTRLBSET_CMD_READSYNC_Val _U_(0x4) /**< \brief (TC_CTRLBSET) Force a read synchronization of COUNT */
-#define TC_CTRLBSET_CMD_DMAOS_Val _U_(0x5) /**< \brief (TC_CTRLBSET) One-shot DMA trigger */
-#define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos)
-#define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
-#define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos)
-#define TC_CTRLBSET_CMD_UPDATE (TC_CTRLBSET_CMD_UPDATE_Val << TC_CTRLBSET_CMD_Pos)
-#define TC_CTRLBSET_CMD_READSYNC (TC_CTRLBSET_CMD_READSYNC_Val << TC_CTRLBSET_CMD_Pos)
-#define TC_CTRLBSET_CMD_DMAOS (TC_CTRLBSET_CMD_DMAOS_Val << TC_CTRLBSET_CMD_Pos)
-#define TC_CTRLBSET_MASK _U_(0xE7) /**< \brief (TC_CTRLBSET) MASK Register */
-
-/* -------- TC_EVCTRL : (TC Offset: 0x06) (R/W 16) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
- uint16_t :1; /*!< bit: 3 Reserved */
- uint16_t TCINV:1; /*!< bit: 4 TC Event Input Polarity */
- uint16_t TCEI:1; /*!< bit: 5 TC Event Enable */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t OVFEO:1; /*!< bit: 8 Event Output Enable */
- uint16_t :3; /*!< bit: 9..11 Reserved */
- uint16_t MCEO0:1; /*!< bit: 12 MC Event Output Enable 0 */
- uint16_t MCEO1:1; /*!< bit: 13 MC Event Output Enable 1 */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t :12; /*!< bit: 0..11 Reserved */
- uint16_t MCEO:2; /*!< bit: 12..13 MC Event Output Enable x */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} TC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_EVCTRL_OFFSET 0x06 /**< \brief (TC_EVCTRL offset) Event Control */
-#define TC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (TC_EVCTRL reset_value) Event Control */
-
-#define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */
-#define TC_EVCTRL_EVACT_Msk (_U_(0x7) << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
-#define TC_EVCTRL_EVACT_OFF_Val _U_(0x0) /**< \brief (TC_EVCTRL) Event action disabled */
-#define TC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1) /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
-#define TC_EVCTRL_EVACT_COUNT_Val _U_(0x2) /**< \brief (TC_EVCTRL) Count on event */
-#define TC_EVCTRL_EVACT_START_Val _U_(0x3) /**< \brief (TC_EVCTRL) Start TC on event */
-#define TC_EVCTRL_EVACT_STAMP_Val _U_(0x4) /**< \brief (TC_EVCTRL) Time stamp capture */
-#define TC_EVCTRL_EVACT_PPW_Val _U_(0x5) /**< \brief (TC_EVCTRL) Period catured in CC0, pulse width in CC1 */
-#define TC_EVCTRL_EVACT_PWP_Val _U_(0x6) /**< \brief (TC_EVCTRL) Period catured in CC1, pulse width in CC0 */
-#define TC_EVCTRL_EVACT_PW_Val _U_(0x7) /**< \brief (TC_EVCTRL) Pulse width capture */
-#define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_STAMP (TC_EVCTRL_EVACT_STAMP_Val << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_PW (TC_EVCTRL_EVACT_PW_Val << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Event Input Polarity */
-#define TC_EVCTRL_TCINV (_U_(0x1) << TC_EVCTRL_TCINV_Pos)
-#define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Enable */
-#define TC_EVCTRL_TCEI (_U_(0x1) << TC_EVCTRL_TCEI_Pos)
-#define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Event Output Enable */
-#define TC_EVCTRL_OVFEO (_U_(0x1) << TC_EVCTRL_OVFEO_Pos)
-#define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable 0 */
-#define TC_EVCTRL_MCEO0 (_U_(1) << TC_EVCTRL_MCEO0_Pos)
-#define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) MC Event Output Enable 1 */
-#define TC_EVCTRL_MCEO1 (_U_(1) << TC_EVCTRL_MCEO1_Pos)
-#define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable x */
-#define TC_EVCTRL_MCEO_Msk (_U_(0x3) << TC_EVCTRL_MCEO_Pos)
-#define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
-#define TC_EVCTRL_MASK _U_(0x3137) /**< \brief (TC_EVCTRL) MASK Register */
-
-/* -------- TC_INTENCLR : (TC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Disable */
- uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Disable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t MC0:1; /*!< bit: 4 MC Interrupt Disable 0 */
- uint8_t MC1:1; /*!< bit: 5 MC Interrupt Disable 1 */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Disable x */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} TC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_INTENCLR_OFFSET 0x08 /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
-#define TC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) OVF Interrupt Disable */
-#define TC_INTENCLR_OVF (_U_(0x1) << TC_INTENCLR_OVF_Pos)
-#define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) ERR Interrupt Disable */
-#define TC_INTENCLR_ERR (_U_(0x1) << TC_INTENCLR_ERR_Pos)
-#define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable 0 */
-#define TC_INTENCLR_MC0 (_U_(1) << TC_INTENCLR_MC0_Pos)
-#define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) MC Interrupt Disable 1 */
-#define TC_INTENCLR_MC1 (_U_(1) << TC_INTENCLR_MC1_Pos)
-#define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable x */
-#define TC_INTENCLR_MC_Msk (_U_(0x3) << TC_INTENCLR_MC_Pos)
-#define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
-#define TC_INTENCLR_MASK _U_(0x33) /**< \brief (TC_INTENCLR) MASK Register */
-
-/* -------- TC_INTENSET : (TC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Enable */
- uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t MC0:1; /*!< bit: 4 MC Interrupt Enable 0 */
- uint8_t MC1:1; /*!< bit: 5 MC Interrupt Enable 1 */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Enable x */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} TC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_INTENSET_OFFSET 0x09 /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
-#define TC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
-
-#define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) OVF Interrupt Enable */
-#define TC_INTENSET_OVF (_U_(0x1) << TC_INTENSET_OVF_Pos)
-#define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) ERR Interrupt Enable */
-#define TC_INTENSET_ERR (_U_(0x1) << TC_INTENSET_ERR_Pos)
-#define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable 0 */
-#define TC_INTENSET_MC0 (_U_(1) << TC_INTENSET_MC0_Pos)
-#define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) MC Interrupt Enable 1 */
-#define TC_INTENSET_MC1 (_U_(1) << TC_INTENSET_MC1_Pos)
-#define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable x */
-#define TC_INTENSET_MC_Msk (_U_(0x3) << TC_INTENSET_MC_Pos)
-#define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
-#define TC_INTENSET_MASK _U_(0x33) /**< \brief (TC_INTENSET) MASK Register */
-
-/* -------- TC_INTFLAG : (TC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Flag */
- __I uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Flag */
- __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
- __I uint8_t MC0:1; /*!< bit: 4 MC Interrupt Flag 0 */
- __I uint8_t MC1:1; /*!< bit: 5 MC Interrupt Flag 1 */
- __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t :4; /*!< bit: 0.. 3 Reserved */
- __I uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Flag x */
- __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} TC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_INTFLAG_OFFSET 0x0A /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define TC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) OVF Interrupt Flag */
-#define TC_INTFLAG_OVF (_U_(0x1) << TC_INTFLAG_OVF_Pos)
-#define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) ERR Interrupt Flag */
-#define TC_INTFLAG_ERR (_U_(0x1) << TC_INTFLAG_ERR_Pos)
-#define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag 0 */
-#define TC_INTFLAG_MC0 (_U_(1) << TC_INTFLAG_MC0_Pos)
-#define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) MC Interrupt Flag 1 */
-#define TC_INTFLAG_MC1 (_U_(1) << TC_INTFLAG_MC1_Pos)
-#define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag x */
-#define TC_INTFLAG_MC_Msk (_U_(0x3) << TC_INTFLAG_MC_Pos)
-#define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
-#define TC_INTFLAG_MASK _U_(0x33) /**< \brief (TC_INTFLAG) MASK Register */
-
-/* -------- TC_STATUS : (TC Offset: 0x0B) (R/W 8) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t STOP:1; /*!< bit: 0 Stop Status Flag */
- uint8_t SLAVE:1; /*!< bit: 1 Slave Status Flag */
- uint8_t :1; /*!< bit: 2 Reserved */
- uint8_t PERBUFV:1; /*!< bit: 3 Synchronization Busy Status */
- uint8_t CCBUFV0:1; /*!< bit: 4 Compare channel buffer 0 valid */
- uint8_t CCBUFV1:1; /*!< bit: 5 Compare channel buffer 1 valid */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t CCBUFV:2; /*!< bit: 4.. 5 Compare channel buffer x valid */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} TC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_STATUS_OFFSET 0x0B /**< \brief (TC_STATUS offset) Status */
-#define TC_STATUS_RESETVALUE _U_(0x01) /**< \brief (TC_STATUS reset_value) Status */
-
-#define TC_STATUS_STOP_Pos 0 /**< \brief (TC_STATUS) Stop Status Flag */
-#define TC_STATUS_STOP (_U_(0x1) << TC_STATUS_STOP_Pos)
-#define TC_STATUS_SLAVE_Pos 1 /**< \brief (TC_STATUS) Slave Status Flag */
-#define TC_STATUS_SLAVE (_U_(0x1) << TC_STATUS_SLAVE_Pos)
-#define TC_STATUS_PERBUFV_Pos 3 /**< \brief (TC_STATUS) Synchronization Busy Status */
-#define TC_STATUS_PERBUFV (_U_(0x1) << TC_STATUS_PERBUFV_Pos)
-#define TC_STATUS_CCBUFV0_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer 0 valid */
-#define TC_STATUS_CCBUFV0 (_U_(1) << TC_STATUS_CCBUFV0_Pos)
-#define TC_STATUS_CCBUFV1_Pos 5 /**< \brief (TC_STATUS) Compare channel buffer 1 valid */
-#define TC_STATUS_CCBUFV1 (_U_(1) << TC_STATUS_CCBUFV1_Pos)
-#define TC_STATUS_CCBUFV_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer x valid */
-#define TC_STATUS_CCBUFV_Msk (_U_(0x3) << TC_STATUS_CCBUFV_Pos)
-#define TC_STATUS_CCBUFV(value) (TC_STATUS_CCBUFV_Msk & ((value) << TC_STATUS_CCBUFV_Pos))
-#define TC_STATUS_MASK _U_(0x3B) /**< \brief (TC_STATUS) MASK Register */
-
-/* -------- TC_WAVE : (TC Offset: 0x0C) (R/W 8) Waveform Generation Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t WAVEGEN:2; /*!< bit: 0.. 1 Waveform Generation Mode */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} TC_WAVE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_WAVE_OFFSET 0x0C /**< \brief (TC_WAVE offset) Waveform Generation Control */
-#define TC_WAVE_RESETVALUE _U_(0x00) /**< \brief (TC_WAVE reset_value) Waveform Generation Control */
-
-#define TC_WAVE_WAVEGEN_Pos 0 /**< \brief (TC_WAVE) Waveform Generation Mode */
-#define TC_WAVE_WAVEGEN_Msk (_U_(0x3) << TC_WAVE_WAVEGEN_Pos)
-#define TC_WAVE_WAVEGEN(value) (TC_WAVE_WAVEGEN_Msk & ((value) << TC_WAVE_WAVEGEN_Pos))
-#define TC_WAVE_WAVEGEN_NFRQ_Val _U_(0x0) /**< \brief (TC_WAVE) Normal frequency */
-#define TC_WAVE_WAVEGEN_MFRQ_Val _U_(0x1) /**< \brief (TC_WAVE) Match frequency */
-#define TC_WAVE_WAVEGEN_NPWM_Val _U_(0x2) /**< \brief (TC_WAVE) Normal PWM */
-#define TC_WAVE_WAVEGEN_MPWM_Val _U_(0x3) /**< \brief (TC_WAVE) Match PWM */
-#define TC_WAVE_WAVEGEN_NFRQ (TC_WAVE_WAVEGEN_NFRQ_Val << TC_WAVE_WAVEGEN_Pos)
-#define TC_WAVE_WAVEGEN_MFRQ (TC_WAVE_WAVEGEN_MFRQ_Val << TC_WAVE_WAVEGEN_Pos)
-#define TC_WAVE_WAVEGEN_NPWM (TC_WAVE_WAVEGEN_NPWM_Val << TC_WAVE_WAVEGEN_Pos)
-#define TC_WAVE_WAVEGEN_MPWM (TC_WAVE_WAVEGEN_MPWM_Val << TC_WAVE_WAVEGEN_Pos)
-#define TC_WAVE_MASK _U_(0x03) /**< \brief (TC_WAVE) MASK Register */
-
-/* -------- TC_DRVCTRL : (TC Offset: 0x0D) (R/W 8) Control C -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t INVEN0:1; /*!< bit: 0 Output Waveform Invert Enable 0 */
- uint8_t INVEN1:1; /*!< bit: 1 Output Waveform Invert Enable 1 */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform Invert Enable x */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} TC_DRVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_DRVCTRL_OFFSET 0x0D /**< \brief (TC_DRVCTRL offset) Control C */
-#define TC_DRVCTRL_RESETVALUE _U_(0x00) /**< \brief (TC_DRVCTRL reset_value) Control C */
-
-#define TC_DRVCTRL_INVEN0_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 0 */
-#define TC_DRVCTRL_INVEN0 (_U_(1) << TC_DRVCTRL_INVEN0_Pos)
-#define TC_DRVCTRL_INVEN1_Pos 1 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 1 */
-#define TC_DRVCTRL_INVEN1 (_U_(1) << TC_DRVCTRL_INVEN1_Pos)
-#define TC_DRVCTRL_INVEN_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable x */
-#define TC_DRVCTRL_INVEN_Msk (_U_(0x3) << TC_DRVCTRL_INVEN_Pos)
-#define TC_DRVCTRL_INVEN(value) (TC_DRVCTRL_INVEN_Msk & ((value) << TC_DRVCTRL_INVEN_Pos))
-#define TC_DRVCTRL_MASK _U_(0x03) /**< \brief (TC_DRVCTRL) MASK Register */
-
-/* -------- TC_DBGCTRL : (TC Offset: 0x0F) (R/W 8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} TC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_DBGCTRL_OFFSET 0x0F /**< \brief (TC_DBGCTRL offset) Debug Control */
-#define TC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (TC_DBGCTRL reset_value) Debug Control */
-
-#define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Run During Debug */
-#define TC_DBGCTRL_DBGRUN (_U_(0x1) << TC_DBGCTRL_DBGRUN_Pos)
-#define TC_DBGCTRL_MASK _U_(0x01) /**< \brief (TC_DBGCTRL) MASK Register */
-
-/* -------- TC_SYNCBUSY : (TC Offset: 0x10) (R/ 32) Synchronization Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 swrst */
- uint32_t ENABLE:1; /*!< bit: 1 enable */
- uint32_t CTRLB:1; /*!< bit: 2 CTRLB */
- uint32_t STATUS:1; /*!< bit: 3 STATUS */
- uint32_t COUNT:1; /*!< bit: 4 Counter */
- uint32_t PER:1; /*!< bit: 5 Period */
- uint32_t CC0:1; /*!< bit: 6 Compare Channel 0 */
- uint32_t CC1:1; /*!< bit: 7 Compare Channel 1 */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :6; /*!< bit: 0.. 5 Reserved */
- uint32_t CC:2; /*!< bit: 6.. 7 Compare Channel x */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} TC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_SYNCBUSY_OFFSET 0x10 /**< \brief (TC_SYNCBUSY offset) Synchronization Status */
-#define TC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (TC_SYNCBUSY reset_value) Synchronization Status */
-
-#define TC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TC_SYNCBUSY) swrst */
-#define TC_SYNCBUSY_SWRST (_U_(0x1) << TC_SYNCBUSY_SWRST_Pos)
-#define TC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TC_SYNCBUSY) enable */
-#define TC_SYNCBUSY_ENABLE (_U_(0x1) << TC_SYNCBUSY_ENABLE_Pos)
-#define TC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TC_SYNCBUSY) CTRLB */
-#define TC_SYNCBUSY_CTRLB (_U_(0x1) << TC_SYNCBUSY_CTRLB_Pos)
-#define TC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TC_SYNCBUSY) STATUS */
-#define TC_SYNCBUSY_STATUS (_U_(0x1) << TC_SYNCBUSY_STATUS_Pos)
-#define TC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TC_SYNCBUSY) Counter */
-#define TC_SYNCBUSY_COUNT (_U_(0x1) << TC_SYNCBUSY_COUNT_Pos)
-#define TC_SYNCBUSY_PER_Pos 5 /**< \brief (TC_SYNCBUSY) Period */
-#define TC_SYNCBUSY_PER (_U_(0x1) << TC_SYNCBUSY_PER_Pos)
-#define TC_SYNCBUSY_CC0_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel 0 */
-#define TC_SYNCBUSY_CC0 (_U_(1) << TC_SYNCBUSY_CC0_Pos)
-#define TC_SYNCBUSY_CC1_Pos 7 /**< \brief (TC_SYNCBUSY) Compare Channel 1 */
-#define TC_SYNCBUSY_CC1 (_U_(1) << TC_SYNCBUSY_CC1_Pos)
-#define TC_SYNCBUSY_CC_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel x */
-#define TC_SYNCBUSY_CC_Msk (_U_(0x3) << TC_SYNCBUSY_CC_Pos)
-#define TC_SYNCBUSY_CC(value) (TC_SYNCBUSY_CC_Msk & ((value) << TC_SYNCBUSY_CC_Pos))
-#define TC_SYNCBUSY_MASK _U_(0x000000FF) /**< \brief (TC_SYNCBUSY) MASK Register */
-
-/* -------- TC_COUNT16_COUNT : (TC Offset: 0x14) (R/W 16) COUNT16 COUNT16 Count -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} TC_COUNT16_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT16_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Count */
-#define TC_COUNT16_COUNT_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Count */
-
-#define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Counter Value */
-#define TC_COUNT16_COUNT_COUNT_Msk (_U_(0xFFFF) << TC_COUNT16_COUNT_COUNT_Pos)
-#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
-#define TC_COUNT16_COUNT_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_COUNT) MASK Register */
-
-/* -------- TC_COUNT32_COUNT : (TC Offset: 0x14) (R/W 32) COUNT32 COUNT32 Count -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} TC_COUNT32_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT32_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Count */
-#define TC_COUNT32_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Count */
-
-#define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Counter Value */
-#define TC_COUNT32_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_COUNT_COUNT_Pos)
-#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
-#define TC_COUNT32_COUNT_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_COUNT) MASK Register */
-
-/* -------- TC_COUNT8_COUNT : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Count -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} TC_COUNT8_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT8_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Count */
-#define TC_COUNT8_COUNT_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Count */
-
-#define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */
-#define TC_COUNT8_COUNT_COUNT_Msk (_U_(0xFF) << TC_COUNT8_COUNT_COUNT_Pos)
-#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
-#define TC_COUNT8_COUNT_MASK _U_(0xFF) /**< \brief (TC_COUNT8_COUNT) MASK Register */
-
-/* -------- TC_COUNT8_PER : (TC Offset: 0x1B) (R/W 8) COUNT8 COUNT8 Period -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} TC_COUNT8_PER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT8_PER_OFFSET 0x1B /**< \brief (TC_COUNT8_PER offset) COUNT8 Period */
-#define TC_COUNT8_PER_RESETVALUE _U_(0xFF) /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period */
-
-#define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */
-#define TC_COUNT8_PER_PER_Msk (_U_(0xFF) << TC_COUNT8_PER_PER_Pos)
-#define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
-#define TC_COUNT8_PER_MASK _U_(0xFF) /**< \brief (TC_COUNT8_PER) MASK Register */
-
-/* -------- TC_COUNT16_CC : (TC Offset: 0x1C) (R/W 16) COUNT16 COUNT16 Compare and Capture -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t CC:16; /*!< bit: 0..15 Counter/Compare Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} TC_COUNT16_CC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT16_CC_OFFSET 0x1C /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare and Capture */
-#define TC_COUNT16_CC_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare and Capture */
-
-#define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Counter/Compare Value */
-#define TC_COUNT16_CC_CC_Msk (_U_(0xFFFF) << TC_COUNT16_CC_CC_Pos)
-#define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
-#define TC_COUNT16_CC_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_CC) MASK Register */
-
-/* -------- TC_COUNT32_CC : (TC Offset: 0x1C) (R/W 32) COUNT32 COUNT32 Compare and Capture -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CC:32; /*!< bit: 0..31 Counter/Compare Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} TC_COUNT32_CC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT32_CC_OFFSET 0x1C /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare and Capture */
-#define TC_COUNT32_CC_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare and Capture */
-
-#define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Counter/Compare Value */
-#define TC_COUNT32_CC_CC_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CC_CC_Pos)
-#define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
-#define TC_COUNT32_CC_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CC) MASK Register */
-
-/* -------- TC_COUNT8_CC : (TC Offset: 0x1C) (R/W 8) COUNT8 COUNT8 Compare and Capture -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t CC:8; /*!< bit: 0.. 7 Counter/Compare Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} TC_COUNT8_CC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT8_CC_OFFSET 0x1C /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare and Capture */
-#define TC_COUNT8_CC_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare and Capture */
-
-#define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Counter/Compare Value */
-#define TC_COUNT8_CC_CC_Msk (_U_(0xFF) << TC_COUNT8_CC_CC_Pos)
-#define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
-#define TC_COUNT8_CC_MASK _U_(0xFF) /**< \brief (TC_COUNT8_CC) MASK Register */
-
-/* -------- TC_COUNT8_PERBUF : (TC Offset: 0x2F) (R/W 8) COUNT8 COUNT8 Period Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t PERBUF:8; /*!< bit: 0.. 7 Period Buffer Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} TC_COUNT8_PERBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT8_PERBUF_OFFSET 0x2F /**< \brief (TC_COUNT8_PERBUF offset) COUNT8 Period Buffer */
-#define TC_COUNT8_PERBUF_RESETVALUE _U_(0xFF) /**< \brief (TC_COUNT8_PERBUF reset_value) COUNT8 Period Buffer */
-
-#define TC_COUNT8_PERBUF_PERBUF_Pos 0 /**< \brief (TC_COUNT8_PERBUF) Period Buffer Value */
-#define TC_COUNT8_PERBUF_PERBUF_Msk (_U_(0xFF) << TC_COUNT8_PERBUF_PERBUF_Pos)
-#define TC_COUNT8_PERBUF_PERBUF(value) (TC_COUNT8_PERBUF_PERBUF_Msk & ((value) << TC_COUNT8_PERBUF_PERBUF_Pos))
-#define TC_COUNT8_PERBUF_MASK _U_(0xFF) /**< \brief (TC_COUNT8_PERBUF) MASK Register */
-
-/* -------- TC_COUNT16_CCBUF : (TC Offset: 0x30) (R/W 16) COUNT16 COUNT16 Compare and Capture Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t CCBUF:16; /*!< bit: 0..15 Counter/Compare Buffer Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} TC_COUNT16_CCBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT16_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT16_CCBUF offset) COUNT16 Compare and Capture Buffer */
-#define TC_COUNT16_CCBUF_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_CCBUF reset_value) COUNT16 Compare and Capture Buffer */
-
-#define TC_COUNT16_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT16_CCBUF) Counter/Compare Buffer Value */
-#define TC_COUNT16_CCBUF_CCBUF_Msk (_U_(0xFFFF) << TC_COUNT16_CCBUF_CCBUF_Pos)
-#define TC_COUNT16_CCBUF_CCBUF(value) (TC_COUNT16_CCBUF_CCBUF_Msk & ((value) << TC_COUNT16_CCBUF_CCBUF_Pos))
-#define TC_COUNT16_CCBUF_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_CCBUF) MASK Register */
-
-/* -------- TC_COUNT32_CCBUF : (TC Offset: 0x30) (R/W 32) COUNT32 COUNT32 Compare and Capture Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CCBUF:32; /*!< bit: 0..31 Counter/Compare Buffer Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} TC_COUNT32_CCBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT32_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT32_CCBUF offset) COUNT32 Compare and Capture Buffer */
-#define TC_COUNT32_CCBUF_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_CCBUF reset_value) COUNT32 Compare and Capture Buffer */
-
-#define TC_COUNT32_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT32_CCBUF) Counter/Compare Buffer Value */
-#define TC_COUNT32_CCBUF_CCBUF_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CCBUF_CCBUF_Pos)
-#define TC_COUNT32_CCBUF_CCBUF(value) (TC_COUNT32_CCBUF_CCBUF_Msk & ((value) << TC_COUNT32_CCBUF_CCBUF_Pos))
-#define TC_COUNT32_CCBUF_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CCBUF) MASK Register */
-
-/* -------- TC_COUNT8_CCBUF : (TC Offset: 0x30) (R/W 8) COUNT8 COUNT8 Compare and Capture Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t CCBUF:8; /*!< bit: 0.. 7 Counter/Compare Buffer Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} TC_COUNT8_CCBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT8_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT8_CCBUF offset) COUNT8 Compare and Capture Buffer */
-#define TC_COUNT8_CCBUF_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_CCBUF reset_value) COUNT8 Compare and Capture Buffer */
-
-#define TC_COUNT8_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT8_CCBUF) Counter/Compare Buffer Value */
-#define TC_COUNT8_CCBUF_CCBUF_Msk (_U_(0xFF) << TC_COUNT8_CCBUF_CCBUF_Pos)
-#define TC_COUNT8_CCBUF_CCBUF(value) (TC_COUNT8_CCBUF_CCBUF_Msk & ((value) << TC_COUNT8_CCBUF_CCBUF_Pos))
-#define TC_COUNT8_CCBUF_MASK _U_(0xFF) /**< \brief (TC_COUNT8_CCBUF) MASK Register */
-
-/** \brief TC_COUNT8 hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* 8-bit Counter Mode */
- __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
- __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
- __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
- __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
- __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
- __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
- __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */
- __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
- RoReg8 Reserved1[0x1];
- __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
- __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
- __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Count */
- RoReg8 Reserved2[0x6];
- __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x1B (R/W 8) COUNT8 Period */
- __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 8) COUNT8 Compare and Capture */
- RoReg8 Reserved3[0x11];
- __IO TC_COUNT8_PERBUF_Type PERBUF; /**< \brief Offset: 0x2F (R/W 8) COUNT8 Period Buffer */
- __IO TC_COUNT8_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 8) COUNT8 Compare and Capture Buffer */
-} TcCount8;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief TC_COUNT16 hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* 16-bit Counter Mode */
- __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
- __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
- __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
- __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
- __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
- __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
- __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */
- __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
- RoReg8 Reserved1[0x1];
- __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
- __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
- __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 16) COUNT16 Count */
- RoReg8 Reserved2[0x6];
- __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 16) COUNT16 Compare and Capture */
- RoReg8 Reserved3[0x10];
- __IO TC_COUNT16_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 16) COUNT16 Compare and Capture Buffer */
-} TcCount16;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief TC_COUNT32 hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* 32-bit Counter Mode */
- __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
- __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
- __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
- __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
- __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
- __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
- __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */
- __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
- RoReg8 Reserved1[0x1];
- __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
- __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
- __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 32) COUNT32 Count */
- RoReg8 Reserved2[0x4];
- __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 32) COUNT32 Compare and Capture */
- RoReg8 Reserved3[0xC];
- __IO TC_COUNT32_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 32) COUNT32 Compare and Capture Buffer */
-} TcCount32;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
- TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
- TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
-} Tc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_TC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for TC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TC_COMPONENT_
+#define _SAME54_TC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR TC */
+/* ========================================================================== */
+/** \addtogroup SAME54_TC Basic Timer Counter */
+/*@{*/
+
+#define TC_U2249
+#define REV_TC 0x300
+
+/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:2; /*!< bit: 2.. 3 Timer Counter Mode */
+ uint32_t PRESCSYNC:2; /*!< bit: 4.. 5 Prescaler and Counter Synchronization */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 Clock On Demand */
+ uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint32_t ALOCK:1; /*!< bit: 11 Auto Lock */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t CAPTEN0:1; /*!< bit: 16 Capture Channel 0 Enable */
+ uint32_t CAPTEN1:1; /*!< bit: 17 Capture Channel 1 Enable */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t COPEN0:1; /*!< bit: 20 Capture On Pin 0 Enable */
+ uint32_t COPEN1:1; /*!< bit: 21 Capture On Pin 1 Enable */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t CAPTMODE0:2; /*!< bit: 24..25 Capture Mode Channel 0 */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t CAPTMODE1:2; /*!< bit: 27..28 Capture mode Channel 1 */
+ uint32_t :3; /*!< bit: 29..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t CAPTEN:2; /*!< bit: 16..17 Capture Channel x Enable */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t COPEN:2; /*!< bit: 20..21 Capture On Pin x Enable */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */
+#define TC_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (TC_CTRLA reset_value) Control A */
+
+#define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */
+#define TC_CTRLA_SWRST (_U_(0x1) << TC_CTRLA_SWRST_Pos)
+#define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */
+#define TC_CTRLA_ENABLE (_U_(0x1) << TC_CTRLA_ENABLE_Pos)
+#define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) Timer Counter Mode */
+#define TC_CTRLA_MODE_Msk (_U_(0x3) << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
+#define TC_CTRLA_MODE_COUNT16_Val _U_(0x0) /**< \brief (TC_CTRLA) Counter in 16-bit mode */
+#define TC_CTRLA_MODE_COUNT8_Val _U_(0x1) /**< \brief (TC_CTRLA) Counter in 8-bit mode */
+#define TC_CTRLA_MODE_COUNT32_Val _U_(0x2) /**< \brief (TC_CTRLA) Counter in 32-bit mode */
+#define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_PRESCSYNC_Pos 4 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
+#define TC_CTRLA_PRESCSYNC_Msk (_U_(0x3) << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
+#define TC_CTRLA_PRESCSYNC_GCLK_Val _U_(0x0) /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
+#define TC_CTRLA_PRESCSYNC_PRESC_Val _U_(0x1) /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
+#define TC_CTRLA_PRESCSYNC_RESYNC_Val _U_(0x2) /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock and reset the prescaler counter */
+#define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TC_CTRLA) Run during Standby */
+#define TC_CTRLA_RUNSTDBY (_U_(0x1) << TC_CTRLA_RUNSTDBY_Pos)
+#define TC_CTRLA_ONDEMAND_Pos 7 /**< \brief (TC_CTRLA) Clock On Demand */
+#define TC_CTRLA_ONDEMAND (_U_(0x1) << TC_CTRLA_ONDEMAND_Pos)
+#define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */
+#define TC_CTRLA_PRESCALER_Msk (_U_(0x7) << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
+#define TC_CTRLA_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
+#define TC_CTRLA_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
+#define TC_CTRLA_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
+#define TC_CTRLA_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
+#define TC_CTRLA_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
+#define TC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
+#define TC_CTRLA_PRESCALER_DIV256_Val _U_(0x6) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
+#define TC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
+#define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_ALOCK_Pos 11 /**< \brief (TC_CTRLA) Auto Lock */
+#define TC_CTRLA_ALOCK (_U_(0x1) << TC_CTRLA_ALOCK_Pos)
+#define TC_CTRLA_CAPTEN0_Pos 16 /**< \brief (TC_CTRLA) Capture Channel 0 Enable */
+#define TC_CTRLA_CAPTEN0 (_U_(1) << TC_CTRLA_CAPTEN0_Pos)
+#define TC_CTRLA_CAPTEN1_Pos 17 /**< \brief (TC_CTRLA) Capture Channel 1 Enable */
+#define TC_CTRLA_CAPTEN1 (_U_(1) << TC_CTRLA_CAPTEN1_Pos)
+#define TC_CTRLA_CAPTEN_Pos 16 /**< \brief (TC_CTRLA) Capture Channel x Enable */
+#define TC_CTRLA_CAPTEN_Msk (_U_(0x3) << TC_CTRLA_CAPTEN_Pos)
+#define TC_CTRLA_CAPTEN(value) (TC_CTRLA_CAPTEN_Msk & ((value) << TC_CTRLA_CAPTEN_Pos))
+#define TC_CTRLA_COPEN0_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin 0 Enable */
+#define TC_CTRLA_COPEN0 (_U_(1) << TC_CTRLA_COPEN0_Pos)
+#define TC_CTRLA_COPEN1_Pos 21 /**< \brief (TC_CTRLA) Capture On Pin 1 Enable */
+#define TC_CTRLA_COPEN1 (_U_(1) << TC_CTRLA_COPEN1_Pos)
+#define TC_CTRLA_COPEN_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin x Enable */
+#define TC_CTRLA_COPEN_Msk (_U_(0x3) << TC_CTRLA_COPEN_Pos)
+#define TC_CTRLA_COPEN(value) (TC_CTRLA_COPEN_Msk & ((value) << TC_CTRLA_COPEN_Pos))
+#define TC_CTRLA_CAPTMODE0_Pos 24 /**< \brief (TC_CTRLA) Capture Mode Channel 0 */
+#define TC_CTRLA_CAPTMODE0_Msk (_U_(0x3) << TC_CTRLA_CAPTMODE0_Pos)
+#define TC_CTRLA_CAPTMODE0(value) (TC_CTRLA_CAPTMODE0_Msk & ((value) << TC_CTRLA_CAPTMODE0_Pos))
+#define TC_CTRLA_CAPTMODE0_DEFAULT_Val _U_(0x0) /**< \brief (TC_CTRLA) Default capture */
+#define TC_CTRLA_CAPTMODE0_CAPTMIN_Val _U_(0x1) /**< \brief (TC_CTRLA) Minimum capture */
+#define TC_CTRLA_CAPTMODE0_CAPTMAX_Val _U_(0x2) /**< \brief (TC_CTRLA) Maximum capture */
+#define TC_CTRLA_CAPTMODE0_DEFAULT (TC_CTRLA_CAPTMODE0_DEFAULT_Val << TC_CTRLA_CAPTMODE0_Pos)
+#define TC_CTRLA_CAPTMODE0_CAPTMIN (TC_CTRLA_CAPTMODE0_CAPTMIN_Val << TC_CTRLA_CAPTMODE0_Pos)
+#define TC_CTRLA_CAPTMODE0_CAPTMAX (TC_CTRLA_CAPTMODE0_CAPTMAX_Val << TC_CTRLA_CAPTMODE0_Pos)
+#define TC_CTRLA_CAPTMODE1_Pos 27 /**< \brief (TC_CTRLA) Capture mode Channel 1 */
+#define TC_CTRLA_CAPTMODE1_Msk (_U_(0x3) << TC_CTRLA_CAPTMODE1_Pos)
+#define TC_CTRLA_CAPTMODE1(value) (TC_CTRLA_CAPTMODE1_Msk & ((value) << TC_CTRLA_CAPTMODE1_Pos))
+#define TC_CTRLA_CAPTMODE1_DEFAULT_Val _U_(0x0) /**< \brief (TC_CTRLA) Default capture */
+#define TC_CTRLA_CAPTMODE1_CAPTMIN_Val _U_(0x1) /**< \brief (TC_CTRLA) Minimum capture */
+#define TC_CTRLA_CAPTMODE1_CAPTMAX_Val _U_(0x2) /**< \brief (TC_CTRLA) Maximum capture */
+#define TC_CTRLA_CAPTMODE1_DEFAULT (TC_CTRLA_CAPTMODE1_DEFAULT_Val << TC_CTRLA_CAPTMODE1_Pos)
+#define TC_CTRLA_CAPTMODE1_CAPTMIN (TC_CTRLA_CAPTMODE1_CAPTMIN_Val << TC_CTRLA_CAPTMODE1_Pos)
+#define TC_CTRLA_CAPTMODE1_CAPTMAX (TC_CTRLA_CAPTMODE1_CAPTMAX_Val << TC_CTRLA_CAPTMODE1_Pos)
+#define TC_CTRLA_MASK _U_(0x1B330FFF) /**< \brief (TC_CTRLA) MASK Register */
+
+/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */
+ uint8_t :2; /*!< bit: 3.. 4 Reserved */
+ uint8_t CMD:3; /*!< bit: 5.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */
+#define TC_CTRLBCLR_RESETVALUE _U_(0x00) /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
+
+#define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */
+#define TC_CTRLBCLR_DIR (_U_(0x1) << TC_CTRLBCLR_DIR_Pos)
+#define TC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TC_CTRLBCLR) Lock Update */
+#define TC_CTRLBCLR_LUPD (_U_(0x1) << TC_CTRLBCLR_LUPD_Pos)
+#define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot on Counter */
+#define TC_CTRLBCLR_ONESHOT (_U_(0x1) << TC_CTRLBCLR_ONESHOT_Pos)
+#define TC_CTRLBCLR_CMD_Pos 5 /**< \brief (TC_CTRLBCLR) Command */
+#define TC_CTRLBCLR_CMD_Msk (_U_(0x7) << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
+#define TC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< \brief (TC_CTRLBCLR) No action */
+#define TC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
+#define TC_CTRLBCLR_CMD_STOP_Val _U_(0x2) /**< \brief (TC_CTRLBCLR) Force a stop */
+#define TC_CTRLBCLR_CMD_UPDATE_Val _U_(0x3) /**< \brief (TC_CTRLBCLR) Force update of double-buffered register */
+#define TC_CTRLBCLR_CMD_READSYNC_Val _U_(0x4) /**< \brief (TC_CTRLBCLR) Force a read synchronization of COUNT */
+#define TC_CTRLBCLR_CMD_DMAOS_Val _U_(0x5) /**< \brief (TC_CTRLBCLR) One-shot DMA trigger */
+#define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_UPDATE (TC_CTRLBCLR_CMD_UPDATE_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_READSYNC (TC_CTRLBCLR_CMD_READSYNC_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_DMAOS (TC_CTRLBCLR_CMD_DMAOS_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_MASK _U_(0xE7) /**< \brief (TC_CTRLBCLR) MASK Register */
+
+/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */
+ uint8_t :2; /*!< bit: 3.. 4 Reserved */
+ uint8_t CMD:3; /*!< bit: 5.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */
+#define TC_CTRLBSET_RESETVALUE _U_(0x00) /**< \brief (TC_CTRLBSET reset_value) Control B Set */
+
+#define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */
+#define TC_CTRLBSET_DIR (_U_(0x1) << TC_CTRLBSET_DIR_Pos)
+#define TC_CTRLBSET_LUPD_Pos 1 /**< \brief (TC_CTRLBSET) Lock Update */
+#define TC_CTRLBSET_LUPD (_U_(0x1) << TC_CTRLBSET_LUPD_Pos)
+#define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot on Counter */
+#define TC_CTRLBSET_ONESHOT (_U_(0x1) << TC_CTRLBSET_ONESHOT_Pos)
+#define TC_CTRLBSET_CMD_Pos 5 /**< \brief (TC_CTRLBSET) Command */
+#define TC_CTRLBSET_CMD_Msk (_U_(0x7) << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
+#define TC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< \brief (TC_CTRLBSET) No action */
+#define TC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
+#define TC_CTRLBSET_CMD_STOP_Val _U_(0x2) /**< \brief (TC_CTRLBSET) Force a stop */
+#define TC_CTRLBSET_CMD_UPDATE_Val _U_(0x3) /**< \brief (TC_CTRLBSET) Force update of double-buffered register */
+#define TC_CTRLBSET_CMD_READSYNC_Val _U_(0x4) /**< \brief (TC_CTRLBSET) Force a read synchronization of COUNT */
+#define TC_CTRLBSET_CMD_DMAOS_Val _U_(0x5) /**< \brief (TC_CTRLBSET) One-shot DMA trigger */
+#define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_UPDATE (TC_CTRLBSET_CMD_UPDATE_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_READSYNC (TC_CTRLBSET_CMD_READSYNC_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_DMAOS (TC_CTRLBSET_CMD_DMAOS_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_MASK _U_(0xE7) /**< \brief (TC_CTRLBSET) MASK Register */
+
+/* -------- TC_EVCTRL : (TC Offset: 0x06) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t TCINV:1; /*!< bit: 4 TC Event Input Polarity */
+ uint16_t TCEI:1; /*!< bit: 5 TC Event Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 8 Event Output Enable */
+ uint16_t :3; /*!< bit: 9..11 Reserved */
+ uint16_t MCEO0:1; /*!< bit: 12 MC Event Output Enable 0 */
+ uint16_t MCEO1:1; /*!< bit: 13 MC Event Output Enable 1 */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :12; /*!< bit: 0..11 Reserved */
+ uint16_t MCEO:2; /*!< bit: 12..13 MC Event Output Enable x */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_EVCTRL_OFFSET 0x06 /**< \brief (TC_EVCTRL offset) Event Control */
+#define TC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (TC_EVCTRL reset_value) Event Control */
+
+#define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */
+#define TC_EVCTRL_EVACT_Msk (_U_(0x7) << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
+#define TC_EVCTRL_EVACT_OFF_Val _U_(0x0) /**< \brief (TC_EVCTRL) Event action disabled */
+#define TC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1) /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
+#define TC_EVCTRL_EVACT_COUNT_Val _U_(0x2) /**< \brief (TC_EVCTRL) Count on event */
+#define TC_EVCTRL_EVACT_START_Val _U_(0x3) /**< \brief (TC_EVCTRL) Start TC on event */
+#define TC_EVCTRL_EVACT_STAMP_Val _U_(0x4) /**< \brief (TC_EVCTRL) Time stamp capture */
+#define TC_EVCTRL_EVACT_PPW_Val _U_(0x5) /**< \brief (TC_EVCTRL) Period catured in CC0, pulse width in CC1 */
+#define TC_EVCTRL_EVACT_PWP_Val _U_(0x6) /**< \brief (TC_EVCTRL) Period catured in CC1, pulse width in CC0 */
+#define TC_EVCTRL_EVACT_PW_Val _U_(0x7) /**< \brief (TC_EVCTRL) Pulse width capture */
+#define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_STAMP (TC_EVCTRL_EVACT_STAMP_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PW (TC_EVCTRL_EVACT_PW_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Event Input Polarity */
+#define TC_EVCTRL_TCINV (_U_(0x1) << TC_EVCTRL_TCINV_Pos)
+#define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Enable */
+#define TC_EVCTRL_TCEI (_U_(0x1) << TC_EVCTRL_TCEI_Pos)
+#define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Event Output Enable */
+#define TC_EVCTRL_OVFEO (_U_(0x1) << TC_EVCTRL_OVFEO_Pos)
+#define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable 0 */
+#define TC_EVCTRL_MCEO0 (_U_(1) << TC_EVCTRL_MCEO0_Pos)
+#define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) MC Event Output Enable 1 */
+#define TC_EVCTRL_MCEO1 (_U_(1) << TC_EVCTRL_MCEO1_Pos)
+#define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable x */
+#define TC_EVCTRL_MCEO_Msk (_U_(0x3) << TC_EVCTRL_MCEO_Pos)
+#define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
+#define TC_EVCTRL_MASK _U_(0x3137) /**< \brief (TC_EVCTRL) MASK Register */
+
+/* -------- TC_INTENCLR : (TC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Disable */
+ uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Disable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t MC0:1; /*!< bit: 4 MC Interrupt Disable 0 */
+ uint8_t MC1:1; /*!< bit: 5 MC Interrupt Disable 1 */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Disable x */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENCLR_OFFSET 0x08 /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
+#define TC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) OVF Interrupt Disable */
+#define TC_INTENCLR_OVF (_U_(0x1) << TC_INTENCLR_OVF_Pos)
+#define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) ERR Interrupt Disable */
+#define TC_INTENCLR_ERR (_U_(0x1) << TC_INTENCLR_ERR_Pos)
+#define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable 0 */
+#define TC_INTENCLR_MC0 (_U_(1) << TC_INTENCLR_MC0_Pos)
+#define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) MC Interrupt Disable 1 */
+#define TC_INTENCLR_MC1 (_U_(1) << TC_INTENCLR_MC1_Pos)
+#define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable x */
+#define TC_INTENCLR_MC_Msk (_U_(0x3) << TC_INTENCLR_MC_Pos)
+#define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
+#define TC_INTENCLR_MASK _U_(0x33) /**< \brief (TC_INTENCLR) MASK Register */
+
+/* -------- TC_INTENSET : (TC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Enable */
+ uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t MC0:1; /*!< bit: 4 MC Interrupt Enable 0 */
+ uint8_t MC1:1; /*!< bit: 5 MC Interrupt Enable 1 */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Enable x */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENSET_OFFSET 0x09 /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
+#define TC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) OVF Interrupt Enable */
+#define TC_INTENSET_OVF (_U_(0x1) << TC_INTENSET_OVF_Pos)
+#define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) ERR Interrupt Enable */
+#define TC_INTENSET_ERR (_U_(0x1) << TC_INTENSET_ERR_Pos)
+#define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable 0 */
+#define TC_INTENSET_MC0 (_U_(1) << TC_INTENSET_MC0_Pos)
+#define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) MC Interrupt Enable 1 */
+#define TC_INTENSET_MC1 (_U_(1) << TC_INTENSET_MC1_Pos)
+#define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable x */
+#define TC_INTENSET_MC_Msk (_U_(0x3) << TC_INTENSET_MC_Pos)
+#define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
+#define TC_INTENSET_MASK _U_(0x33) /**< \brief (TC_INTENSET) MASK Register */
+
+/* -------- TC_INTFLAG : (TC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Flag */
+ __I uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Flag */
+ __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint8_t MC0:1; /*!< bit: 4 MC Interrupt Flag 0 */
+ __I uint8_t MC1:1; /*!< bit: 5 MC Interrupt Flag 1 */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ __I uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Flag x */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTFLAG_OFFSET 0x0A /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) OVF Interrupt Flag */
+#define TC_INTFLAG_OVF (_U_(0x1) << TC_INTFLAG_OVF_Pos)
+#define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) ERR Interrupt Flag */
+#define TC_INTFLAG_ERR (_U_(0x1) << TC_INTFLAG_ERR_Pos)
+#define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag 0 */
+#define TC_INTFLAG_MC0 (_U_(1) << TC_INTFLAG_MC0_Pos)
+#define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) MC Interrupt Flag 1 */
+#define TC_INTFLAG_MC1 (_U_(1) << TC_INTFLAG_MC1_Pos)
+#define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag x */
+#define TC_INTFLAG_MC_Msk (_U_(0x3) << TC_INTFLAG_MC_Pos)
+#define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
+#define TC_INTFLAG_MASK _U_(0x33) /**< \brief (TC_INTFLAG) MASK Register */
+
+/* -------- TC_STATUS : (TC Offset: 0x0B) (R/W 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STOP:1; /*!< bit: 0 Stop Status Flag */
+ uint8_t SLAVE:1; /*!< bit: 1 Slave Status Flag */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t PERBUFV:1; /*!< bit: 3 Synchronization Busy Status */
+ uint8_t CCBUFV0:1; /*!< bit: 4 Compare channel buffer 0 valid */
+ uint8_t CCBUFV1:1; /*!< bit: 5 Compare channel buffer 1 valid */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t CCBUFV:2; /*!< bit: 4.. 5 Compare channel buffer x valid */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_STATUS_OFFSET 0x0B /**< \brief (TC_STATUS offset) Status */
+#define TC_STATUS_RESETVALUE _U_(0x01) /**< \brief (TC_STATUS reset_value) Status */
+
+#define TC_STATUS_STOP_Pos 0 /**< \brief (TC_STATUS) Stop Status Flag */
+#define TC_STATUS_STOP (_U_(0x1) << TC_STATUS_STOP_Pos)
+#define TC_STATUS_SLAVE_Pos 1 /**< \brief (TC_STATUS) Slave Status Flag */
+#define TC_STATUS_SLAVE (_U_(0x1) << TC_STATUS_SLAVE_Pos)
+#define TC_STATUS_PERBUFV_Pos 3 /**< \brief (TC_STATUS) Synchronization Busy Status */
+#define TC_STATUS_PERBUFV (_U_(0x1) << TC_STATUS_PERBUFV_Pos)
+#define TC_STATUS_CCBUFV0_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer 0 valid */
+#define TC_STATUS_CCBUFV0 (_U_(1) << TC_STATUS_CCBUFV0_Pos)
+#define TC_STATUS_CCBUFV1_Pos 5 /**< \brief (TC_STATUS) Compare channel buffer 1 valid */
+#define TC_STATUS_CCBUFV1 (_U_(1) << TC_STATUS_CCBUFV1_Pos)
+#define TC_STATUS_CCBUFV_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer x valid */
+#define TC_STATUS_CCBUFV_Msk (_U_(0x3) << TC_STATUS_CCBUFV_Pos)
+#define TC_STATUS_CCBUFV(value) (TC_STATUS_CCBUFV_Msk & ((value) << TC_STATUS_CCBUFV_Pos))
+#define TC_STATUS_MASK _U_(0x3B) /**< \brief (TC_STATUS) MASK Register */
+
+/* -------- TC_WAVE : (TC Offset: 0x0C) (R/W 8) Waveform Generation Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t WAVEGEN:2; /*!< bit: 0.. 1 Waveform Generation Mode */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_WAVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_WAVE_OFFSET 0x0C /**< \brief (TC_WAVE offset) Waveform Generation Control */
+#define TC_WAVE_RESETVALUE _U_(0x00) /**< \brief (TC_WAVE reset_value) Waveform Generation Control */
+
+#define TC_WAVE_WAVEGEN_Pos 0 /**< \brief (TC_WAVE) Waveform Generation Mode */
+#define TC_WAVE_WAVEGEN_Msk (_U_(0x3) << TC_WAVE_WAVEGEN_Pos)
+#define TC_WAVE_WAVEGEN(value) (TC_WAVE_WAVEGEN_Msk & ((value) << TC_WAVE_WAVEGEN_Pos))
+#define TC_WAVE_WAVEGEN_NFRQ_Val _U_(0x0) /**< \brief (TC_WAVE) Normal frequency */
+#define TC_WAVE_WAVEGEN_MFRQ_Val _U_(0x1) /**< \brief (TC_WAVE) Match frequency */
+#define TC_WAVE_WAVEGEN_NPWM_Val _U_(0x2) /**< \brief (TC_WAVE) Normal PWM */
+#define TC_WAVE_WAVEGEN_MPWM_Val _U_(0x3) /**< \brief (TC_WAVE) Match PWM */
+#define TC_WAVE_WAVEGEN_NFRQ (TC_WAVE_WAVEGEN_NFRQ_Val << TC_WAVE_WAVEGEN_Pos)
+#define TC_WAVE_WAVEGEN_MFRQ (TC_WAVE_WAVEGEN_MFRQ_Val << TC_WAVE_WAVEGEN_Pos)
+#define TC_WAVE_WAVEGEN_NPWM (TC_WAVE_WAVEGEN_NPWM_Val << TC_WAVE_WAVEGEN_Pos)
+#define TC_WAVE_WAVEGEN_MPWM (TC_WAVE_WAVEGEN_MPWM_Val << TC_WAVE_WAVEGEN_Pos)
+#define TC_WAVE_MASK _U_(0x03) /**< \brief (TC_WAVE) MASK Register */
+
+/* -------- TC_DRVCTRL : (TC Offset: 0x0D) (R/W 8) Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t INVEN0:1; /*!< bit: 0 Output Waveform Invert Enable 0 */
+ uint8_t INVEN1:1; /*!< bit: 1 Output Waveform Invert Enable 1 */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform Invert Enable x */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_DRVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_DRVCTRL_OFFSET 0x0D /**< \brief (TC_DRVCTRL offset) Control C */
+#define TC_DRVCTRL_RESETVALUE _U_(0x00) /**< \brief (TC_DRVCTRL reset_value) Control C */
+
+#define TC_DRVCTRL_INVEN0_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 0 */
+#define TC_DRVCTRL_INVEN0 (_U_(1) << TC_DRVCTRL_INVEN0_Pos)
+#define TC_DRVCTRL_INVEN1_Pos 1 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 1 */
+#define TC_DRVCTRL_INVEN1 (_U_(1) << TC_DRVCTRL_INVEN1_Pos)
+#define TC_DRVCTRL_INVEN_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable x */
+#define TC_DRVCTRL_INVEN_Msk (_U_(0x3) << TC_DRVCTRL_INVEN_Pos)
+#define TC_DRVCTRL_INVEN(value) (TC_DRVCTRL_INVEN_Msk & ((value) << TC_DRVCTRL_INVEN_Pos))
+#define TC_DRVCTRL_MASK _U_(0x03) /**< \brief (TC_DRVCTRL) MASK Register */
+
+/* -------- TC_DBGCTRL : (TC Offset: 0x0F) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_DBGCTRL_OFFSET 0x0F /**< \brief (TC_DBGCTRL offset) Debug Control */
+#define TC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (TC_DBGCTRL reset_value) Debug Control */
+
+#define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Run During Debug */
+#define TC_DBGCTRL_DBGRUN (_U_(0x1) << TC_DBGCTRL_DBGRUN_Pos)
+#define TC_DBGCTRL_MASK _U_(0x01) /**< \brief (TC_DBGCTRL) MASK Register */
+
+/* -------- TC_SYNCBUSY : (TC Offset: 0x10) (R/ 32) Synchronization Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 swrst */
+ uint32_t ENABLE:1; /*!< bit: 1 enable */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB */
+ uint32_t STATUS:1; /*!< bit: 3 STATUS */
+ uint32_t COUNT:1; /*!< bit: 4 Counter */
+ uint32_t PER:1; /*!< bit: 5 Period */
+ uint32_t CC0:1; /*!< bit: 6 Compare Channel 0 */
+ uint32_t CC1:1; /*!< bit: 7 Compare Channel 1 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :6; /*!< bit: 0.. 5 Reserved */
+ uint32_t CC:2; /*!< bit: 6.. 7 Compare Channel x */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_SYNCBUSY_OFFSET 0x10 /**< \brief (TC_SYNCBUSY offset) Synchronization Status */
+#define TC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (TC_SYNCBUSY reset_value) Synchronization Status */
+
+#define TC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TC_SYNCBUSY) swrst */
+#define TC_SYNCBUSY_SWRST (_U_(0x1) << TC_SYNCBUSY_SWRST_Pos)
+#define TC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TC_SYNCBUSY) enable */
+#define TC_SYNCBUSY_ENABLE (_U_(0x1) << TC_SYNCBUSY_ENABLE_Pos)
+#define TC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TC_SYNCBUSY) CTRLB */
+#define TC_SYNCBUSY_CTRLB (_U_(0x1) << TC_SYNCBUSY_CTRLB_Pos)
+#define TC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TC_SYNCBUSY) STATUS */
+#define TC_SYNCBUSY_STATUS (_U_(0x1) << TC_SYNCBUSY_STATUS_Pos)
+#define TC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TC_SYNCBUSY) Counter */
+#define TC_SYNCBUSY_COUNT (_U_(0x1) << TC_SYNCBUSY_COUNT_Pos)
+#define TC_SYNCBUSY_PER_Pos 5 /**< \brief (TC_SYNCBUSY) Period */
+#define TC_SYNCBUSY_PER (_U_(0x1) << TC_SYNCBUSY_PER_Pos)
+#define TC_SYNCBUSY_CC0_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel 0 */
+#define TC_SYNCBUSY_CC0 (_U_(1) << TC_SYNCBUSY_CC0_Pos)
+#define TC_SYNCBUSY_CC1_Pos 7 /**< \brief (TC_SYNCBUSY) Compare Channel 1 */
+#define TC_SYNCBUSY_CC1 (_U_(1) << TC_SYNCBUSY_CC1_Pos)
+#define TC_SYNCBUSY_CC_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel x */
+#define TC_SYNCBUSY_CC_Msk (_U_(0x3) << TC_SYNCBUSY_CC_Pos)
+#define TC_SYNCBUSY_CC(value) (TC_SYNCBUSY_CC_Msk & ((value) << TC_SYNCBUSY_CC_Pos))
+#define TC_SYNCBUSY_MASK _U_(0x000000FF) /**< \brief (TC_SYNCBUSY) MASK Register */
+
+/* -------- TC_COUNT16_COUNT : (TC Offset: 0x14) (R/W 16) COUNT16 COUNT16 Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_COUNT16_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Count */
+#define TC_COUNT16_COUNT_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Count */
+
+#define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Counter Value */
+#define TC_COUNT16_COUNT_COUNT_Msk (_U_(0xFFFF) << TC_COUNT16_COUNT_COUNT_Pos)
+#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
+#define TC_COUNT16_COUNT_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_COUNT) MASK Register */
+
+/* -------- TC_COUNT32_COUNT : (TC Offset: 0x14) (R/W 32) COUNT32 COUNT32 Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TC_COUNT32_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Count */
+#define TC_COUNT32_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Count */
+
+#define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Counter Value */
+#define TC_COUNT32_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_COUNT_COUNT_Pos)
+#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
+#define TC_COUNT32_COUNT_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_COUNT : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Count */
+#define TC_COUNT8_COUNT_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Count */
+
+#define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */
+#define TC_COUNT8_COUNT_COUNT_Msk (_U_(0xFF) << TC_COUNT8_COUNT_COUNT_Pos)
+#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
+#define TC_COUNT8_COUNT_MASK _U_(0xFF) /**< \brief (TC_COUNT8_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_PER : (TC Offset: 0x1B) (R/W 8) COUNT8 COUNT8 Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_PER_OFFSET 0x1B /**< \brief (TC_COUNT8_PER offset) COUNT8 Period */
+#define TC_COUNT8_PER_RESETVALUE _U_(0xFF) /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period */
+
+#define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */
+#define TC_COUNT8_PER_PER_Msk (_U_(0xFF) << TC_COUNT8_PER_PER_Pos)
+#define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
+#define TC_COUNT8_PER_MASK _U_(0xFF) /**< \brief (TC_COUNT8_PER) MASK Register */
+
+/* -------- TC_COUNT16_CC : (TC Offset: 0x1C) (R/W 16) COUNT16 COUNT16 Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CC:16; /*!< bit: 0..15 Counter/Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_COUNT16_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_CC_OFFSET 0x1C /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare and Capture */
+#define TC_COUNT16_CC_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare and Capture */
+
+#define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Counter/Compare Value */
+#define TC_COUNT16_CC_CC_Msk (_U_(0xFFFF) << TC_COUNT16_CC_CC_Pos)
+#define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
+#define TC_COUNT16_CC_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_CC) MASK Register */
+
+/* -------- TC_COUNT32_CC : (TC Offset: 0x1C) (R/W 32) COUNT32 COUNT32 Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CC:32; /*!< bit: 0..31 Counter/Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TC_COUNT32_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_CC_OFFSET 0x1C /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare and Capture */
+#define TC_COUNT32_CC_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare and Capture */
+
+#define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Counter/Compare Value */
+#define TC_COUNT32_CC_CC_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CC_CC_Pos)
+#define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
+#define TC_COUNT32_CC_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CC) MASK Register */
+
+/* -------- TC_COUNT8_CC : (TC Offset: 0x1C) (R/W 8) COUNT8 COUNT8 Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CC:8; /*!< bit: 0.. 7 Counter/Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_CC_OFFSET 0x1C /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare and Capture */
+#define TC_COUNT8_CC_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare and Capture */
+
+#define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Counter/Compare Value */
+#define TC_COUNT8_CC_CC_Msk (_U_(0xFF) << TC_COUNT8_CC_CC_Pos)
+#define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
+#define TC_COUNT8_CC_MASK _U_(0xFF) /**< \brief (TC_COUNT8_CC) MASK Register */
+
+/* -------- TC_COUNT8_PERBUF : (TC Offset: 0x2F) (R/W 8) COUNT8 COUNT8 Period Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PERBUF:8; /*!< bit: 0.. 7 Period Buffer Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_PERBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_PERBUF_OFFSET 0x2F /**< \brief (TC_COUNT8_PERBUF offset) COUNT8 Period Buffer */
+#define TC_COUNT8_PERBUF_RESETVALUE _U_(0xFF) /**< \brief (TC_COUNT8_PERBUF reset_value) COUNT8 Period Buffer */
+
+#define TC_COUNT8_PERBUF_PERBUF_Pos 0 /**< \brief (TC_COUNT8_PERBUF) Period Buffer Value */
+#define TC_COUNT8_PERBUF_PERBUF_Msk (_U_(0xFF) << TC_COUNT8_PERBUF_PERBUF_Pos)
+#define TC_COUNT8_PERBUF_PERBUF(value) (TC_COUNT8_PERBUF_PERBUF_Msk & ((value) << TC_COUNT8_PERBUF_PERBUF_Pos))
+#define TC_COUNT8_PERBUF_MASK _U_(0xFF) /**< \brief (TC_COUNT8_PERBUF) MASK Register */
+
+/* -------- TC_COUNT16_CCBUF : (TC Offset: 0x30) (R/W 16) COUNT16 COUNT16 Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CCBUF:16; /*!< bit: 0..15 Counter/Compare Buffer Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_COUNT16_CCBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT16_CCBUF offset) COUNT16 Compare and Capture Buffer */
+#define TC_COUNT16_CCBUF_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_CCBUF reset_value) COUNT16 Compare and Capture Buffer */
+
+#define TC_COUNT16_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT16_CCBUF) Counter/Compare Buffer Value */
+#define TC_COUNT16_CCBUF_CCBUF_Msk (_U_(0xFFFF) << TC_COUNT16_CCBUF_CCBUF_Pos)
+#define TC_COUNT16_CCBUF_CCBUF(value) (TC_COUNT16_CCBUF_CCBUF_Msk & ((value) << TC_COUNT16_CCBUF_CCBUF_Pos))
+#define TC_COUNT16_CCBUF_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_CCBUF) MASK Register */
+
+/* -------- TC_COUNT32_CCBUF : (TC Offset: 0x30) (R/W 32) COUNT32 COUNT32 Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CCBUF:32; /*!< bit: 0..31 Counter/Compare Buffer Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TC_COUNT32_CCBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT32_CCBUF offset) COUNT32 Compare and Capture Buffer */
+#define TC_COUNT32_CCBUF_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_CCBUF reset_value) COUNT32 Compare and Capture Buffer */
+
+#define TC_COUNT32_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT32_CCBUF) Counter/Compare Buffer Value */
+#define TC_COUNT32_CCBUF_CCBUF_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CCBUF_CCBUF_Pos)
+#define TC_COUNT32_CCBUF_CCBUF(value) (TC_COUNT32_CCBUF_CCBUF_Msk & ((value) << TC_COUNT32_CCBUF_CCBUF_Pos))
+#define TC_COUNT32_CCBUF_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CCBUF) MASK Register */
+
+/* -------- TC_COUNT8_CCBUF : (TC Offset: 0x30) (R/W 8) COUNT8 COUNT8 Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CCBUF:8; /*!< bit: 0.. 7 Counter/Compare Buffer Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_CCBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT8_CCBUF offset) COUNT8 Compare and Capture Buffer */
+#define TC_COUNT8_CCBUF_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_CCBUF reset_value) COUNT8 Compare and Capture Buffer */
+
+#define TC_COUNT8_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT8_CCBUF) Counter/Compare Buffer Value */
+#define TC_COUNT8_CCBUF_CCBUF_Msk (_U_(0xFF) << TC_COUNT8_CCBUF_CCBUF_Pos)
+#define TC_COUNT8_CCBUF_CCBUF(value) (TC_COUNT8_CCBUF_CCBUF_Msk & ((value) << TC_COUNT8_CCBUF_CCBUF_Pos))
+#define TC_COUNT8_CCBUF_MASK _U_(0xFF) /**< \brief (TC_COUNT8_CCBUF) MASK Register */
+
+/** \brief TC_COUNT8 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 8-bit Counter Mode */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
+ __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
+ __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */
+ __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
+ __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
+ __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Count */
+ RoReg8 Reserved2[0x6];
+ __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x1B (R/W 8) COUNT8 Period */
+ __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 8) COUNT8 Compare and Capture */
+ RoReg8 Reserved3[0x11];
+ __IO TC_COUNT8_PERBUF_Type PERBUF; /**< \brief Offset: 0x2F (R/W 8) COUNT8 Period Buffer */
+ __IO TC_COUNT8_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 8) COUNT8 Compare and Capture Buffer */
+} TcCount8;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT16 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter Mode */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
+ __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
+ __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */
+ __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
+ __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
+ __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 16) COUNT16 Count */
+ RoReg8 Reserved2[0x6];
+ __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 16) COUNT16 Compare and Capture */
+ RoReg8 Reserved3[0x10];
+ __IO TC_COUNT16_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 16) COUNT16 Compare and Capture Buffer */
+} TcCount16;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT32 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter Mode */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
+ __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
+ __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */
+ __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
+ __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
+ __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 32) COUNT32 Count */
+ RoReg8 Reserved2[0x4];
+ __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 32) COUNT32 Compare and Capture */
+ RoReg8 Reserved3[0xC];
+ __IO TC_COUNT32_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 32) COUNT32 Compare and Capture Buffer */
+} TcCount32;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
+ TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
+ TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_TC_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/tcc.h b/sysmoOCTSIM/include/component/tcc.h
index bdd641d..507920c 100644
--- a/sysmoOCTSIM/include/component/tcc.h
+++ b/sysmoOCTSIM/include/component/tcc.h
@@ -1,1762 +1,1762 @@
-/**
- * \file
- *
- * \brief Component description for TCC
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_TCC_COMPONENT_
-#define _SAME54_TCC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR TCC */
-/* ========================================================================== */
-/** \addtogroup SAME54_TCC Timer Counter Control */
-/*@{*/
-
-#define TCC_U2213
-#define REV_TCC 0x310
-
-/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t :3; /*!< bit: 2.. 4 Reserved */
- uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
- uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
- uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
- uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
- uint32_t MSYNC:1; /*!< bit: 15 Master Synchronization (only for TCC Slave Instance) */
- uint32_t :7; /*!< bit: 16..22 Reserved */
- uint32_t DMAOS:1; /*!< bit: 23 DMA One-shot Trigger Mode */
- uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
- uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
- uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
- uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
- uint32_t CPTEN4:1; /*!< bit: 28 Capture Channel 4 Enable */
- uint32_t CPTEN5:1; /*!< bit: 29 Capture Channel 5 Enable */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :24; /*!< bit: 0..23 Reserved */
- uint32_t CPTEN:6; /*!< bit: 24..29 Capture Channel x Enable */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} TCC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */
-#define TCC_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (TCC_CTRLA reset_value) Control A */
-
-#define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */
-#define TCC_CTRLA_SWRST (_U_(0x1) << TCC_CTRLA_SWRST_Pos)
-#define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */
-#define TCC_CTRLA_ENABLE (_U_(0x1) << TCC_CTRLA_ENABLE_Pos)
-#define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */
-#define TCC_CTRLA_RESOLUTION_Msk (_U_(0x3) << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
-#define TCC_CTRLA_RESOLUTION_NONE_Val _U_(0x0) /**< \brief (TCC_CTRLA) Dithering is disabled */
-#define TCC_CTRLA_RESOLUTION_DITH4_Val _U_(0x1) /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
-#define TCC_CTRLA_RESOLUTION_DITH5_Val _U_(0x2) /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
-#define TCC_CTRLA_RESOLUTION_DITH6_Val _U_(0x3) /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */
-#define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */
-#define TCC_CTRLA_PRESCALER_Msk (_U_(0x7) << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER(value) (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
-#define TCC_CTRLA_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (TCC_CTRLA) No division */
-#define TCC_CTRLA_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (TCC_CTRLA) Divide by 2 */
-#define TCC_CTRLA_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (TCC_CTRLA) Divide by 4 */
-#define TCC_CTRLA_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (TCC_CTRLA) Divide by 8 */
-#define TCC_CTRLA_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (TCC_CTRLA) Divide by 16 */
-#define TCC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (TCC_CTRLA) Divide by 64 */
-#define TCC_CTRLA_PRESCALER_DIV256_Val _U_(0x6) /**< \brief (TCC_CTRLA) Divide by 256 */
-#define TCC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7) /**< \brief (TCC_CTRLA) Divide by 1024 */
-#define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */
-#define TCC_CTRLA_RUNSTDBY (_U_(0x1) << TCC_CTRLA_RUNSTDBY_Pos)
-#define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
-#define TCC_CTRLA_PRESCSYNC_Msk (_U_(0x3) << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_PRESCSYNC(value) (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
-#define TCC_CTRLA_PRESCSYNC_GCLK_Val _U_(0x0) /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
-#define TCC_CTRLA_PRESCSYNC_PRESC_Val _U_(0x1) /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
-#define TCC_CTRLA_PRESCSYNC_RESYNC_Val _U_(0x2) /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
-#define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */
-#define TCC_CTRLA_ALOCK (_U_(0x1) << TCC_CTRLA_ALOCK_Pos)
-#define TCC_CTRLA_MSYNC_Pos 15 /**< \brief (TCC_CTRLA) Master Synchronization (only for TCC Slave Instance) */
-#define TCC_CTRLA_MSYNC (_U_(0x1) << TCC_CTRLA_MSYNC_Pos)
-#define TCC_CTRLA_DMAOS_Pos 23 /**< \brief (TCC_CTRLA) DMA One-shot Trigger Mode */
-#define TCC_CTRLA_DMAOS (_U_(0x1) << TCC_CTRLA_DMAOS_Pos)
-#define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
-#define TCC_CTRLA_CPTEN0 (_U_(1) << TCC_CTRLA_CPTEN0_Pos)
-#define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
-#define TCC_CTRLA_CPTEN1 (_U_(1) << TCC_CTRLA_CPTEN1_Pos)
-#define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
-#define TCC_CTRLA_CPTEN2 (_U_(1) << TCC_CTRLA_CPTEN2_Pos)
-#define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
-#define TCC_CTRLA_CPTEN3 (_U_(1) << TCC_CTRLA_CPTEN3_Pos)
-#define TCC_CTRLA_CPTEN4_Pos 28 /**< \brief (TCC_CTRLA) Capture Channel 4 Enable */
-#define TCC_CTRLA_CPTEN4 (_U_(1) << TCC_CTRLA_CPTEN4_Pos)
-#define TCC_CTRLA_CPTEN5_Pos 29 /**< \brief (TCC_CTRLA) Capture Channel 5 Enable */
-#define TCC_CTRLA_CPTEN5 (_U_(1) << TCC_CTRLA_CPTEN5_Pos)
-#define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */
-#define TCC_CTRLA_CPTEN_Msk (_U_(0x3F) << TCC_CTRLA_CPTEN_Pos)
-#define TCC_CTRLA_CPTEN(value) (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
-#define TCC_CTRLA_MASK _U_(0x3F80FF63) /**< \brief (TCC_CTRLA) MASK Register */
-
-/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t LUPD:1; /*!< bit: 1 Lock Update */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
- uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} TCC_CTRLBCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
-#define TCC_CTRLBCLR_RESETVALUE _U_(0x00) /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
-
-#define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */
-#define TCC_CTRLBCLR_DIR (_U_(0x1) << TCC_CTRLBCLR_DIR_Pos)
-#define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */
-#define TCC_CTRLBCLR_LUPD (_U_(0x1) << TCC_CTRLBCLR_LUPD_Pos)
-#define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */
-#define TCC_CTRLBCLR_ONESHOT (_U_(0x1) << TCC_CTRLBCLR_ONESHOT_Pos)
-#define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
-#define TCC_CTRLBCLR_IDXCMD_Msk (_U_(0x3) << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD(value) (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
-#define TCC_CTRLBCLR_IDXCMD_DISABLE_Val _U_(0x0) /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
-#define TCC_CTRLBCLR_IDXCMD_SET_Val _U_(0x1) /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
-#define TCC_CTRLBCLR_IDXCMD_CLEAR_Val _U_(0x2) /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
-#define TCC_CTRLBCLR_IDXCMD_HOLD_Val _U_(0x3) /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */
-#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */
-#define TCC_CTRLBCLR_CMD_Msk (_U_(0x7) << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD(value) (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
-#define TCC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< \brief (TCC_CTRLBCLR) No action */
-#define TCC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
-#define TCC_CTRLBCLR_CMD_STOP_Val _U_(0x2) /**< \brief (TCC_CTRLBCLR) Force stop */
-#define TCC_CTRLBCLR_CMD_UPDATE_Val _U_(0x3) /**< \brief (TCC_CTRLBCLR) Force update or double buffered registers */
-#define TCC_CTRLBCLR_CMD_READSYNC_Val _U_(0x4) /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
-#define TCC_CTRLBCLR_CMD_DMAOS_Val _U_(0x5) /**< \brief (TCC_CTRLBCLR) One-shot DMA trigger */
-#define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_DMAOS (TCC_CTRLBCLR_CMD_DMAOS_Val << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_MASK _U_(0xFF) /**< \brief (TCC_CTRLBCLR) MASK Register */
-
-/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t LUPD:1; /*!< bit: 1 Lock Update */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
- uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} TCC_CTRLBSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */
-#define TCC_CTRLBSET_RESETVALUE _U_(0x00) /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
-
-#define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */
-#define TCC_CTRLBSET_DIR (_U_(0x1) << TCC_CTRLBSET_DIR_Pos)
-#define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock Update */
-#define TCC_CTRLBSET_LUPD (_U_(0x1) << TCC_CTRLBSET_LUPD_Pos)
-#define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */
-#define TCC_CTRLBSET_ONESHOT (_U_(0x1) << TCC_CTRLBSET_ONESHOT_Pos)
-#define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */
-#define TCC_CTRLBSET_IDXCMD_Msk (_U_(0x3) << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD(value) (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
-#define TCC_CTRLBSET_IDXCMD_DISABLE_Val _U_(0x0) /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
-#define TCC_CTRLBSET_IDXCMD_SET_Val _U_(0x1) /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
-#define TCC_CTRLBSET_IDXCMD_CLEAR_Val _U_(0x2) /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
-#define TCC_CTRLBSET_IDXCMD_HOLD_Val _U_(0x3) /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */
-#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */
-#define TCC_CTRLBSET_CMD_Msk (_U_(0x7) << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD(value) (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
-#define TCC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< \brief (TCC_CTRLBSET) No action */
-#define TCC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
-#define TCC_CTRLBSET_CMD_STOP_Val _U_(0x2) /**< \brief (TCC_CTRLBSET) Force stop */
-#define TCC_CTRLBSET_CMD_UPDATE_Val _U_(0x3) /**< \brief (TCC_CTRLBSET) Force update or double buffered registers */
-#define TCC_CTRLBSET_CMD_READSYNC_Val _U_(0x4) /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
-#define TCC_CTRLBSET_CMD_DMAOS_Val _U_(0x5) /**< \brief (TCC_CTRLBSET) One-shot DMA trigger */
-#define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_DMAOS (TCC_CTRLBSET_CMD_DMAOS_Val << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_MASK _U_(0xFF) /**< \brief (TCC_CTRLBSET) MASK Register */
-
-/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
- uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
- uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
- uint32_t STATUS:1; /*!< bit: 3 Status Busy */
- uint32_t COUNT:1; /*!< bit: 4 Count Busy */
- uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
- uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
- uint32_t PER:1; /*!< bit: 7 Period Busy */
- uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
- uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
- uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
- uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
- uint32_t CC4:1; /*!< bit: 12 Compare Channel 4 Busy */
- uint32_t CC5:1; /*!< bit: 13 Compare Channel 5 Busy */
- uint32_t :18; /*!< bit: 14..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CC:6; /*!< bit: 8..13 Compare Channel x Busy */
- uint32_t :18; /*!< bit: 14..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} TCC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
-#define TCC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
-
-#define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */
-#define TCC_SYNCBUSY_SWRST (_U_(0x1) << TCC_SYNCBUSY_SWRST_Pos)
-#define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */
-#define TCC_SYNCBUSY_ENABLE (_U_(0x1) << TCC_SYNCBUSY_ENABLE_Pos)
-#define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
-#define TCC_SYNCBUSY_CTRLB (_U_(0x1) << TCC_SYNCBUSY_CTRLB_Pos)
-#define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */
-#define TCC_SYNCBUSY_STATUS (_U_(0x1) << TCC_SYNCBUSY_STATUS_Pos)
-#define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */
-#define TCC_SYNCBUSY_COUNT (_U_(0x1) << TCC_SYNCBUSY_COUNT_Pos)
-#define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */
-#define TCC_SYNCBUSY_PATT (_U_(0x1) << TCC_SYNCBUSY_PATT_Pos)
-#define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */
-#define TCC_SYNCBUSY_WAVE (_U_(0x1) << TCC_SYNCBUSY_WAVE_Pos)
-#define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period Busy */
-#define TCC_SYNCBUSY_PER (_U_(0x1) << TCC_SYNCBUSY_PER_Pos)
-#define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */
-#define TCC_SYNCBUSY_CC0 (_U_(1) << TCC_SYNCBUSY_CC0_Pos)
-#define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */
-#define TCC_SYNCBUSY_CC1 (_U_(1) << TCC_SYNCBUSY_CC1_Pos)
-#define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */
-#define TCC_SYNCBUSY_CC2 (_U_(1) << TCC_SYNCBUSY_CC2_Pos)
-#define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */
-#define TCC_SYNCBUSY_CC3 (_U_(1) << TCC_SYNCBUSY_CC3_Pos)
-#define TCC_SYNCBUSY_CC4_Pos 12 /**< \brief (TCC_SYNCBUSY) Compare Channel 4 Busy */
-#define TCC_SYNCBUSY_CC4 (_U_(1) << TCC_SYNCBUSY_CC4_Pos)
-#define TCC_SYNCBUSY_CC5_Pos 13 /**< \brief (TCC_SYNCBUSY) Compare Channel 5 Busy */
-#define TCC_SYNCBUSY_CC5 (_U_(1) << TCC_SYNCBUSY_CC5_Pos)
-#define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
-#define TCC_SYNCBUSY_CC_Msk (_U_(0x3F) << TCC_SYNCBUSY_CC_Pos)
-#define TCC_SYNCBUSY_CC(value) (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
-#define TCC_SYNCBUSY_MASK _U_(0x00003FFF) /**< \brief (TCC_SYNCBUSY) MASK Register */
-
-/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
- uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
- uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
- uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
- uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
- uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
- uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
- uint32_t BLANKPRESC:1; /*!< bit: 15 Fault A Blanking Prescaler */
- uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
- uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} TCC_FCTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */
-#define TCC_FCTRLA_RESETVALUE _U_(0x00000000) /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */
-
-#define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */
-#define TCC_FCTRLA_SRC_Msk (_U_(0x3) << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC(value) (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
-#define TCC_FCTRLA_SRC_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Fault input disabled */
-#define TCC_FCTRLA_SRC_ENABLE_Val _U_(0x1) /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
-#define TCC_FCTRLA_SRC_INVERT_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
-#define TCC_FCTRLA_SRC_ALTFAULT_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */
-#define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) Fault A Keeper */
-#define TCC_FCTRLA_KEEP (_U_(0x1) << TCC_FCTRLA_KEEP_Pos)
-#define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) Fault A Qualification */
-#define TCC_FCTRLA_QUAL (_U_(0x1) << TCC_FCTRLA_QUAL_Pos)
-#define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
-#define TCC_FCTRLA_BLANK_Msk (_U_(0x3) << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK(value) (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
-#define TCC_FCTRLA_BLANK_START_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Blanking applied from start of the ramp */
-#define TCC_FCTRLA_BLANK_RISE_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
-#define TCC_FCTRLA_BLANK_FALL_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
-#define TCC_FCTRLA_BLANK_BOTH_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
-#define TCC_FCTRLA_BLANK_START (TCC_FCTRLA_BLANK_START_Val << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) Fault A Restart */
-#define TCC_FCTRLA_RESTART (_U_(0x1) << TCC_FCTRLA_RESTART_Pos)
-#define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
-#define TCC_FCTRLA_HALT_Msk (_U_(0x3) << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT(value) (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
-#define TCC_FCTRLA_HALT_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Halt action disabled */
-#define TCC_FCTRLA_HALT_HW_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Hardware halt action */
-#define TCC_FCTRLA_HALT_SW_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Software halt action */
-#define TCC_FCTRLA_HALT_NR_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Non-recoverable fault */
-#define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
-#define TCC_FCTRLA_CHSEL_Msk (_U_(0x3) << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL(value) (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
-#define TCC_FCTRLA_CHSEL_CC0_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
-#define TCC_FCTRLA_CHSEL_CC1_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
-#define TCC_FCTRLA_CHSEL_CC2_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
-#define TCC_FCTRLA_CHSEL_CC3_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */
-#define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */
-#define TCC_FCTRLA_CAPTURE_Msk (_U_(0x7) << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE(value) (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
-#define TCC_FCTRLA_CAPTURE_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLA) No capture */
-#define TCC_FCTRLA_CAPTURE_CAPT_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Capture on fault */
-#define TCC_FCTRLA_CAPTURE_CAPTMIN_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Minimum capture */
-#define TCC_FCTRLA_CAPTURE_CAPTMAX_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Maximum capture */
-#define TCC_FCTRLA_CAPTURE_LOCMIN_Val _U_(0x4) /**< \brief (TCC_FCTRLA) Minimum local detection */
-#define TCC_FCTRLA_CAPTURE_LOCMAX_Val _U_(0x5) /**< \brief (TCC_FCTRLA) Maximum local detection */
-#define TCC_FCTRLA_CAPTURE_DERIV0_Val _U_(0x6) /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
-#define TCC_FCTRLA_CAPTURE_CAPTMARK_Val _U_(0x7) /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */
-#define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_BLANKPRESC_Pos 15 /**< \brief (TCC_FCTRLA) Fault A Blanking Prescaler */
-#define TCC_FCTRLA_BLANKPRESC (_U_(0x1) << TCC_FCTRLA_BLANKPRESC_Pos)
-#define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
-#define TCC_FCTRLA_BLANKVAL_Msk (_U_(0xFF) << TCC_FCTRLA_BLANKVAL_Pos)
-#define TCC_FCTRLA_BLANKVAL(value) (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
-#define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */
-#define TCC_FCTRLA_FILTERVAL_Msk (_U_(0xF) << TCC_FCTRLA_FILTERVAL_Pos)
-#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
-#define TCC_FCTRLA_MASK _U_(0x0FFFFFFB) /**< \brief (TCC_FCTRLA) MASK Register */
-
-/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
- uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
- uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
- uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
- uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
- uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
- uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
- uint32_t BLANKPRESC:1; /*!< bit: 15 Fault B Blanking Prescaler */
- uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
- uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} TCC_FCTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */
-#define TCC_FCTRLB_RESETVALUE _U_(0x00000000) /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */
-
-#define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */
-#define TCC_FCTRLB_SRC_Msk (_U_(0x3) << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC(value) (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
-#define TCC_FCTRLB_SRC_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Fault input disabled */
-#define TCC_FCTRLB_SRC_ENABLE_Val _U_(0x1) /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
-#define TCC_FCTRLB_SRC_INVERT_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
-#define TCC_FCTRLB_SRC_ALTFAULT_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */
-#define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) Fault B Keeper */
-#define TCC_FCTRLB_KEEP (_U_(0x1) << TCC_FCTRLB_KEEP_Pos)
-#define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) Fault B Qualification */
-#define TCC_FCTRLB_QUAL (_U_(0x1) << TCC_FCTRLB_QUAL_Pos)
-#define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
-#define TCC_FCTRLB_BLANK_Msk (_U_(0x3) << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK(value) (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
-#define TCC_FCTRLB_BLANK_START_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Blanking applied from start of the ramp */
-#define TCC_FCTRLB_BLANK_RISE_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
-#define TCC_FCTRLB_BLANK_FALL_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
-#define TCC_FCTRLB_BLANK_BOTH_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
-#define TCC_FCTRLB_BLANK_START (TCC_FCTRLB_BLANK_START_Val << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) Fault B Restart */
-#define TCC_FCTRLB_RESTART (_U_(0x1) << TCC_FCTRLB_RESTART_Pos)
-#define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
-#define TCC_FCTRLB_HALT_Msk (_U_(0x3) << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT(value) (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
-#define TCC_FCTRLB_HALT_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Halt action disabled */
-#define TCC_FCTRLB_HALT_HW_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Hardware halt action */
-#define TCC_FCTRLB_HALT_SW_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Software halt action */
-#define TCC_FCTRLB_HALT_NR_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Non-recoverable fault */
-#define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
-#define TCC_FCTRLB_CHSEL_Msk (_U_(0x3) << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL(value) (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
-#define TCC_FCTRLB_CHSEL_CC0_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
-#define TCC_FCTRLB_CHSEL_CC1_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
-#define TCC_FCTRLB_CHSEL_CC2_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
-#define TCC_FCTRLB_CHSEL_CC3_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */
-#define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */
-#define TCC_FCTRLB_CAPTURE_Msk (_U_(0x7) << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE(value) (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
-#define TCC_FCTRLB_CAPTURE_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLB) No capture */
-#define TCC_FCTRLB_CAPTURE_CAPT_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Capture on fault */
-#define TCC_FCTRLB_CAPTURE_CAPTMIN_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Minimum capture */
-#define TCC_FCTRLB_CAPTURE_CAPTMAX_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Maximum capture */
-#define TCC_FCTRLB_CAPTURE_LOCMIN_Val _U_(0x4) /**< \brief (TCC_FCTRLB) Minimum local detection */
-#define TCC_FCTRLB_CAPTURE_LOCMAX_Val _U_(0x5) /**< \brief (TCC_FCTRLB) Maximum local detection */
-#define TCC_FCTRLB_CAPTURE_DERIV0_Val _U_(0x6) /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
-#define TCC_FCTRLB_CAPTURE_CAPTMARK_Val _U_(0x7) /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */
-#define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_BLANKPRESC_Pos 15 /**< \brief (TCC_FCTRLB) Fault B Blanking Prescaler */
-#define TCC_FCTRLB_BLANKPRESC (_U_(0x1) << TCC_FCTRLB_BLANKPRESC_Pos)
-#define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
-#define TCC_FCTRLB_BLANKVAL_Msk (_U_(0xFF) << TCC_FCTRLB_BLANKVAL_Pos)
-#define TCC_FCTRLB_BLANKVAL(value) (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
-#define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */
-#define TCC_FCTRLB_FILTERVAL_Msk (_U_(0xF) << TCC_FCTRLB_FILTERVAL_Pos)
-#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
-#define TCC_FCTRLB_MASK _U_(0x0FFFFFFB) /**< \brief (TCC_FCTRLB) MASK Register */
-
-/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
- uint32_t :6; /*!< bit: 2.. 7 Reserved */
- uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
- uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
- uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
- uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
- uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} TCC_WEXCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
-#define TCC_WEXCTRL_RESETVALUE _U_(0x00000000) /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
-
-#define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */
-#define TCC_WEXCTRL_OTMX_Msk (_U_(0x3) << TCC_WEXCTRL_OTMX_Pos)
-#define TCC_WEXCTRL_OTMX(value) (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
-#define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
-#define TCC_WEXCTRL_DTIEN0 (_U_(1) << TCC_WEXCTRL_DTIEN0_Pos)
-#define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
-#define TCC_WEXCTRL_DTIEN1 (_U_(1) << TCC_WEXCTRL_DTIEN1_Pos)
-#define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
-#define TCC_WEXCTRL_DTIEN2 (_U_(1) << TCC_WEXCTRL_DTIEN2_Pos)
-#define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
-#define TCC_WEXCTRL_DTIEN3 (_U_(1) << TCC_WEXCTRL_DTIEN3_Pos)
-#define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
-#define TCC_WEXCTRL_DTIEN_Msk (_U_(0xF) << TCC_WEXCTRL_DTIEN_Pos)
-#define TCC_WEXCTRL_DTIEN(value) (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
-#define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
-#define TCC_WEXCTRL_DTLS_Msk (_U_(0xFF) << TCC_WEXCTRL_DTLS_Pos)
-#define TCC_WEXCTRL_DTLS(value) (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
-#define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
-#define TCC_WEXCTRL_DTHS_Msk (_U_(0xFF) << TCC_WEXCTRL_DTHS_Pos)
-#define TCC_WEXCTRL_DTHS(value) (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
-#define TCC_WEXCTRL_MASK _U_(0xFFFF0F03) /**< \brief (TCC_WEXCTRL) MASK Register */
-
-/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
- uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
- uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
- uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
- uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
- uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
- uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
- uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
- uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
- uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
- uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
- uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
- uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
- uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
- uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
- uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
- uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
- uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
- uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
- uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
- uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
- uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
- uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
- uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
- uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
- uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
- uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
- uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} TCC_DRVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Control */
-#define TCC_DRVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (TCC_DRVCTRL reset_value) Driver Control */
-
-#define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
-#define TCC_DRVCTRL_NRE0 (_U_(1) << TCC_DRVCTRL_NRE0_Pos)
-#define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
-#define TCC_DRVCTRL_NRE1 (_U_(1) << TCC_DRVCTRL_NRE1_Pos)
-#define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
-#define TCC_DRVCTRL_NRE2 (_U_(1) << TCC_DRVCTRL_NRE2_Pos)
-#define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
-#define TCC_DRVCTRL_NRE3 (_U_(1) << TCC_DRVCTRL_NRE3_Pos)
-#define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
-#define TCC_DRVCTRL_NRE4 (_U_(1) << TCC_DRVCTRL_NRE4_Pos)
-#define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
-#define TCC_DRVCTRL_NRE5 (_U_(1) << TCC_DRVCTRL_NRE5_Pos)
-#define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
-#define TCC_DRVCTRL_NRE6 (_U_(1) << TCC_DRVCTRL_NRE6_Pos)
-#define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
-#define TCC_DRVCTRL_NRE7 (_U_(1) << TCC_DRVCTRL_NRE7_Pos)
-#define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
-#define TCC_DRVCTRL_NRE_Msk (_U_(0xFF) << TCC_DRVCTRL_NRE_Pos)
-#define TCC_DRVCTRL_NRE(value) (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
-#define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
-#define TCC_DRVCTRL_NRV0 (_U_(1) << TCC_DRVCTRL_NRV0_Pos)
-#define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
-#define TCC_DRVCTRL_NRV1 (_U_(1) << TCC_DRVCTRL_NRV1_Pos)
-#define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
-#define TCC_DRVCTRL_NRV2 (_U_(1) << TCC_DRVCTRL_NRV2_Pos)
-#define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
-#define TCC_DRVCTRL_NRV3 (_U_(1) << TCC_DRVCTRL_NRV3_Pos)
-#define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
-#define TCC_DRVCTRL_NRV4 (_U_(1) << TCC_DRVCTRL_NRV4_Pos)
-#define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
-#define TCC_DRVCTRL_NRV5 (_U_(1) << TCC_DRVCTRL_NRV5_Pos)
-#define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
-#define TCC_DRVCTRL_NRV6 (_U_(1) << TCC_DRVCTRL_NRV6_Pos)
-#define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
-#define TCC_DRVCTRL_NRV7 (_U_(1) << TCC_DRVCTRL_NRV7_Pos)
-#define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
-#define TCC_DRVCTRL_NRV_Msk (_U_(0xFF) << TCC_DRVCTRL_NRV_Pos)
-#define TCC_DRVCTRL_NRV(value) (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
-#define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
-#define TCC_DRVCTRL_INVEN0 (_U_(1) << TCC_DRVCTRL_INVEN0_Pos)
-#define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
-#define TCC_DRVCTRL_INVEN1 (_U_(1) << TCC_DRVCTRL_INVEN1_Pos)
-#define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
-#define TCC_DRVCTRL_INVEN2 (_U_(1) << TCC_DRVCTRL_INVEN2_Pos)
-#define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
-#define TCC_DRVCTRL_INVEN3 (_U_(1) << TCC_DRVCTRL_INVEN3_Pos)
-#define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
-#define TCC_DRVCTRL_INVEN4 (_U_(1) << TCC_DRVCTRL_INVEN4_Pos)
-#define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
-#define TCC_DRVCTRL_INVEN5 (_U_(1) << TCC_DRVCTRL_INVEN5_Pos)
-#define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
-#define TCC_DRVCTRL_INVEN6 (_U_(1) << TCC_DRVCTRL_INVEN6_Pos)
-#define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
-#define TCC_DRVCTRL_INVEN7 (_U_(1) << TCC_DRVCTRL_INVEN7_Pos)
-#define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
-#define TCC_DRVCTRL_INVEN_Msk (_U_(0xFF) << TCC_DRVCTRL_INVEN_Pos)
-#define TCC_DRVCTRL_INVEN(value) (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
-#define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
-#define TCC_DRVCTRL_FILTERVAL0_Msk (_U_(0xF) << TCC_DRVCTRL_FILTERVAL0_Pos)
-#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
-#define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
-#define TCC_DRVCTRL_FILTERVAL1_Msk (_U_(0xF) << TCC_DRVCTRL_FILTERVAL1_Pos)
-#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
-#define TCC_DRVCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (TCC_DRVCTRL) MASK Register */
-
-/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} TCC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */
-#define TCC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
-
-#define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */
-#define TCC_DBGCTRL_DBGRUN (_U_(0x1) << TCC_DBGCTRL_DBGRUN_Pos)
-#define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
-#define TCC_DBGCTRL_FDDBD (_U_(0x1) << TCC_DBGCTRL_FDDBD_Pos)
-#define TCC_DBGCTRL_MASK _U_(0x05) /**< \brief (TCC_DBGCTRL) MASK Register */
-
-/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
- uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
- uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
- uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
- uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
- uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
- uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
- uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
- uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
- uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
- uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
- uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
- uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
- uint32_t MCEI4:1; /*!< bit: 20 Match or Capture Channel 4 Event Input Enable */
- uint32_t MCEI5:1; /*!< bit: 21 Match or Capture Channel 5 Event Input Enable */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
- uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
- uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
- uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
- uint32_t MCEO4:1; /*!< bit: 28 Match or Capture Channel 4 Event Output Enable */
- uint32_t MCEO5:1; /*!< bit: 29 Match or Capture Channel 5 Event Output Enable */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :12; /*!< bit: 0..11 Reserved */
- uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
- uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
- uint32_t MCEI:6; /*!< bit: 16..21 Match or Capture Channel x Event Input Enable */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t MCEO:6; /*!< bit: 24..29 Match or Capture Channel x Event Output Enable */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} TCC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */
-#define TCC_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (TCC_EVCTRL reset_value) Event Control */
-
-#define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
-#define TCC_EVCTRL_EVACT0_Msk (_U_(0x7) << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0(value) (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
-#define TCC_EVCTRL_EVACT0_OFF_Val _U_(0x0) /**< \brief (TCC_EVCTRL) Event action disabled */
-#define TCC_EVCTRL_EVACT0_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
-#define TCC_EVCTRL_EVACT0_COUNTEV_Val _U_(0x2) /**< \brief (TCC_EVCTRL) Count on event */
-#define TCC_EVCTRL_EVACT0_START_Val _U_(0x3) /**< \brief (TCC_EVCTRL) Start counter on event */
-#define TCC_EVCTRL_EVACT0_INC_Val _U_(0x4) /**< \brief (TCC_EVCTRL) Increment counter on event */
-#define TCC_EVCTRL_EVACT0_COUNT_Val _U_(0x5) /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
-#define TCC_EVCTRL_EVACT0_STAMP_Val _U_(0x6) /**< \brief (TCC_EVCTRL) Stamp capture */
-#define TCC_EVCTRL_EVACT0_FAULT_Val _U_(0x7) /**< \brief (TCC_EVCTRL) Non-recoverable fault */
-#define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_STAMP (TCC_EVCTRL_EVACT0_STAMP_Val << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
-#define TCC_EVCTRL_EVACT1_Msk (_U_(0x7) << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1(value) (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
-#define TCC_EVCTRL_EVACT1_OFF_Val _U_(0x0) /**< \brief (TCC_EVCTRL) Event action disabled */
-#define TCC_EVCTRL_EVACT1_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
-#define TCC_EVCTRL_EVACT1_DIR_Val _U_(0x2) /**< \brief (TCC_EVCTRL) Direction control */
-#define TCC_EVCTRL_EVACT1_STOP_Val _U_(0x3) /**< \brief (TCC_EVCTRL) Stop counter on event */
-#define TCC_EVCTRL_EVACT1_DEC_Val _U_(0x4) /**< \brief (TCC_EVCTRL) Decrement counter on event */
-#define TCC_EVCTRL_EVACT1_PPW_Val _U_(0x5) /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */
-#define TCC_EVCTRL_EVACT1_PWP_Val _U_(0x6) /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */
-#define TCC_EVCTRL_EVACT1_FAULT_Val _U_(0x7) /**< \brief (TCC_EVCTRL) Non-recoverable fault */
-#define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
-#define TCC_EVCTRL_CNTSEL_Msk (_U_(0x3) << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL(value) (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
-#define TCC_EVCTRL_CNTSEL_START_Val _U_(0x0) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
-#define TCC_EVCTRL_CNTSEL_END_Val _U_(0x1) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
-#define TCC_EVCTRL_CNTSEL_BETWEEN_Val _U_(0x2) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
-#define TCC_EVCTRL_CNTSEL_BOUNDARY_Val _U_(0x3) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
-#define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
-#define TCC_EVCTRL_OVFEO (_U_(0x1) << TCC_EVCTRL_OVFEO_Pos)
-#define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
-#define TCC_EVCTRL_TRGEO (_U_(0x1) << TCC_EVCTRL_TRGEO_Pos)
-#define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
-#define TCC_EVCTRL_CNTEO (_U_(0x1) << TCC_EVCTRL_CNTEO_Pos)
-#define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
-#define TCC_EVCTRL_TCINV0 (_U_(1) << TCC_EVCTRL_TCINV0_Pos)
-#define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
-#define TCC_EVCTRL_TCINV1 (_U_(1) << TCC_EVCTRL_TCINV1_Pos)
-#define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
-#define TCC_EVCTRL_TCINV_Msk (_U_(0x3) << TCC_EVCTRL_TCINV_Pos)
-#define TCC_EVCTRL_TCINV(value) (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
-#define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
-#define TCC_EVCTRL_TCEI0 (_U_(1) << TCC_EVCTRL_TCEI0_Pos)
-#define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
-#define TCC_EVCTRL_TCEI1 (_U_(1) << TCC_EVCTRL_TCEI1_Pos)
-#define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
-#define TCC_EVCTRL_TCEI_Msk (_U_(0x3) << TCC_EVCTRL_TCEI_Pos)
-#define TCC_EVCTRL_TCEI(value) (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
-#define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
-#define TCC_EVCTRL_MCEI0 (_U_(1) << TCC_EVCTRL_MCEI0_Pos)
-#define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
-#define TCC_EVCTRL_MCEI1 (_U_(1) << TCC_EVCTRL_MCEI1_Pos)
-#define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
-#define TCC_EVCTRL_MCEI2 (_U_(1) << TCC_EVCTRL_MCEI2_Pos)
-#define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
-#define TCC_EVCTRL_MCEI3 (_U_(1) << TCC_EVCTRL_MCEI3_Pos)
-#define TCC_EVCTRL_MCEI4_Pos 20 /**< \brief (TCC_EVCTRL) Match or Capture Channel 4 Event Input Enable */
-#define TCC_EVCTRL_MCEI4 (_U_(1) << TCC_EVCTRL_MCEI4_Pos)
-#define TCC_EVCTRL_MCEI5_Pos 21 /**< \brief (TCC_EVCTRL) Match or Capture Channel 5 Event Input Enable */
-#define TCC_EVCTRL_MCEI5 (_U_(1) << TCC_EVCTRL_MCEI5_Pos)
-#define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
-#define TCC_EVCTRL_MCEI_Msk (_U_(0x3F) << TCC_EVCTRL_MCEI_Pos)
-#define TCC_EVCTRL_MCEI(value) (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
-#define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
-#define TCC_EVCTRL_MCEO0 (_U_(1) << TCC_EVCTRL_MCEO0_Pos)
-#define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
-#define TCC_EVCTRL_MCEO1 (_U_(1) << TCC_EVCTRL_MCEO1_Pos)
-#define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
-#define TCC_EVCTRL_MCEO2 (_U_(1) << TCC_EVCTRL_MCEO2_Pos)
-#define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
-#define TCC_EVCTRL_MCEO3 (_U_(1) << TCC_EVCTRL_MCEO3_Pos)
-#define TCC_EVCTRL_MCEO4_Pos 28 /**< \brief (TCC_EVCTRL) Match or Capture Channel 4 Event Output Enable */
-#define TCC_EVCTRL_MCEO4 (_U_(1) << TCC_EVCTRL_MCEO4_Pos)
-#define TCC_EVCTRL_MCEO5_Pos 29 /**< \brief (TCC_EVCTRL) Match or Capture Channel 5 Event Output Enable */
-#define TCC_EVCTRL_MCEO5 (_U_(1) << TCC_EVCTRL_MCEO5_Pos)
-#define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
-#define TCC_EVCTRL_MCEO_Msk (_U_(0x3F) << TCC_EVCTRL_MCEO_Pos)
-#define TCC_EVCTRL_MCEO(value) (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
-#define TCC_EVCTRL_MASK _U_(0x3F3FF7FF) /**< \brief (TCC_EVCTRL) MASK Register */
-
-/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
- uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
- uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
- uint32_t :6; /*!< bit: 4.. 9 Reserved */
- uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */
- uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
- uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
- uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
- uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
- uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
- uint32_t MC4:1; /*!< bit: 20 Match or Capture Channel 4 Interrupt Enable */
- uint32_t MC5:1; /*!< bit: 21 Match or Capture Channel 5 Interrupt Enable */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t MC:6; /*!< bit: 16..21 Match or Capture Channel x Interrupt Enable */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} TCC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
-#define TCC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
-#define TCC_INTENCLR_OVF (_U_(0x1) << TCC_INTENCLR_OVF_Pos)
-#define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
-#define TCC_INTENCLR_TRG (_U_(0x1) << TCC_INTENCLR_TRG_Pos)
-#define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
-#define TCC_INTENCLR_CNT (_U_(0x1) << TCC_INTENCLR_CNT_Pos)
-#define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
-#define TCC_INTENCLR_ERR (_U_(0x1) << TCC_INTENCLR_ERR_Pos)
-#define TCC_INTENCLR_UFS_Pos 10 /**< \brief (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable */
-#define TCC_INTENCLR_UFS (_U_(0x1) << TCC_INTENCLR_UFS_Pos)
-#define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
-#define TCC_INTENCLR_DFS (_U_(0x1) << TCC_INTENCLR_DFS_Pos)
-#define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
-#define TCC_INTENCLR_FAULTA (_U_(0x1) << TCC_INTENCLR_FAULTA_Pos)
-#define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */
-#define TCC_INTENCLR_FAULTB (_U_(0x1) << TCC_INTENCLR_FAULTB_Pos)
-#define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
-#define TCC_INTENCLR_FAULT0 (_U_(0x1) << TCC_INTENCLR_FAULT0_Pos)
-#define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
-#define TCC_INTENCLR_FAULT1 (_U_(0x1) << TCC_INTENCLR_FAULT1_Pos)
-#define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
-#define TCC_INTENCLR_MC0 (_U_(1) << TCC_INTENCLR_MC0_Pos)
-#define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
-#define TCC_INTENCLR_MC1 (_U_(1) << TCC_INTENCLR_MC1_Pos)
-#define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
-#define TCC_INTENCLR_MC2 (_U_(1) << TCC_INTENCLR_MC2_Pos)
-#define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
-#define TCC_INTENCLR_MC3 (_U_(1) << TCC_INTENCLR_MC3_Pos)
-#define TCC_INTENCLR_MC4_Pos 20 /**< \brief (TCC_INTENCLR) Match or Capture Channel 4 Interrupt Enable */
-#define TCC_INTENCLR_MC4 (_U_(1) << TCC_INTENCLR_MC4_Pos)
-#define TCC_INTENCLR_MC5_Pos 21 /**< \brief (TCC_INTENCLR) Match or Capture Channel 5 Interrupt Enable */
-#define TCC_INTENCLR_MC5 (_U_(1) << TCC_INTENCLR_MC5_Pos)
-#define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
-#define TCC_INTENCLR_MC_Msk (_U_(0x3F) << TCC_INTENCLR_MC_Pos)
-#define TCC_INTENCLR_MC(value) (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
-#define TCC_INTENCLR_MASK _U_(0x003FFC0F) /**< \brief (TCC_INTENCLR) MASK Register */
-
-/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
- uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
- uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
- uint32_t :6; /*!< bit: 4.. 9 Reserved */
- uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */
- uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
- uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
- uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
- uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
- uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
- uint32_t MC4:1; /*!< bit: 20 Match or Capture Channel 4 Interrupt Enable */
- uint32_t MC5:1; /*!< bit: 21 Match or Capture Channel 5 Interrupt Enable */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t MC:6; /*!< bit: 16..21 Match or Capture Channel x Interrupt Enable */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} TCC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
-#define TCC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
-
-#define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
-#define TCC_INTENSET_OVF (_U_(0x1) << TCC_INTENSET_OVF_Pos)
-#define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
-#define TCC_INTENSET_TRG (_U_(0x1) << TCC_INTENSET_TRG_Pos)
-#define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
-#define TCC_INTENSET_CNT (_U_(0x1) << TCC_INTENSET_CNT_Pos)
-#define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */
-#define TCC_INTENSET_ERR (_U_(0x1) << TCC_INTENSET_ERR_Pos)
-#define TCC_INTENSET_UFS_Pos 10 /**< \brief (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable */
-#define TCC_INTENSET_UFS (_U_(0x1) << TCC_INTENSET_UFS_Pos)
-#define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
-#define TCC_INTENSET_DFS (_U_(0x1) << TCC_INTENSET_DFS_Pos)
-#define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
-#define TCC_INTENSET_FAULTA (_U_(0x1) << TCC_INTENSET_FAULTA_Pos)
-#define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */
-#define TCC_INTENSET_FAULTB (_U_(0x1) << TCC_INTENSET_FAULTB_Pos)
-#define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
-#define TCC_INTENSET_FAULT0 (_U_(0x1) << TCC_INTENSET_FAULT0_Pos)
-#define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */
-#define TCC_INTENSET_FAULT1 (_U_(0x1) << TCC_INTENSET_FAULT1_Pos)
-#define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
-#define TCC_INTENSET_MC0 (_U_(1) << TCC_INTENSET_MC0_Pos)
-#define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
-#define TCC_INTENSET_MC1 (_U_(1) << TCC_INTENSET_MC1_Pos)
-#define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
-#define TCC_INTENSET_MC2 (_U_(1) << TCC_INTENSET_MC2_Pos)
-#define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
-#define TCC_INTENSET_MC3 (_U_(1) << TCC_INTENSET_MC3_Pos)
-#define TCC_INTENSET_MC4_Pos 20 /**< \brief (TCC_INTENSET) Match or Capture Channel 4 Interrupt Enable */
-#define TCC_INTENSET_MC4 (_U_(1) << TCC_INTENSET_MC4_Pos)
-#define TCC_INTENSET_MC5_Pos 21 /**< \brief (TCC_INTENSET) Match or Capture Channel 5 Interrupt Enable */
-#define TCC_INTENSET_MC5 (_U_(1) << TCC_INTENSET_MC5_Pos)
-#define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
-#define TCC_INTENSET_MC_Msk (_U_(0x3F) << TCC_INTENSET_MC_Pos)
-#define TCC_INTENSET_MC(value) (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
-#define TCC_INTENSET_MASK _U_(0x003FFC0F) /**< \brief (TCC_INTENSET) MASK Register */
-
-/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint32_t OVF:1; /*!< bit: 0 Overflow */
- __I uint32_t TRG:1; /*!< bit: 1 Retrigger */
- __I uint32_t CNT:1; /*!< bit: 2 Counter */
- __I uint32_t ERR:1; /*!< bit: 3 Error */
- __I uint32_t :6; /*!< bit: 4.. 9 Reserved */
- __I uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */
- __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
- __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
- __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
- __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
- __I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
- __I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
- __I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
- __I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
- __I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
- __I uint32_t MC4:1; /*!< bit: 20 Match or Capture 4 */
- __I uint32_t MC5:1; /*!< bit: 21 Match or Capture 5 */
- __I uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint32_t :16; /*!< bit: 0..15 Reserved */
- __I uint32_t MC:6; /*!< bit: 16..21 Match or Capture x */
- __I uint32_t :10; /*!< bit: 22..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} TCC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define TCC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */
-#define TCC_INTFLAG_OVF (_U_(0x1) << TCC_INTFLAG_OVF_Pos)
-#define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */
-#define TCC_INTFLAG_TRG (_U_(0x1) << TCC_INTFLAG_TRG_Pos)
-#define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */
-#define TCC_INTFLAG_CNT (_U_(0x1) << TCC_INTFLAG_CNT_Pos)
-#define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */
-#define TCC_INTFLAG_ERR (_U_(0x1) << TCC_INTFLAG_ERR_Pos)
-#define TCC_INTFLAG_UFS_Pos 10 /**< \brief (TCC_INTFLAG) Non-Recoverable Update Fault */
-#define TCC_INTFLAG_UFS (_U_(0x1) << TCC_INTFLAG_UFS_Pos)
-#define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
-#define TCC_INTFLAG_DFS (_U_(0x1) << TCC_INTFLAG_DFS_Pos)
-#define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable Fault A */
-#define TCC_INTFLAG_FAULTA (_U_(0x1) << TCC_INTFLAG_FAULTA_Pos)
-#define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable Fault B */
-#define TCC_INTFLAG_FAULTB (_U_(0x1) << TCC_INTFLAG_FAULTB_Pos)
-#define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
-#define TCC_INTFLAG_FAULT0 (_U_(0x1) << TCC_INTFLAG_FAULT0_Pos)
-#define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
-#define TCC_INTFLAG_FAULT1 (_U_(0x1) << TCC_INTFLAG_FAULT1_Pos)
-#define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */
-#define TCC_INTFLAG_MC0 (_U_(1) << TCC_INTFLAG_MC0_Pos)
-#define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */
-#define TCC_INTFLAG_MC1 (_U_(1) << TCC_INTFLAG_MC1_Pos)
-#define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */
-#define TCC_INTFLAG_MC2 (_U_(1) << TCC_INTFLAG_MC2_Pos)
-#define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */
-#define TCC_INTFLAG_MC3 (_U_(1) << TCC_INTFLAG_MC3_Pos)
-#define TCC_INTFLAG_MC4_Pos 20 /**< \brief (TCC_INTFLAG) Match or Capture 4 */
-#define TCC_INTFLAG_MC4 (_U_(1) << TCC_INTFLAG_MC4_Pos)
-#define TCC_INTFLAG_MC5_Pos 21 /**< \brief (TCC_INTFLAG) Match or Capture 5 */
-#define TCC_INTFLAG_MC5 (_U_(1) << TCC_INTFLAG_MC5_Pos)
-#define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */
-#define TCC_INTFLAG_MC_Msk (_U_(0x3F) << TCC_INTFLAG_MC_Pos)
-#define TCC_INTFLAG_MC(value) (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
-#define TCC_INTFLAG_MASK _U_(0x003FFC0F) /**< \brief (TCC_INTFLAG) MASK Register */
-
-/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t STOP:1; /*!< bit: 0 Stop */
- uint32_t IDX:1; /*!< bit: 1 Ramp */
- uint32_t UFS:1; /*!< bit: 2 Non-recoverable Update Fault State */
- uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
- uint32_t SLAVE:1; /*!< bit: 4 Slave */
- uint32_t PATTBUFV:1; /*!< bit: 5 Pattern Buffer Valid */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t PERBUFV:1; /*!< bit: 7 Period Buffer Valid */
- uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
- uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
- uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
- uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
- uint32_t CCBUFV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
- uint32_t CCBUFV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
- uint32_t CCBUFV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
- uint32_t CCBUFV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
- uint32_t CCBUFV4:1; /*!< bit: 20 Compare Channel 4 Buffer Valid */
- uint32_t CCBUFV5:1; /*!< bit: 21 Compare Channel 5 Buffer Valid */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
- uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
- uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
- uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
- uint32_t CMP4:1; /*!< bit: 28 Compare Channel 4 Value */
- uint32_t CMP5:1; /*!< bit: 29 Compare Channel 5 Value */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t CCBUFV:6; /*!< bit: 16..21 Compare Channel x Buffer Valid */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t CMP:6; /*!< bit: 24..29 Compare Channel x Value */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} TCC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */
-#define TCC_STATUS_RESETVALUE _U_(0x00000001) /**< \brief (TCC_STATUS reset_value) Status */
-
-#define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */
-#define TCC_STATUS_STOP (_U_(0x1) << TCC_STATUS_STOP_Pos)
-#define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */
-#define TCC_STATUS_IDX (_U_(0x1) << TCC_STATUS_IDX_Pos)
-#define TCC_STATUS_UFS_Pos 2 /**< \brief (TCC_STATUS) Non-recoverable Update Fault State */
-#define TCC_STATUS_UFS (_U_(0x1) << TCC_STATUS_UFS_Pos)
-#define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
-#define TCC_STATUS_DFS (_U_(0x1) << TCC_STATUS_DFS_Pos)
-#define TCC_STATUS_SLAVE_Pos 4 /**< \brief (TCC_STATUS) Slave */
-#define TCC_STATUS_SLAVE (_U_(0x1) << TCC_STATUS_SLAVE_Pos)
-#define TCC_STATUS_PATTBUFV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */
-#define TCC_STATUS_PATTBUFV (_U_(0x1) << TCC_STATUS_PATTBUFV_Pos)
-#define TCC_STATUS_PERBUFV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */
-#define TCC_STATUS_PERBUFV (_U_(0x1) << TCC_STATUS_PERBUFV_Pos)
-#define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable Fault A Input */
-#define TCC_STATUS_FAULTAIN (_U_(0x1) << TCC_STATUS_FAULTAIN_Pos)
-#define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable Fault B Input */
-#define TCC_STATUS_FAULTBIN (_U_(0x1) << TCC_STATUS_FAULTBIN_Pos)
-#define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
-#define TCC_STATUS_FAULT0IN (_U_(0x1) << TCC_STATUS_FAULT0IN_Pos)
-#define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
-#define TCC_STATUS_FAULT1IN (_U_(0x1) << TCC_STATUS_FAULT1IN_Pos)
-#define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable Fault A State */
-#define TCC_STATUS_FAULTA (_U_(0x1) << TCC_STATUS_FAULTA_Pos)
-#define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable Fault B State */
-#define TCC_STATUS_FAULTB (_U_(0x1) << TCC_STATUS_FAULTB_Pos)
-#define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
-#define TCC_STATUS_FAULT0 (_U_(0x1) << TCC_STATUS_FAULT0_Pos)
-#define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
-#define TCC_STATUS_FAULT1 (_U_(0x1) << TCC_STATUS_FAULT1_Pos)
-#define TCC_STATUS_CCBUFV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
-#define TCC_STATUS_CCBUFV0 (_U_(1) << TCC_STATUS_CCBUFV0_Pos)
-#define TCC_STATUS_CCBUFV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
-#define TCC_STATUS_CCBUFV1 (_U_(1) << TCC_STATUS_CCBUFV1_Pos)
-#define TCC_STATUS_CCBUFV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
-#define TCC_STATUS_CCBUFV2 (_U_(1) << TCC_STATUS_CCBUFV2_Pos)
-#define TCC_STATUS_CCBUFV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
-#define TCC_STATUS_CCBUFV3 (_U_(1) << TCC_STATUS_CCBUFV3_Pos)
-#define TCC_STATUS_CCBUFV4_Pos 20 /**< \brief (TCC_STATUS) Compare Channel 4 Buffer Valid */
-#define TCC_STATUS_CCBUFV4 (_U_(1) << TCC_STATUS_CCBUFV4_Pos)
-#define TCC_STATUS_CCBUFV5_Pos 21 /**< \brief (TCC_STATUS) Compare Channel 5 Buffer Valid */
-#define TCC_STATUS_CCBUFV5 (_U_(1) << TCC_STATUS_CCBUFV5_Pos)
-#define TCC_STATUS_CCBUFV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
-#define TCC_STATUS_CCBUFV_Msk (_U_(0x3F) << TCC_STATUS_CCBUFV_Pos)
-#define TCC_STATUS_CCBUFV(value) (TCC_STATUS_CCBUFV_Msk & ((value) << TCC_STATUS_CCBUFV_Pos))
-#define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */
-#define TCC_STATUS_CMP0 (_U_(1) << TCC_STATUS_CMP0_Pos)
-#define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */
-#define TCC_STATUS_CMP1 (_U_(1) << TCC_STATUS_CMP1_Pos)
-#define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */
-#define TCC_STATUS_CMP2 (_U_(1) << TCC_STATUS_CMP2_Pos)
-#define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */
-#define TCC_STATUS_CMP3 (_U_(1) << TCC_STATUS_CMP3_Pos)
-#define TCC_STATUS_CMP4_Pos 28 /**< \brief (TCC_STATUS) Compare Channel 4 Value */
-#define TCC_STATUS_CMP4 (_U_(1) << TCC_STATUS_CMP4_Pos)
-#define TCC_STATUS_CMP5_Pos 29 /**< \brief (TCC_STATUS) Compare Channel 5 Value */
-#define TCC_STATUS_CMP5 (_U_(1) << TCC_STATUS_CMP5_Pos)
-#define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */
-#define TCC_STATUS_CMP_Msk (_U_(0x3F) << TCC_STATUS_CMP_Pos)
-#define TCC_STATUS_CMP(value) (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
-#define TCC_STATUS_MASK _U_(0x3F3FFFBF) /**< \brief (TCC_STATUS) MASK Register */
-
-/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct { // DITH4 mode
- uint32_t :4; /*!< bit: 0.. 3 Reserved */
- uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t :5; /*!< bit: 0.. 4 Reserved */
- uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t :6; /*!< bit: 0.. 5 Reserved */
- uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} TCC_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */
-#define TCC_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (TCC_COUNT reset_value) Count */
-
-// DITH4 mode
-#define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */
-#define TCC_COUNT_DITH4_COUNT_Msk (_U_(0xFFFFF) << TCC_COUNT_DITH4_COUNT_Pos)
-#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
-#define TCC_COUNT_DITH4_MASK _U_(0x00FFFFF0) /**< \brief (TCC_COUNT_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */
-#define TCC_COUNT_DITH5_COUNT_Msk (_U_(0x7FFFF) << TCC_COUNT_DITH5_COUNT_Pos)
-#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
-#define TCC_COUNT_DITH5_MASK _U_(0x00FFFFE0) /**< \brief (TCC_COUNT_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */
-#define TCC_COUNT_DITH6_COUNT_Msk (_U_(0x3FFFF) << TCC_COUNT_DITH6_COUNT_Pos)
-#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
-#define TCC_COUNT_DITH6_MASK _U_(0x00FFFFC0) /**< \brief (TCC_COUNT_DITH6) MASK Register */
-
-#define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */
-#define TCC_COUNT_COUNT_Msk (_U_(0xFFFFFF) << TCC_COUNT_COUNT_Pos)
-#define TCC_COUNT_COUNT(value) (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
-#define TCC_COUNT_MASK _U_(0x00FFFFFF) /**< \brief (TCC_COUNT) MASK Register */
-
-/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
- uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
- uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
- uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
- uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
- uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
- uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
- uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
- uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
- uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
- uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
- uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
- uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
- uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
- uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
- uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
- uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} TCC_PATT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */
-#define TCC_PATT_RESETVALUE _U_(0x0000) /**< \brief (TCC_PATT reset_value) Pattern */
-
-#define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
-#define TCC_PATT_PGE0 (_U_(1) << TCC_PATT_PGE0_Pos)
-#define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
-#define TCC_PATT_PGE1 (_U_(1) << TCC_PATT_PGE1_Pos)
-#define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
-#define TCC_PATT_PGE2 (_U_(1) << TCC_PATT_PGE2_Pos)
-#define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
-#define TCC_PATT_PGE3 (_U_(1) << TCC_PATT_PGE3_Pos)
-#define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
-#define TCC_PATT_PGE4 (_U_(1) << TCC_PATT_PGE4_Pos)
-#define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
-#define TCC_PATT_PGE5 (_U_(1) << TCC_PATT_PGE5_Pos)
-#define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
-#define TCC_PATT_PGE6 (_U_(1) << TCC_PATT_PGE6_Pos)
-#define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
-#define TCC_PATT_PGE7 (_U_(1) << TCC_PATT_PGE7_Pos)
-#define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
-#define TCC_PATT_PGE_Msk (_U_(0xFF) << TCC_PATT_PGE_Pos)
-#define TCC_PATT_PGE(value) (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
-#define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
-#define TCC_PATT_PGV0 (_U_(1) << TCC_PATT_PGV0_Pos)
-#define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
-#define TCC_PATT_PGV1 (_U_(1) << TCC_PATT_PGV1_Pos)
-#define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
-#define TCC_PATT_PGV2 (_U_(1) << TCC_PATT_PGV2_Pos)
-#define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
-#define TCC_PATT_PGV3 (_U_(1) << TCC_PATT_PGV3_Pos)
-#define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
-#define TCC_PATT_PGV4 (_U_(1) << TCC_PATT_PGV4_Pos)
-#define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
-#define TCC_PATT_PGV5 (_U_(1) << TCC_PATT_PGV5_Pos)
-#define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
-#define TCC_PATT_PGV6 (_U_(1) << TCC_PATT_PGV6_Pos)
-#define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
-#define TCC_PATT_PGV7 (_U_(1) << TCC_PATT_PGV7_Pos)
-#define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */
-#define TCC_PATT_PGV_Msk (_U_(0xFF) << TCC_PATT_PGV_Pos)
-#define TCC_PATT_PGV(value) (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
-#define TCC_PATT_MASK _U_(0xFFFF) /**< \brief (TCC_PATT) MASK Register */
-
-/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
- uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
- uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
- uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
- uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
- uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
- uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
- uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
- uint32_t POL4:1; /*!< bit: 20 Channel 4 Polarity */
- uint32_t POL5:1; /*!< bit: 21 Channel 5 Polarity */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
- uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
- uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
- uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POL:6; /*!< bit: 16..21 Channel x Polarity */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} TCC_WAVE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */
-#define TCC_WAVE_RESETVALUE _U_(0x00000000) /**< \brief (TCC_WAVE reset_value) Waveform Control */
-
-#define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */
-#define TCC_WAVE_WAVEGEN_Msk (_U_(0x7) << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN(value) (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
-#define TCC_WAVE_WAVEGEN_NFRQ_Val _U_(0x0) /**< \brief (TCC_WAVE) Normal frequency */
-#define TCC_WAVE_WAVEGEN_MFRQ_Val _U_(0x1) /**< \brief (TCC_WAVE) Match frequency */
-#define TCC_WAVE_WAVEGEN_NPWM_Val _U_(0x2) /**< \brief (TCC_WAVE) Normal PWM */
-#define TCC_WAVE_WAVEGEN_DSCRITICAL_Val _U_(0x4) /**< \brief (TCC_WAVE) Dual-slope critical */
-#define TCC_WAVE_WAVEGEN_DSBOTTOM_Val _U_(0x5) /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
-#define TCC_WAVE_WAVEGEN_DSBOTH_Val _U_(0x6) /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
-#define TCC_WAVE_WAVEGEN_DSTOP_Val _U_(0x7) /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */
-#define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */
-#define TCC_WAVE_RAMP_Msk (_U_(0x3) << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP(value) (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
-#define TCC_WAVE_RAMP_RAMP1_Val _U_(0x0) /**< \brief (TCC_WAVE) RAMP1 operation */
-#define TCC_WAVE_RAMP_RAMP2A_Val _U_(0x1) /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
-#define TCC_WAVE_RAMP_RAMP2_Val _U_(0x2) /**< \brief (TCC_WAVE) RAMP2 operation */
-#define TCC_WAVE_RAMP_RAMP2C_Val _U_(0x3) /**< \brief (TCC_WAVE) Critical RAMP2 operation */
-#define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP_RAMP2C (TCC_WAVE_RAMP_RAMP2C_Val << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */
-#define TCC_WAVE_CIPEREN (_U_(0x1) << TCC_WAVE_CIPEREN_Pos)
-#define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
-#define TCC_WAVE_CICCEN0 (_U_(1) << TCC_WAVE_CICCEN0_Pos)
-#define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
-#define TCC_WAVE_CICCEN1 (_U_(1) << TCC_WAVE_CICCEN1_Pos)
-#define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
-#define TCC_WAVE_CICCEN2 (_U_(1) << TCC_WAVE_CICCEN2_Pos)
-#define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
-#define TCC_WAVE_CICCEN3 (_U_(1) << TCC_WAVE_CICCEN3_Pos)
-#define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */
-#define TCC_WAVE_CICCEN_Msk (_U_(0xF) << TCC_WAVE_CICCEN_Pos)
-#define TCC_WAVE_CICCEN(value) (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
-#define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */
-#define TCC_WAVE_POL0 (_U_(1) << TCC_WAVE_POL0_Pos)
-#define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */
-#define TCC_WAVE_POL1 (_U_(1) << TCC_WAVE_POL1_Pos)
-#define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */
-#define TCC_WAVE_POL2 (_U_(1) << TCC_WAVE_POL2_Pos)
-#define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */
-#define TCC_WAVE_POL3 (_U_(1) << TCC_WAVE_POL3_Pos)
-#define TCC_WAVE_POL4_Pos 20 /**< \brief (TCC_WAVE) Channel 4 Polarity */
-#define TCC_WAVE_POL4 (_U_(1) << TCC_WAVE_POL4_Pos)
-#define TCC_WAVE_POL5_Pos 21 /**< \brief (TCC_WAVE) Channel 5 Polarity */
-#define TCC_WAVE_POL5 (_U_(1) << TCC_WAVE_POL5_Pos)
-#define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */
-#define TCC_WAVE_POL_Msk (_U_(0x3F) << TCC_WAVE_POL_Pos)
-#define TCC_WAVE_POL(value) (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
-#define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
-#define TCC_WAVE_SWAP0 (_U_(1) << TCC_WAVE_SWAP0_Pos)
-#define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
-#define TCC_WAVE_SWAP1 (_U_(1) << TCC_WAVE_SWAP1_Pos)
-#define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
-#define TCC_WAVE_SWAP2 (_U_(1) << TCC_WAVE_SWAP2_Pos)
-#define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
-#define TCC_WAVE_SWAP3 (_U_(1) << TCC_WAVE_SWAP3_Pos)
-#define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
-#define TCC_WAVE_SWAP_Msk (_U_(0xF) << TCC_WAVE_SWAP_Pos)
-#define TCC_WAVE_SWAP(value) (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
-#define TCC_WAVE_MASK _U_(0x0F3F0FB7) /**< \brief (TCC_WAVE) MASK Register */
-
-/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct { // DITH4 mode
- uint32_t DITHER:4; /*!< bit: 0.. 3 Dithering Cycle Number */
- uint32_t PER:20; /*!< bit: 4..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHER:5; /*!< bit: 0.. 4 Dithering Cycle Number */
- uint32_t PER:19; /*!< bit: 5..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHER:6; /*!< bit: 0.. 5 Dithering Cycle Number */
- uint32_t PER:18; /*!< bit: 6..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t PER:24; /*!< bit: 0..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} TCC_PER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */
-#define TCC_PER_RESETVALUE _U_(0xFFFFFFFF) /**< \brief (TCC_PER reset_value) Period */
-
-// DITH4 mode
-#define TCC_PER_DITH4_DITHER_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
-#define TCC_PER_DITH4_DITHER_Msk (_U_(0xF) << TCC_PER_DITH4_DITHER_Pos)
-#define TCC_PER_DITH4_DITHER(value) (TCC_PER_DITH4_DITHER_Msk & ((value) << TCC_PER_DITH4_DITHER_Pos))
-#define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */
-#define TCC_PER_DITH4_PER_Msk (_U_(0xFFFFF) << TCC_PER_DITH4_PER_Pos)
-#define TCC_PER_DITH4_PER(value) (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
-#define TCC_PER_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_PER_DITH5_DITHER_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
-#define TCC_PER_DITH5_DITHER_Msk (_U_(0x1F) << TCC_PER_DITH5_DITHER_Pos)
-#define TCC_PER_DITH5_DITHER(value) (TCC_PER_DITH5_DITHER_Msk & ((value) << TCC_PER_DITH5_DITHER_Pos))
-#define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */
-#define TCC_PER_DITH5_PER_Msk (_U_(0x7FFFF) << TCC_PER_DITH5_PER_Pos)
-#define TCC_PER_DITH5_PER(value) (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
-#define TCC_PER_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_PER_DITH6_DITHER_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
-#define TCC_PER_DITH6_DITHER_Msk (_U_(0x3F) << TCC_PER_DITH6_DITHER_Pos)
-#define TCC_PER_DITH6_DITHER(value) (TCC_PER_DITH6_DITHER_Msk & ((value) << TCC_PER_DITH6_DITHER_Pos))
-#define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */
-#define TCC_PER_DITH6_PER_Msk (_U_(0x3FFFF) << TCC_PER_DITH6_PER_Pos)
-#define TCC_PER_DITH6_PER(value) (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
-#define TCC_PER_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH6) MASK Register */
-
-#define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */
-#define TCC_PER_PER_Msk (_U_(0xFFFFFF) << TCC_PER_PER_Pos)
-#define TCC_PER_PER(value) (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
-#define TCC_PER_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER) MASK Register */
-
-/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct { // DITH4 mode
- uint32_t DITHER:4; /*!< bit: 0.. 3 Dithering Cycle Number */
- uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHER:5; /*!< bit: 0.. 4 Dithering Cycle Number */
- uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHER:6; /*!< bit: 0.. 5 Dithering Cycle Number */
- uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} TCC_CC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */
-#define TCC_CC_RESETVALUE _U_(0x00000000) /**< \brief (TCC_CC reset_value) Compare and Capture */
-
-// DITH4 mode
-#define TCC_CC_DITH4_DITHER_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
-#define TCC_CC_DITH4_DITHER_Msk (_U_(0xF) << TCC_CC_DITH4_DITHER_Pos)
-#define TCC_CC_DITH4_DITHER(value) (TCC_CC_DITH4_DITHER_Msk & ((value) << TCC_CC_DITH4_DITHER_Pos))
-#define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
-#define TCC_CC_DITH4_CC_Msk (_U_(0xFFFFF) << TCC_CC_DITH4_CC_Pos)
-#define TCC_CC_DITH4_CC(value) (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
-#define TCC_CC_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_CC_DITH5_DITHER_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
-#define TCC_CC_DITH5_DITHER_Msk (_U_(0x1F) << TCC_CC_DITH5_DITHER_Pos)
-#define TCC_CC_DITH5_DITHER(value) (TCC_CC_DITH5_DITHER_Msk & ((value) << TCC_CC_DITH5_DITHER_Pos))
-#define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
-#define TCC_CC_DITH5_CC_Msk (_U_(0x7FFFF) << TCC_CC_DITH5_CC_Pos)
-#define TCC_CC_DITH5_CC(value) (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
-#define TCC_CC_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_CC_DITH6_DITHER_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
-#define TCC_CC_DITH6_DITHER_Msk (_U_(0x3F) << TCC_CC_DITH6_DITHER_Pos)
-#define TCC_CC_DITH6_DITHER(value) (TCC_CC_DITH6_DITHER_Msk & ((value) << TCC_CC_DITH6_DITHER_Pos))
-#define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
-#define TCC_CC_DITH6_CC_Msk (_U_(0x3FFFF) << TCC_CC_DITH6_CC_Pos)
-#define TCC_CC_DITH6_CC(value) (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
-#define TCC_CC_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH6) MASK Register */
-
-#define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */
-#define TCC_CC_CC_Msk (_U_(0xFFFFFF) << TCC_CC_CC_Pos)
-#define TCC_CC_CC(value) (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
-#define TCC_CC_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC) MASK Register */
-
-/* -------- TCC_PATTBUF : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
- uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
- uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
- uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
- uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
- uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
- uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
- uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
- uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
- uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
- uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
- uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
- uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
- uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
- uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
- uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
- uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} TCC_PATTBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PATTBUF_OFFSET 0x64 /**< \brief (TCC_PATTBUF offset) Pattern Buffer */
-#define TCC_PATTBUF_RESETVALUE _U_(0x0000) /**< \brief (TCC_PATTBUF reset_value) Pattern Buffer */
-
-#define TCC_PATTBUF_PGEB0_Pos 0 /**< \brief (TCC_PATTBUF) Pattern Generator 0 Output Enable Buffer */
-#define TCC_PATTBUF_PGEB0 (_U_(1) << TCC_PATTBUF_PGEB0_Pos)
-#define TCC_PATTBUF_PGEB1_Pos 1 /**< \brief (TCC_PATTBUF) Pattern Generator 1 Output Enable Buffer */
-#define TCC_PATTBUF_PGEB1 (_U_(1) << TCC_PATTBUF_PGEB1_Pos)
-#define TCC_PATTBUF_PGEB2_Pos 2 /**< \brief (TCC_PATTBUF) Pattern Generator 2 Output Enable Buffer */
-#define TCC_PATTBUF_PGEB2 (_U_(1) << TCC_PATTBUF_PGEB2_Pos)
-#define TCC_PATTBUF_PGEB3_Pos 3 /**< \brief (TCC_PATTBUF) Pattern Generator 3 Output Enable Buffer */
-#define TCC_PATTBUF_PGEB3 (_U_(1) << TCC_PATTBUF_PGEB3_Pos)
-#define TCC_PATTBUF_PGEB4_Pos 4 /**< \brief (TCC_PATTBUF) Pattern Generator 4 Output Enable Buffer */
-#define TCC_PATTBUF_PGEB4 (_U_(1) << TCC_PATTBUF_PGEB4_Pos)
-#define TCC_PATTBUF_PGEB5_Pos 5 /**< \brief (TCC_PATTBUF) Pattern Generator 5 Output Enable Buffer */
-#define TCC_PATTBUF_PGEB5 (_U_(1) << TCC_PATTBUF_PGEB5_Pos)
-#define TCC_PATTBUF_PGEB6_Pos 6 /**< \brief (TCC_PATTBUF) Pattern Generator 6 Output Enable Buffer */
-#define TCC_PATTBUF_PGEB6 (_U_(1) << TCC_PATTBUF_PGEB6_Pos)
-#define TCC_PATTBUF_PGEB7_Pos 7 /**< \brief (TCC_PATTBUF) Pattern Generator 7 Output Enable Buffer */
-#define TCC_PATTBUF_PGEB7 (_U_(1) << TCC_PATTBUF_PGEB7_Pos)
-#define TCC_PATTBUF_PGEB_Pos 0 /**< \brief (TCC_PATTBUF) Pattern Generator x Output Enable Buffer */
-#define TCC_PATTBUF_PGEB_Msk (_U_(0xFF) << TCC_PATTBUF_PGEB_Pos)
-#define TCC_PATTBUF_PGEB(value) (TCC_PATTBUF_PGEB_Msk & ((value) << TCC_PATTBUF_PGEB_Pos))
-#define TCC_PATTBUF_PGVB0_Pos 8 /**< \brief (TCC_PATTBUF) Pattern Generator 0 Output Enable */
-#define TCC_PATTBUF_PGVB0 (_U_(1) << TCC_PATTBUF_PGVB0_Pos)
-#define TCC_PATTBUF_PGVB1_Pos 9 /**< \brief (TCC_PATTBUF) Pattern Generator 1 Output Enable */
-#define TCC_PATTBUF_PGVB1 (_U_(1) << TCC_PATTBUF_PGVB1_Pos)
-#define TCC_PATTBUF_PGVB2_Pos 10 /**< \brief (TCC_PATTBUF) Pattern Generator 2 Output Enable */
-#define TCC_PATTBUF_PGVB2 (_U_(1) << TCC_PATTBUF_PGVB2_Pos)
-#define TCC_PATTBUF_PGVB3_Pos 11 /**< \brief (TCC_PATTBUF) Pattern Generator 3 Output Enable */
-#define TCC_PATTBUF_PGVB3 (_U_(1) << TCC_PATTBUF_PGVB3_Pos)
-#define TCC_PATTBUF_PGVB4_Pos 12 /**< \brief (TCC_PATTBUF) Pattern Generator 4 Output Enable */
-#define TCC_PATTBUF_PGVB4 (_U_(1) << TCC_PATTBUF_PGVB4_Pos)
-#define TCC_PATTBUF_PGVB5_Pos 13 /**< \brief (TCC_PATTBUF) Pattern Generator 5 Output Enable */
-#define TCC_PATTBUF_PGVB5 (_U_(1) << TCC_PATTBUF_PGVB5_Pos)
-#define TCC_PATTBUF_PGVB6_Pos 14 /**< \brief (TCC_PATTBUF) Pattern Generator 6 Output Enable */
-#define TCC_PATTBUF_PGVB6 (_U_(1) << TCC_PATTBUF_PGVB6_Pos)
-#define TCC_PATTBUF_PGVB7_Pos 15 /**< \brief (TCC_PATTBUF) Pattern Generator 7 Output Enable */
-#define TCC_PATTBUF_PGVB7 (_U_(1) << TCC_PATTBUF_PGVB7_Pos)
-#define TCC_PATTBUF_PGVB_Pos 8 /**< \brief (TCC_PATTBUF) Pattern Generator x Output Enable */
-#define TCC_PATTBUF_PGVB_Msk (_U_(0xFF) << TCC_PATTBUF_PGVB_Pos)
-#define TCC_PATTBUF_PGVB(value) (TCC_PATTBUF_PGVB_Msk & ((value) << TCC_PATTBUF_PGVB_Pos))
-#define TCC_PATTBUF_MASK _U_(0xFFFF) /**< \brief (TCC_PATTBUF) MASK Register */
-
-/* -------- TCC_PERBUF : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct { // DITH4 mode
- uint32_t DITHERBUF:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
- uint32_t PERBUF:20; /*!< bit: 4..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERBUF:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
- uint32_t PERBUF:19; /*!< bit: 5..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERBUF:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
- uint32_t PERBUF:18; /*!< bit: 6..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t PERBUF:24; /*!< bit: 0..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} TCC_PERBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PERBUF_OFFSET 0x6C /**< \brief (TCC_PERBUF offset) Period Buffer */
-#define TCC_PERBUF_RESETVALUE _U_(0xFFFFFFFF) /**< \brief (TCC_PERBUF reset_value) Period Buffer */
-
-// DITH4 mode
-#define TCC_PERBUF_DITH4_DITHERBUF_Pos 0 /**< \brief (TCC_PERBUF_DITH4) Dithering Buffer Cycle Number */
-#define TCC_PERBUF_DITH4_DITHERBUF_Msk (_U_(0xF) << TCC_PERBUF_DITH4_DITHERBUF_Pos)
-#define TCC_PERBUF_DITH4_DITHERBUF(value) (TCC_PERBUF_DITH4_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH4_DITHERBUF_Pos))
-#define TCC_PERBUF_DITH4_PERBUF_Pos 4 /**< \brief (TCC_PERBUF_DITH4) Period Buffer Value */
-#define TCC_PERBUF_DITH4_PERBUF_Msk (_U_(0xFFFFF) << TCC_PERBUF_DITH4_PERBUF_Pos)
-#define TCC_PERBUF_DITH4_PERBUF(value) (TCC_PERBUF_DITH4_PERBUF_Msk & ((value) << TCC_PERBUF_DITH4_PERBUF_Pos))
-#define TCC_PERBUF_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_PERBUF_DITH5_DITHERBUF_Pos 0 /**< \brief (TCC_PERBUF_DITH5) Dithering Buffer Cycle Number */
-#define TCC_PERBUF_DITH5_DITHERBUF_Msk (_U_(0x1F) << TCC_PERBUF_DITH5_DITHERBUF_Pos)
-#define TCC_PERBUF_DITH5_DITHERBUF(value) (TCC_PERBUF_DITH5_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH5_DITHERBUF_Pos))
-#define TCC_PERBUF_DITH5_PERBUF_Pos 5 /**< \brief (TCC_PERBUF_DITH5) Period Buffer Value */
-#define TCC_PERBUF_DITH5_PERBUF_Msk (_U_(0x7FFFF) << TCC_PERBUF_DITH5_PERBUF_Pos)
-#define TCC_PERBUF_DITH5_PERBUF(value) (TCC_PERBUF_DITH5_PERBUF_Msk & ((value) << TCC_PERBUF_DITH5_PERBUF_Pos))
-#define TCC_PERBUF_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_PERBUF_DITH6_DITHERBUF_Pos 0 /**< \brief (TCC_PERBUF_DITH6) Dithering Buffer Cycle Number */
-#define TCC_PERBUF_DITH6_DITHERBUF_Msk (_U_(0x3F) << TCC_PERBUF_DITH6_DITHERBUF_Pos)
-#define TCC_PERBUF_DITH6_DITHERBUF(value) (TCC_PERBUF_DITH6_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH6_DITHERBUF_Pos))
-#define TCC_PERBUF_DITH6_PERBUF_Pos 6 /**< \brief (TCC_PERBUF_DITH6) Period Buffer Value */
-#define TCC_PERBUF_DITH6_PERBUF_Msk (_U_(0x3FFFF) << TCC_PERBUF_DITH6_PERBUF_Pos)
-#define TCC_PERBUF_DITH6_PERBUF(value) (TCC_PERBUF_DITH6_PERBUF_Msk & ((value) << TCC_PERBUF_DITH6_PERBUF_Pos))
-#define TCC_PERBUF_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF_DITH6) MASK Register */
-
-#define TCC_PERBUF_PERBUF_Pos 0 /**< \brief (TCC_PERBUF) Period Buffer Value */
-#define TCC_PERBUF_PERBUF_Msk (_U_(0xFFFFFF) << TCC_PERBUF_PERBUF_Pos)
-#define TCC_PERBUF_PERBUF(value) (TCC_PERBUF_PERBUF_Msk & ((value) << TCC_PERBUF_PERBUF_Pos))
-#define TCC_PERBUF_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF) MASK Register */
-
-/* -------- TCC_CCBUF : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct { // DITH4 mode
- uint32_t CCBUF:4; /*!< bit: 0.. 3 Channel Compare/Capture Buffer Value */
- uint32_t DITHERBUF:20; /*!< bit: 4..23 Dithering Buffer Cycle Number */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERBUF:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
- uint32_t CCBUF:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERBUF:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
- uint32_t CCBUF:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t CCBUF:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} TCC_CCBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CCBUF_OFFSET 0x70 /**< \brief (TCC_CCBUF offset) Compare and Capture Buffer */
-#define TCC_CCBUF_RESETVALUE _U_(0x00000000) /**< \brief (TCC_CCBUF reset_value) Compare and Capture Buffer */
-
-// DITH4 mode
-#define TCC_CCBUF_DITH4_CCBUF_Pos 0 /**< \brief (TCC_CCBUF_DITH4) Channel Compare/Capture Buffer Value */
-#define TCC_CCBUF_DITH4_CCBUF_Msk (_U_(0xF) << TCC_CCBUF_DITH4_CCBUF_Pos)
-#define TCC_CCBUF_DITH4_CCBUF(value) (TCC_CCBUF_DITH4_CCBUF_Msk & ((value) << TCC_CCBUF_DITH4_CCBUF_Pos))
-#define TCC_CCBUF_DITH4_DITHERBUF_Pos 4 /**< \brief (TCC_CCBUF_DITH4) Dithering Buffer Cycle Number */
-#define TCC_CCBUF_DITH4_DITHERBUF_Msk (_U_(0xFFFFF) << TCC_CCBUF_DITH4_DITHERBUF_Pos)
-#define TCC_CCBUF_DITH4_DITHERBUF(value) (TCC_CCBUF_DITH4_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH4_DITHERBUF_Pos))
-#define TCC_CCBUF_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_CCBUF_DITH5_DITHERBUF_Pos 0 /**< \brief (TCC_CCBUF_DITH5) Dithering Buffer Cycle Number */
-#define TCC_CCBUF_DITH5_DITHERBUF_Msk (_U_(0x1F) << TCC_CCBUF_DITH5_DITHERBUF_Pos)
-#define TCC_CCBUF_DITH5_DITHERBUF(value) (TCC_CCBUF_DITH5_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH5_DITHERBUF_Pos))
-#define TCC_CCBUF_DITH5_CCBUF_Pos 5 /**< \brief (TCC_CCBUF_DITH5) Channel Compare/Capture Buffer Value */
-#define TCC_CCBUF_DITH5_CCBUF_Msk (_U_(0x7FFFF) << TCC_CCBUF_DITH5_CCBUF_Pos)
-#define TCC_CCBUF_DITH5_CCBUF(value) (TCC_CCBUF_DITH5_CCBUF_Msk & ((value) << TCC_CCBUF_DITH5_CCBUF_Pos))
-#define TCC_CCBUF_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_CCBUF_DITH6_DITHERBUF_Pos 0 /**< \brief (TCC_CCBUF_DITH6) Dithering Buffer Cycle Number */
-#define TCC_CCBUF_DITH6_DITHERBUF_Msk (_U_(0x3F) << TCC_CCBUF_DITH6_DITHERBUF_Pos)
-#define TCC_CCBUF_DITH6_DITHERBUF(value) (TCC_CCBUF_DITH6_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH6_DITHERBUF_Pos))
-#define TCC_CCBUF_DITH6_CCBUF_Pos 6 /**< \brief (TCC_CCBUF_DITH6) Channel Compare/Capture Buffer Value */
-#define TCC_CCBUF_DITH6_CCBUF_Msk (_U_(0x3FFFF) << TCC_CCBUF_DITH6_CCBUF_Pos)
-#define TCC_CCBUF_DITH6_CCBUF(value) (TCC_CCBUF_DITH6_CCBUF_Msk & ((value) << TCC_CCBUF_DITH6_CCBUF_Pos))
-#define TCC_CCBUF_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF_DITH6) MASK Register */
-
-#define TCC_CCBUF_CCBUF_Pos 0 /**< \brief (TCC_CCBUF) Channel Compare/Capture Buffer Value */
-#define TCC_CCBUF_CCBUF_Msk (_U_(0xFFFFFF) << TCC_CCBUF_CCBUF_Pos)
-#define TCC_CCBUF_CCBUF(value) (TCC_CCBUF_CCBUF_Msk & ((value) << TCC_CCBUF_CCBUF_Pos))
-#define TCC_CCBUF_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF) MASK Register */
-
-/** \brief TCC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
- __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- RoReg8 Reserved1[0x2];
- __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
- __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
- __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
- __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
- __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
- RoReg8 Reserved2[0x2];
- __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
- RoReg8 Reserved3[0x1];
- __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
- __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
- __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
- __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
- __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
- __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
- __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
- RoReg8 Reserved4[0x2];
- __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
- __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
- __IO TCC_CC_Type CC[6]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
- RoReg8 Reserved5[0x8];
- __IO TCC_PATTBUF_Type PATTBUF; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
- RoReg8 Reserved6[0x6];
- __IO TCC_PERBUF_Type PERBUF; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
- __IO TCC_CCBUF_Type CCBUF[6]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
-} Tcc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_TCC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for TCC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TCC_COMPONENT_
+#define _SAME54_TCC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR TCC */
+/* ========================================================================== */
+/** \addtogroup SAME54_TCC Timer Counter Control */
+/*@{*/
+
+#define TCC_U2213
+#define REV_TCC 0x310
+
+/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t :3; /*!< bit: 2.. 4 Reserved */
+ uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
+ uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
+ uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
+ uint32_t MSYNC:1; /*!< bit: 15 Master Synchronization (only for TCC Slave Instance) */
+ uint32_t :7; /*!< bit: 16..22 Reserved */
+ uint32_t DMAOS:1; /*!< bit: 23 DMA One-shot Trigger Mode */
+ uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
+ uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
+ uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
+ uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
+ uint32_t CPTEN4:1; /*!< bit: 28 Capture Channel 4 Enable */
+ uint32_t CPTEN5:1; /*!< bit: 29 Capture Channel 5 Enable */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :24; /*!< bit: 0..23 Reserved */
+ uint32_t CPTEN:6; /*!< bit: 24..29 Capture Channel x Enable */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */
+#define TCC_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (TCC_CTRLA reset_value) Control A */
+
+#define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */
+#define TCC_CTRLA_SWRST (_U_(0x1) << TCC_CTRLA_SWRST_Pos)
+#define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */
+#define TCC_CTRLA_ENABLE (_U_(0x1) << TCC_CTRLA_ENABLE_Pos)
+#define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */
+#define TCC_CTRLA_RESOLUTION_Msk (_U_(0x3) << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
+#define TCC_CTRLA_RESOLUTION_NONE_Val _U_(0x0) /**< \brief (TCC_CTRLA) Dithering is disabled */
+#define TCC_CTRLA_RESOLUTION_DITH4_Val _U_(0x1) /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
+#define TCC_CTRLA_RESOLUTION_DITH5_Val _U_(0x2) /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
+#define TCC_CTRLA_RESOLUTION_DITH6_Val _U_(0x3) /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */
+#define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */
+#define TCC_CTRLA_PRESCALER_Msk (_U_(0x7) << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER(value) (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
+#define TCC_CTRLA_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (TCC_CTRLA) No division */
+#define TCC_CTRLA_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (TCC_CTRLA) Divide by 2 */
+#define TCC_CTRLA_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (TCC_CTRLA) Divide by 4 */
+#define TCC_CTRLA_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (TCC_CTRLA) Divide by 8 */
+#define TCC_CTRLA_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (TCC_CTRLA) Divide by 16 */
+#define TCC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (TCC_CTRLA) Divide by 64 */
+#define TCC_CTRLA_PRESCALER_DIV256_Val _U_(0x6) /**< \brief (TCC_CTRLA) Divide by 256 */
+#define TCC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7) /**< \brief (TCC_CTRLA) Divide by 1024 */
+#define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */
+#define TCC_CTRLA_RUNSTDBY (_U_(0x1) << TCC_CTRLA_RUNSTDBY_Pos)
+#define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
+#define TCC_CTRLA_PRESCSYNC_Msk (_U_(0x3) << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC(value) (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
+#define TCC_CTRLA_PRESCSYNC_GCLK_Val _U_(0x0) /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
+#define TCC_CTRLA_PRESCSYNC_PRESC_Val _U_(0x1) /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
+#define TCC_CTRLA_PRESCSYNC_RESYNC_Val _U_(0x2) /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
+#define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */
+#define TCC_CTRLA_ALOCK (_U_(0x1) << TCC_CTRLA_ALOCK_Pos)
+#define TCC_CTRLA_MSYNC_Pos 15 /**< \brief (TCC_CTRLA) Master Synchronization (only for TCC Slave Instance) */
+#define TCC_CTRLA_MSYNC (_U_(0x1) << TCC_CTRLA_MSYNC_Pos)
+#define TCC_CTRLA_DMAOS_Pos 23 /**< \brief (TCC_CTRLA) DMA One-shot Trigger Mode */
+#define TCC_CTRLA_DMAOS (_U_(0x1) << TCC_CTRLA_DMAOS_Pos)
+#define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
+#define TCC_CTRLA_CPTEN0 (_U_(1) << TCC_CTRLA_CPTEN0_Pos)
+#define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
+#define TCC_CTRLA_CPTEN1 (_U_(1) << TCC_CTRLA_CPTEN1_Pos)
+#define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
+#define TCC_CTRLA_CPTEN2 (_U_(1) << TCC_CTRLA_CPTEN2_Pos)
+#define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
+#define TCC_CTRLA_CPTEN3 (_U_(1) << TCC_CTRLA_CPTEN3_Pos)
+#define TCC_CTRLA_CPTEN4_Pos 28 /**< \brief (TCC_CTRLA) Capture Channel 4 Enable */
+#define TCC_CTRLA_CPTEN4 (_U_(1) << TCC_CTRLA_CPTEN4_Pos)
+#define TCC_CTRLA_CPTEN5_Pos 29 /**< \brief (TCC_CTRLA) Capture Channel 5 Enable */
+#define TCC_CTRLA_CPTEN5 (_U_(1) << TCC_CTRLA_CPTEN5_Pos)
+#define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */
+#define TCC_CTRLA_CPTEN_Msk (_U_(0x3F) << TCC_CTRLA_CPTEN_Pos)
+#define TCC_CTRLA_CPTEN(value) (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
+#define TCC_CTRLA_MASK _U_(0x3F80FF63) /**< \brief (TCC_CTRLA) MASK Register */
+
+/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TCC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
+#define TCC_CTRLBCLR_RESETVALUE _U_(0x00) /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
+
+#define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */
+#define TCC_CTRLBCLR_DIR (_U_(0x1) << TCC_CTRLBCLR_DIR_Pos)
+#define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */
+#define TCC_CTRLBCLR_LUPD (_U_(0x1) << TCC_CTRLBCLR_LUPD_Pos)
+#define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */
+#define TCC_CTRLBCLR_ONESHOT (_U_(0x1) << TCC_CTRLBCLR_ONESHOT_Pos)
+#define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
+#define TCC_CTRLBCLR_IDXCMD_Msk (_U_(0x3) << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD(value) (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
+#define TCC_CTRLBCLR_IDXCMD_DISABLE_Val _U_(0x0) /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
+#define TCC_CTRLBCLR_IDXCMD_SET_Val _U_(0x1) /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
+#define TCC_CTRLBCLR_IDXCMD_CLEAR_Val _U_(0x2) /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
+#define TCC_CTRLBCLR_IDXCMD_HOLD_Val _U_(0x3) /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */
+#define TCC_CTRLBCLR_CMD_Msk (_U_(0x7) << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD(value) (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
+#define TCC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< \brief (TCC_CTRLBCLR) No action */
+#define TCC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
+#define TCC_CTRLBCLR_CMD_STOP_Val _U_(0x2) /**< \brief (TCC_CTRLBCLR) Force stop */
+#define TCC_CTRLBCLR_CMD_UPDATE_Val _U_(0x3) /**< \brief (TCC_CTRLBCLR) Force update or double buffered registers */
+#define TCC_CTRLBCLR_CMD_READSYNC_Val _U_(0x4) /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
+#define TCC_CTRLBCLR_CMD_DMAOS_Val _U_(0x5) /**< \brief (TCC_CTRLBCLR) One-shot DMA trigger */
+#define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_DMAOS (TCC_CTRLBCLR_CMD_DMAOS_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_MASK _U_(0xFF) /**< \brief (TCC_CTRLBCLR) MASK Register */
+
+/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TCC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */
+#define TCC_CTRLBSET_RESETVALUE _U_(0x00) /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
+
+#define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */
+#define TCC_CTRLBSET_DIR (_U_(0x1) << TCC_CTRLBSET_DIR_Pos)
+#define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock Update */
+#define TCC_CTRLBSET_LUPD (_U_(0x1) << TCC_CTRLBSET_LUPD_Pos)
+#define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */
+#define TCC_CTRLBSET_ONESHOT (_U_(0x1) << TCC_CTRLBSET_ONESHOT_Pos)
+#define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */
+#define TCC_CTRLBSET_IDXCMD_Msk (_U_(0x3) << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD(value) (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
+#define TCC_CTRLBSET_IDXCMD_DISABLE_Val _U_(0x0) /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
+#define TCC_CTRLBSET_IDXCMD_SET_Val _U_(0x1) /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
+#define TCC_CTRLBSET_IDXCMD_CLEAR_Val _U_(0x2) /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
+#define TCC_CTRLBSET_IDXCMD_HOLD_Val _U_(0x3) /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */
+#define TCC_CTRLBSET_CMD_Msk (_U_(0x7) << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD(value) (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
+#define TCC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< \brief (TCC_CTRLBSET) No action */
+#define TCC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
+#define TCC_CTRLBSET_CMD_STOP_Val _U_(0x2) /**< \brief (TCC_CTRLBSET) Force stop */
+#define TCC_CTRLBSET_CMD_UPDATE_Val _U_(0x3) /**< \brief (TCC_CTRLBSET) Force update or double buffered registers */
+#define TCC_CTRLBSET_CMD_READSYNC_Val _U_(0x4) /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
+#define TCC_CTRLBSET_CMD_DMAOS_Val _U_(0x5) /**< \brief (TCC_CTRLBSET) One-shot DMA trigger */
+#define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_DMAOS (TCC_CTRLBSET_CMD_DMAOS_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_MASK _U_(0xFF) /**< \brief (TCC_CTRLBSET) MASK Register */
+
+/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
+ uint32_t STATUS:1; /*!< bit: 3 Status Busy */
+ uint32_t COUNT:1; /*!< bit: 4 Count Busy */
+ uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
+ uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
+ uint32_t PER:1; /*!< bit: 7 Period Busy */
+ uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
+ uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
+ uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
+ uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
+ uint32_t CC4:1; /*!< bit: 12 Compare Channel 4 Busy */
+ uint32_t CC5:1; /*!< bit: 13 Compare Channel 5 Busy */
+ uint32_t :18; /*!< bit: 14..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CC:6; /*!< bit: 8..13 Compare Channel x Busy */
+ uint32_t :18; /*!< bit: 14..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
+#define TCC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */
+#define TCC_SYNCBUSY_SWRST (_U_(0x1) << TCC_SYNCBUSY_SWRST_Pos)
+#define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */
+#define TCC_SYNCBUSY_ENABLE (_U_(0x1) << TCC_SYNCBUSY_ENABLE_Pos)
+#define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
+#define TCC_SYNCBUSY_CTRLB (_U_(0x1) << TCC_SYNCBUSY_CTRLB_Pos)
+#define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */
+#define TCC_SYNCBUSY_STATUS (_U_(0x1) << TCC_SYNCBUSY_STATUS_Pos)
+#define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */
+#define TCC_SYNCBUSY_COUNT (_U_(0x1) << TCC_SYNCBUSY_COUNT_Pos)
+#define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */
+#define TCC_SYNCBUSY_PATT (_U_(0x1) << TCC_SYNCBUSY_PATT_Pos)
+#define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */
+#define TCC_SYNCBUSY_WAVE (_U_(0x1) << TCC_SYNCBUSY_WAVE_Pos)
+#define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period Busy */
+#define TCC_SYNCBUSY_PER (_U_(0x1) << TCC_SYNCBUSY_PER_Pos)
+#define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */
+#define TCC_SYNCBUSY_CC0 (_U_(1) << TCC_SYNCBUSY_CC0_Pos)
+#define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */
+#define TCC_SYNCBUSY_CC1 (_U_(1) << TCC_SYNCBUSY_CC1_Pos)
+#define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */
+#define TCC_SYNCBUSY_CC2 (_U_(1) << TCC_SYNCBUSY_CC2_Pos)
+#define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */
+#define TCC_SYNCBUSY_CC3 (_U_(1) << TCC_SYNCBUSY_CC3_Pos)
+#define TCC_SYNCBUSY_CC4_Pos 12 /**< \brief (TCC_SYNCBUSY) Compare Channel 4 Busy */
+#define TCC_SYNCBUSY_CC4 (_U_(1) << TCC_SYNCBUSY_CC4_Pos)
+#define TCC_SYNCBUSY_CC5_Pos 13 /**< \brief (TCC_SYNCBUSY) Compare Channel 5 Busy */
+#define TCC_SYNCBUSY_CC5 (_U_(1) << TCC_SYNCBUSY_CC5_Pos)
+#define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
+#define TCC_SYNCBUSY_CC_Msk (_U_(0x3F) << TCC_SYNCBUSY_CC_Pos)
+#define TCC_SYNCBUSY_CC(value) (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
+#define TCC_SYNCBUSY_MASK _U_(0x00003FFF) /**< \brief (TCC_SYNCBUSY) MASK Register */
+
+/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
+ uint32_t BLANKPRESC:1; /*!< bit: 15 Fault A Blanking Prescaler */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_FCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */
+#define TCC_FCTRLA_RESETVALUE _U_(0x00000000) /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */
+
+#define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */
+#define TCC_FCTRLA_SRC_Msk (_U_(0x3) << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC(value) (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
+#define TCC_FCTRLA_SRC_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Fault input disabled */
+#define TCC_FCTRLA_SRC_ENABLE_Val _U_(0x1) /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
+#define TCC_FCTRLA_SRC_INVERT_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
+#define TCC_FCTRLA_SRC_ALTFAULT_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) Fault A Keeper */
+#define TCC_FCTRLA_KEEP (_U_(0x1) << TCC_FCTRLA_KEEP_Pos)
+#define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) Fault A Qualification */
+#define TCC_FCTRLA_QUAL (_U_(0x1) << TCC_FCTRLA_QUAL_Pos)
+#define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
+#define TCC_FCTRLA_BLANK_Msk (_U_(0x3) << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK(value) (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
+#define TCC_FCTRLA_BLANK_START_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Blanking applied from start of the ramp */
+#define TCC_FCTRLA_BLANK_RISE_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
+#define TCC_FCTRLA_BLANK_FALL_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
+#define TCC_FCTRLA_BLANK_BOTH_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLA_BLANK_START (TCC_FCTRLA_BLANK_START_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) Fault A Restart */
+#define TCC_FCTRLA_RESTART (_U_(0x1) << TCC_FCTRLA_RESTART_Pos)
+#define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
+#define TCC_FCTRLA_HALT_Msk (_U_(0x3) << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT(value) (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
+#define TCC_FCTRLA_HALT_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Halt action disabled */
+#define TCC_FCTRLA_HALT_HW_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Hardware halt action */
+#define TCC_FCTRLA_HALT_SW_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Software halt action */
+#define TCC_FCTRLA_HALT_NR_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Non-recoverable fault */
+#define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
+#define TCC_FCTRLA_CHSEL_Msk (_U_(0x3) << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL(value) (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
+#define TCC_FCTRLA_CHSEL_CC0_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
+#define TCC_FCTRLA_CHSEL_CC1_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
+#define TCC_FCTRLA_CHSEL_CC2_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
+#define TCC_FCTRLA_CHSEL_CC3_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */
+#define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */
+#define TCC_FCTRLA_CAPTURE_Msk (_U_(0x7) << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE(value) (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
+#define TCC_FCTRLA_CAPTURE_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLA) No capture */
+#define TCC_FCTRLA_CAPTURE_CAPT_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Capture on fault */
+#define TCC_FCTRLA_CAPTURE_CAPTMIN_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Minimum capture */
+#define TCC_FCTRLA_CAPTURE_CAPTMAX_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Maximum capture */
+#define TCC_FCTRLA_CAPTURE_LOCMIN_Val _U_(0x4) /**< \brief (TCC_FCTRLA) Minimum local detection */
+#define TCC_FCTRLA_CAPTURE_LOCMAX_Val _U_(0x5) /**< \brief (TCC_FCTRLA) Maximum local detection */
+#define TCC_FCTRLA_CAPTURE_DERIV0_Val _U_(0x6) /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
+#define TCC_FCTRLA_CAPTURE_CAPTMARK_Val _U_(0x7) /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */
+#define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_BLANKPRESC_Pos 15 /**< \brief (TCC_FCTRLA) Fault A Blanking Prescaler */
+#define TCC_FCTRLA_BLANKPRESC (_U_(0x1) << TCC_FCTRLA_BLANKPRESC_Pos)
+#define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
+#define TCC_FCTRLA_BLANKVAL_Msk (_U_(0xFF) << TCC_FCTRLA_BLANKVAL_Pos)
+#define TCC_FCTRLA_BLANKVAL(value) (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
+#define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */
+#define TCC_FCTRLA_FILTERVAL_Msk (_U_(0xF) << TCC_FCTRLA_FILTERVAL_Pos)
+#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
+#define TCC_FCTRLA_MASK _U_(0x0FFFFFFB) /**< \brief (TCC_FCTRLA) MASK Register */
+
+/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
+ uint32_t BLANKPRESC:1; /*!< bit: 15 Fault B Blanking Prescaler */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_FCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */
+#define TCC_FCTRLB_RESETVALUE _U_(0x00000000) /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */
+
+#define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */
+#define TCC_FCTRLB_SRC_Msk (_U_(0x3) << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC(value) (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
+#define TCC_FCTRLB_SRC_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Fault input disabled */
+#define TCC_FCTRLB_SRC_ENABLE_Val _U_(0x1) /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
+#define TCC_FCTRLB_SRC_INVERT_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
+#define TCC_FCTRLB_SRC_ALTFAULT_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) Fault B Keeper */
+#define TCC_FCTRLB_KEEP (_U_(0x1) << TCC_FCTRLB_KEEP_Pos)
+#define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) Fault B Qualification */
+#define TCC_FCTRLB_QUAL (_U_(0x1) << TCC_FCTRLB_QUAL_Pos)
+#define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
+#define TCC_FCTRLB_BLANK_Msk (_U_(0x3) << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK(value) (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
+#define TCC_FCTRLB_BLANK_START_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Blanking applied from start of the ramp */
+#define TCC_FCTRLB_BLANK_RISE_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
+#define TCC_FCTRLB_BLANK_FALL_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
+#define TCC_FCTRLB_BLANK_BOTH_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLB_BLANK_START (TCC_FCTRLB_BLANK_START_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) Fault B Restart */
+#define TCC_FCTRLB_RESTART (_U_(0x1) << TCC_FCTRLB_RESTART_Pos)
+#define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
+#define TCC_FCTRLB_HALT_Msk (_U_(0x3) << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT(value) (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
+#define TCC_FCTRLB_HALT_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Halt action disabled */
+#define TCC_FCTRLB_HALT_HW_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Hardware halt action */
+#define TCC_FCTRLB_HALT_SW_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Software halt action */
+#define TCC_FCTRLB_HALT_NR_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Non-recoverable fault */
+#define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
+#define TCC_FCTRLB_CHSEL_Msk (_U_(0x3) << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL(value) (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
+#define TCC_FCTRLB_CHSEL_CC0_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
+#define TCC_FCTRLB_CHSEL_CC1_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
+#define TCC_FCTRLB_CHSEL_CC2_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
+#define TCC_FCTRLB_CHSEL_CC3_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */
+#define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */
+#define TCC_FCTRLB_CAPTURE_Msk (_U_(0x7) << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE(value) (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
+#define TCC_FCTRLB_CAPTURE_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLB) No capture */
+#define TCC_FCTRLB_CAPTURE_CAPT_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Capture on fault */
+#define TCC_FCTRLB_CAPTURE_CAPTMIN_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Minimum capture */
+#define TCC_FCTRLB_CAPTURE_CAPTMAX_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Maximum capture */
+#define TCC_FCTRLB_CAPTURE_LOCMIN_Val _U_(0x4) /**< \brief (TCC_FCTRLB) Minimum local detection */
+#define TCC_FCTRLB_CAPTURE_LOCMAX_Val _U_(0x5) /**< \brief (TCC_FCTRLB) Maximum local detection */
+#define TCC_FCTRLB_CAPTURE_DERIV0_Val _U_(0x6) /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
+#define TCC_FCTRLB_CAPTURE_CAPTMARK_Val _U_(0x7) /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */
+#define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_BLANKPRESC_Pos 15 /**< \brief (TCC_FCTRLB) Fault B Blanking Prescaler */
+#define TCC_FCTRLB_BLANKPRESC (_U_(0x1) << TCC_FCTRLB_BLANKPRESC_Pos)
+#define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
+#define TCC_FCTRLB_BLANKVAL_Msk (_U_(0xFF) << TCC_FCTRLB_BLANKVAL_Pos)
+#define TCC_FCTRLB_BLANKVAL(value) (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
+#define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */
+#define TCC_FCTRLB_FILTERVAL_Msk (_U_(0xF) << TCC_FCTRLB_FILTERVAL_Pos)
+#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
+#define TCC_FCTRLB_MASK _U_(0x0FFFFFFB) /**< \brief (TCC_FCTRLB) MASK Register */
+
+/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
+ uint32_t :6; /*!< bit: 2.. 7 Reserved */
+ uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
+ uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
+ uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
+ uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
+ uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_WEXCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
+#define TCC_WEXCTRL_RESETVALUE _U_(0x00000000) /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
+
+#define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */
+#define TCC_WEXCTRL_OTMX_Msk (_U_(0x3) << TCC_WEXCTRL_OTMX_Pos)
+#define TCC_WEXCTRL_OTMX(value) (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
+#define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
+#define TCC_WEXCTRL_DTIEN0 (_U_(1) << TCC_WEXCTRL_DTIEN0_Pos)
+#define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
+#define TCC_WEXCTRL_DTIEN1 (_U_(1) << TCC_WEXCTRL_DTIEN1_Pos)
+#define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
+#define TCC_WEXCTRL_DTIEN2 (_U_(1) << TCC_WEXCTRL_DTIEN2_Pos)
+#define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
+#define TCC_WEXCTRL_DTIEN3 (_U_(1) << TCC_WEXCTRL_DTIEN3_Pos)
+#define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
+#define TCC_WEXCTRL_DTIEN_Msk (_U_(0xF) << TCC_WEXCTRL_DTIEN_Pos)
+#define TCC_WEXCTRL_DTIEN(value) (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
+#define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
+#define TCC_WEXCTRL_DTLS_Msk (_U_(0xFF) << TCC_WEXCTRL_DTLS_Pos)
+#define TCC_WEXCTRL_DTLS(value) (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
+#define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
+#define TCC_WEXCTRL_DTHS_Msk (_U_(0xFF) << TCC_WEXCTRL_DTHS_Pos)
+#define TCC_WEXCTRL_DTHS(value) (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
+#define TCC_WEXCTRL_MASK _U_(0xFFFF0F03) /**< \brief (TCC_WEXCTRL) MASK Register */
+
+/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
+ uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
+ uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
+ uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
+ uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
+ uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
+ uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
+ uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
+ uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
+ uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
+ uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
+ uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
+ uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
+ uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
+ uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
+ uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
+ uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
+ uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
+ uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
+ uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
+ uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
+ uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
+ uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
+ uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
+ uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
+ uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
+ uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
+ uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_DRVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Control */
+#define TCC_DRVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (TCC_DRVCTRL reset_value) Driver Control */
+
+#define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
+#define TCC_DRVCTRL_NRE0 (_U_(1) << TCC_DRVCTRL_NRE0_Pos)
+#define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
+#define TCC_DRVCTRL_NRE1 (_U_(1) << TCC_DRVCTRL_NRE1_Pos)
+#define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
+#define TCC_DRVCTRL_NRE2 (_U_(1) << TCC_DRVCTRL_NRE2_Pos)
+#define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
+#define TCC_DRVCTRL_NRE3 (_U_(1) << TCC_DRVCTRL_NRE3_Pos)
+#define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
+#define TCC_DRVCTRL_NRE4 (_U_(1) << TCC_DRVCTRL_NRE4_Pos)
+#define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
+#define TCC_DRVCTRL_NRE5 (_U_(1) << TCC_DRVCTRL_NRE5_Pos)
+#define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
+#define TCC_DRVCTRL_NRE6 (_U_(1) << TCC_DRVCTRL_NRE6_Pos)
+#define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
+#define TCC_DRVCTRL_NRE7 (_U_(1) << TCC_DRVCTRL_NRE7_Pos)
+#define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
+#define TCC_DRVCTRL_NRE_Msk (_U_(0xFF) << TCC_DRVCTRL_NRE_Pos)
+#define TCC_DRVCTRL_NRE(value) (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
+#define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
+#define TCC_DRVCTRL_NRV0 (_U_(1) << TCC_DRVCTRL_NRV0_Pos)
+#define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
+#define TCC_DRVCTRL_NRV1 (_U_(1) << TCC_DRVCTRL_NRV1_Pos)
+#define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
+#define TCC_DRVCTRL_NRV2 (_U_(1) << TCC_DRVCTRL_NRV2_Pos)
+#define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
+#define TCC_DRVCTRL_NRV3 (_U_(1) << TCC_DRVCTRL_NRV3_Pos)
+#define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
+#define TCC_DRVCTRL_NRV4 (_U_(1) << TCC_DRVCTRL_NRV4_Pos)
+#define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
+#define TCC_DRVCTRL_NRV5 (_U_(1) << TCC_DRVCTRL_NRV5_Pos)
+#define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
+#define TCC_DRVCTRL_NRV6 (_U_(1) << TCC_DRVCTRL_NRV6_Pos)
+#define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
+#define TCC_DRVCTRL_NRV7 (_U_(1) << TCC_DRVCTRL_NRV7_Pos)
+#define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
+#define TCC_DRVCTRL_NRV_Msk (_U_(0xFF) << TCC_DRVCTRL_NRV_Pos)
+#define TCC_DRVCTRL_NRV(value) (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
+#define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
+#define TCC_DRVCTRL_INVEN0 (_U_(1) << TCC_DRVCTRL_INVEN0_Pos)
+#define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
+#define TCC_DRVCTRL_INVEN1 (_U_(1) << TCC_DRVCTRL_INVEN1_Pos)
+#define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
+#define TCC_DRVCTRL_INVEN2 (_U_(1) << TCC_DRVCTRL_INVEN2_Pos)
+#define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
+#define TCC_DRVCTRL_INVEN3 (_U_(1) << TCC_DRVCTRL_INVEN3_Pos)
+#define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
+#define TCC_DRVCTRL_INVEN4 (_U_(1) << TCC_DRVCTRL_INVEN4_Pos)
+#define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
+#define TCC_DRVCTRL_INVEN5 (_U_(1) << TCC_DRVCTRL_INVEN5_Pos)
+#define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
+#define TCC_DRVCTRL_INVEN6 (_U_(1) << TCC_DRVCTRL_INVEN6_Pos)
+#define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
+#define TCC_DRVCTRL_INVEN7 (_U_(1) << TCC_DRVCTRL_INVEN7_Pos)
+#define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
+#define TCC_DRVCTRL_INVEN_Msk (_U_(0xFF) << TCC_DRVCTRL_INVEN_Pos)
+#define TCC_DRVCTRL_INVEN(value) (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
+#define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL0_Msk (_U_(0xF) << TCC_DRVCTRL_FILTERVAL0_Pos)
+#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
+#define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL1_Msk (_U_(0xF) << TCC_DRVCTRL_FILTERVAL1_Pos)
+#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
+#define TCC_DRVCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (TCC_DRVCTRL) MASK Register */
+
+/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TCC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */
+#define TCC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
+
+#define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */
+#define TCC_DBGCTRL_DBGRUN (_U_(0x1) << TCC_DBGCTRL_DBGRUN_Pos)
+#define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
+#define TCC_DBGCTRL_FDDBD (_U_(0x1) << TCC_DBGCTRL_FDDBD_Pos)
+#define TCC_DBGCTRL_MASK _U_(0x05) /**< \brief (TCC_DBGCTRL) MASK Register */
+
+/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
+ uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
+ uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
+ uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
+ uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
+ uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
+ uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
+ uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
+ uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
+ uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
+ uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
+ uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
+ uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
+ uint32_t MCEI4:1; /*!< bit: 20 Match or Capture Channel 4 Event Input Enable */
+ uint32_t MCEI5:1; /*!< bit: 21 Match or Capture Channel 5 Event Input Enable */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
+ uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
+ uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
+ uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
+ uint32_t MCEO4:1; /*!< bit: 28 Match or Capture Channel 4 Event Output Enable */
+ uint32_t MCEO5:1; /*!< bit: 29 Match or Capture Channel 5 Event Output Enable */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :12; /*!< bit: 0..11 Reserved */
+ uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
+ uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
+ uint32_t MCEI:6; /*!< bit: 16..21 Match or Capture Channel x Event Input Enable */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t MCEO:6; /*!< bit: 24..29 Match or Capture Channel x Event Output Enable */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */
+#define TCC_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (TCC_EVCTRL reset_value) Event Control */
+
+#define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
+#define TCC_EVCTRL_EVACT0_Msk (_U_(0x7) << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0(value) (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
+#define TCC_EVCTRL_EVACT0_OFF_Val _U_(0x0) /**< \brief (TCC_EVCTRL) Event action disabled */
+#define TCC_EVCTRL_EVACT0_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
+#define TCC_EVCTRL_EVACT0_COUNTEV_Val _U_(0x2) /**< \brief (TCC_EVCTRL) Count on event */
+#define TCC_EVCTRL_EVACT0_START_Val _U_(0x3) /**< \brief (TCC_EVCTRL) Start counter on event */
+#define TCC_EVCTRL_EVACT0_INC_Val _U_(0x4) /**< \brief (TCC_EVCTRL) Increment counter on event */
+#define TCC_EVCTRL_EVACT0_COUNT_Val _U_(0x5) /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
+#define TCC_EVCTRL_EVACT0_STAMP_Val _U_(0x6) /**< \brief (TCC_EVCTRL) Stamp capture */
+#define TCC_EVCTRL_EVACT0_FAULT_Val _U_(0x7) /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_STAMP (TCC_EVCTRL_EVACT0_STAMP_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
+#define TCC_EVCTRL_EVACT1_Msk (_U_(0x7) << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1(value) (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
+#define TCC_EVCTRL_EVACT1_OFF_Val _U_(0x0) /**< \brief (TCC_EVCTRL) Event action disabled */
+#define TCC_EVCTRL_EVACT1_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
+#define TCC_EVCTRL_EVACT1_DIR_Val _U_(0x2) /**< \brief (TCC_EVCTRL) Direction control */
+#define TCC_EVCTRL_EVACT1_STOP_Val _U_(0x3) /**< \brief (TCC_EVCTRL) Stop counter on event */
+#define TCC_EVCTRL_EVACT1_DEC_Val _U_(0x4) /**< \brief (TCC_EVCTRL) Decrement counter on event */
+#define TCC_EVCTRL_EVACT1_PPW_Val _U_(0x5) /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */
+#define TCC_EVCTRL_EVACT1_PWP_Val _U_(0x6) /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */
+#define TCC_EVCTRL_EVACT1_FAULT_Val _U_(0x7) /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
+#define TCC_EVCTRL_CNTSEL_Msk (_U_(0x3) << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL(value) (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
+#define TCC_EVCTRL_CNTSEL_START_Val _U_(0x0) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
+#define TCC_EVCTRL_CNTSEL_END_Val _U_(0x1) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
+#define TCC_EVCTRL_CNTSEL_BETWEEN_Val _U_(0x2) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
+#define TCC_EVCTRL_CNTSEL_BOUNDARY_Val _U_(0x3) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
+#define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
+#define TCC_EVCTRL_OVFEO (_U_(0x1) << TCC_EVCTRL_OVFEO_Pos)
+#define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
+#define TCC_EVCTRL_TRGEO (_U_(0x1) << TCC_EVCTRL_TRGEO_Pos)
+#define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
+#define TCC_EVCTRL_CNTEO (_U_(0x1) << TCC_EVCTRL_CNTEO_Pos)
+#define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
+#define TCC_EVCTRL_TCINV0 (_U_(1) << TCC_EVCTRL_TCINV0_Pos)
+#define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
+#define TCC_EVCTRL_TCINV1 (_U_(1) << TCC_EVCTRL_TCINV1_Pos)
+#define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
+#define TCC_EVCTRL_TCINV_Msk (_U_(0x3) << TCC_EVCTRL_TCINV_Pos)
+#define TCC_EVCTRL_TCINV(value) (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
+#define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
+#define TCC_EVCTRL_TCEI0 (_U_(1) << TCC_EVCTRL_TCEI0_Pos)
+#define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
+#define TCC_EVCTRL_TCEI1 (_U_(1) << TCC_EVCTRL_TCEI1_Pos)
+#define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
+#define TCC_EVCTRL_TCEI_Msk (_U_(0x3) << TCC_EVCTRL_TCEI_Pos)
+#define TCC_EVCTRL_TCEI(value) (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
+#define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
+#define TCC_EVCTRL_MCEI0 (_U_(1) << TCC_EVCTRL_MCEI0_Pos)
+#define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
+#define TCC_EVCTRL_MCEI1 (_U_(1) << TCC_EVCTRL_MCEI1_Pos)
+#define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
+#define TCC_EVCTRL_MCEI2 (_U_(1) << TCC_EVCTRL_MCEI2_Pos)
+#define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
+#define TCC_EVCTRL_MCEI3 (_U_(1) << TCC_EVCTRL_MCEI3_Pos)
+#define TCC_EVCTRL_MCEI4_Pos 20 /**< \brief (TCC_EVCTRL) Match or Capture Channel 4 Event Input Enable */
+#define TCC_EVCTRL_MCEI4 (_U_(1) << TCC_EVCTRL_MCEI4_Pos)
+#define TCC_EVCTRL_MCEI5_Pos 21 /**< \brief (TCC_EVCTRL) Match or Capture Channel 5 Event Input Enable */
+#define TCC_EVCTRL_MCEI5 (_U_(1) << TCC_EVCTRL_MCEI5_Pos)
+#define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
+#define TCC_EVCTRL_MCEI_Msk (_U_(0x3F) << TCC_EVCTRL_MCEI_Pos)
+#define TCC_EVCTRL_MCEI(value) (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
+#define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TCC_EVCTRL_MCEO0 (_U_(1) << TCC_EVCTRL_MCEO0_Pos)
+#define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TCC_EVCTRL_MCEO1 (_U_(1) << TCC_EVCTRL_MCEO1_Pos)
+#define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
+#define TCC_EVCTRL_MCEO2 (_U_(1) << TCC_EVCTRL_MCEO2_Pos)
+#define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
+#define TCC_EVCTRL_MCEO3 (_U_(1) << TCC_EVCTRL_MCEO3_Pos)
+#define TCC_EVCTRL_MCEO4_Pos 28 /**< \brief (TCC_EVCTRL) Match or Capture Channel 4 Event Output Enable */
+#define TCC_EVCTRL_MCEO4 (_U_(1) << TCC_EVCTRL_MCEO4_Pos)
+#define TCC_EVCTRL_MCEO5_Pos 29 /**< \brief (TCC_EVCTRL) Match or Capture Channel 5 Event Output Enable */
+#define TCC_EVCTRL_MCEO5 (_U_(1) << TCC_EVCTRL_MCEO5_Pos)
+#define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TCC_EVCTRL_MCEO_Msk (_U_(0x3F) << TCC_EVCTRL_MCEO_Pos)
+#define TCC_EVCTRL_MCEO(value) (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
+#define TCC_EVCTRL_MASK _U_(0x3F3FF7FF) /**< \brief (TCC_EVCTRL) MASK Register */
+
+/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :6; /*!< bit: 4.. 9 Reserved */
+ uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t MC4:1; /*!< bit: 20 Match or Capture Channel 4 Interrupt Enable */
+ uint32_t MC5:1; /*!< bit: 21 Match or Capture Channel 5 Interrupt Enable */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:6; /*!< bit: 16..21 Match or Capture Channel x Interrupt Enable */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
+#define TCC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
+#define TCC_INTENCLR_OVF (_U_(0x1) << TCC_INTENCLR_OVF_Pos)
+#define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
+#define TCC_INTENCLR_TRG (_U_(0x1) << TCC_INTENCLR_TRG_Pos)
+#define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
+#define TCC_INTENCLR_CNT (_U_(0x1) << TCC_INTENCLR_CNT_Pos)
+#define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
+#define TCC_INTENCLR_ERR (_U_(0x1) << TCC_INTENCLR_ERR_Pos)
+#define TCC_INTENCLR_UFS_Pos 10 /**< \brief (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable */
+#define TCC_INTENCLR_UFS (_U_(0x1) << TCC_INTENCLR_UFS_Pos)
+#define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENCLR_DFS (_U_(0x1) << TCC_INTENCLR_DFS_Pos)
+#define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENCLR_FAULTA (_U_(0x1) << TCC_INTENCLR_FAULTA_Pos)
+#define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENCLR_FAULTB (_U_(0x1) << TCC_INTENCLR_FAULTB_Pos)
+#define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENCLR_FAULT0 (_U_(0x1) << TCC_INTENCLR_FAULT0_Pos)
+#define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENCLR_FAULT1 (_U_(0x1) << TCC_INTENCLR_FAULT1_Pos)
+#define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENCLR_MC0 (_U_(1) << TCC_INTENCLR_MC0_Pos)
+#define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENCLR_MC1 (_U_(1) << TCC_INTENCLR_MC1_Pos)
+#define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENCLR_MC2 (_U_(1) << TCC_INTENCLR_MC2_Pos)
+#define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENCLR_MC3 (_U_(1) << TCC_INTENCLR_MC3_Pos)
+#define TCC_INTENCLR_MC4_Pos 20 /**< \brief (TCC_INTENCLR) Match or Capture Channel 4 Interrupt Enable */
+#define TCC_INTENCLR_MC4 (_U_(1) << TCC_INTENCLR_MC4_Pos)
+#define TCC_INTENCLR_MC5_Pos 21 /**< \brief (TCC_INTENCLR) Match or Capture Channel 5 Interrupt Enable */
+#define TCC_INTENCLR_MC5 (_U_(1) << TCC_INTENCLR_MC5_Pos)
+#define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENCLR_MC_Msk (_U_(0x3F) << TCC_INTENCLR_MC_Pos)
+#define TCC_INTENCLR_MC(value) (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
+#define TCC_INTENCLR_MASK _U_(0x003FFC0F) /**< \brief (TCC_INTENCLR) MASK Register */
+
+/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :6; /*!< bit: 4.. 9 Reserved */
+ uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t MC4:1; /*!< bit: 20 Match or Capture Channel 4 Interrupt Enable */
+ uint32_t MC5:1; /*!< bit: 21 Match or Capture Channel 5 Interrupt Enable */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:6; /*!< bit: 16..21 Match or Capture Channel x Interrupt Enable */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
+#define TCC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
+#define TCC_INTENSET_OVF (_U_(0x1) << TCC_INTENSET_OVF_Pos)
+#define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
+#define TCC_INTENSET_TRG (_U_(0x1) << TCC_INTENSET_TRG_Pos)
+#define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
+#define TCC_INTENSET_CNT (_U_(0x1) << TCC_INTENSET_CNT_Pos)
+#define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */
+#define TCC_INTENSET_ERR (_U_(0x1) << TCC_INTENSET_ERR_Pos)
+#define TCC_INTENSET_UFS_Pos 10 /**< \brief (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable */
+#define TCC_INTENSET_UFS (_U_(0x1) << TCC_INTENSET_UFS_Pos)
+#define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENSET_DFS (_U_(0x1) << TCC_INTENSET_DFS_Pos)
+#define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENSET_FAULTA (_U_(0x1) << TCC_INTENSET_FAULTA_Pos)
+#define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENSET_FAULTB (_U_(0x1) << TCC_INTENSET_FAULTB_Pos)
+#define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENSET_FAULT0 (_U_(0x1) << TCC_INTENSET_FAULT0_Pos)
+#define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENSET_FAULT1 (_U_(0x1) << TCC_INTENSET_FAULT1_Pos)
+#define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENSET_MC0 (_U_(1) << TCC_INTENSET_MC0_Pos)
+#define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENSET_MC1 (_U_(1) << TCC_INTENSET_MC1_Pos)
+#define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENSET_MC2 (_U_(1) << TCC_INTENSET_MC2_Pos)
+#define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENSET_MC3 (_U_(1) << TCC_INTENSET_MC3_Pos)
+#define TCC_INTENSET_MC4_Pos 20 /**< \brief (TCC_INTENSET) Match or Capture Channel 4 Interrupt Enable */
+#define TCC_INTENSET_MC4 (_U_(1) << TCC_INTENSET_MC4_Pos)
+#define TCC_INTENSET_MC5_Pos 21 /**< \brief (TCC_INTENSET) Match or Capture Channel 5 Interrupt Enable */
+#define TCC_INTENSET_MC5 (_U_(1) << TCC_INTENSET_MC5_Pos)
+#define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENSET_MC_Msk (_U_(0x3F) << TCC_INTENSET_MC_Pos)
+#define TCC_INTENSET_MC(value) (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
+#define TCC_INTENSET_MASK _U_(0x003FFC0F) /**< \brief (TCC_INTENSET) MASK Register */
+
+/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t OVF:1; /*!< bit: 0 Overflow */
+ __I uint32_t TRG:1; /*!< bit: 1 Retrigger */
+ __I uint32_t CNT:1; /*!< bit: 2 Counter */
+ __I uint32_t ERR:1; /*!< bit: 3 Error */
+ __I uint32_t :6; /*!< bit: 4.. 9 Reserved */
+ __I uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */
+ __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
+ __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
+ __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
+ __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
+ __I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
+ __I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
+ __I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
+ __I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
+ __I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
+ __I uint32_t MC4:1; /*!< bit: 20 Match or Capture 4 */
+ __I uint32_t MC5:1; /*!< bit: 21 Match or Capture 5 */
+ __I uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint32_t :16; /*!< bit: 0..15 Reserved */
+ __I uint32_t MC:6; /*!< bit: 16..21 Match or Capture x */
+ __I uint32_t :10; /*!< bit: 22..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TCC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */
+#define TCC_INTFLAG_OVF (_U_(0x1) << TCC_INTFLAG_OVF_Pos)
+#define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */
+#define TCC_INTFLAG_TRG (_U_(0x1) << TCC_INTFLAG_TRG_Pos)
+#define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */
+#define TCC_INTFLAG_CNT (_U_(0x1) << TCC_INTFLAG_CNT_Pos)
+#define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */
+#define TCC_INTFLAG_ERR (_U_(0x1) << TCC_INTFLAG_ERR_Pos)
+#define TCC_INTFLAG_UFS_Pos 10 /**< \brief (TCC_INTFLAG) Non-Recoverable Update Fault */
+#define TCC_INTFLAG_UFS (_U_(0x1) << TCC_INTFLAG_UFS_Pos)
+#define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
+#define TCC_INTFLAG_DFS (_U_(0x1) << TCC_INTFLAG_DFS_Pos)
+#define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable Fault A */
+#define TCC_INTFLAG_FAULTA (_U_(0x1) << TCC_INTFLAG_FAULTA_Pos)
+#define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable Fault B */
+#define TCC_INTFLAG_FAULTB (_U_(0x1) << TCC_INTFLAG_FAULTB_Pos)
+#define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
+#define TCC_INTFLAG_FAULT0 (_U_(0x1) << TCC_INTFLAG_FAULT0_Pos)
+#define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
+#define TCC_INTFLAG_FAULT1 (_U_(0x1) << TCC_INTFLAG_FAULT1_Pos)
+#define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */
+#define TCC_INTFLAG_MC0 (_U_(1) << TCC_INTFLAG_MC0_Pos)
+#define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */
+#define TCC_INTFLAG_MC1 (_U_(1) << TCC_INTFLAG_MC1_Pos)
+#define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */
+#define TCC_INTFLAG_MC2 (_U_(1) << TCC_INTFLAG_MC2_Pos)
+#define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */
+#define TCC_INTFLAG_MC3 (_U_(1) << TCC_INTFLAG_MC3_Pos)
+#define TCC_INTFLAG_MC4_Pos 20 /**< \brief (TCC_INTFLAG) Match or Capture 4 */
+#define TCC_INTFLAG_MC4 (_U_(1) << TCC_INTFLAG_MC4_Pos)
+#define TCC_INTFLAG_MC5_Pos 21 /**< \brief (TCC_INTFLAG) Match or Capture 5 */
+#define TCC_INTFLAG_MC5 (_U_(1) << TCC_INTFLAG_MC5_Pos)
+#define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */
+#define TCC_INTFLAG_MC_Msk (_U_(0x3F) << TCC_INTFLAG_MC_Pos)
+#define TCC_INTFLAG_MC(value) (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
+#define TCC_INTFLAG_MASK _U_(0x003FFC0F) /**< \brief (TCC_INTFLAG) MASK Register */
+
+/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t STOP:1; /*!< bit: 0 Stop */
+ uint32_t IDX:1; /*!< bit: 1 Ramp */
+ uint32_t UFS:1; /*!< bit: 2 Non-recoverable Update Fault State */
+ uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
+ uint32_t SLAVE:1; /*!< bit: 4 Slave */
+ uint32_t PATTBUFV:1; /*!< bit: 5 Pattern Buffer Valid */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t PERBUFV:1; /*!< bit: 7 Period Buffer Valid */
+ uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
+ uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
+ uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
+ uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
+ uint32_t CCBUFV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
+ uint32_t CCBUFV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
+ uint32_t CCBUFV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
+ uint32_t CCBUFV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
+ uint32_t CCBUFV4:1; /*!< bit: 20 Compare Channel 4 Buffer Valid */
+ uint32_t CCBUFV5:1; /*!< bit: 21 Compare Channel 5 Buffer Valid */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
+ uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
+ uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
+ uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
+ uint32_t CMP4:1; /*!< bit: 28 Compare Channel 4 Value */
+ uint32_t CMP5:1; /*!< bit: 29 Compare Channel 5 Value */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t CCBUFV:6; /*!< bit: 16..21 Compare Channel x Buffer Valid */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t CMP:6; /*!< bit: 24..29 Compare Channel x Value */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */
+#define TCC_STATUS_RESETVALUE _U_(0x00000001) /**< \brief (TCC_STATUS reset_value) Status */
+
+#define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */
+#define TCC_STATUS_STOP (_U_(0x1) << TCC_STATUS_STOP_Pos)
+#define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */
+#define TCC_STATUS_IDX (_U_(0x1) << TCC_STATUS_IDX_Pos)
+#define TCC_STATUS_UFS_Pos 2 /**< \brief (TCC_STATUS) Non-recoverable Update Fault State */
+#define TCC_STATUS_UFS (_U_(0x1) << TCC_STATUS_UFS_Pos)
+#define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
+#define TCC_STATUS_DFS (_U_(0x1) << TCC_STATUS_DFS_Pos)
+#define TCC_STATUS_SLAVE_Pos 4 /**< \brief (TCC_STATUS) Slave */
+#define TCC_STATUS_SLAVE (_U_(0x1) << TCC_STATUS_SLAVE_Pos)
+#define TCC_STATUS_PATTBUFV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */
+#define TCC_STATUS_PATTBUFV (_U_(0x1) << TCC_STATUS_PATTBUFV_Pos)
+#define TCC_STATUS_PERBUFV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */
+#define TCC_STATUS_PERBUFV (_U_(0x1) << TCC_STATUS_PERBUFV_Pos)
+#define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable Fault A Input */
+#define TCC_STATUS_FAULTAIN (_U_(0x1) << TCC_STATUS_FAULTAIN_Pos)
+#define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable Fault B Input */
+#define TCC_STATUS_FAULTBIN (_U_(0x1) << TCC_STATUS_FAULTBIN_Pos)
+#define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
+#define TCC_STATUS_FAULT0IN (_U_(0x1) << TCC_STATUS_FAULT0IN_Pos)
+#define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
+#define TCC_STATUS_FAULT1IN (_U_(0x1) << TCC_STATUS_FAULT1IN_Pos)
+#define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable Fault A State */
+#define TCC_STATUS_FAULTA (_U_(0x1) << TCC_STATUS_FAULTA_Pos)
+#define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable Fault B State */
+#define TCC_STATUS_FAULTB (_U_(0x1) << TCC_STATUS_FAULTB_Pos)
+#define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
+#define TCC_STATUS_FAULT0 (_U_(0x1) << TCC_STATUS_FAULT0_Pos)
+#define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
+#define TCC_STATUS_FAULT1 (_U_(0x1) << TCC_STATUS_FAULT1_Pos)
+#define TCC_STATUS_CCBUFV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
+#define TCC_STATUS_CCBUFV0 (_U_(1) << TCC_STATUS_CCBUFV0_Pos)
+#define TCC_STATUS_CCBUFV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
+#define TCC_STATUS_CCBUFV1 (_U_(1) << TCC_STATUS_CCBUFV1_Pos)
+#define TCC_STATUS_CCBUFV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
+#define TCC_STATUS_CCBUFV2 (_U_(1) << TCC_STATUS_CCBUFV2_Pos)
+#define TCC_STATUS_CCBUFV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
+#define TCC_STATUS_CCBUFV3 (_U_(1) << TCC_STATUS_CCBUFV3_Pos)
+#define TCC_STATUS_CCBUFV4_Pos 20 /**< \brief (TCC_STATUS) Compare Channel 4 Buffer Valid */
+#define TCC_STATUS_CCBUFV4 (_U_(1) << TCC_STATUS_CCBUFV4_Pos)
+#define TCC_STATUS_CCBUFV5_Pos 21 /**< \brief (TCC_STATUS) Compare Channel 5 Buffer Valid */
+#define TCC_STATUS_CCBUFV5 (_U_(1) << TCC_STATUS_CCBUFV5_Pos)
+#define TCC_STATUS_CCBUFV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
+#define TCC_STATUS_CCBUFV_Msk (_U_(0x3F) << TCC_STATUS_CCBUFV_Pos)
+#define TCC_STATUS_CCBUFV(value) (TCC_STATUS_CCBUFV_Msk & ((value) << TCC_STATUS_CCBUFV_Pos))
+#define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */
+#define TCC_STATUS_CMP0 (_U_(1) << TCC_STATUS_CMP0_Pos)
+#define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */
+#define TCC_STATUS_CMP1 (_U_(1) << TCC_STATUS_CMP1_Pos)
+#define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */
+#define TCC_STATUS_CMP2 (_U_(1) << TCC_STATUS_CMP2_Pos)
+#define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */
+#define TCC_STATUS_CMP3 (_U_(1) << TCC_STATUS_CMP3_Pos)
+#define TCC_STATUS_CMP4_Pos 28 /**< \brief (TCC_STATUS) Compare Channel 4 Value */
+#define TCC_STATUS_CMP4 (_U_(1) << TCC_STATUS_CMP4_Pos)
+#define TCC_STATUS_CMP5_Pos 29 /**< \brief (TCC_STATUS) Compare Channel 5 Value */
+#define TCC_STATUS_CMP5 (_U_(1) << TCC_STATUS_CMP5_Pos)
+#define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */
+#define TCC_STATUS_CMP_Msk (_U_(0x3F) << TCC_STATUS_CMP_Pos)
+#define TCC_STATUS_CMP(value) (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
+#define TCC_STATUS_MASK _U_(0x3F3FFFBF) /**< \brief (TCC_STATUS) MASK Register */
+
+/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t :4; /*!< bit: 0.. 3 Reserved */
+ uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t :5; /*!< bit: 0.. 4 Reserved */
+ uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t :6; /*!< bit: 0.. 5 Reserved */
+ uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */
+#define TCC_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (TCC_COUNT reset_value) Count */
+
+// DITH4 mode
+#define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */
+#define TCC_COUNT_DITH4_COUNT_Msk (_U_(0xFFFFF) << TCC_COUNT_DITH4_COUNT_Pos)
+#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
+#define TCC_COUNT_DITH4_MASK _U_(0x00FFFFF0) /**< \brief (TCC_COUNT_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */
+#define TCC_COUNT_DITH5_COUNT_Msk (_U_(0x7FFFF) << TCC_COUNT_DITH5_COUNT_Pos)
+#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
+#define TCC_COUNT_DITH5_MASK _U_(0x00FFFFE0) /**< \brief (TCC_COUNT_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */
+#define TCC_COUNT_DITH6_COUNT_Msk (_U_(0x3FFFF) << TCC_COUNT_DITH6_COUNT_Pos)
+#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
+#define TCC_COUNT_DITH6_MASK _U_(0x00FFFFC0) /**< \brief (TCC_COUNT_DITH6) MASK Register */
+
+#define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */
+#define TCC_COUNT_COUNT_Msk (_U_(0xFFFFFF) << TCC_COUNT_COUNT_Pos)
+#define TCC_COUNT_COUNT(value) (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
+#define TCC_COUNT_MASK _U_(0x00FFFFFF) /**< \brief (TCC_COUNT) MASK Register */
+
+/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
+ uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
+ uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
+ uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
+ uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
+ uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
+ uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
+ uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
+ uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
+ uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
+ uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
+ uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
+ uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
+ uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
+ uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
+ uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
+ uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} TCC_PATT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */
+#define TCC_PATT_RESETVALUE _U_(0x0000) /**< \brief (TCC_PATT reset_value) Pattern */
+
+#define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
+#define TCC_PATT_PGE0 (_U_(1) << TCC_PATT_PGE0_Pos)
+#define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
+#define TCC_PATT_PGE1 (_U_(1) << TCC_PATT_PGE1_Pos)
+#define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
+#define TCC_PATT_PGE2 (_U_(1) << TCC_PATT_PGE2_Pos)
+#define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
+#define TCC_PATT_PGE3 (_U_(1) << TCC_PATT_PGE3_Pos)
+#define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
+#define TCC_PATT_PGE4 (_U_(1) << TCC_PATT_PGE4_Pos)
+#define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
+#define TCC_PATT_PGE5 (_U_(1) << TCC_PATT_PGE5_Pos)
+#define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
+#define TCC_PATT_PGE6 (_U_(1) << TCC_PATT_PGE6_Pos)
+#define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
+#define TCC_PATT_PGE7 (_U_(1) << TCC_PATT_PGE7_Pos)
+#define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
+#define TCC_PATT_PGE_Msk (_U_(0xFF) << TCC_PATT_PGE_Pos)
+#define TCC_PATT_PGE(value) (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
+#define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
+#define TCC_PATT_PGV0 (_U_(1) << TCC_PATT_PGV0_Pos)
+#define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
+#define TCC_PATT_PGV1 (_U_(1) << TCC_PATT_PGV1_Pos)
+#define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
+#define TCC_PATT_PGV2 (_U_(1) << TCC_PATT_PGV2_Pos)
+#define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
+#define TCC_PATT_PGV3 (_U_(1) << TCC_PATT_PGV3_Pos)
+#define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
+#define TCC_PATT_PGV4 (_U_(1) << TCC_PATT_PGV4_Pos)
+#define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
+#define TCC_PATT_PGV5 (_U_(1) << TCC_PATT_PGV5_Pos)
+#define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
+#define TCC_PATT_PGV6 (_U_(1) << TCC_PATT_PGV6_Pos)
+#define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
+#define TCC_PATT_PGV7 (_U_(1) << TCC_PATT_PGV7_Pos)
+#define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */
+#define TCC_PATT_PGV_Msk (_U_(0xFF) << TCC_PATT_PGV_Pos)
+#define TCC_PATT_PGV(value) (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
+#define TCC_PATT_MASK _U_(0xFFFF) /**< \brief (TCC_PATT) MASK Register */
+
+/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
+ uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
+ uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
+ uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
+ uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
+ uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
+ uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
+ uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
+ uint32_t POL4:1; /*!< bit: 20 Channel 4 Polarity */
+ uint32_t POL5:1; /*!< bit: 21 Channel 5 Polarity */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
+ uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
+ uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
+ uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL:6; /*!< bit: 16..21 Channel x Polarity */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_WAVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */
+#define TCC_WAVE_RESETVALUE _U_(0x00000000) /**< \brief (TCC_WAVE reset_value) Waveform Control */
+
+#define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */
+#define TCC_WAVE_WAVEGEN_Msk (_U_(0x7) << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN(value) (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
+#define TCC_WAVE_WAVEGEN_NFRQ_Val _U_(0x0) /**< \brief (TCC_WAVE) Normal frequency */
+#define TCC_WAVE_WAVEGEN_MFRQ_Val _U_(0x1) /**< \brief (TCC_WAVE) Match frequency */
+#define TCC_WAVE_WAVEGEN_NPWM_Val _U_(0x2) /**< \brief (TCC_WAVE) Normal PWM */
+#define TCC_WAVE_WAVEGEN_DSCRITICAL_Val _U_(0x4) /**< \brief (TCC_WAVE) Dual-slope critical */
+#define TCC_WAVE_WAVEGEN_DSBOTTOM_Val _U_(0x5) /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define TCC_WAVE_WAVEGEN_DSBOTH_Val _U_(0x6) /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define TCC_WAVE_WAVEGEN_DSTOP_Val _U_(0x7) /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */
+#define TCC_WAVE_RAMP_Msk (_U_(0x3) << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP(value) (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
+#define TCC_WAVE_RAMP_RAMP1_Val _U_(0x0) /**< \brief (TCC_WAVE) RAMP1 operation */
+#define TCC_WAVE_RAMP_RAMP2A_Val _U_(0x1) /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
+#define TCC_WAVE_RAMP_RAMP2_Val _U_(0x2) /**< \brief (TCC_WAVE) RAMP2 operation */
+#define TCC_WAVE_RAMP_RAMP2C_Val _U_(0x3) /**< \brief (TCC_WAVE) Critical RAMP2 operation */
+#define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2C (TCC_WAVE_RAMP_RAMP2C_Val << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */
+#define TCC_WAVE_CIPEREN (_U_(0x1) << TCC_WAVE_CIPEREN_Pos)
+#define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
+#define TCC_WAVE_CICCEN0 (_U_(1) << TCC_WAVE_CICCEN0_Pos)
+#define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
+#define TCC_WAVE_CICCEN1 (_U_(1) << TCC_WAVE_CICCEN1_Pos)
+#define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
+#define TCC_WAVE_CICCEN2 (_U_(1) << TCC_WAVE_CICCEN2_Pos)
+#define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
+#define TCC_WAVE_CICCEN3 (_U_(1) << TCC_WAVE_CICCEN3_Pos)
+#define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */
+#define TCC_WAVE_CICCEN_Msk (_U_(0xF) << TCC_WAVE_CICCEN_Pos)
+#define TCC_WAVE_CICCEN(value) (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
+#define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */
+#define TCC_WAVE_POL0 (_U_(1) << TCC_WAVE_POL0_Pos)
+#define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */
+#define TCC_WAVE_POL1 (_U_(1) << TCC_WAVE_POL1_Pos)
+#define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */
+#define TCC_WAVE_POL2 (_U_(1) << TCC_WAVE_POL2_Pos)
+#define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */
+#define TCC_WAVE_POL3 (_U_(1) << TCC_WAVE_POL3_Pos)
+#define TCC_WAVE_POL4_Pos 20 /**< \brief (TCC_WAVE) Channel 4 Polarity */
+#define TCC_WAVE_POL4 (_U_(1) << TCC_WAVE_POL4_Pos)
+#define TCC_WAVE_POL5_Pos 21 /**< \brief (TCC_WAVE) Channel 5 Polarity */
+#define TCC_WAVE_POL5 (_U_(1) << TCC_WAVE_POL5_Pos)
+#define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */
+#define TCC_WAVE_POL_Msk (_U_(0x3F) << TCC_WAVE_POL_Pos)
+#define TCC_WAVE_POL(value) (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
+#define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
+#define TCC_WAVE_SWAP0 (_U_(1) << TCC_WAVE_SWAP0_Pos)
+#define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
+#define TCC_WAVE_SWAP1 (_U_(1) << TCC_WAVE_SWAP1_Pos)
+#define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
+#define TCC_WAVE_SWAP2 (_U_(1) << TCC_WAVE_SWAP2_Pos)
+#define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
+#define TCC_WAVE_SWAP3 (_U_(1) << TCC_WAVE_SWAP3_Pos)
+#define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
+#define TCC_WAVE_SWAP_Msk (_U_(0xF) << TCC_WAVE_SWAP_Pos)
+#define TCC_WAVE_SWAP(value) (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
+#define TCC_WAVE_MASK _U_(0x0F3F0FB7) /**< \brief (TCC_WAVE) MASK Register */
+
+/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t DITHER:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t PER:20; /*!< bit: 4..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHER:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t PER:19; /*!< bit: 5..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHER:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t PER:18; /*!< bit: 6..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PER:24; /*!< bit: 0..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */
+#define TCC_PER_RESETVALUE _U_(0xFFFFFFFF) /**< \brief (TCC_PER reset_value) Period */
+
+// DITH4 mode
+#define TCC_PER_DITH4_DITHER_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
+#define TCC_PER_DITH4_DITHER_Msk (_U_(0xF) << TCC_PER_DITH4_DITHER_Pos)
+#define TCC_PER_DITH4_DITHER(value) (TCC_PER_DITH4_DITHER_Msk & ((value) << TCC_PER_DITH4_DITHER_Pos))
+#define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */
+#define TCC_PER_DITH4_PER_Msk (_U_(0xFFFFF) << TCC_PER_DITH4_PER_Pos)
+#define TCC_PER_DITH4_PER(value) (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
+#define TCC_PER_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PER_DITH5_DITHER_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
+#define TCC_PER_DITH5_DITHER_Msk (_U_(0x1F) << TCC_PER_DITH5_DITHER_Pos)
+#define TCC_PER_DITH5_DITHER(value) (TCC_PER_DITH5_DITHER_Msk & ((value) << TCC_PER_DITH5_DITHER_Pos))
+#define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */
+#define TCC_PER_DITH5_PER_Msk (_U_(0x7FFFF) << TCC_PER_DITH5_PER_Pos)
+#define TCC_PER_DITH5_PER(value) (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
+#define TCC_PER_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PER_DITH6_DITHER_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
+#define TCC_PER_DITH6_DITHER_Msk (_U_(0x3F) << TCC_PER_DITH6_DITHER_Pos)
+#define TCC_PER_DITH6_DITHER(value) (TCC_PER_DITH6_DITHER_Msk & ((value) << TCC_PER_DITH6_DITHER_Pos))
+#define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */
+#define TCC_PER_DITH6_PER_Msk (_U_(0x3FFFF) << TCC_PER_DITH6_PER_Pos)
+#define TCC_PER_DITH6_PER(value) (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
+#define TCC_PER_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH6) MASK Register */
+
+#define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */
+#define TCC_PER_PER_Msk (_U_(0xFFFFFF) << TCC_PER_PER_Pos)
+#define TCC_PER_PER(value) (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
+#define TCC_PER_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER) MASK Register */
+
+/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t DITHER:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHER:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHER:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */
+#define TCC_CC_RESETVALUE _U_(0x00000000) /**< \brief (TCC_CC reset_value) Compare and Capture */
+
+// DITH4 mode
+#define TCC_CC_DITH4_DITHER_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
+#define TCC_CC_DITH4_DITHER_Msk (_U_(0xF) << TCC_CC_DITH4_DITHER_Pos)
+#define TCC_CC_DITH4_DITHER(value) (TCC_CC_DITH4_DITHER_Msk & ((value) << TCC_CC_DITH4_DITHER_Pos))
+#define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
+#define TCC_CC_DITH4_CC_Msk (_U_(0xFFFFF) << TCC_CC_DITH4_CC_Pos)
+#define TCC_CC_DITH4_CC(value) (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
+#define TCC_CC_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CC_DITH5_DITHER_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
+#define TCC_CC_DITH5_DITHER_Msk (_U_(0x1F) << TCC_CC_DITH5_DITHER_Pos)
+#define TCC_CC_DITH5_DITHER(value) (TCC_CC_DITH5_DITHER_Msk & ((value) << TCC_CC_DITH5_DITHER_Pos))
+#define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
+#define TCC_CC_DITH5_CC_Msk (_U_(0x7FFFF) << TCC_CC_DITH5_CC_Pos)
+#define TCC_CC_DITH5_CC(value) (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
+#define TCC_CC_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CC_DITH6_DITHER_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
+#define TCC_CC_DITH6_DITHER_Msk (_U_(0x3F) << TCC_CC_DITH6_DITHER_Pos)
+#define TCC_CC_DITH6_DITHER(value) (TCC_CC_DITH6_DITHER_Msk & ((value) << TCC_CC_DITH6_DITHER_Pos))
+#define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
+#define TCC_CC_DITH6_CC_Msk (_U_(0x3FFFF) << TCC_CC_DITH6_CC_Pos)
+#define TCC_CC_DITH6_CC(value) (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
+#define TCC_CC_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH6) MASK Register */
+
+#define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */
+#define TCC_CC_CC_Msk (_U_(0xFFFFFF) << TCC_CC_CC_Pos)
+#define TCC_CC_CC(value) (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
+#define TCC_CC_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC) MASK Register */
+
+/* -------- TCC_PATTBUF : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
+ uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
+ uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
+ uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
+ uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
+ uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
+ uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
+ uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
+ uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
+ uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
+ uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
+ uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
+ uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
+ uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
+ uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
+ uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
+ uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} TCC_PATTBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATTBUF_OFFSET 0x64 /**< \brief (TCC_PATTBUF offset) Pattern Buffer */
+#define TCC_PATTBUF_RESETVALUE _U_(0x0000) /**< \brief (TCC_PATTBUF reset_value) Pattern Buffer */
+
+#define TCC_PATTBUF_PGEB0_Pos 0 /**< \brief (TCC_PATTBUF) Pattern Generator 0 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB0 (_U_(1) << TCC_PATTBUF_PGEB0_Pos)
+#define TCC_PATTBUF_PGEB1_Pos 1 /**< \brief (TCC_PATTBUF) Pattern Generator 1 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB1 (_U_(1) << TCC_PATTBUF_PGEB1_Pos)
+#define TCC_PATTBUF_PGEB2_Pos 2 /**< \brief (TCC_PATTBUF) Pattern Generator 2 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB2 (_U_(1) << TCC_PATTBUF_PGEB2_Pos)
+#define TCC_PATTBUF_PGEB3_Pos 3 /**< \brief (TCC_PATTBUF) Pattern Generator 3 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB3 (_U_(1) << TCC_PATTBUF_PGEB3_Pos)
+#define TCC_PATTBUF_PGEB4_Pos 4 /**< \brief (TCC_PATTBUF) Pattern Generator 4 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB4 (_U_(1) << TCC_PATTBUF_PGEB4_Pos)
+#define TCC_PATTBUF_PGEB5_Pos 5 /**< \brief (TCC_PATTBUF) Pattern Generator 5 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB5 (_U_(1) << TCC_PATTBUF_PGEB5_Pos)
+#define TCC_PATTBUF_PGEB6_Pos 6 /**< \brief (TCC_PATTBUF) Pattern Generator 6 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB6 (_U_(1) << TCC_PATTBUF_PGEB6_Pos)
+#define TCC_PATTBUF_PGEB7_Pos 7 /**< \brief (TCC_PATTBUF) Pattern Generator 7 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB7 (_U_(1) << TCC_PATTBUF_PGEB7_Pos)
+#define TCC_PATTBUF_PGEB_Pos 0 /**< \brief (TCC_PATTBUF) Pattern Generator x Output Enable Buffer */
+#define TCC_PATTBUF_PGEB_Msk (_U_(0xFF) << TCC_PATTBUF_PGEB_Pos)
+#define TCC_PATTBUF_PGEB(value) (TCC_PATTBUF_PGEB_Msk & ((value) << TCC_PATTBUF_PGEB_Pos))
+#define TCC_PATTBUF_PGVB0_Pos 8 /**< \brief (TCC_PATTBUF) Pattern Generator 0 Output Enable */
+#define TCC_PATTBUF_PGVB0 (_U_(1) << TCC_PATTBUF_PGVB0_Pos)
+#define TCC_PATTBUF_PGVB1_Pos 9 /**< \brief (TCC_PATTBUF) Pattern Generator 1 Output Enable */
+#define TCC_PATTBUF_PGVB1 (_U_(1) << TCC_PATTBUF_PGVB1_Pos)
+#define TCC_PATTBUF_PGVB2_Pos 10 /**< \brief (TCC_PATTBUF) Pattern Generator 2 Output Enable */
+#define TCC_PATTBUF_PGVB2 (_U_(1) << TCC_PATTBUF_PGVB2_Pos)
+#define TCC_PATTBUF_PGVB3_Pos 11 /**< \brief (TCC_PATTBUF) Pattern Generator 3 Output Enable */
+#define TCC_PATTBUF_PGVB3 (_U_(1) << TCC_PATTBUF_PGVB3_Pos)
+#define TCC_PATTBUF_PGVB4_Pos 12 /**< \brief (TCC_PATTBUF) Pattern Generator 4 Output Enable */
+#define TCC_PATTBUF_PGVB4 (_U_(1) << TCC_PATTBUF_PGVB4_Pos)
+#define TCC_PATTBUF_PGVB5_Pos 13 /**< \brief (TCC_PATTBUF) Pattern Generator 5 Output Enable */
+#define TCC_PATTBUF_PGVB5 (_U_(1) << TCC_PATTBUF_PGVB5_Pos)
+#define TCC_PATTBUF_PGVB6_Pos 14 /**< \brief (TCC_PATTBUF) Pattern Generator 6 Output Enable */
+#define TCC_PATTBUF_PGVB6 (_U_(1) << TCC_PATTBUF_PGVB6_Pos)
+#define TCC_PATTBUF_PGVB7_Pos 15 /**< \brief (TCC_PATTBUF) Pattern Generator 7 Output Enable */
+#define TCC_PATTBUF_PGVB7 (_U_(1) << TCC_PATTBUF_PGVB7_Pos)
+#define TCC_PATTBUF_PGVB_Pos 8 /**< \brief (TCC_PATTBUF) Pattern Generator x Output Enable */
+#define TCC_PATTBUF_PGVB_Msk (_U_(0xFF) << TCC_PATTBUF_PGVB_Pos)
+#define TCC_PATTBUF_PGVB(value) (TCC_PATTBUF_PGVB_Msk & ((value) << TCC_PATTBUF_PGVB_Pos))
+#define TCC_PATTBUF_MASK _U_(0xFFFF) /**< \brief (TCC_PATTBUF) MASK Register */
+
+/* -------- TCC_PERBUF : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t DITHERBUF:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
+ uint32_t PERBUF:20; /*!< bit: 4..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERBUF:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t PERBUF:19; /*!< bit: 5..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERBUF:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t PERBUF:18; /*!< bit: 6..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PERBUF:24; /*!< bit: 0..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_PERBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PERBUF_OFFSET 0x6C /**< \brief (TCC_PERBUF offset) Period Buffer */
+#define TCC_PERBUF_RESETVALUE _U_(0xFFFFFFFF) /**< \brief (TCC_PERBUF reset_value) Period Buffer */
+
+// DITH4 mode
+#define TCC_PERBUF_DITH4_DITHERBUF_Pos 0 /**< \brief (TCC_PERBUF_DITH4) Dithering Buffer Cycle Number */
+#define TCC_PERBUF_DITH4_DITHERBUF_Msk (_U_(0xF) << TCC_PERBUF_DITH4_DITHERBUF_Pos)
+#define TCC_PERBUF_DITH4_DITHERBUF(value) (TCC_PERBUF_DITH4_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH4_DITHERBUF_Pos))
+#define TCC_PERBUF_DITH4_PERBUF_Pos 4 /**< \brief (TCC_PERBUF_DITH4) Period Buffer Value */
+#define TCC_PERBUF_DITH4_PERBUF_Msk (_U_(0xFFFFF) << TCC_PERBUF_DITH4_PERBUF_Pos)
+#define TCC_PERBUF_DITH4_PERBUF(value) (TCC_PERBUF_DITH4_PERBUF_Msk & ((value) << TCC_PERBUF_DITH4_PERBUF_Pos))
+#define TCC_PERBUF_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PERBUF_DITH5_DITHERBUF_Pos 0 /**< \brief (TCC_PERBUF_DITH5) Dithering Buffer Cycle Number */
+#define TCC_PERBUF_DITH5_DITHERBUF_Msk (_U_(0x1F) << TCC_PERBUF_DITH5_DITHERBUF_Pos)
+#define TCC_PERBUF_DITH5_DITHERBUF(value) (TCC_PERBUF_DITH5_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH5_DITHERBUF_Pos))
+#define TCC_PERBUF_DITH5_PERBUF_Pos 5 /**< \brief (TCC_PERBUF_DITH5) Period Buffer Value */
+#define TCC_PERBUF_DITH5_PERBUF_Msk (_U_(0x7FFFF) << TCC_PERBUF_DITH5_PERBUF_Pos)
+#define TCC_PERBUF_DITH5_PERBUF(value) (TCC_PERBUF_DITH5_PERBUF_Msk & ((value) << TCC_PERBUF_DITH5_PERBUF_Pos))
+#define TCC_PERBUF_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PERBUF_DITH6_DITHERBUF_Pos 0 /**< \brief (TCC_PERBUF_DITH6) Dithering Buffer Cycle Number */
+#define TCC_PERBUF_DITH6_DITHERBUF_Msk (_U_(0x3F) << TCC_PERBUF_DITH6_DITHERBUF_Pos)
+#define TCC_PERBUF_DITH6_DITHERBUF(value) (TCC_PERBUF_DITH6_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH6_DITHERBUF_Pos))
+#define TCC_PERBUF_DITH6_PERBUF_Pos 6 /**< \brief (TCC_PERBUF_DITH6) Period Buffer Value */
+#define TCC_PERBUF_DITH6_PERBUF_Msk (_U_(0x3FFFF) << TCC_PERBUF_DITH6_PERBUF_Pos)
+#define TCC_PERBUF_DITH6_PERBUF(value) (TCC_PERBUF_DITH6_PERBUF_Msk & ((value) << TCC_PERBUF_DITH6_PERBUF_Pos))
+#define TCC_PERBUF_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF_DITH6) MASK Register */
+
+#define TCC_PERBUF_PERBUF_Pos 0 /**< \brief (TCC_PERBUF) Period Buffer Value */
+#define TCC_PERBUF_PERBUF_Msk (_U_(0xFFFFFF) << TCC_PERBUF_PERBUF_Pos)
+#define TCC_PERBUF_PERBUF(value) (TCC_PERBUF_PERBUF_Msk & ((value) << TCC_PERBUF_PERBUF_Pos))
+#define TCC_PERBUF_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF) MASK Register */
+
+/* -------- TCC_CCBUF : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t CCBUF:4; /*!< bit: 0.. 3 Channel Compare/Capture Buffer Value */
+ uint32_t DITHERBUF:20; /*!< bit: 4..23 Dithering Buffer Cycle Number */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERBUF:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t CCBUF:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERBUF:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t CCBUF:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CCBUF:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_CCBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CCBUF_OFFSET 0x70 /**< \brief (TCC_CCBUF offset) Compare and Capture Buffer */
+#define TCC_CCBUF_RESETVALUE _U_(0x00000000) /**< \brief (TCC_CCBUF reset_value) Compare and Capture Buffer */
+
+// DITH4 mode
+#define TCC_CCBUF_DITH4_CCBUF_Pos 0 /**< \brief (TCC_CCBUF_DITH4) Channel Compare/Capture Buffer Value */
+#define TCC_CCBUF_DITH4_CCBUF_Msk (_U_(0xF) << TCC_CCBUF_DITH4_CCBUF_Pos)
+#define TCC_CCBUF_DITH4_CCBUF(value) (TCC_CCBUF_DITH4_CCBUF_Msk & ((value) << TCC_CCBUF_DITH4_CCBUF_Pos))
+#define TCC_CCBUF_DITH4_DITHERBUF_Pos 4 /**< \brief (TCC_CCBUF_DITH4) Dithering Buffer Cycle Number */
+#define TCC_CCBUF_DITH4_DITHERBUF_Msk (_U_(0xFFFFF) << TCC_CCBUF_DITH4_DITHERBUF_Pos)
+#define TCC_CCBUF_DITH4_DITHERBUF(value) (TCC_CCBUF_DITH4_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH4_DITHERBUF_Pos))
+#define TCC_CCBUF_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CCBUF_DITH5_DITHERBUF_Pos 0 /**< \brief (TCC_CCBUF_DITH5) Dithering Buffer Cycle Number */
+#define TCC_CCBUF_DITH5_DITHERBUF_Msk (_U_(0x1F) << TCC_CCBUF_DITH5_DITHERBUF_Pos)
+#define TCC_CCBUF_DITH5_DITHERBUF(value) (TCC_CCBUF_DITH5_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH5_DITHERBUF_Pos))
+#define TCC_CCBUF_DITH5_CCBUF_Pos 5 /**< \brief (TCC_CCBUF_DITH5) Channel Compare/Capture Buffer Value */
+#define TCC_CCBUF_DITH5_CCBUF_Msk (_U_(0x7FFFF) << TCC_CCBUF_DITH5_CCBUF_Pos)
+#define TCC_CCBUF_DITH5_CCBUF(value) (TCC_CCBUF_DITH5_CCBUF_Msk & ((value) << TCC_CCBUF_DITH5_CCBUF_Pos))
+#define TCC_CCBUF_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CCBUF_DITH6_DITHERBUF_Pos 0 /**< \brief (TCC_CCBUF_DITH6) Dithering Buffer Cycle Number */
+#define TCC_CCBUF_DITH6_DITHERBUF_Msk (_U_(0x3F) << TCC_CCBUF_DITH6_DITHERBUF_Pos)
+#define TCC_CCBUF_DITH6_DITHERBUF(value) (TCC_CCBUF_DITH6_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH6_DITHERBUF_Pos))
+#define TCC_CCBUF_DITH6_CCBUF_Pos 6 /**< \brief (TCC_CCBUF_DITH6) Channel Compare/Capture Buffer Value */
+#define TCC_CCBUF_DITH6_CCBUF_Msk (_U_(0x3FFFF) << TCC_CCBUF_DITH6_CCBUF_Pos)
+#define TCC_CCBUF_DITH6_CCBUF(value) (TCC_CCBUF_DITH6_CCBUF_Msk & ((value) << TCC_CCBUF_DITH6_CCBUF_Pos))
+#define TCC_CCBUF_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF_DITH6) MASK Register */
+
+#define TCC_CCBUF_CCBUF_Pos 0 /**< \brief (TCC_CCBUF) Channel Compare/Capture Buffer Value */
+#define TCC_CCBUF_CCBUF_Msk (_U_(0xFFFFFF) << TCC_CCBUF_CCBUF_Pos)
+#define TCC_CCBUF_CCBUF(value) (TCC_CCBUF_CCBUF_Msk & ((value) << TCC_CCBUF_CCBUF_Pos))
+#define TCC_CCBUF_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF) MASK Register */
+
+/** \brief TCC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ RoReg8 Reserved1[0x2];
+ __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
+ __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
+ __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
+ __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
+ __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
+ RoReg8 Reserved2[0x2];
+ __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
+ RoReg8 Reserved3[0x1];
+ __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
+ __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
+ __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
+ __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
+ __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
+ __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
+ __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
+ RoReg8 Reserved4[0x2];
+ __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
+ __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
+ __IO TCC_CC_Type CC[6]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
+ RoReg8 Reserved5[0x8];
+ __IO TCC_PATTBUF_Type PATTBUF; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
+ RoReg8 Reserved6[0x6];
+ __IO TCC_PERBUF_Type PERBUF; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
+ __IO TCC_CCBUF_Type CCBUF[6]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
+} Tcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_TCC_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/trng.h b/sysmoOCTSIM/include/component/trng.h
index e15cd57..4442fec 100644
--- a/sysmoOCTSIM/include/component/trng.h
+++ b/sysmoOCTSIM/include/component/trng.h
@@ -1,172 +1,172 @@
-/**
- * \file
- *
- * \brief Component description for TRNG
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_TRNG_COMPONENT_
-#define _SAME54_TRNG_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR TRNG */
-/* ========================================================================== */
-/** \addtogroup SAME54_TRNG True Random Generator */
-/*@{*/
-
-#define TRNG_U2242
-#define REV_TRNG 0x110
-
-/* -------- TRNG_CTRLA : (TRNG Offset: 0x00) (R/W 8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t :1; /*!< bit: 0 Reserved */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} TRNG_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TRNG_CTRLA_OFFSET 0x00 /**< \brief (TRNG_CTRLA offset) Control A */
-#define TRNG_CTRLA_RESETVALUE _U_(0x00) /**< \brief (TRNG_CTRLA reset_value) Control A */
-
-#define TRNG_CTRLA_ENABLE_Pos 1 /**< \brief (TRNG_CTRLA) Enable */
-#define TRNG_CTRLA_ENABLE (_U_(0x1) << TRNG_CTRLA_ENABLE_Pos)
-#define TRNG_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TRNG_CTRLA) Run in Standby */
-#define TRNG_CTRLA_RUNSTDBY (_U_(0x1) << TRNG_CTRLA_RUNSTDBY_Pos)
-#define TRNG_CTRLA_MASK _U_(0x42) /**< \brief (TRNG_CTRLA) MASK Register */
-
-/* -------- TRNG_EVCTRL : (TRNG Offset: 0x04) (R/W 8) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DATARDYEO:1; /*!< bit: 0 Data Ready Event Output */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} TRNG_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TRNG_EVCTRL_OFFSET 0x04 /**< \brief (TRNG_EVCTRL offset) Event Control */
-#define TRNG_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (TRNG_EVCTRL reset_value) Event Control */
-
-#define TRNG_EVCTRL_DATARDYEO_Pos 0 /**< \brief (TRNG_EVCTRL) Data Ready Event Output */
-#define TRNG_EVCTRL_DATARDYEO (_U_(0x1) << TRNG_EVCTRL_DATARDYEO_Pos)
-#define TRNG_EVCTRL_MASK _U_(0x01) /**< \brief (TRNG_EVCTRL) MASK Register */
-
-/* -------- TRNG_INTENCLR : (TRNG Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} TRNG_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TRNG_INTENCLR_OFFSET 0x08 /**< \brief (TRNG_INTENCLR offset) Interrupt Enable Clear */
-#define TRNG_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (TRNG_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define TRNG_INTENCLR_DATARDY_Pos 0 /**< \brief (TRNG_INTENCLR) Data Ready Interrupt Enable */
-#define TRNG_INTENCLR_DATARDY (_U_(0x1) << TRNG_INTENCLR_DATARDY_Pos)
-#define TRNG_INTENCLR_MASK _U_(0x01) /**< \brief (TRNG_INTENCLR) MASK Register */
-
-/* -------- TRNG_INTENSET : (TRNG Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} TRNG_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TRNG_INTENSET_OFFSET 0x09 /**< \brief (TRNG_INTENSET offset) Interrupt Enable Set */
-#define TRNG_INTENSET_RESETVALUE _U_(0x00) /**< \brief (TRNG_INTENSET reset_value) Interrupt Enable Set */
-
-#define TRNG_INTENSET_DATARDY_Pos 0 /**< \brief (TRNG_INTENSET) Data Ready Interrupt Enable */
-#define TRNG_INTENSET_DATARDY (_U_(0x1) << TRNG_INTENSET_DATARDY_Pos)
-#define TRNG_INTENSET_MASK _U_(0x01) /**< \brief (TRNG_INTENSET) MASK Register */
-
-/* -------- TRNG_INTFLAG : (TRNG Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Flag */
- __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} TRNG_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TRNG_INTFLAG_OFFSET 0x0A /**< \brief (TRNG_INTFLAG offset) Interrupt Flag Status and Clear */
-#define TRNG_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (TRNG_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define TRNG_INTFLAG_DATARDY_Pos 0 /**< \brief (TRNG_INTFLAG) Data Ready Interrupt Flag */
-#define TRNG_INTFLAG_DATARDY (_U_(0x1) << TRNG_INTFLAG_DATARDY_Pos)
-#define TRNG_INTFLAG_MASK _U_(0x01) /**< \brief (TRNG_INTFLAG) MASK Register */
-
-/* -------- TRNG_DATA : (TRNG Offset: 0x20) (R/ 32) Output Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 Output Data */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} TRNG_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TRNG_DATA_OFFSET 0x20 /**< \brief (TRNG_DATA offset) Output Data */
-#define TRNG_DATA_RESETVALUE _U_(0x00000000) /**< \brief (TRNG_DATA reset_value) Output Data */
-
-#define TRNG_DATA_DATA_Pos 0 /**< \brief (TRNG_DATA) Output Data */
-#define TRNG_DATA_DATA_Msk (_U_(0xFFFFFFFF) << TRNG_DATA_DATA_Pos)
-#define TRNG_DATA_DATA(value) (TRNG_DATA_DATA_Msk & ((value) << TRNG_DATA_DATA_Pos))
-#define TRNG_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (TRNG_DATA) MASK Register */
-
-/** \brief TRNG hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO TRNG_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
- RoReg8 Reserved1[0x3];
- __IO TRNG_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event Control */
- RoReg8 Reserved2[0x3];
- __IO TRNG_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
- __IO TRNG_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
- __IO TRNG_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
- RoReg8 Reserved3[0x15];
- __I TRNG_DATA_Type DATA; /**< \brief Offset: 0x20 (R/ 32) Output Data */
-} Trng;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_TRNG_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for TRNG
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TRNG_COMPONENT_
+#define _SAME54_TRNG_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR TRNG */
+/* ========================================================================== */
+/** \addtogroup SAME54_TRNG True Random Generator */
+/*@{*/
+
+#define TRNG_U2242
+#define REV_TRNG 0x110
+
+/* -------- TRNG_CTRLA : (TRNG Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TRNG_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TRNG_CTRLA_OFFSET 0x00 /**< \brief (TRNG_CTRLA offset) Control A */
+#define TRNG_CTRLA_RESETVALUE _U_(0x00) /**< \brief (TRNG_CTRLA reset_value) Control A */
+
+#define TRNG_CTRLA_ENABLE_Pos 1 /**< \brief (TRNG_CTRLA) Enable */
+#define TRNG_CTRLA_ENABLE (_U_(0x1) << TRNG_CTRLA_ENABLE_Pos)
+#define TRNG_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TRNG_CTRLA) Run in Standby */
+#define TRNG_CTRLA_RUNSTDBY (_U_(0x1) << TRNG_CTRLA_RUNSTDBY_Pos)
+#define TRNG_CTRLA_MASK _U_(0x42) /**< \brief (TRNG_CTRLA) MASK Register */
+
+/* -------- TRNG_EVCTRL : (TRNG Offset: 0x04) (R/W 8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DATARDYEO:1; /*!< bit: 0 Data Ready Event Output */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TRNG_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TRNG_EVCTRL_OFFSET 0x04 /**< \brief (TRNG_EVCTRL offset) Event Control */
+#define TRNG_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (TRNG_EVCTRL reset_value) Event Control */
+
+#define TRNG_EVCTRL_DATARDYEO_Pos 0 /**< \brief (TRNG_EVCTRL) Data Ready Event Output */
+#define TRNG_EVCTRL_DATARDYEO (_U_(0x1) << TRNG_EVCTRL_DATARDYEO_Pos)
+#define TRNG_EVCTRL_MASK _U_(0x01) /**< \brief (TRNG_EVCTRL) MASK Register */
+
+/* -------- TRNG_INTENCLR : (TRNG Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TRNG_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TRNG_INTENCLR_OFFSET 0x08 /**< \brief (TRNG_INTENCLR offset) Interrupt Enable Clear */
+#define TRNG_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (TRNG_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TRNG_INTENCLR_DATARDY_Pos 0 /**< \brief (TRNG_INTENCLR) Data Ready Interrupt Enable */
+#define TRNG_INTENCLR_DATARDY (_U_(0x1) << TRNG_INTENCLR_DATARDY_Pos)
+#define TRNG_INTENCLR_MASK _U_(0x01) /**< \brief (TRNG_INTENCLR) MASK Register */
+
+/* -------- TRNG_INTENSET : (TRNG Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TRNG_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TRNG_INTENSET_OFFSET 0x09 /**< \brief (TRNG_INTENSET offset) Interrupt Enable Set */
+#define TRNG_INTENSET_RESETVALUE _U_(0x00) /**< \brief (TRNG_INTENSET reset_value) Interrupt Enable Set */
+
+#define TRNG_INTENSET_DATARDY_Pos 0 /**< \brief (TRNG_INTENSET) Data Ready Interrupt Enable */
+#define TRNG_INTENSET_DATARDY (_U_(0x1) << TRNG_INTENSET_DATARDY_Pos)
+#define TRNG_INTENSET_MASK _U_(0x01) /**< \brief (TRNG_INTENSET) MASK Register */
+
+/* -------- TRNG_INTFLAG : (TRNG Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Flag */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TRNG_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TRNG_INTFLAG_OFFSET 0x0A /**< \brief (TRNG_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TRNG_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (TRNG_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TRNG_INTFLAG_DATARDY_Pos 0 /**< \brief (TRNG_INTFLAG) Data Ready Interrupt Flag */
+#define TRNG_INTFLAG_DATARDY (_U_(0x1) << TRNG_INTFLAG_DATARDY_Pos)
+#define TRNG_INTFLAG_MASK _U_(0x01) /**< \brief (TRNG_INTFLAG) MASK Register */
+
+/* -------- TRNG_DATA : (TRNG Offset: 0x20) (R/ 32) Output Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Output Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TRNG_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TRNG_DATA_OFFSET 0x20 /**< \brief (TRNG_DATA offset) Output Data */
+#define TRNG_DATA_RESETVALUE _U_(0x00000000) /**< \brief (TRNG_DATA reset_value) Output Data */
+
+#define TRNG_DATA_DATA_Pos 0 /**< \brief (TRNG_DATA) Output Data */
+#define TRNG_DATA_DATA_Msk (_U_(0xFFFFFFFF) << TRNG_DATA_DATA_Pos)
+#define TRNG_DATA_DATA(value) (TRNG_DATA_DATA_Msk & ((value) << TRNG_DATA_DATA_Pos))
+#define TRNG_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (TRNG_DATA) MASK Register */
+
+/** \brief TRNG hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO TRNG_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ RoReg8 Reserved1[0x3];
+ __IO TRNG_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event Control */
+ RoReg8 Reserved2[0x3];
+ __IO TRNG_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
+ __IO TRNG_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
+ __IO TRNG_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved3[0x15];
+ __I TRNG_DATA_Type DATA; /**< \brief Offset: 0x20 (R/ 32) Output Data */
+} Trng;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_TRNG_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/usb.h b/sysmoOCTSIM/include/component/usb.h
index 5aa9f61..b433aae 100644
--- a/sysmoOCTSIM/include/component/usb.h
+++ b/sysmoOCTSIM/include/component/usb.h
@@ -1,1777 +1,1777 @@
-/**
- * \file
- *
- * \brief Component description for USB
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_USB_COMPONENT_
-#define _SAME54_USB_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR USB */
-/* ========================================================================== */
-/** \addtogroup SAME54_USB Universal Serial Bus */
-/*@{*/
-
-#define USB_U2222
-#define REV_USB 0x120
-
-/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t MODE:1; /*!< bit: 7 Operating Mode */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} USB_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_CTRLA_OFFSET 0x000 /**< \brief (USB_CTRLA offset) Control A */
-#define USB_CTRLA_RESETVALUE _U_(0x00) /**< \brief (USB_CTRLA reset_value) Control A */
-
-#define USB_CTRLA_SWRST_Pos 0 /**< \brief (USB_CTRLA) Software Reset */
-#define USB_CTRLA_SWRST (_U_(0x1) << USB_CTRLA_SWRST_Pos)
-#define USB_CTRLA_ENABLE_Pos 1 /**< \brief (USB_CTRLA) Enable */
-#define USB_CTRLA_ENABLE (_U_(0x1) << USB_CTRLA_ENABLE_Pos)
-#define USB_CTRLA_RUNSTDBY_Pos 2 /**< \brief (USB_CTRLA) Run in Standby Mode */
-#define USB_CTRLA_RUNSTDBY (_U_(0x1) << USB_CTRLA_RUNSTDBY_Pos)
-#define USB_CTRLA_MODE_Pos 7 /**< \brief (USB_CTRLA) Operating Mode */
-#define USB_CTRLA_MODE (_U_(0x1) << USB_CTRLA_MODE_Pos)
-#define USB_CTRLA_MODE_DEVICE_Val _U_(0x0) /**< \brief (USB_CTRLA) Device Mode */
-#define USB_CTRLA_MODE_HOST_Val _U_(0x1) /**< \brief (USB_CTRLA) Host Mode */
-#define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos)
-#define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos)
-#define USB_CTRLA_MASK _U_(0x87) /**< \brief (USB_CTRLA) MASK Register */
-
-/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} USB_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_SYNCBUSY_OFFSET 0x002 /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */
-#define USB_SYNCBUSY_RESETVALUE _U_(0x00) /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */
-
-#define USB_SYNCBUSY_SWRST_Pos 0 /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */
-#define USB_SYNCBUSY_SWRST (_U_(0x1) << USB_SYNCBUSY_SWRST_Pos)
-#define USB_SYNCBUSY_ENABLE_Pos 1 /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */
-#define USB_SYNCBUSY_ENABLE (_U_(0x1) << USB_SYNCBUSY_ENABLE_Pos)
-#define USB_SYNCBUSY_MASK _U_(0x03) /**< \brief (USB_SYNCBUSY) MASK Register */
-
-/* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */
- uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} USB_QOSCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_QOSCTRL_OFFSET 0x003 /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */
-#define USB_QOSCTRL_RESETVALUE _U_(0x0F) /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */
-
-#define USB_QOSCTRL_CQOS_Pos 0 /**< \brief (USB_QOSCTRL) Configuration Quality of Service */
-#define USB_QOSCTRL_CQOS_Msk (_U_(0x3) << USB_QOSCTRL_CQOS_Pos)
-#define USB_QOSCTRL_CQOS(value) (USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos))
-#define USB_QOSCTRL_DQOS_Pos 2 /**< \brief (USB_QOSCTRL) Data Quality of Service */
-#define USB_QOSCTRL_DQOS_Msk (_U_(0x3) << USB_QOSCTRL_DQOS_Pos)
-#define USB_QOSCTRL_DQOS(value) (USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos))
-#define USB_QOSCTRL_MASK _U_(0x0F) /**< \brief (USB_QOSCTRL) MASK Register */
-
-/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t DETACH:1; /*!< bit: 0 Detach */
- uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */
- uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */
- uint16_t NREPLY:1; /*!< bit: 4 No Reply */
- uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
- uint16_t TSTK:1; /*!< bit: 6 Test mode K */
- uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */
- uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */
- uint16_t GNAK:1; /*!< bit: 9 Global NAK */
- uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} USB_DEVICE_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_CTRLB_OFFSET 0x008 /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */
-#define USB_DEVICE_CTRLB_RESETVALUE _U_(0x0001) /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */
-
-#define USB_DEVICE_CTRLB_DETACH_Pos 0 /**< \brief (USB_DEVICE_CTRLB) Detach */
-#define USB_DEVICE_CTRLB_DETACH (_U_(0x1) << USB_DEVICE_CTRLB_DETACH_Pos)
-#define USB_DEVICE_CTRLB_UPRSM_Pos 1 /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */
-#define USB_DEVICE_CTRLB_UPRSM (_U_(0x1) << USB_DEVICE_CTRLB_UPRSM_Pos)
-#define USB_DEVICE_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */
-#define USB_DEVICE_CTRLB_SPDCONF_Msk (_U_(0x3) << USB_DEVICE_CTRLB_SPDCONF_Pos)
-#define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos))
-#define USB_DEVICE_CTRLB_SPDCONF_FS_Val _U_(0x0) /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */
-#define USB_DEVICE_CTRLB_SPDCONF_LS_Val _U_(0x1) /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */
-#define USB_DEVICE_CTRLB_SPDCONF_HS_Val _U_(0x2) /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */
-#define USB_DEVICE_CTRLB_SPDCONF_HSTM_Val _U_(0x3) /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */
-#define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
-#define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
-#define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
-#define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
-#define USB_DEVICE_CTRLB_NREPLY_Pos 4 /**< \brief (USB_DEVICE_CTRLB) No Reply */
-#define USB_DEVICE_CTRLB_NREPLY (_U_(0x1) << USB_DEVICE_CTRLB_NREPLY_Pos)
-#define USB_DEVICE_CTRLB_TSTJ_Pos 5 /**< \brief (USB_DEVICE_CTRLB) Test mode J */
-#define USB_DEVICE_CTRLB_TSTJ (_U_(0x1) << USB_DEVICE_CTRLB_TSTJ_Pos)
-#define USB_DEVICE_CTRLB_TSTK_Pos 6 /**< \brief (USB_DEVICE_CTRLB) Test mode K */
-#define USB_DEVICE_CTRLB_TSTK (_U_(0x1) << USB_DEVICE_CTRLB_TSTK_Pos)
-#define USB_DEVICE_CTRLB_TSTPCKT_Pos 7 /**< \brief (USB_DEVICE_CTRLB) Test packet mode */
-#define USB_DEVICE_CTRLB_TSTPCKT (_U_(0x1) << USB_DEVICE_CTRLB_TSTPCKT_Pos)
-#define USB_DEVICE_CTRLB_OPMODE2_Pos 8 /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */
-#define USB_DEVICE_CTRLB_OPMODE2 (_U_(0x1) << USB_DEVICE_CTRLB_OPMODE2_Pos)
-#define USB_DEVICE_CTRLB_GNAK_Pos 9 /**< \brief (USB_DEVICE_CTRLB) Global NAK */
-#define USB_DEVICE_CTRLB_GNAK (_U_(0x1) << USB_DEVICE_CTRLB_GNAK_Pos)
-#define USB_DEVICE_CTRLB_LPMHDSK_Pos 10 /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */
-#define USB_DEVICE_CTRLB_LPMHDSK_Msk (_U_(0x3) << USB_DEVICE_CTRLB_LPMHDSK_Pos)
-#define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos))
-#define USB_DEVICE_CTRLB_LPMHDSK_NO_Val _U_(0x0) /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */
-#define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val _U_(0x1) /**< \brief (USB_DEVICE_CTRLB) ACK */
-#define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val _U_(0x2) /**< \brief (USB_DEVICE_CTRLB) NYET */
-#define USB_DEVICE_CTRLB_LPMHDSK_STALL_Val _U_(0x3) /**< \brief (USB_DEVICE_CTRLB) STALL */
-#define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
-#define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
-#define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
-#define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
-#define USB_DEVICE_CTRLB_MASK _U_(0x0FFF) /**< \brief (USB_DEVICE_CTRLB) MASK Register */
-
-/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t :1; /*!< bit: 0 Reserved */
- uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */
- uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */
- uint16_t AUTORESUME:1; /*!< bit: 4 Auto Resume Enable */
- uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
- uint16_t TSTK:1; /*!< bit: 6 Test mode K */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */
- uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */
- uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */
- uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} USB_HOST_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_CTRLB_OFFSET 0x008 /**< \brief (USB_HOST_CTRLB offset) HOST Control B */
-#define USB_HOST_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */
-
-#define USB_HOST_CTRLB_RESUME_Pos 1 /**< \brief (USB_HOST_CTRLB) Send USB Resume */
-#define USB_HOST_CTRLB_RESUME (_U_(0x1) << USB_HOST_CTRLB_RESUME_Pos)
-#define USB_HOST_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */
-#define USB_HOST_CTRLB_SPDCONF_Msk (_U_(0x3) << USB_HOST_CTRLB_SPDCONF_Pos)
-#define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos))
-#define USB_HOST_CTRLB_SPDCONF_NORMAL_Val _U_(0x0) /**< \brief (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */
-#define USB_HOST_CTRLB_SPDCONF_FS_Val _U_(0x3) /**< \brief (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */
-#define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos)
-#define USB_HOST_CTRLB_SPDCONF_FS (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos)
-#define USB_HOST_CTRLB_AUTORESUME_Pos 4 /**< \brief (USB_HOST_CTRLB) Auto Resume Enable */
-#define USB_HOST_CTRLB_AUTORESUME (_U_(0x1) << USB_HOST_CTRLB_AUTORESUME_Pos)
-#define USB_HOST_CTRLB_TSTJ_Pos 5 /**< \brief (USB_HOST_CTRLB) Test mode J */
-#define USB_HOST_CTRLB_TSTJ (_U_(0x1) << USB_HOST_CTRLB_TSTJ_Pos)
-#define USB_HOST_CTRLB_TSTK_Pos 6 /**< \brief (USB_HOST_CTRLB) Test mode K */
-#define USB_HOST_CTRLB_TSTK (_U_(0x1) << USB_HOST_CTRLB_TSTK_Pos)
-#define USB_HOST_CTRLB_SOFE_Pos 8 /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */
-#define USB_HOST_CTRLB_SOFE (_U_(0x1) << USB_HOST_CTRLB_SOFE_Pos)
-#define USB_HOST_CTRLB_BUSRESET_Pos 9 /**< \brief (USB_HOST_CTRLB) Send USB Reset */
-#define USB_HOST_CTRLB_BUSRESET (_U_(0x1) << USB_HOST_CTRLB_BUSRESET_Pos)
-#define USB_HOST_CTRLB_VBUSOK_Pos 10 /**< \brief (USB_HOST_CTRLB) VBUS is OK */
-#define USB_HOST_CTRLB_VBUSOK (_U_(0x1) << USB_HOST_CTRLB_VBUSOK_Pos)
-#define USB_HOST_CTRLB_L1RESUME_Pos 11 /**< \brief (USB_HOST_CTRLB) Send L1 Resume */
-#define USB_HOST_CTRLB_L1RESUME (_U_(0x1) << USB_HOST_CTRLB_L1RESUME_Pos)
-#define USB_HOST_CTRLB_MASK _U_(0x0F7E) /**< \brief (USB_HOST_CTRLB) MASK Register */
-
-/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */
- uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} USB_DEVICE_DADD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_DADD_OFFSET 0x00A /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */
-#define USB_DEVICE_DADD_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */
-
-#define USB_DEVICE_DADD_DADD_Pos 0 /**< \brief (USB_DEVICE_DADD) Device Address */
-#define USB_DEVICE_DADD_DADD_Msk (_U_(0x7F) << USB_DEVICE_DADD_DADD_Pos)
-#define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos))
-#define USB_DEVICE_DADD_ADDEN_Pos 7 /**< \brief (USB_DEVICE_DADD) Device Address Enable */
-#define USB_DEVICE_DADD_ADDEN (_U_(0x1) << USB_DEVICE_DADD_ADDEN_Pos)
-#define USB_DEVICE_DADD_MASK _U_(0xFF) /**< \brief (USB_DEVICE_DADD) MASK Register */
-
-/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} USB_HOST_HSOFC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_HSOFC_OFFSET 0x00A /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */
-#define USB_HOST_HSOFC_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */
-
-#define USB_HOST_HSOFC_FLENC_Pos 0 /**< \brief (USB_HOST_HSOFC) Frame Length Control */
-#define USB_HOST_HSOFC_FLENC_Msk (_U_(0xF) << USB_HOST_HSOFC_FLENC_Pos)
-#define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos))
-#define USB_HOST_HSOFC_FLENCE_Pos 7 /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */
-#define USB_HOST_HSOFC_FLENCE (_U_(0x1) << USB_HOST_HSOFC_FLENCE_Pos)
-#define USB_HOST_HSOFC_MASK _U_(0x8F) /**< \brief (USB_HOST_HSOFC) MASK Register */
-
-/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t :2; /*!< bit: 0.. 1 Reserved */
- uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
- uint8_t :2; /*!< bit: 4.. 5 Reserved */
- uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} USB_DEVICE_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_STATUS_OFFSET 0x00C /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */
-#define USB_DEVICE_STATUS_RESETVALUE _U_(0x40) /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */
-
-#define USB_DEVICE_STATUS_SPEED_Pos 2 /**< \brief (USB_DEVICE_STATUS) Speed Status */
-#define USB_DEVICE_STATUS_SPEED_Msk (_U_(0x3) << USB_DEVICE_STATUS_SPEED_Pos)
-#define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos))
-#define USB_DEVICE_STATUS_SPEED_FS_Val _U_(0x0) /**< \brief (USB_DEVICE_STATUS) Full-speed mode */
-#define USB_DEVICE_STATUS_SPEED_LS_Val _U_(0x1) /**< \brief (USB_DEVICE_STATUS) Low-speed mode */
-#define USB_DEVICE_STATUS_SPEED_HS_Val _U_(0x2) /**< \brief (USB_DEVICE_STATUS) High-speed mode */
-#define USB_DEVICE_STATUS_SPEED_FS (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos)
-#define USB_DEVICE_STATUS_SPEED_LS (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos)
-#define USB_DEVICE_STATUS_SPEED_HS (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos)
-#define USB_DEVICE_STATUS_LINESTATE_Pos 6 /**< \brief (USB_DEVICE_STATUS) USB Line State Status */
-#define USB_DEVICE_STATUS_LINESTATE_Msk (_U_(0x3) << USB_DEVICE_STATUS_LINESTATE_Pos)
-#define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos))
-#define USB_DEVICE_STATUS_LINESTATE_0_Val _U_(0x0) /**< \brief (USB_DEVICE_STATUS) SE0/RESET */
-#define USB_DEVICE_STATUS_LINESTATE_1_Val _U_(0x1) /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */
-#define USB_DEVICE_STATUS_LINESTATE_2_Val _U_(0x2) /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */
-#define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
-#define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
-#define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
-#define USB_DEVICE_STATUS_MASK _U_(0xCC) /**< \brief (USB_DEVICE_STATUS) MASK Register */
-
-/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t :2; /*!< bit: 0.. 1 Reserved */
- uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
- uint8_t :2; /*!< bit: 4.. 5 Reserved */
- uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} USB_HOST_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_STATUS_OFFSET 0x00C /**< \brief (USB_HOST_STATUS offset) HOST Status */
-#define USB_HOST_STATUS_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_STATUS reset_value) HOST Status */
-
-#define USB_HOST_STATUS_SPEED_Pos 2 /**< \brief (USB_HOST_STATUS) Speed Status */
-#define USB_HOST_STATUS_SPEED_Msk (_U_(0x3) << USB_HOST_STATUS_SPEED_Pos)
-#define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos))
-#define USB_HOST_STATUS_LINESTATE_Pos 6 /**< \brief (USB_HOST_STATUS) USB Line State Status */
-#define USB_HOST_STATUS_LINESTATE_Msk (_U_(0x3) << USB_HOST_STATUS_LINESTATE_Pos)
-#define USB_HOST_STATUS_LINESTATE(value) (USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos))
-#define USB_HOST_STATUS_MASK _U_(0xCC) /**< \brief (USB_HOST_STATUS) MASK Register */
-
-/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t FSMSTATE:7; /*!< bit: 0.. 6 Fine State Machine Status */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} USB_FSMSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_FSMSTATUS_OFFSET 0x00D /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */
-#define USB_FSMSTATUS_RESETVALUE _U_(0x01) /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */
-
-#define USB_FSMSTATUS_FSMSTATE_Pos 0 /**< \brief (USB_FSMSTATUS) Fine State Machine Status */
-#define USB_FSMSTATUS_FSMSTATE_Msk (_U_(0x7F) << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE(value) (USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos))
-#define USB_FSMSTATUS_FSMSTATE_OFF_Val _U_(0x1) /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */
-#define USB_FSMSTATUS_FSMSTATE_ON_Val _U_(0x2) /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */
-#define USB_FSMSTATUS_FSMSTATE_SUSPEND_Val _U_(0x4) /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */
-#define USB_FSMSTATUS_FSMSTATE_SLEEP_Val _U_(0x8) /**< \brief (USB_FSMSTATUS) SLEEP (L1) */
-#define USB_FSMSTATUS_FSMSTATE_DNRESUME_Val _U_(0x10) /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */
-#define USB_FSMSTATUS_FSMSTATE_UPRESUME_Val _U_(0x20) /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */
-#define USB_FSMSTATUS_FSMSTATE_RESET_Val _U_(0x40) /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */
-#define USB_FSMSTATUS_FSMSTATE_OFF (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE_ON (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_MASK _U_(0x7F) /**< \brief (USB_FSMSTATUS) MASK Register */
-
-/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
- uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
- uint16_t :1; /*!< bit: 14 Reserved */
- uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} USB_DEVICE_FNUM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_FNUM_OFFSET 0x010 /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */
-#define USB_DEVICE_FNUM_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */
-
-#define USB_DEVICE_FNUM_MFNUM_Pos 0 /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */
-#define USB_DEVICE_FNUM_MFNUM_Msk (_U_(0x7) << USB_DEVICE_FNUM_MFNUM_Pos)
-#define USB_DEVICE_FNUM_MFNUM(value) (USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos))
-#define USB_DEVICE_FNUM_FNUM_Pos 3 /**< \brief (USB_DEVICE_FNUM) Frame Number */
-#define USB_DEVICE_FNUM_FNUM_Msk (_U_(0x7FF) << USB_DEVICE_FNUM_FNUM_Pos)
-#define USB_DEVICE_FNUM_FNUM(value) (USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos))
-#define USB_DEVICE_FNUM_FNCERR_Pos 15 /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */
-#define USB_DEVICE_FNUM_FNCERR (_U_(0x1) << USB_DEVICE_FNUM_FNCERR_Pos)
-#define USB_DEVICE_FNUM_MASK _U_(0xBFFF) /**< \brief (USB_DEVICE_FNUM) MASK Register */
-
-/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
- uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} USB_HOST_FNUM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_FNUM_OFFSET 0x010 /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */
-#define USB_HOST_FNUM_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */
-
-#define USB_HOST_FNUM_MFNUM_Pos 0 /**< \brief (USB_HOST_FNUM) Micro Frame Number */
-#define USB_HOST_FNUM_MFNUM_Msk (_U_(0x7) << USB_HOST_FNUM_MFNUM_Pos)
-#define USB_HOST_FNUM_MFNUM(value) (USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos))
-#define USB_HOST_FNUM_FNUM_Pos 3 /**< \brief (USB_HOST_FNUM) Frame Number */
-#define USB_HOST_FNUM_FNUM_Msk (_U_(0x7FF) << USB_HOST_FNUM_FNUM_Pos)
-#define USB_HOST_FNUM_FNUM(value) (USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos))
-#define USB_HOST_FNUM_MASK _U_(0x3FFF) /**< \brief (USB_HOST_FNUM) MASK Register */
-
-/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} USB_HOST_FLENHIGH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_FLENHIGH_OFFSET 0x012 /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */
-#define USB_HOST_FLENHIGH_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */
-
-#define USB_HOST_FLENHIGH_FLENHIGH_Pos 0 /**< \brief (USB_HOST_FLENHIGH) Frame Length */
-#define USB_HOST_FLENHIGH_FLENHIGH_Msk (_U_(0xFF) << USB_HOST_FLENHIGH_FLENHIGH_Pos)
-#define USB_HOST_FLENHIGH_FLENHIGH(value) (USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos))
-#define USB_HOST_FLENHIGH_MASK _U_(0xFF) /**< \brief (USB_HOST_FLENHIGH) MASK Register */
-
-/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
- uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
- uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
- uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
- uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
- uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
- uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} USB_DEVICE_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_INTENCLR_OFFSET 0x014 /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */
-#define USB_DEVICE_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */
-
-#define USB_DEVICE_INTENCLR_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */
-#define USB_DEVICE_INTENCLR_SUSPEND (_U_(0x1) << USB_DEVICE_INTENCLR_SUSPEND_Pos)
-#define USB_DEVICE_INTENCLR_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */
-#define USB_DEVICE_INTENCLR_MSOF (_U_(0x1) << USB_DEVICE_INTENCLR_MSOF_Pos)
-#define USB_DEVICE_INTENCLR_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */
-#define USB_DEVICE_INTENCLR_SOF (_U_(0x1) << USB_DEVICE_INTENCLR_SOF_Pos)
-#define USB_DEVICE_INTENCLR_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */
-#define USB_DEVICE_INTENCLR_EORST (_U_(0x1) << USB_DEVICE_INTENCLR_EORST_Pos)
-#define USB_DEVICE_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */
-#define USB_DEVICE_INTENCLR_WAKEUP (_U_(0x1) << USB_DEVICE_INTENCLR_WAKEUP_Pos)
-#define USB_DEVICE_INTENCLR_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */
-#define USB_DEVICE_INTENCLR_EORSM (_U_(0x1) << USB_DEVICE_INTENCLR_EORSM_Pos)
-#define USB_DEVICE_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */
-#define USB_DEVICE_INTENCLR_UPRSM (_U_(0x1) << USB_DEVICE_INTENCLR_UPRSM_Pos)
-#define USB_DEVICE_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */
-#define USB_DEVICE_INTENCLR_RAMACER (_U_(0x1) << USB_DEVICE_INTENCLR_RAMACER_Pos)
-#define USB_DEVICE_INTENCLR_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */
-#define USB_DEVICE_INTENCLR_LPMNYET (_U_(0x1) << USB_DEVICE_INTENCLR_LPMNYET_Pos)
-#define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */
-#define USB_DEVICE_INTENCLR_LPMSUSP (_U_(0x1) << USB_DEVICE_INTENCLR_LPMSUSP_Pos)
-#define USB_DEVICE_INTENCLR_MASK _U_(0x03FF) /**< \brief (USB_DEVICE_INTENCLR) MASK Register */
-
-/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */
- uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */
- uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */
- uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */
- uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} USB_HOST_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_INTENCLR_OFFSET 0x014 /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */
-#define USB_HOST_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */
-
-#define USB_HOST_INTENCLR_HSOF_Pos 2 /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */
-#define USB_HOST_INTENCLR_HSOF (_U_(0x1) << USB_HOST_INTENCLR_HSOF_Pos)
-#define USB_HOST_INTENCLR_RST_Pos 3 /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */
-#define USB_HOST_INTENCLR_RST (_U_(0x1) << USB_HOST_INTENCLR_RST_Pos)
-#define USB_HOST_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */
-#define USB_HOST_INTENCLR_WAKEUP (_U_(0x1) << USB_HOST_INTENCLR_WAKEUP_Pos)
-#define USB_HOST_INTENCLR_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */
-#define USB_HOST_INTENCLR_DNRSM (_U_(0x1) << USB_HOST_INTENCLR_DNRSM_Pos)
-#define USB_HOST_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */
-#define USB_HOST_INTENCLR_UPRSM (_U_(0x1) << USB_HOST_INTENCLR_UPRSM_Pos)
-#define USB_HOST_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */
-#define USB_HOST_INTENCLR_RAMACER (_U_(0x1) << USB_HOST_INTENCLR_RAMACER_Pos)
-#define USB_HOST_INTENCLR_DCONN_Pos 8 /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */
-#define USB_HOST_INTENCLR_DCONN (_U_(0x1) << USB_HOST_INTENCLR_DCONN_Pos)
-#define USB_HOST_INTENCLR_DDISC_Pos 9 /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */
-#define USB_HOST_INTENCLR_DDISC (_U_(0x1) << USB_HOST_INTENCLR_DDISC_Pos)
-#define USB_HOST_INTENCLR_MASK _U_(0x03FC) /**< \brief (USB_HOST_INTENCLR) MASK Register */
-
-/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
- uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
- uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
- uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
- uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
- uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
- uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} USB_DEVICE_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_INTENSET_OFFSET 0x018 /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */
-#define USB_DEVICE_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */
-
-#define USB_DEVICE_INTENSET_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */
-#define USB_DEVICE_INTENSET_SUSPEND (_U_(0x1) << USB_DEVICE_INTENSET_SUSPEND_Pos)
-#define USB_DEVICE_INTENSET_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */
-#define USB_DEVICE_INTENSET_MSOF (_U_(0x1) << USB_DEVICE_INTENSET_MSOF_Pos)
-#define USB_DEVICE_INTENSET_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */
-#define USB_DEVICE_INTENSET_SOF (_U_(0x1) << USB_DEVICE_INTENSET_SOF_Pos)
-#define USB_DEVICE_INTENSET_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */
-#define USB_DEVICE_INTENSET_EORST (_U_(0x1) << USB_DEVICE_INTENSET_EORST_Pos)
-#define USB_DEVICE_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */
-#define USB_DEVICE_INTENSET_WAKEUP (_U_(0x1) << USB_DEVICE_INTENSET_WAKEUP_Pos)
-#define USB_DEVICE_INTENSET_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */
-#define USB_DEVICE_INTENSET_EORSM (_U_(0x1) << USB_DEVICE_INTENSET_EORSM_Pos)
-#define USB_DEVICE_INTENSET_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */
-#define USB_DEVICE_INTENSET_UPRSM (_U_(0x1) << USB_DEVICE_INTENSET_UPRSM_Pos)
-#define USB_DEVICE_INTENSET_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */
-#define USB_DEVICE_INTENSET_RAMACER (_U_(0x1) << USB_DEVICE_INTENSET_RAMACER_Pos)
-#define USB_DEVICE_INTENSET_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */
-#define USB_DEVICE_INTENSET_LPMNYET (_U_(0x1) << USB_DEVICE_INTENSET_LPMNYET_Pos)
-#define USB_DEVICE_INTENSET_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */
-#define USB_DEVICE_INTENSET_LPMSUSP (_U_(0x1) << USB_DEVICE_INTENSET_LPMSUSP_Pos)
-#define USB_DEVICE_INTENSET_MASK _U_(0x03FF) /**< \brief (USB_DEVICE_INTENSET) MASK Register */
-
-/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */
- uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
- uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
- uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */
- uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} USB_HOST_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_INTENSET_OFFSET 0x018 /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */
-#define USB_HOST_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */
-
-#define USB_HOST_INTENSET_HSOF_Pos 2 /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */
-#define USB_HOST_INTENSET_HSOF (_U_(0x1) << USB_HOST_INTENSET_HSOF_Pos)
-#define USB_HOST_INTENSET_RST_Pos 3 /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */
-#define USB_HOST_INTENSET_RST (_U_(0x1) << USB_HOST_INTENSET_RST_Pos)
-#define USB_HOST_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */
-#define USB_HOST_INTENSET_WAKEUP (_U_(0x1) << USB_HOST_INTENSET_WAKEUP_Pos)
-#define USB_HOST_INTENSET_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */
-#define USB_HOST_INTENSET_DNRSM (_U_(0x1) << USB_HOST_INTENSET_DNRSM_Pos)
-#define USB_HOST_INTENSET_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */
-#define USB_HOST_INTENSET_UPRSM (_U_(0x1) << USB_HOST_INTENSET_UPRSM_Pos)
-#define USB_HOST_INTENSET_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */
-#define USB_HOST_INTENSET_RAMACER (_U_(0x1) << USB_HOST_INTENSET_RAMACER_Pos)
-#define USB_HOST_INTENSET_DCONN_Pos 8 /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */
-#define USB_HOST_INTENSET_DCONN (_U_(0x1) << USB_HOST_INTENSET_DCONN_Pos)
-#define USB_HOST_INTENSET_DDISC_Pos 9 /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */
-#define USB_HOST_INTENSET_DDISC (_U_(0x1) << USB_HOST_INTENSET_DDISC_Pos)
-#define USB_HOST_INTENSET_MASK _U_(0x03FC) /**< \brief (USB_HOST_INTENSET) MASK Register */
-
-/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
- __I uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
- __I uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
- __I uint16_t EORST:1; /*!< bit: 3 End of Reset */
- __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
- __I uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
- __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
- __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
- __I uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
- __I uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
- __I uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} USB_DEVICE_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_INTFLAG_OFFSET 0x01C /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */
-#define USB_DEVICE_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */
-
-#define USB_DEVICE_INTFLAG_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTFLAG) Suspend */
-#define USB_DEVICE_INTFLAG_SUSPEND (_U_(0x1) << USB_DEVICE_INTFLAG_SUSPEND_Pos)
-#define USB_DEVICE_INTFLAG_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */
-#define USB_DEVICE_INTFLAG_MSOF (_U_(0x1) << USB_DEVICE_INTFLAG_MSOF_Pos)
-#define USB_DEVICE_INTFLAG_SOF_Pos 2 /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */
-#define USB_DEVICE_INTFLAG_SOF (_U_(0x1) << USB_DEVICE_INTFLAG_SOF_Pos)
-#define USB_DEVICE_INTFLAG_EORST_Pos 3 /**< \brief (USB_DEVICE_INTFLAG) End of Reset */
-#define USB_DEVICE_INTFLAG_EORST (_U_(0x1) << USB_DEVICE_INTFLAG_EORST_Pos)
-#define USB_DEVICE_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTFLAG) Wake Up */
-#define USB_DEVICE_INTFLAG_WAKEUP (_U_(0x1) << USB_DEVICE_INTFLAG_WAKEUP_Pos)
-#define USB_DEVICE_INTFLAG_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */
-#define USB_DEVICE_INTFLAG_EORSM (_U_(0x1) << USB_DEVICE_INTFLAG_EORSM_Pos)
-#define USB_DEVICE_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */
-#define USB_DEVICE_INTFLAG_UPRSM (_U_(0x1) << USB_DEVICE_INTFLAG_UPRSM_Pos)
-#define USB_DEVICE_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTFLAG) Ram Access */
-#define USB_DEVICE_INTFLAG_RAMACER (_U_(0x1) << USB_DEVICE_INTFLAG_RAMACER_Pos)
-#define USB_DEVICE_INTFLAG_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */
-#define USB_DEVICE_INTFLAG_LPMNYET (_U_(0x1) << USB_DEVICE_INTFLAG_LPMNYET_Pos)
-#define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */
-#define USB_DEVICE_INTFLAG_LPMSUSP (_U_(0x1) << USB_DEVICE_INTFLAG_LPMSUSP_Pos)
-#define USB_DEVICE_INTFLAG_MASK _U_(0x03FF) /**< \brief (USB_DEVICE_INTFLAG) MASK Register */
-
-/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint16_t :2; /*!< bit: 0.. 1 Reserved */
- __I uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
- __I uint16_t RST:1; /*!< bit: 3 Bus Reset */
- __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
- __I uint16_t DNRSM:1; /*!< bit: 5 Downstream */
- __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
- __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
- __I uint16_t DCONN:1; /*!< bit: 8 Device Connection */
- __I uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
- __I uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} USB_HOST_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_INTFLAG_OFFSET 0x01C /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */
-#define USB_HOST_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */
-
-#define USB_HOST_INTFLAG_HSOF_Pos 2 /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */
-#define USB_HOST_INTFLAG_HSOF (_U_(0x1) << USB_HOST_INTFLAG_HSOF_Pos)
-#define USB_HOST_INTFLAG_RST_Pos 3 /**< \brief (USB_HOST_INTFLAG) Bus Reset */
-#define USB_HOST_INTFLAG_RST (_U_(0x1) << USB_HOST_INTFLAG_RST_Pos)
-#define USB_HOST_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTFLAG) Wake Up */
-#define USB_HOST_INTFLAG_WAKEUP (_U_(0x1) << USB_HOST_INTFLAG_WAKEUP_Pos)
-#define USB_HOST_INTFLAG_DNRSM_Pos 5 /**< \brief (USB_HOST_INTFLAG) Downstream */
-#define USB_HOST_INTFLAG_DNRSM (_U_(0x1) << USB_HOST_INTFLAG_DNRSM_Pos)
-#define USB_HOST_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */
-#define USB_HOST_INTFLAG_UPRSM (_U_(0x1) << USB_HOST_INTFLAG_UPRSM_Pos)
-#define USB_HOST_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_HOST_INTFLAG) Ram Access */
-#define USB_HOST_INTFLAG_RAMACER (_U_(0x1) << USB_HOST_INTFLAG_RAMACER_Pos)
-#define USB_HOST_INTFLAG_DCONN_Pos 8 /**< \brief (USB_HOST_INTFLAG) Device Connection */
-#define USB_HOST_INTFLAG_DCONN (_U_(0x1) << USB_HOST_INTFLAG_DCONN_Pos)
-#define USB_HOST_INTFLAG_DDISC_Pos 9 /**< \brief (USB_HOST_INTFLAG) Device Disconnection */
-#define USB_HOST_INTFLAG_DDISC (_U_(0x1) << USB_HOST_INTFLAG_DDISC_Pos)
-#define USB_HOST_INTFLAG_MASK _U_(0x03FC) /**< \brief (USB_HOST_INTFLAG) MASK Register */
-
-/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */
- uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */
- uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */
- uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */
- uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */
- uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */
- uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */
- uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} USB_DEVICE_EPINTSMRY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPINTSMRY_OFFSET 0x020 /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */
-#define USB_DEVICE_EPINTSMRY_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */
-
-#define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT0 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT0_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT1 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT1_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT2 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT2_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT3 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT3_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT4 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT4_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT5 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT5_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT6 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT6_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT7 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT7_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT_Msk (_U_(0xFF) << USB_DEVICE_EPINTSMRY_EPINT_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT(value) (USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos))
-#define USB_DEVICE_EPINTSMRY_MASK _U_(0x00FF) /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */
-
-/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */
- uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */
- uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */
- uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */
- uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */
- uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */
- uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */
- uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} USB_HOST_PINTSMRY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PINTSMRY_OFFSET 0x020 /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */
-#define USB_HOST_PINTSMRY_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */
-
-#define USB_HOST_PINTSMRY_EPINT0_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT0 (_U_(1) << USB_HOST_PINTSMRY_EPINT0_Pos)
-#define USB_HOST_PINTSMRY_EPINT1_Pos 1 /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT1 (_U_(1) << USB_HOST_PINTSMRY_EPINT1_Pos)
-#define USB_HOST_PINTSMRY_EPINT2_Pos 2 /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT2 (_U_(1) << USB_HOST_PINTSMRY_EPINT2_Pos)
-#define USB_HOST_PINTSMRY_EPINT3_Pos 3 /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT3 (_U_(1) << USB_HOST_PINTSMRY_EPINT3_Pos)
-#define USB_HOST_PINTSMRY_EPINT4_Pos 4 /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT4 (_U_(1) << USB_HOST_PINTSMRY_EPINT4_Pos)
-#define USB_HOST_PINTSMRY_EPINT5_Pos 5 /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT5 (_U_(1) << USB_HOST_PINTSMRY_EPINT5_Pos)
-#define USB_HOST_PINTSMRY_EPINT6_Pos 6 /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT6 (_U_(1) << USB_HOST_PINTSMRY_EPINT6_Pos)
-#define USB_HOST_PINTSMRY_EPINT7_Pos 7 /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT7 (_U_(1) << USB_HOST_PINTSMRY_EPINT7_Pos)
-#define USB_HOST_PINTSMRY_EPINT_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */
-#define USB_HOST_PINTSMRY_EPINT_Msk (_U_(0xFF) << USB_HOST_PINTSMRY_EPINT_Pos)
-#define USB_HOST_PINTSMRY_EPINT(value) (USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos))
-#define USB_HOST_PINTSMRY_MASK _U_(0x00FF) /**< \brief (USB_HOST_PINTSMRY) MASK Register */
-
-/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} USB_DESCADD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DESCADD_OFFSET 0x024 /**< \brief (USB_DESCADD offset) Descriptor Address */
-#define USB_DESCADD_RESETVALUE _U_(0x00000000) /**< \brief (USB_DESCADD reset_value) Descriptor Address */
-
-#define USB_DESCADD_DESCADD_Pos 0 /**< \brief (USB_DESCADD) Descriptor Address Value */
-#define USB_DESCADD_DESCADD_Msk (_U_(0xFFFFFFFF) << USB_DESCADD_DESCADD_Pos)
-#define USB_DESCADD_DESCADD(value) (USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos))
-#define USB_DESCADD_MASK _U_(0xFFFFFFFF) /**< \brief (USB_DESCADD) MASK Register */
-
-/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */
- uint16_t :1; /*!< bit: 5 Reserved */
- uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */
- uint16_t :1; /*!< bit: 11 Reserved */
- uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} USB_PADCAL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_PADCAL_OFFSET 0x028 /**< \brief (USB_PADCAL offset) USB PAD Calibration */
-#define USB_PADCAL_RESETVALUE _U_(0x0000) /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */
-
-#define USB_PADCAL_TRANSP_Pos 0 /**< \brief (USB_PADCAL) USB Pad Transp calibration */
-#define USB_PADCAL_TRANSP_Msk (_U_(0x1F) << USB_PADCAL_TRANSP_Pos)
-#define USB_PADCAL_TRANSP(value) (USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos))
-#define USB_PADCAL_TRANSN_Pos 6 /**< \brief (USB_PADCAL) USB Pad Transn calibration */
-#define USB_PADCAL_TRANSN_Msk (_U_(0x1F) << USB_PADCAL_TRANSN_Pos)
-#define USB_PADCAL_TRANSN(value) (USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos))
-#define USB_PADCAL_TRIM_Pos 12 /**< \brief (USB_PADCAL) USB Pad Trim calibration */
-#define USB_PADCAL_TRIM_Msk (_U_(0x7) << USB_PADCAL_TRIM_Pos)
-#define USB_PADCAL_TRIM(value) (USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos))
-#define USB_PADCAL_MASK _U_(0x77DF) /**< \brief (USB_PADCAL) MASK Register */
-
-/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */
- uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} USB_DEVICE_EPCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPCFG_OFFSET 0x100 /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */
-#define USB_DEVICE_EPCFG_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */
-
-#define USB_DEVICE_EPCFG_EPTYPE0_Pos 0 /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */
-#define USB_DEVICE_EPCFG_EPTYPE0_Msk (_U_(0x7) << USB_DEVICE_EPCFG_EPTYPE0_Pos)
-#define USB_DEVICE_EPCFG_EPTYPE0(value) (USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos))
-#define USB_DEVICE_EPCFG_EPTYPE1_Pos 4 /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */
-#define USB_DEVICE_EPCFG_EPTYPE1_Msk (_U_(0x7) << USB_DEVICE_EPCFG_EPTYPE1_Pos)
-#define USB_DEVICE_EPCFG_EPTYPE1(value) (USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos))
-#define USB_DEVICE_EPCFG_NYETDIS_Pos 7 /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */
-#define USB_DEVICE_EPCFG_NYETDIS (_U_(0x1) << USB_DEVICE_EPCFG_NYETDIS_Pos)
-#define USB_DEVICE_EPCFG_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPCFG) MASK Register */
-
-/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */
- uint8_t BK:1; /*!< bit: 2 Pipe Bank */
- uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} USB_HOST_PCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PCFG_OFFSET 0x100 /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */
-#define USB_HOST_PCFG_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */
-
-#define USB_HOST_PCFG_PTOKEN_Pos 0 /**< \brief (USB_HOST_PCFG) Pipe Token */
-#define USB_HOST_PCFG_PTOKEN_Msk (_U_(0x3) << USB_HOST_PCFG_PTOKEN_Pos)
-#define USB_HOST_PCFG_PTOKEN(value) (USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos))
-#define USB_HOST_PCFG_BK_Pos 2 /**< \brief (USB_HOST_PCFG) Pipe Bank */
-#define USB_HOST_PCFG_BK (_U_(0x1) << USB_HOST_PCFG_BK_Pos)
-#define USB_HOST_PCFG_PTYPE_Pos 3 /**< \brief (USB_HOST_PCFG) Pipe Type */
-#define USB_HOST_PCFG_PTYPE_Msk (_U_(0x7) << USB_HOST_PCFG_PTYPE_Pos)
-#define USB_HOST_PCFG_PTYPE(value) (USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos))
-#define USB_HOST_PCFG_MASK _U_(0x3F) /**< \brief (USB_HOST_PCFG) MASK Register */
-
-/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} USB_HOST_BINTERVAL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_BINTERVAL_OFFSET 0x103 /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */
-#define USB_HOST_BINTERVAL_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */
-
-#define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0 /**< \brief (USB_HOST_BINTERVAL) Bit Interval */
-#define USB_HOST_BINTERVAL_BITINTERVAL_Msk (_U_(0xFF) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)
-#define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos))
-#define USB_HOST_BINTERVAL_MASK _U_(0xFF) /**< \brief (USB_HOST_BINTERVAL) MASK Register */
-
-/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */
- uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank Clear */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */
- uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} USB_DEVICE_EPSTATUSCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104 /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */
-#define USB_DEVICE_EPSTATUSCLR_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */
-
-#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */
-#define USB_DEVICE_EPSTATUSCLR_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos)
-#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */
-#define USB_DEVICE_EPSTATUSCLR_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)
-#define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSCLR) Current Bank Clear */
-#define USB_DEVICE_EPSTATUSCLR_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos)
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos))
-#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */
-#define USB_DEVICE_EPSTATUSCLR_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)
-#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */
-#define USB_DEVICE_EPSTATUSCLR_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)
-#define USB_DEVICE_EPSTATUSCLR_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */
-
-/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */
- uint8_t :1; /*!< bit: 5 Reserved */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} USB_HOST_PSTATUSCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PSTATUSCLR_OFFSET 0x104 /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */
-#define USB_HOST_PSTATUSCLR_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */
-
-#define USB_HOST_PSTATUSCLR_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */
-#define USB_HOST_PSTATUSCLR_DTGL (_U_(0x1) << USB_HOST_PSTATUSCLR_DTGL_Pos)
-#define USB_HOST_PSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */
-#define USB_HOST_PSTATUSCLR_CURBK (_U_(0x1) << USB_HOST_PSTATUSCLR_CURBK_Pos)
-#define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */
-#define USB_HOST_PSTATUSCLR_PFREEZE (_U_(0x1) << USB_HOST_PSTATUSCLR_PFREEZE_Pos)
-#define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */
-#define USB_HOST_PSTATUSCLR_BK0RDY (_U_(0x1) << USB_HOST_PSTATUSCLR_BK0RDY_Pos)
-#define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */
-#define USB_HOST_PSTATUSCLR_BK1RDY (_U_(0x1) << USB_HOST_PSTATUSCLR_BK1RDY_Pos)
-#define USB_HOST_PSTATUSCLR_MASK _U_(0xD5) /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */
-
-/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */
- uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */
- uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} USB_DEVICE_EPSTATUSSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPSTATUSSET_OFFSET 0x105 /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */
-#define USB_DEVICE_EPSTATUSSET_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */
-
-#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */
-#define USB_DEVICE_EPSTATUSSET_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos)
-#define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */
-#define USB_DEVICE_EPSTATUSSET_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)
-#define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */
-#define USB_DEVICE_EPSTATUSSET_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUSSET_CURBK_Pos)
-#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */
-#define USB_DEVICE_EPSTATUSSET_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos)
-#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */
-#define USB_DEVICE_EPSTATUSSET_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)
-#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */
-#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)
-#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos))
-#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */
-#define USB_DEVICE_EPSTATUSSET_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)
-#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */
-#define USB_DEVICE_EPSTATUSSET_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)
-#define USB_DEVICE_EPSTATUSSET_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */
-
-/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */
- uint8_t :1; /*!< bit: 5 Reserved */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} USB_HOST_PSTATUSSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PSTATUSSET_OFFSET 0x105 /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */
-#define USB_HOST_PSTATUSSET_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */
-
-#define USB_HOST_PSTATUSSET_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */
-#define USB_HOST_PSTATUSSET_DTGL (_U_(0x1) << USB_HOST_PSTATUSSET_DTGL_Pos)
-#define USB_HOST_PSTATUSSET_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */
-#define USB_HOST_PSTATUSSET_CURBK (_U_(0x1) << USB_HOST_PSTATUSSET_CURBK_Pos)
-#define USB_HOST_PSTATUSSET_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */
-#define USB_HOST_PSTATUSSET_PFREEZE (_U_(0x1) << USB_HOST_PSTATUSSET_PFREEZE_Pos)
-#define USB_HOST_PSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */
-#define USB_HOST_PSTATUSSET_BK0RDY (_U_(0x1) << USB_HOST_PSTATUSSET_BK0RDY_Pos)
-#define USB_HOST_PSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */
-#define USB_HOST_PSTATUSSET_BK1RDY (_U_(0x1) << USB_HOST_PSTATUSSET_BK1RDY_Pos)
-#define USB_HOST_PSTATUSSET_MASK _U_(0xD5) /**< \brief (USB_HOST_PSTATUSSET) MASK Register */
-
-/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */
- uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */
- uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} USB_DEVICE_EPSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPSTATUS_OFFSET 0x106 /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */
-#define USB_DEVICE_EPSTATUS_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */
-
-#define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */
-#define USB_DEVICE_EPSTATUS_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)
-#define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */
-#define USB_DEVICE_EPSTATUS_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUS_DTGLIN_Pos)
-#define USB_DEVICE_EPSTATUS_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */
-#define USB_DEVICE_EPSTATUS_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUS_CURBK_Pos)
-#define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */
-#define USB_DEVICE_EPSTATUS_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)
-#define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */
-#define USB_DEVICE_EPSTATUS_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)
-#define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */
-#define USB_DEVICE_EPSTATUS_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)
-#define USB_DEVICE_EPSTATUS_STALLRQ(value) (USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos))
-#define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */
-#define USB_DEVICE_EPSTATUS_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUS_BK0RDY_Pos)
-#define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */
-#define USB_DEVICE_EPSTATUS_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUS_BK1RDY_Pos)
-#define USB_DEVICE_EPSTATUS_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */
-
-/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DTGL:1; /*!< bit: 0 Data Toggle */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */
- uint8_t :1; /*!< bit: 5 Reserved */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} USB_HOST_PSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PSTATUS_OFFSET 0x106 /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */
-#define USB_HOST_PSTATUS_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */
-
-#define USB_HOST_PSTATUS_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUS) Data Toggle */
-#define USB_HOST_PSTATUS_DTGL (_U_(0x1) << USB_HOST_PSTATUS_DTGL_Pos)
-#define USB_HOST_PSTATUS_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUS) Current Bank */
-#define USB_HOST_PSTATUS_CURBK (_U_(0x1) << USB_HOST_PSTATUS_CURBK_Pos)
-#define USB_HOST_PSTATUS_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */
-#define USB_HOST_PSTATUS_PFREEZE (_U_(0x1) << USB_HOST_PSTATUS_PFREEZE_Pos)
-#define USB_HOST_PSTATUS_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */
-#define USB_HOST_PSTATUS_BK0RDY (_U_(0x1) << USB_HOST_PSTATUS_BK0RDY_Pos)
-#define USB_HOST_PSTATUS_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */
-#define USB_HOST_PSTATUS_BK1RDY (_U_(0x1) << USB_HOST_PSTATUS_BK1RDY_Pos)
-#define USB_HOST_PSTATUS_MASK _U_(0xD5) /**< \brief (USB_HOST_PSTATUS) MASK Register */
-
-/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
- __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
- __I uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
- __I uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
- __I uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
- __I uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
- __I uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
- __I uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
- __I uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
- __I uint8_t :1; /*!< bit: 4 Reserved */
- __I uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
- __I uint8_t :1; /*!< bit: 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} USB_DEVICE_EPINTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPINTFLAG_OFFSET 0x107 /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */
-#define USB_DEVICE_EPINTFLAG_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */
-
-#define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */
-#define USB_DEVICE_EPINTFLAG_TRCPT0 (_U_(1) << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)
-#define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */
-#define USB_DEVICE_EPINTFLAG_TRCPT1 (_U_(1) << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)
-#define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */
-#define USB_DEVICE_EPINTFLAG_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)
-#define USB_DEVICE_EPINTFLAG_TRCPT(value) (USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos))
-#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */
-#define USB_DEVICE_EPINTFLAG_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)
-#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */
-#define USB_DEVICE_EPINTFLAG_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)
-#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */
-#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)
-#define USB_DEVICE_EPINTFLAG_TRFAIL(value) (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos))
-#define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */
-#define USB_DEVICE_EPINTFLAG_RXSTP (_U_(0x1) << USB_DEVICE_EPINTFLAG_RXSTP_Pos)
-#define USB_DEVICE_EPINTFLAG_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */
-#define USB_DEVICE_EPINTFLAG_STALL0 (_U_(1) << USB_DEVICE_EPINTFLAG_STALL0_Pos)
-#define USB_DEVICE_EPINTFLAG_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */
-#define USB_DEVICE_EPINTFLAG_STALL1 (_U_(1) << USB_DEVICE_EPINTFLAG_STALL1_Pos)
-#define USB_DEVICE_EPINTFLAG_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */
-#define USB_DEVICE_EPINTFLAG_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_STALL_Pos)
-#define USB_DEVICE_EPINTFLAG_STALL(value) (USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos))
-#define USB_DEVICE_EPINTFLAG_MASK _U_(0x7F) /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */
-
-/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
- __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
- __I uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
- __I uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
- __I uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
- __I uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
- __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
- __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} USB_HOST_PINTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PINTFLAG_OFFSET 0x107 /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */
-#define USB_HOST_PINTFLAG_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */
-
-#define USB_HOST_PINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */
-#define USB_HOST_PINTFLAG_TRCPT0 (_U_(1) << USB_HOST_PINTFLAG_TRCPT0_Pos)
-#define USB_HOST_PINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */
-#define USB_HOST_PINTFLAG_TRCPT1 (_U_(1) << USB_HOST_PINTFLAG_TRCPT1_Pos)
-#define USB_HOST_PINTFLAG_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */
-#define USB_HOST_PINTFLAG_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTFLAG_TRCPT_Pos)
-#define USB_HOST_PINTFLAG_TRCPT(value) (USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos))
-#define USB_HOST_PINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */
-#define USB_HOST_PINTFLAG_TRFAIL (_U_(0x1) << USB_HOST_PINTFLAG_TRFAIL_Pos)
-#define USB_HOST_PINTFLAG_PERR_Pos 3 /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */
-#define USB_HOST_PINTFLAG_PERR (_U_(0x1) << USB_HOST_PINTFLAG_PERR_Pos)
-#define USB_HOST_PINTFLAG_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag */
-#define USB_HOST_PINTFLAG_TXSTP (_U_(0x1) << USB_HOST_PINTFLAG_TXSTP_Pos)
-#define USB_HOST_PINTFLAG_STALL_Pos 5 /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */
-#define USB_HOST_PINTFLAG_STALL (_U_(0x1) << USB_HOST_PINTFLAG_STALL_Pos)
-#define USB_HOST_PINTFLAG_MASK _U_(0x3F) /**< \brief (USB_HOST_PINTFLAG) MASK Register */
-
-/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */
- uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */
- uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */
- uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */
- uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */
- uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */
- uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */
- uint8_t :1; /*!< bit: 4 Reserved */
- uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} USB_DEVICE_EPINTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPINTENCLR_OFFSET 0x108 /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
-#define USB_DEVICE_EPINTENCLR_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
-
-#define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_TRCPT0 (_U_(1) << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)
-#define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_TRCPT1 (_U_(1) << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)
-#define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)
-#define USB_DEVICE_EPINTENCLR_TRCPT(value) (USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos))
-#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)
-#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)
-#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)
-#define USB_DEVICE_EPINTENCLR_TRFAIL(value) (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos))
-#define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_RXSTP (_U_(0x1) << USB_DEVICE_EPINTENCLR_RXSTP_Pos)
-#define USB_DEVICE_EPINTENCLR_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_STALL0 (_U_(1) << USB_DEVICE_EPINTENCLR_STALL0_Pos)
-#define USB_DEVICE_EPINTENCLR_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_STALL1 (_U_(1) << USB_DEVICE_EPINTENCLR_STALL1_Pos)
-#define USB_DEVICE_EPINTENCLR_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_STALL_Pos)
-#define USB_DEVICE_EPINTENCLR_STALL(value) (USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos))
-#define USB_DEVICE_EPINTENCLR_MASK _U_(0x7F) /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */
-
-/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */
- uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */
- uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */
- uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */
- uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} USB_HOST_PINTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PINTENCLR_OFFSET 0x108 /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */
-#define USB_HOST_PINTENCLR_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */
-
-#define USB_HOST_PINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */
-#define USB_HOST_PINTENCLR_TRCPT0 (_U_(1) << USB_HOST_PINTENCLR_TRCPT0_Pos)
-#define USB_HOST_PINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */
-#define USB_HOST_PINTENCLR_TRCPT1 (_U_(1) << USB_HOST_PINTENCLR_TRCPT1_Pos)
-#define USB_HOST_PINTENCLR_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */
-#define USB_HOST_PINTENCLR_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTENCLR_TRCPT_Pos)
-#define USB_HOST_PINTENCLR_TRCPT(value) (USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos))
-#define USB_HOST_PINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */
-#define USB_HOST_PINTENCLR_TRFAIL (_U_(0x1) << USB_HOST_PINTENCLR_TRFAIL_Pos)
-#define USB_HOST_PINTENCLR_PERR_Pos 3 /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */
-#define USB_HOST_PINTENCLR_PERR (_U_(0x1) << USB_HOST_PINTENCLR_PERR_Pos)
-#define USB_HOST_PINTENCLR_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */
-#define USB_HOST_PINTENCLR_TXSTP (_U_(0x1) << USB_HOST_PINTENCLR_TXSTP_Pos)
-#define USB_HOST_PINTENCLR_STALL_Pos 5 /**< \brief (USB_HOST_PINTENCLR) Stall Inetrrupt Disable */
-#define USB_HOST_PINTENCLR_STALL (_U_(0x1) << USB_HOST_PINTENCLR_STALL_Pos)
-#define USB_HOST_PINTENCLR_MASK _U_(0x3F) /**< \brief (USB_HOST_PINTENCLR) MASK Register */
-
-/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
- uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */
- uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */
- uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */
- uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */
- uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
- uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */
- uint8_t :1; /*!< bit: 4 Reserved */
- uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} USB_DEVICE_EPINTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPINTENSET_OFFSET 0x109 /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */
-#define USB_DEVICE_EPINTENSET_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */
-
-#define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_TRCPT0 (_U_(1) << USB_DEVICE_EPINTENSET_TRCPT0_Pos)
-#define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_TRCPT1 (_U_(1) << USB_DEVICE_EPINTENSET_TRCPT1_Pos)
-#define USB_DEVICE_EPINTENSET_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_TRCPT_Pos)
-#define USB_DEVICE_EPINTENSET_TRCPT(value) (USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos))
-#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)
-#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)
-#define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)
-#define USB_DEVICE_EPINTENSET_TRFAIL(value) (USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos))
-#define USB_DEVICE_EPINTENSET_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_RXSTP (_U_(0x1) << USB_DEVICE_EPINTENSET_RXSTP_Pos)
-#define USB_DEVICE_EPINTENSET_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */
-#define USB_DEVICE_EPINTENSET_STALL0 (_U_(1) << USB_DEVICE_EPINTENSET_STALL0_Pos)
-#define USB_DEVICE_EPINTENSET_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */
-#define USB_DEVICE_EPINTENSET_STALL1 (_U_(1) << USB_DEVICE_EPINTENSET_STALL1_Pos)
-#define USB_DEVICE_EPINTENSET_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */
-#define USB_DEVICE_EPINTENSET_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_STALL_Pos)
-#define USB_DEVICE_EPINTENSET_STALL(value) (USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos))
-#define USB_DEVICE_EPINTENSET_MASK _U_(0x7F) /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */
-
-/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
- uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */
- uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */
- uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */
- uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} USB_HOST_PINTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PINTENSET_OFFSET 0x109 /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */
-#define USB_HOST_PINTENSET_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */
-
-#define USB_HOST_PINTENSET_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */
-#define USB_HOST_PINTENSET_TRCPT0 (_U_(1) << USB_HOST_PINTENSET_TRCPT0_Pos)
-#define USB_HOST_PINTENSET_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */
-#define USB_HOST_PINTENSET_TRCPT1 (_U_(1) << USB_HOST_PINTENSET_TRCPT1_Pos)
-#define USB_HOST_PINTENSET_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */
-#define USB_HOST_PINTENSET_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTENSET_TRCPT_Pos)
-#define USB_HOST_PINTENSET_TRCPT(value) (USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos))
-#define USB_HOST_PINTENSET_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */
-#define USB_HOST_PINTENSET_TRFAIL (_U_(0x1) << USB_HOST_PINTENSET_TRFAIL_Pos)
-#define USB_HOST_PINTENSET_PERR_Pos 3 /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */
-#define USB_HOST_PINTENSET_PERR (_U_(0x1) << USB_HOST_PINTENSET_PERR_Pos)
-#define USB_HOST_PINTENSET_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable */
-#define USB_HOST_PINTENSET_TXSTP (_U_(0x1) << USB_HOST_PINTENSET_TXSTP_Pos)
-#define USB_HOST_PINTENSET_STALL_Pos 5 /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */
-#define USB_HOST_PINTENSET_STALL (_U_(0x1) << USB_HOST_PINTENSET_STALL_Pos)
-#define USB_HOST_PINTENSET_MASK _U_(0x3F) /**< \brief (USB_HOST_PINTENSET) MASK Register */
-
-/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} USB_DEVICE_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_ADDR_OFFSET 0x000 /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
-
-#define USB_DEVICE_ADDR_ADDR_Pos 0 /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */
-#define USB_DEVICE_ADDR_ADDR_Msk (_U_(0xFFFFFFFF) << USB_DEVICE_ADDR_ADDR_Pos)
-#define USB_DEVICE_ADDR_ADDR(value) (USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos))
-#define USB_DEVICE_ADDR_MASK _U_(0xFFFFFFFF) /**< \brief (USB_DEVICE_ADDR) MASK Register */
-
-/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} USB_HOST_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_ADDR_OFFSET 0x000 /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
-
-#define USB_HOST_ADDR_ADDR_Pos 0 /**< \brief (USB_HOST_ADDR) Adress of data buffer */
-#define USB_HOST_ADDR_ADDR_Msk (_U_(0xFFFFFFFF) << USB_HOST_ADDR_ADDR_Pos)
-#define USB_HOST_ADDR_ADDR(value) (USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos))
-#define USB_HOST_ADDR_MASK _U_(0xFFFFFFFF) /**< \brief (USB_HOST_ADDR) MASK Register */
-
-/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
- uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
- uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */
- uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} USB_DEVICE_PCKSIZE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_PCKSIZE_OFFSET 0x004 /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
-
-#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */
-#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (_U_(0x3FFF) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)
-#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos))
-#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */
-#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U_(0x3FFF) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)
-#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos))
-#define USB_DEVICE_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */
-#define USB_DEVICE_PCKSIZE_SIZE_Msk (_U_(0x7) << USB_DEVICE_PCKSIZE_SIZE_Pos)
-#define USB_DEVICE_PCKSIZE_SIZE(value) (USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos))
-#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */
-#define USB_DEVICE_PCKSIZE_AUTO_ZLP (_U_(0x1) << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)
-#define USB_DEVICE_PCKSIZE_MASK _U_(0xFFFFFFFF) /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */
-
-/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
- uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
- uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */
- uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} USB_HOST_PCKSIZE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PCKSIZE_OFFSET 0x004 /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */
-
-#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_HOST_PCKSIZE) Byte Count */
-#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (_U_(0x3FFF) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)
-#define USB_HOST_PCKSIZE_BYTE_COUNT(value) (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos))
-#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */
-#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U_(0x3FFF) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)
-#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos))
-#define USB_HOST_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_HOST_PCKSIZE) Pipe size */
-#define USB_HOST_PCKSIZE_SIZE_Msk (_U_(0x7) << USB_HOST_PCKSIZE_SIZE_Pos)
-#define USB_HOST_PCKSIZE_SIZE(value) (USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos))
-#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */
-#define USB_HOST_PCKSIZE_AUTO_ZLP (_U_(0x1) << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)
-#define USB_HOST_PCKSIZE_MASK _U_(0xFFFFFFFF) /**< \brief (USB_HOST_PCKSIZE) MASK Register */
-
-/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
- uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} USB_DEVICE_EXTREG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EXTREG_OFFSET 0x008 /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */
-
-#define USB_DEVICE_EXTREG_SUBPID_Pos 0 /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */
-#define USB_DEVICE_EXTREG_SUBPID_Msk (_U_(0xF) << USB_DEVICE_EXTREG_SUBPID_Pos)
-#define USB_DEVICE_EXTREG_SUBPID(value) (USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos))
-#define USB_DEVICE_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */
-#define USB_DEVICE_EXTREG_VARIABLE_Msk (_U_(0x7FF) << USB_DEVICE_EXTREG_VARIABLE_Pos)
-#define USB_DEVICE_EXTREG_VARIABLE(value) (USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos))
-#define USB_DEVICE_EXTREG_MASK _U_(0x7FFF) /**< \brief (USB_DEVICE_EXTREG) MASK Register */
-
-/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
- uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} USB_HOST_EXTREG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_EXTREG_OFFSET 0x008 /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */
-
-#define USB_HOST_EXTREG_SUBPID_Pos 0 /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */
-#define USB_HOST_EXTREG_SUBPID_Msk (_U_(0xF) << USB_HOST_EXTREG_SUBPID_Pos)
-#define USB_HOST_EXTREG_SUBPID(value) (USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos))
-#define USB_HOST_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */
-#define USB_HOST_EXTREG_VARIABLE_Msk (_U_(0x7FF) << USB_HOST_EXTREG_VARIABLE_Pos)
-#define USB_HOST_EXTREG_VARIABLE(value) (USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos))
-#define USB_HOST_EXTREG_MASK _U_(0x7FFF) /**< \brief (USB_HOST_EXTREG) MASK Register */
-
-/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
- uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} USB_DEVICE_STATUS_BK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_STATUS_BK_OFFSET 0x00A /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
-
-#define USB_DEVICE_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */
-#define USB_DEVICE_STATUS_BK_CRCERR (_U_(0x1) << USB_DEVICE_STATUS_BK_CRCERR_Pos)
-#define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */
-#define USB_DEVICE_STATUS_BK_ERRORFLOW (_U_(0x1) << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos)
-#define USB_DEVICE_STATUS_BK_MASK _U_(0x03) /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */
-
-/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
- uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} USB_HOST_STATUS_BK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_STATUS_BK_OFFSET 0x00A /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */
-
-#define USB_HOST_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */
-#define USB_HOST_STATUS_BK_CRCERR (_U_(0x1) << USB_HOST_STATUS_BK_CRCERR_Pos)
-#define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */
-#define USB_HOST_STATUS_BK_ERRORFLOW (_U_(0x1) << USB_HOST_STATUS_BK_ERRORFLOW_Pos)
-#define USB_HOST_STATUS_BK_MASK _U_(0x03) /**< \brief (USB_HOST_STATUS_BK) MASK Register */
-
-/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */
- uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} USB_HOST_CTRL_PIPE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_CTRL_PIPE_OFFSET 0x00C /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */
-#define USB_HOST_CTRL_PIPE_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */
-
-#define USB_HOST_CTRL_PIPE_PDADDR_Pos 0 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */
-#define USB_HOST_CTRL_PIPE_PDADDR_Msk (_U_(0x7F) << USB_HOST_CTRL_PIPE_PDADDR_Pos)
-#define USB_HOST_CTRL_PIPE_PDADDR(value) (USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos))
-#define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */
-#define USB_HOST_CTRL_PIPE_PEPNUM_Msk (_U_(0xF) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)
-#define USB_HOST_CTRL_PIPE_PEPNUM(value) (USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos))
-#define USB_HOST_CTRL_PIPE_PERMAX_Pos 12 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */
-#define USB_HOST_CTRL_PIPE_PERMAX_Msk (_U_(0xF) << USB_HOST_CTRL_PIPE_PERMAX_Pos)
-#define USB_HOST_CTRL_PIPE_PERMAX(value) (USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos))
-#define USB_HOST_CTRL_PIPE_MASK _U_(0xFF7F) /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */
-
-/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */
- uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */
- uint16_t PIDER:1; /*!< bit: 2 PID Error */
- uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */
- uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */
- uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} USB_HOST_STATUS_PIPE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_STATUS_PIPE_OFFSET 0x00E /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */
-
-#define USB_HOST_STATUS_PIPE_DTGLER_Pos 0 /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */
-#define USB_HOST_STATUS_PIPE_DTGLER (_U_(0x1) << USB_HOST_STATUS_PIPE_DTGLER_Pos)
-#define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1 /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */
-#define USB_HOST_STATUS_PIPE_DAPIDER (_U_(0x1) << USB_HOST_STATUS_PIPE_DAPIDER_Pos)
-#define USB_HOST_STATUS_PIPE_PIDER_Pos 2 /**< \brief (USB_HOST_STATUS_PIPE) PID Error */
-#define USB_HOST_STATUS_PIPE_PIDER (_U_(0x1) << USB_HOST_STATUS_PIPE_PIDER_Pos)
-#define USB_HOST_STATUS_PIPE_TOUTER_Pos 3 /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */
-#define USB_HOST_STATUS_PIPE_TOUTER (_U_(0x1) << USB_HOST_STATUS_PIPE_TOUTER_Pos)
-#define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4 /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */
-#define USB_HOST_STATUS_PIPE_CRC16ER (_U_(0x1) << USB_HOST_STATUS_PIPE_CRC16ER_Pos)
-#define USB_HOST_STATUS_PIPE_ERCNT_Pos 5 /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */
-#define USB_HOST_STATUS_PIPE_ERCNT_Msk (_U_(0x7) << USB_HOST_STATUS_PIPE_ERCNT_Pos)
-#define USB_HOST_STATUS_PIPE_ERCNT(value) (USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos))
-#define USB_HOST_STATUS_PIPE_MASK _U_(0x00FF) /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */
-
-/** \brief UsbDeviceDescBank SRAM registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
- __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
- __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
- __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
- RoReg8 Reserved1[0x5];
-} UsbDeviceDescBank;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief UsbHostDescBank SRAM registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
- __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
- __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
- __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */
- RoReg8 Reserved1[0x1];
- __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
- __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
-} UsbHostDescBank;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief UsbDeviceEndpoint hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */
- RoReg8 Reserved1[0x3];
- __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */
- __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */
- __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */
- __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */
- __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
- __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
- RoReg8 Reserved2[0x16];
-} UsbDeviceEndpoint;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief UsbHostPipe hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */
- RoReg8 Reserved1[0x2];
- __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */
- __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */
- __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */
- __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */
- __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */
- __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */
- __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */
- RoReg8 Reserved2[0x16];
-} UsbHostPipe;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief USB_DEVICE APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* USB is Device */
- __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
- RoReg8 Reserved1[0x1];
- __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
- __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
- RoReg8 Reserved2[0x4];
- __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
- __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */
- RoReg8 Reserved3[0x1];
- __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */
- __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
- RoReg8 Reserved4[0x2];
- __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */
- RoReg8 Reserved5[0x2];
- __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
- RoReg8 Reserved6[0x2];
- __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
- RoReg8 Reserved7[0x2];
- __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
- RoReg8 Reserved8[0x2];
- __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */
- RoReg8 Reserved9[0x2];
- __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
- __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
- RoReg8 Reserved10[0xD6];
- UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
-} UsbDevice;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief USB_HOST hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* USB is Host */
- __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
- RoReg8 Reserved1[0x1];
- __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
- __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
- RoReg8 Reserved2[0x4];
- __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
- __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */
- RoReg8 Reserved3[0x1];
- __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */
- __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
- RoReg8 Reserved4[0x2];
- __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
- __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */
- RoReg8 Reserved5[0x1];
- __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
- RoReg8 Reserved6[0x2];
- __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
- RoReg8 Reserved7[0x2];
- __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
- RoReg8 Reserved8[0x2];
- __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */
- RoReg8 Reserved9[0x2];
- __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
- __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
- RoReg8 Reserved10[0xD6];
- UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [PIPE_NUM*HOST_IMPLEMENTED] */
-} UsbHost;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief USB_DEVICE Descriptor SRAM registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* USB is Device */
- UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
-} UsbDeviceDescriptor;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief USB_HOST Descriptor SRAM registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* USB is Host */
- UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
-} UsbHostDescriptor;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SECTION_USB_DESCRIPTOR
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */
- UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */
-} Usb;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_USB_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for USB
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_USB_COMPONENT_
+#define _SAME54_USB_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR USB */
+/* ========================================================================== */
+/** \addtogroup SAME54_USB Universal Serial Bus */
+/*@{*/
+
+#define USB_U2222
+#define REV_USB 0x120
+
+/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t MODE:1; /*!< bit: 7 Operating Mode */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_CTRLA_OFFSET 0x000 /**< \brief (USB_CTRLA offset) Control A */
+#define USB_CTRLA_RESETVALUE _U_(0x00) /**< \brief (USB_CTRLA reset_value) Control A */
+
+#define USB_CTRLA_SWRST_Pos 0 /**< \brief (USB_CTRLA) Software Reset */
+#define USB_CTRLA_SWRST (_U_(0x1) << USB_CTRLA_SWRST_Pos)
+#define USB_CTRLA_ENABLE_Pos 1 /**< \brief (USB_CTRLA) Enable */
+#define USB_CTRLA_ENABLE (_U_(0x1) << USB_CTRLA_ENABLE_Pos)
+#define USB_CTRLA_RUNSTDBY_Pos 2 /**< \brief (USB_CTRLA) Run in Standby Mode */
+#define USB_CTRLA_RUNSTDBY (_U_(0x1) << USB_CTRLA_RUNSTDBY_Pos)
+#define USB_CTRLA_MODE_Pos 7 /**< \brief (USB_CTRLA) Operating Mode */
+#define USB_CTRLA_MODE (_U_(0x1) << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MODE_DEVICE_Val _U_(0x0) /**< \brief (USB_CTRLA) Device Mode */
+#define USB_CTRLA_MODE_HOST_Val _U_(0x1) /**< \brief (USB_CTRLA) Host Mode */
+#define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MASK _U_(0x87) /**< \brief (USB_CTRLA) MASK Register */
+
+/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_SYNCBUSY_OFFSET 0x002 /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */
+#define USB_SYNCBUSY_RESETVALUE _U_(0x00) /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */
+
+#define USB_SYNCBUSY_SWRST_Pos 0 /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */
+#define USB_SYNCBUSY_SWRST (_U_(0x1) << USB_SYNCBUSY_SWRST_Pos)
+#define USB_SYNCBUSY_ENABLE_Pos 1 /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */
+#define USB_SYNCBUSY_ENABLE (_U_(0x1) << USB_SYNCBUSY_ENABLE_Pos)
+#define USB_SYNCBUSY_MASK _U_(0x03) /**< \brief (USB_SYNCBUSY) MASK Register */
+
+/* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */
+ uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_QOSCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_QOSCTRL_OFFSET 0x003 /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */
+#define USB_QOSCTRL_RESETVALUE _U_(0x0F) /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */
+
+#define USB_QOSCTRL_CQOS_Pos 0 /**< \brief (USB_QOSCTRL) Configuration Quality of Service */
+#define USB_QOSCTRL_CQOS_Msk (_U_(0x3) << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS(value) (USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos))
+#define USB_QOSCTRL_DQOS_Pos 2 /**< \brief (USB_QOSCTRL) Data Quality of Service */
+#define USB_QOSCTRL_DQOS_Msk (_U_(0x3) << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS(value) (USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos))
+#define USB_QOSCTRL_MASK _U_(0x0F) /**< \brief (USB_QOSCTRL) MASK Register */
+
+/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DETACH:1; /*!< bit: 0 Detach */
+ uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */
+ uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */
+ uint16_t NREPLY:1; /*!< bit: 4 No Reply */
+ uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
+ uint16_t TSTK:1; /*!< bit: 6 Test mode K */
+ uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */
+ uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */
+ uint16_t GNAK:1; /*!< bit: 9 Global NAK */
+ uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_CTRLB_OFFSET 0x008 /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */
+#define USB_DEVICE_CTRLB_RESETVALUE _U_(0x0001) /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */
+
+#define USB_DEVICE_CTRLB_DETACH_Pos 0 /**< \brief (USB_DEVICE_CTRLB) Detach */
+#define USB_DEVICE_CTRLB_DETACH (_U_(0x1) << USB_DEVICE_CTRLB_DETACH_Pos)
+#define USB_DEVICE_CTRLB_UPRSM_Pos 1 /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */
+#define USB_DEVICE_CTRLB_UPRSM (_U_(0x1) << USB_DEVICE_CTRLB_UPRSM_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */
+#define USB_DEVICE_CTRLB_SPDCONF_Msk (_U_(0x3) << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos))
+#define USB_DEVICE_CTRLB_SPDCONF_FS_Val _U_(0x0) /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */
+#define USB_DEVICE_CTRLB_SPDCONF_LS_Val _U_(0x1) /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */
+#define USB_DEVICE_CTRLB_SPDCONF_HS_Val _U_(0x2) /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */
+#define USB_DEVICE_CTRLB_SPDCONF_HSTM_Val _U_(0x3) /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */
+#define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_NREPLY_Pos 4 /**< \brief (USB_DEVICE_CTRLB) No Reply */
+#define USB_DEVICE_CTRLB_NREPLY (_U_(0x1) << USB_DEVICE_CTRLB_NREPLY_Pos)
+#define USB_DEVICE_CTRLB_TSTJ_Pos 5 /**< \brief (USB_DEVICE_CTRLB) Test mode J */
+#define USB_DEVICE_CTRLB_TSTJ (_U_(0x1) << USB_DEVICE_CTRLB_TSTJ_Pos)
+#define USB_DEVICE_CTRLB_TSTK_Pos 6 /**< \brief (USB_DEVICE_CTRLB) Test mode K */
+#define USB_DEVICE_CTRLB_TSTK (_U_(0x1) << USB_DEVICE_CTRLB_TSTK_Pos)
+#define USB_DEVICE_CTRLB_TSTPCKT_Pos 7 /**< \brief (USB_DEVICE_CTRLB) Test packet mode */
+#define USB_DEVICE_CTRLB_TSTPCKT (_U_(0x1) << USB_DEVICE_CTRLB_TSTPCKT_Pos)
+#define USB_DEVICE_CTRLB_OPMODE2_Pos 8 /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */
+#define USB_DEVICE_CTRLB_OPMODE2 (_U_(0x1) << USB_DEVICE_CTRLB_OPMODE2_Pos)
+#define USB_DEVICE_CTRLB_GNAK_Pos 9 /**< \brief (USB_DEVICE_CTRLB) Global NAK */
+#define USB_DEVICE_CTRLB_GNAK (_U_(0x1) << USB_DEVICE_CTRLB_GNAK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_Pos 10 /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */
+#define USB_DEVICE_CTRLB_LPMHDSK_Msk (_U_(0x3) << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos))
+#define USB_DEVICE_CTRLB_LPMHDSK_NO_Val _U_(0x0) /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */
+#define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val _U_(0x1) /**< \brief (USB_DEVICE_CTRLB) ACK */
+#define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val _U_(0x2) /**< \brief (USB_DEVICE_CTRLB) NYET */
+#define USB_DEVICE_CTRLB_LPMHDSK_STALL_Val _U_(0x3) /**< \brief (USB_DEVICE_CTRLB) STALL */
+#define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_MASK _U_(0x0FFF) /**< \brief (USB_DEVICE_CTRLB) MASK Register */
+
+/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */
+ uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */
+ uint16_t AUTORESUME:1; /*!< bit: 4 Auto Resume Enable */
+ uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
+ uint16_t TSTK:1; /*!< bit: 6 Test mode K */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */
+ uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */
+ uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */
+ uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_CTRLB_OFFSET 0x008 /**< \brief (USB_HOST_CTRLB offset) HOST Control B */
+#define USB_HOST_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */
+
+#define USB_HOST_CTRLB_RESUME_Pos 1 /**< \brief (USB_HOST_CTRLB) Send USB Resume */
+#define USB_HOST_CTRLB_RESUME (_U_(0x1) << USB_HOST_CTRLB_RESUME_Pos)
+#define USB_HOST_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */
+#define USB_HOST_CTRLB_SPDCONF_Msk (_U_(0x3) << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos))
+#define USB_HOST_CTRLB_SPDCONF_NORMAL_Val _U_(0x0) /**< \brief (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */
+#define USB_HOST_CTRLB_SPDCONF_FS_Val _U_(0x3) /**< \brief (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */
+#define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF_FS (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_AUTORESUME_Pos 4 /**< \brief (USB_HOST_CTRLB) Auto Resume Enable */
+#define USB_HOST_CTRLB_AUTORESUME (_U_(0x1) << USB_HOST_CTRLB_AUTORESUME_Pos)
+#define USB_HOST_CTRLB_TSTJ_Pos 5 /**< \brief (USB_HOST_CTRLB) Test mode J */
+#define USB_HOST_CTRLB_TSTJ (_U_(0x1) << USB_HOST_CTRLB_TSTJ_Pos)
+#define USB_HOST_CTRLB_TSTK_Pos 6 /**< \brief (USB_HOST_CTRLB) Test mode K */
+#define USB_HOST_CTRLB_TSTK (_U_(0x1) << USB_HOST_CTRLB_TSTK_Pos)
+#define USB_HOST_CTRLB_SOFE_Pos 8 /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */
+#define USB_HOST_CTRLB_SOFE (_U_(0x1) << USB_HOST_CTRLB_SOFE_Pos)
+#define USB_HOST_CTRLB_BUSRESET_Pos 9 /**< \brief (USB_HOST_CTRLB) Send USB Reset */
+#define USB_HOST_CTRLB_BUSRESET (_U_(0x1) << USB_HOST_CTRLB_BUSRESET_Pos)
+#define USB_HOST_CTRLB_VBUSOK_Pos 10 /**< \brief (USB_HOST_CTRLB) VBUS is OK */
+#define USB_HOST_CTRLB_VBUSOK (_U_(0x1) << USB_HOST_CTRLB_VBUSOK_Pos)
+#define USB_HOST_CTRLB_L1RESUME_Pos 11 /**< \brief (USB_HOST_CTRLB) Send L1 Resume */
+#define USB_HOST_CTRLB_L1RESUME (_U_(0x1) << USB_HOST_CTRLB_L1RESUME_Pos)
+#define USB_HOST_CTRLB_MASK _U_(0x0F7E) /**< \brief (USB_HOST_CTRLB) MASK Register */
+
+/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */
+ uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_DADD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_DADD_OFFSET 0x00A /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */
+#define USB_DEVICE_DADD_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */
+
+#define USB_DEVICE_DADD_DADD_Pos 0 /**< \brief (USB_DEVICE_DADD) Device Address */
+#define USB_DEVICE_DADD_DADD_Msk (_U_(0x7F) << USB_DEVICE_DADD_DADD_Pos)
+#define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos))
+#define USB_DEVICE_DADD_ADDEN_Pos 7 /**< \brief (USB_DEVICE_DADD) Device Address Enable */
+#define USB_DEVICE_DADD_ADDEN (_U_(0x1) << USB_DEVICE_DADD_ADDEN_Pos)
+#define USB_DEVICE_DADD_MASK _U_(0xFF) /**< \brief (USB_DEVICE_DADD) MASK Register */
+
+/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_HSOFC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_HSOFC_OFFSET 0x00A /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */
+#define USB_HOST_HSOFC_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */
+
+#define USB_HOST_HSOFC_FLENC_Pos 0 /**< \brief (USB_HOST_HSOFC) Frame Length Control */
+#define USB_HOST_HSOFC_FLENC_Msk (_U_(0xF) << USB_HOST_HSOFC_FLENC_Pos)
+#define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos))
+#define USB_HOST_HSOFC_FLENCE_Pos 7 /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */
+#define USB_HOST_HSOFC_FLENCE (_U_(0x1) << USB_HOST_HSOFC_FLENCE_Pos)
+#define USB_HOST_HSOFC_MASK _U_(0x8F) /**< \brief (USB_HOST_HSOFC) MASK Register */
+
+/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_STATUS_OFFSET 0x00C /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */
+#define USB_DEVICE_STATUS_RESETVALUE _U_(0x40) /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */
+
+#define USB_DEVICE_STATUS_SPEED_Pos 2 /**< \brief (USB_DEVICE_STATUS) Speed Status */
+#define USB_DEVICE_STATUS_SPEED_Msk (_U_(0x3) << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos))
+#define USB_DEVICE_STATUS_SPEED_FS_Val _U_(0x0) /**< \brief (USB_DEVICE_STATUS) Full-speed mode */
+#define USB_DEVICE_STATUS_SPEED_LS_Val _U_(0x1) /**< \brief (USB_DEVICE_STATUS) Low-speed mode */
+#define USB_DEVICE_STATUS_SPEED_HS_Val _U_(0x2) /**< \brief (USB_DEVICE_STATUS) High-speed mode */
+#define USB_DEVICE_STATUS_SPEED_FS (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED_LS (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED_HS (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_Pos 6 /**< \brief (USB_DEVICE_STATUS) USB Line State Status */
+#define USB_DEVICE_STATUS_LINESTATE_Msk (_U_(0x3) << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos))
+#define USB_DEVICE_STATUS_LINESTATE_0_Val _U_(0x0) /**< \brief (USB_DEVICE_STATUS) SE0/RESET */
+#define USB_DEVICE_STATUS_LINESTATE_1_Val _U_(0x1) /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */
+#define USB_DEVICE_STATUS_LINESTATE_2_Val _U_(0x2) /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */
+#define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_MASK _U_(0xCC) /**< \brief (USB_DEVICE_STATUS) MASK Register */
+
+/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_OFFSET 0x00C /**< \brief (USB_HOST_STATUS offset) HOST Status */
+#define USB_HOST_STATUS_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_STATUS reset_value) HOST Status */
+
+#define USB_HOST_STATUS_SPEED_Pos 2 /**< \brief (USB_HOST_STATUS) Speed Status */
+#define USB_HOST_STATUS_SPEED_Msk (_U_(0x3) << USB_HOST_STATUS_SPEED_Pos)
+#define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos))
+#define USB_HOST_STATUS_LINESTATE_Pos 6 /**< \brief (USB_HOST_STATUS) USB Line State Status */
+#define USB_HOST_STATUS_LINESTATE_Msk (_U_(0x3) << USB_HOST_STATUS_LINESTATE_Pos)
+#define USB_HOST_STATUS_LINESTATE(value) (USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos))
+#define USB_HOST_STATUS_MASK _U_(0xCC) /**< \brief (USB_HOST_STATUS) MASK Register */
+
+/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FSMSTATE:7; /*!< bit: 0.. 6 Fine State Machine Status */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_FSMSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_FSMSTATUS_OFFSET 0x00D /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */
+#define USB_FSMSTATUS_RESETVALUE _U_(0x01) /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */
+
+#define USB_FSMSTATUS_FSMSTATE_Pos 0 /**< \brief (USB_FSMSTATUS) Fine State Machine Status */
+#define USB_FSMSTATUS_FSMSTATE_Msk (_U_(0x7F) << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE(value) (USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos))
+#define USB_FSMSTATUS_FSMSTATE_OFF_Val _U_(0x1) /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */
+#define USB_FSMSTATUS_FSMSTATE_ON_Val _U_(0x2) /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */
+#define USB_FSMSTATUS_FSMSTATE_SUSPEND_Val _U_(0x4) /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */
+#define USB_FSMSTATUS_FSMSTATE_SLEEP_Val _U_(0x8) /**< \brief (USB_FSMSTATUS) SLEEP (L1) */
+#define USB_FSMSTATUS_FSMSTATE_DNRESUME_Val _U_(0x10) /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */
+#define USB_FSMSTATUS_FSMSTATE_UPRESUME_Val _U_(0x20) /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */
+#define USB_FSMSTATUS_FSMSTATE_RESET_Val _U_(0x40) /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */
+#define USB_FSMSTATUS_FSMSTATE_OFF (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_ON (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_MASK _U_(0x7F) /**< \brief (USB_FSMSTATUS) MASK Register */
+
+/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
+ uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
+ uint16_t :1; /*!< bit: 14 Reserved */
+ uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_FNUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_FNUM_OFFSET 0x010 /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */
+#define USB_DEVICE_FNUM_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */
+
+#define USB_DEVICE_FNUM_MFNUM_Pos 0 /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */
+#define USB_DEVICE_FNUM_MFNUM_Msk (_U_(0x7) << USB_DEVICE_FNUM_MFNUM_Pos)
+#define USB_DEVICE_FNUM_MFNUM(value) (USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos))
+#define USB_DEVICE_FNUM_FNUM_Pos 3 /**< \brief (USB_DEVICE_FNUM) Frame Number */
+#define USB_DEVICE_FNUM_FNUM_Msk (_U_(0x7FF) << USB_DEVICE_FNUM_FNUM_Pos)
+#define USB_DEVICE_FNUM_FNUM(value) (USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos))
+#define USB_DEVICE_FNUM_FNCERR_Pos 15 /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */
+#define USB_DEVICE_FNUM_FNCERR (_U_(0x1) << USB_DEVICE_FNUM_FNCERR_Pos)
+#define USB_DEVICE_FNUM_MASK _U_(0xBFFF) /**< \brief (USB_DEVICE_FNUM) MASK Register */
+
+/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
+ uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_FNUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_FNUM_OFFSET 0x010 /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */
+#define USB_HOST_FNUM_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */
+
+#define USB_HOST_FNUM_MFNUM_Pos 0 /**< \brief (USB_HOST_FNUM) Micro Frame Number */
+#define USB_HOST_FNUM_MFNUM_Msk (_U_(0x7) << USB_HOST_FNUM_MFNUM_Pos)
+#define USB_HOST_FNUM_MFNUM(value) (USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos))
+#define USB_HOST_FNUM_FNUM_Pos 3 /**< \brief (USB_HOST_FNUM) Frame Number */
+#define USB_HOST_FNUM_FNUM_Msk (_U_(0x7FF) << USB_HOST_FNUM_FNUM_Pos)
+#define USB_HOST_FNUM_FNUM(value) (USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos))
+#define USB_HOST_FNUM_MASK _U_(0x3FFF) /**< \brief (USB_HOST_FNUM) MASK Register */
+
+/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_FLENHIGH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_FLENHIGH_OFFSET 0x012 /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */
+#define USB_HOST_FLENHIGH_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */
+
+#define USB_HOST_FLENHIGH_FLENHIGH_Pos 0 /**< \brief (USB_HOST_FLENHIGH) Frame Length */
+#define USB_HOST_FLENHIGH_FLENHIGH_Msk (_U_(0xFF) << USB_HOST_FLENHIGH_FLENHIGH_Pos)
+#define USB_HOST_FLENHIGH_FLENHIGH(value) (USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos))
+#define USB_HOST_FLENHIGH_MASK _U_(0xFF) /**< \brief (USB_HOST_FLENHIGH) MASK Register */
+
+/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTENCLR_OFFSET 0x014 /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */
+#define USB_DEVICE_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */
+
+#define USB_DEVICE_INTENCLR_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */
+#define USB_DEVICE_INTENCLR_SUSPEND (_U_(0x1) << USB_DEVICE_INTENCLR_SUSPEND_Pos)
+#define USB_DEVICE_INTENCLR_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */
+#define USB_DEVICE_INTENCLR_MSOF (_U_(0x1) << USB_DEVICE_INTENCLR_MSOF_Pos)
+#define USB_DEVICE_INTENCLR_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */
+#define USB_DEVICE_INTENCLR_SOF (_U_(0x1) << USB_DEVICE_INTENCLR_SOF_Pos)
+#define USB_DEVICE_INTENCLR_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */
+#define USB_DEVICE_INTENCLR_EORST (_U_(0x1) << USB_DEVICE_INTENCLR_EORST_Pos)
+#define USB_DEVICE_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */
+#define USB_DEVICE_INTENCLR_WAKEUP (_U_(0x1) << USB_DEVICE_INTENCLR_WAKEUP_Pos)
+#define USB_DEVICE_INTENCLR_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */
+#define USB_DEVICE_INTENCLR_EORSM (_U_(0x1) << USB_DEVICE_INTENCLR_EORSM_Pos)
+#define USB_DEVICE_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */
+#define USB_DEVICE_INTENCLR_UPRSM (_U_(0x1) << USB_DEVICE_INTENCLR_UPRSM_Pos)
+#define USB_DEVICE_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */
+#define USB_DEVICE_INTENCLR_RAMACER (_U_(0x1) << USB_DEVICE_INTENCLR_RAMACER_Pos)
+#define USB_DEVICE_INTENCLR_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */
+#define USB_DEVICE_INTENCLR_LPMNYET (_U_(0x1) << USB_DEVICE_INTENCLR_LPMNYET_Pos)
+#define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */
+#define USB_DEVICE_INTENCLR_LPMSUSP (_U_(0x1) << USB_DEVICE_INTENCLR_LPMSUSP_Pos)
+#define USB_DEVICE_INTENCLR_MASK _U_(0x03FF) /**< \brief (USB_DEVICE_INTENCLR) MASK Register */
+
+/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */
+ uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */
+ uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */
+ uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTENCLR_OFFSET 0x014 /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */
+#define USB_HOST_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */
+
+#define USB_HOST_INTENCLR_HSOF_Pos 2 /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */
+#define USB_HOST_INTENCLR_HSOF (_U_(0x1) << USB_HOST_INTENCLR_HSOF_Pos)
+#define USB_HOST_INTENCLR_RST_Pos 3 /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */
+#define USB_HOST_INTENCLR_RST (_U_(0x1) << USB_HOST_INTENCLR_RST_Pos)
+#define USB_HOST_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */
+#define USB_HOST_INTENCLR_WAKEUP (_U_(0x1) << USB_HOST_INTENCLR_WAKEUP_Pos)
+#define USB_HOST_INTENCLR_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */
+#define USB_HOST_INTENCLR_DNRSM (_U_(0x1) << USB_HOST_INTENCLR_DNRSM_Pos)
+#define USB_HOST_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */
+#define USB_HOST_INTENCLR_UPRSM (_U_(0x1) << USB_HOST_INTENCLR_UPRSM_Pos)
+#define USB_HOST_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */
+#define USB_HOST_INTENCLR_RAMACER (_U_(0x1) << USB_HOST_INTENCLR_RAMACER_Pos)
+#define USB_HOST_INTENCLR_DCONN_Pos 8 /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */
+#define USB_HOST_INTENCLR_DCONN (_U_(0x1) << USB_HOST_INTENCLR_DCONN_Pos)
+#define USB_HOST_INTENCLR_DDISC_Pos 9 /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */
+#define USB_HOST_INTENCLR_DDISC (_U_(0x1) << USB_HOST_INTENCLR_DDISC_Pos)
+#define USB_HOST_INTENCLR_MASK _U_(0x03FC) /**< \brief (USB_HOST_INTENCLR) MASK Register */
+
+/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTENSET_OFFSET 0x018 /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */
+#define USB_DEVICE_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */
+
+#define USB_DEVICE_INTENSET_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */
+#define USB_DEVICE_INTENSET_SUSPEND (_U_(0x1) << USB_DEVICE_INTENSET_SUSPEND_Pos)
+#define USB_DEVICE_INTENSET_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */
+#define USB_DEVICE_INTENSET_MSOF (_U_(0x1) << USB_DEVICE_INTENSET_MSOF_Pos)
+#define USB_DEVICE_INTENSET_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */
+#define USB_DEVICE_INTENSET_SOF (_U_(0x1) << USB_DEVICE_INTENSET_SOF_Pos)
+#define USB_DEVICE_INTENSET_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */
+#define USB_DEVICE_INTENSET_EORST (_U_(0x1) << USB_DEVICE_INTENSET_EORST_Pos)
+#define USB_DEVICE_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */
+#define USB_DEVICE_INTENSET_WAKEUP (_U_(0x1) << USB_DEVICE_INTENSET_WAKEUP_Pos)
+#define USB_DEVICE_INTENSET_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */
+#define USB_DEVICE_INTENSET_EORSM (_U_(0x1) << USB_DEVICE_INTENSET_EORSM_Pos)
+#define USB_DEVICE_INTENSET_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */
+#define USB_DEVICE_INTENSET_UPRSM (_U_(0x1) << USB_DEVICE_INTENSET_UPRSM_Pos)
+#define USB_DEVICE_INTENSET_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */
+#define USB_DEVICE_INTENSET_RAMACER (_U_(0x1) << USB_DEVICE_INTENSET_RAMACER_Pos)
+#define USB_DEVICE_INTENSET_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */
+#define USB_DEVICE_INTENSET_LPMNYET (_U_(0x1) << USB_DEVICE_INTENSET_LPMNYET_Pos)
+#define USB_DEVICE_INTENSET_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */
+#define USB_DEVICE_INTENSET_LPMSUSP (_U_(0x1) << USB_DEVICE_INTENSET_LPMSUSP_Pos)
+#define USB_DEVICE_INTENSET_MASK _U_(0x03FF) /**< \brief (USB_DEVICE_INTENSET) MASK Register */
+
+/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */
+ uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTENSET_OFFSET 0x018 /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */
+#define USB_HOST_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */
+
+#define USB_HOST_INTENSET_HSOF_Pos 2 /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */
+#define USB_HOST_INTENSET_HSOF (_U_(0x1) << USB_HOST_INTENSET_HSOF_Pos)
+#define USB_HOST_INTENSET_RST_Pos 3 /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */
+#define USB_HOST_INTENSET_RST (_U_(0x1) << USB_HOST_INTENSET_RST_Pos)
+#define USB_HOST_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */
+#define USB_HOST_INTENSET_WAKEUP (_U_(0x1) << USB_HOST_INTENSET_WAKEUP_Pos)
+#define USB_HOST_INTENSET_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */
+#define USB_HOST_INTENSET_DNRSM (_U_(0x1) << USB_HOST_INTENSET_DNRSM_Pos)
+#define USB_HOST_INTENSET_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */
+#define USB_HOST_INTENSET_UPRSM (_U_(0x1) << USB_HOST_INTENSET_UPRSM_Pos)
+#define USB_HOST_INTENSET_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */
+#define USB_HOST_INTENSET_RAMACER (_U_(0x1) << USB_HOST_INTENSET_RAMACER_Pos)
+#define USB_HOST_INTENSET_DCONN_Pos 8 /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */
+#define USB_HOST_INTENSET_DCONN (_U_(0x1) << USB_HOST_INTENSET_DCONN_Pos)
+#define USB_HOST_INTENSET_DDISC_Pos 9 /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */
+#define USB_HOST_INTENSET_DDISC (_U_(0x1) << USB_HOST_INTENSET_DDISC_Pos)
+#define USB_HOST_INTENSET_MASK _U_(0x03FC) /**< \brief (USB_HOST_INTENSET) MASK Register */
+
+/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
+ __I uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
+ __I uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
+ __I uint16_t EORST:1; /*!< bit: 3 End of Reset */
+ __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
+ __I uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
+ __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
+ __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
+ __I uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
+ __I uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
+ __I uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTFLAG_OFFSET 0x01C /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */
+#define USB_DEVICE_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */
+
+#define USB_DEVICE_INTFLAG_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTFLAG) Suspend */
+#define USB_DEVICE_INTFLAG_SUSPEND (_U_(0x1) << USB_DEVICE_INTFLAG_SUSPEND_Pos)
+#define USB_DEVICE_INTFLAG_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */
+#define USB_DEVICE_INTFLAG_MSOF (_U_(0x1) << USB_DEVICE_INTFLAG_MSOF_Pos)
+#define USB_DEVICE_INTFLAG_SOF_Pos 2 /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */
+#define USB_DEVICE_INTFLAG_SOF (_U_(0x1) << USB_DEVICE_INTFLAG_SOF_Pos)
+#define USB_DEVICE_INTFLAG_EORST_Pos 3 /**< \brief (USB_DEVICE_INTFLAG) End of Reset */
+#define USB_DEVICE_INTFLAG_EORST (_U_(0x1) << USB_DEVICE_INTFLAG_EORST_Pos)
+#define USB_DEVICE_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTFLAG) Wake Up */
+#define USB_DEVICE_INTFLAG_WAKEUP (_U_(0x1) << USB_DEVICE_INTFLAG_WAKEUP_Pos)
+#define USB_DEVICE_INTFLAG_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */
+#define USB_DEVICE_INTFLAG_EORSM (_U_(0x1) << USB_DEVICE_INTFLAG_EORSM_Pos)
+#define USB_DEVICE_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */
+#define USB_DEVICE_INTFLAG_UPRSM (_U_(0x1) << USB_DEVICE_INTFLAG_UPRSM_Pos)
+#define USB_DEVICE_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTFLAG) Ram Access */
+#define USB_DEVICE_INTFLAG_RAMACER (_U_(0x1) << USB_DEVICE_INTFLAG_RAMACER_Pos)
+#define USB_DEVICE_INTFLAG_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */
+#define USB_DEVICE_INTFLAG_LPMNYET (_U_(0x1) << USB_DEVICE_INTFLAG_LPMNYET_Pos)
+#define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */
+#define USB_DEVICE_INTFLAG_LPMSUSP (_U_(0x1) << USB_DEVICE_INTFLAG_LPMSUSP_Pos)
+#define USB_DEVICE_INTFLAG_MASK _U_(0x03FF) /**< \brief (USB_DEVICE_INTFLAG) MASK Register */
+
+/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ __I uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
+ __I uint16_t RST:1; /*!< bit: 3 Bus Reset */
+ __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
+ __I uint16_t DNRSM:1; /*!< bit: 5 Downstream */
+ __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
+ __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
+ __I uint16_t DCONN:1; /*!< bit: 8 Device Connection */
+ __I uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
+ __I uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTFLAG_OFFSET 0x01C /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */
+#define USB_HOST_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */
+
+#define USB_HOST_INTFLAG_HSOF_Pos 2 /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */
+#define USB_HOST_INTFLAG_HSOF (_U_(0x1) << USB_HOST_INTFLAG_HSOF_Pos)
+#define USB_HOST_INTFLAG_RST_Pos 3 /**< \brief (USB_HOST_INTFLAG) Bus Reset */
+#define USB_HOST_INTFLAG_RST (_U_(0x1) << USB_HOST_INTFLAG_RST_Pos)
+#define USB_HOST_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTFLAG) Wake Up */
+#define USB_HOST_INTFLAG_WAKEUP (_U_(0x1) << USB_HOST_INTFLAG_WAKEUP_Pos)
+#define USB_HOST_INTFLAG_DNRSM_Pos 5 /**< \brief (USB_HOST_INTFLAG) Downstream */
+#define USB_HOST_INTFLAG_DNRSM (_U_(0x1) << USB_HOST_INTFLAG_DNRSM_Pos)
+#define USB_HOST_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */
+#define USB_HOST_INTFLAG_UPRSM (_U_(0x1) << USB_HOST_INTFLAG_UPRSM_Pos)
+#define USB_HOST_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_HOST_INTFLAG) Ram Access */
+#define USB_HOST_INTFLAG_RAMACER (_U_(0x1) << USB_HOST_INTFLAG_RAMACER_Pos)
+#define USB_HOST_INTFLAG_DCONN_Pos 8 /**< \brief (USB_HOST_INTFLAG) Device Connection */
+#define USB_HOST_INTFLAG_DCONN (_U_(0x1) << USB_HOST_INTFLAG_DCONN_Pos)
+#define USB_HOST_INTFLAG_DDISC_Pos 9 /**< \brief (USB_HOST_INTFLAG) Device Disconnection */
+#define USB_HOST_INTFLAG_DDISC (_U_(0x1) << USB_HOST_INTFLAG_DDISC_Pos)
+#define USB_HOST_INTFLAG_MASK _U_(0x03FC) /**< \brief (USB_HOST_INTFLAG) MASK Register */
+
+/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */
+ uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */
+ uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */
+ uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */
+ uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */
+ uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */
+ uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */
+ uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTSMRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTSMRY_OFFSET 0x020 /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */
+#define USB_DEVICE_EPINTSMRY_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */
+
+#define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT0 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT0_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT1 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT1_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT2 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT2_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT3 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT3_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT4 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT4_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT5 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT5_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT6 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT6_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT7 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT7_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT_Msk (_U_(0xFF) << USB_DEVICE_EPINTSMRY_EPINT_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT(value) (USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos))
+#define USB_DEVICE_EPINTSMRY_MASK _U_(0x00FF) /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */
+
+/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */
+ uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */
+ uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */
+ uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */
+ uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */
+ uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */
+ uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */
+ uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_PINTSMRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTSMRY_OFFSET 0x020 /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */
+#define USB_HOST_PINTSMRY_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */
+
+#define USB_HOST_PINTSMRY_EPINT0_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT0 (_U_(1) << USB_HOST_PINTSMRY_EPINT0_Pos)
+#define USB_HOST_PINTSMRY_EPINT1_Pos 1 /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT1 (_U_(1) << USB_HOST_PINTSMRY_EPINT1_Pos)
+#define USB_HOST_PINTSMRY_EPINT2_Pos 2 /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT2 (_U_(1) << USB_HOST_PINTSMRY_EPINT2_Pos)
+#define USB_HOST_PINTSMRY_EPINT3_Pos 3 /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT3 (_U_(1) << USB_HOST_PINTSMRY_EPINT3_Pos)
+#define USB_HOST_PINTSMRY_EPINT4_Pos 4 /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT4 (_U_(1) << USB_HOST_PINTSMRY_EPINT4_Pos)
+#define USB_HOST_PINTSMRY_EPINT5_Pos 5 /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT5 (_U_(1) << USB_HOST_PINTSMRY_EPINT5_Pos)
+#define USB_HOST_PINTSMRY_EPINT6_Pos 6 /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT6 (_U_(1) << USB_HOST_PINTSMRY_EPINT6_Pos)
+#define USB_HOST_PINTSMRY_EPINT7_Pos 7 /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT7 (_U_(1) << USB_HOST_PINTSMRY_EPINT7_Pos)
+#define USB_HOST_PINTSMRY_EPINT_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */
+#define USB_HOST_PINTSMRY_EPINT_Msk (_U_(0xFF) << USB_HOST_PINTSMRY_EPINT_Pos)
+#define USB_HOST_PINTSMRY_EPINT(value) (USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos))
+#define USB_HOST_PINTSMRY_MASK _U_(0x00FF) /**< \brief (USB_HOST_PINTSMRY) MASK Register */
+
+/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_DESCADD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DESCADD_OFFSET 0x024 /**< \brief (USB_DESCADD offset) Descriptor Address */
+#define USB_DESCADD_RESETVALUE _U_(0x00000000) /**< \brief (USB_DESCADD reset_value) Descriptor Address */
+
+#define USB_DESCADD_DESCADD_Pos 0 /**< \brief (USB_DESCADD) Descriptor Address Value */
+#define USB_DESCADD_DESCADD_Msk (_U_(0xFFFFFFFF) << USB_DESCADD_DESCADD_Pos)
+#define USB_DESCADD_DESCADD(value) (USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos))
+#define USB_DESCADD_MASK _U_(0xFFFFFFFF) /**< \brief (USB_DESCADD) MASK Register */
+
+/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_PADCAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_PADCAL_OFFSET 0x028 /**< \brief (USB_PADCAL offset) USB PAD Calibration */
+#define USB_PADCAL_RESETVALUE _U_(0x0000) /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */
+
+#define USB_PADCAL_TRANSP_Pos 0 /**< \brief (USB_PADCAL) USB Pad Transp calibration */
+#define USB_PADCAL_TRANSP_Msk (_U_(0x1F) << USB_PADCAL_TRANSP_Pos)
+#define USB_PADCAL_TRANSP(value) (USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos))
+#define USB_PADCAL_TRANSN_Pos 6 /**< \brief (USB_PADCAL) USB Pad Transn calibration */
+#define USB_PADCAL_TRANSN_Msk (_U_(0x1F) << USB_PADCAL_TRANSN_Pos)
+#define USB_PADCAL_TRANSN(value) (USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos))
+#define USB_PADCAL_TRIM_Pos 12 /**< \brief (USB_PADCAL) USB Pad Trim calibration */
+#define USB_PADCAL_TRIM_Msk (_U_(0x7) << USB_PADCAL_TRIM_Pos)
+#define USB_PADCAL_TRIM(value) (USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos))
+#define USB_PADCAL_MASK _U_(0x77DF) /**< \brief (USB_PADCAL) MASK Register */
+
+/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */
+ uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPCFG_OFFSET 0x100 /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */
+#define USB_DEVICE_EPCFG_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */
+
+#define USB_DEVICE_EPCFG_EPTYPE0_Pos 0 /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */
+#define USB_DEVICE_EPCFG_EPTYPE0_Msk (_U_(0x7) << USB_DEVICE_EPCFG_EPTYPE0_Pos)
+#define USB_DEVICE_EPCFG_EPTYPE0(value) (USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos))
+#define USB_DEVICE_EPCFG_EPTYPE1_Pos 4 /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */
+#define USB_DEVICE_EPCFG_EPTYPE1_Msk (_U_(0x7) << USB_DEVICE_EPCFG_EPTYPE1_Pos)
+#define USB_DEVICE_EPCFG_EPTYPE1(value) (USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos))
+#define USB_DEVICE_EPCFG_NYETDIS_Pos 7 /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */
+#define USB_DEVICE_EPCFG_NYETDIS (_U_(0x1) << USB_DEVICE_EPCFG_NYETDIS_Pos)
+#define USB_DEVICE_EPCFG_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPCFG) MASK Register */
+
+/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */
+ uint8_t BK:1; /*!< bit: 2 Pipe Bank */
+ uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PCFG_OFFSET 0x100 /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */
+#define USB_HOST_PCFG_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */
+
+#define USB_HOST_PCFG_PTOKEN_Pos 0 /**< \brief (USB_HOST_PCFG) Pipe Token */
+#define USB_HOST_PCFG_PTOKEN_Msk (_U_(0x3) << USB_HOST_PCFG_PTOKEN_Pos)
+#define USB_HOST_PCFG_PTOKEN(value) (USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos))
+#define USB_HOST_PCFG_BK_Pos 2 /**< \brief (USB_HOST_PCFG) Pipe Bank */
+#define USB_HOST_PCFG_BK (_U_(0x1) << USB_HOST_PCFG_BK_Pos)
+#define USB_HOST_PCFG_PTYPE_Pos 3 /**< \brief (USB_HOST_PCFG) Pipe Type */
+#define USB_HOST_PCFG_PTYPE_Msk (_U_(0x7) << USB_HOST_PCFG_PTYPE_Pos)
+#define USB_HOST_PCFG_PTYPE(value) (USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos))
+#define USB_HOST_PCFG_MASK _U_(0x3F) /**< \brief (USB_HOST_PCFG) MASK Register */
+
+/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_BINTERVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_BINTERVAL_OFFSET 0x103 /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */
+#define USB_HOST_BINTERVAL_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */
+
+#define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0 /**< \brief (USB_HOST_BINTERVAL) Bit Interval */
+#define USB_HOST_BINTERVAL_BITINTERVAL_Msk (_U_(0xFF) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)
+#define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos))
+#define USB_HOST_BINTERVAL_MASK _U_(0xFF) /**< \brief (USB_HOST_BINTERVAL) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Clear */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPSTATUSCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104 /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */
+#define USB_DEVICE_EPSTATUSCLR_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */
+
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSCLR) Current Bank Clear */
+#define USB_DEVICE_EPSTATUSCLR_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUSCLR_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */
+
+/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PSTATUSCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUSCLR_OFFSET 0x104 /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */
+#define USB_HOST_PSTATUSCLR_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */
+
+#define USB_HOST_PSTATUSCLR_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */
+#define USB_HOST_PSTATUSCLR_DTGL (_U_(0x1) << USB_HOST_PSTATUSCLR_DTGL_Pos)
+#define USB_HOST_PSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */
+#define USB_HOST_PSTATUSCLR_CURBK (_U_(0x1) << USB_HOST_PSTATUSCLR_CURBK_Pos)
+#define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */
+#define USB_HOST_PSTATUSCLR_PFREEZE (_U_(0x1) << USB_HOST_PSTATUSCLR_PFREEZE_Pos)
+#define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */
+#define USB_HOST_PSTATUSCLR_BK0RDY (_U_(0x1) << USB_HOST_PSTATUSCLR_BK0RDY_Pos)
+#define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */
+#define USB_HOST_PSTATUSCLR_BK1RDY (_U_(0x1) << USB_HOST_PSTATUSCLR_BK1RDY_Pos)
+#define USB_HOST_PSTATUSCLR_MASK _U_(0xD5) /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPSTATUSSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUSSET_OFFSET 0x105 /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */
+#define USB_DEVICE_EPSTATUSSET_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */
+
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */
+#define USB_DEVICE_EPSTATUSSET_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */
+#define USB_DEVICE_EPSTATUSSET_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUSSET_CURBK_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */
+#define USB_DEVICE_EPSTATUSSET_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */
+#define USB_DEVICE_EPSTATUSSET_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUSSET_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */
+
+/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PSTATUSSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUSSET_OFFSET 0x105 /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */
+#define USB_HOST_PSTATUSSET_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */
+
+#define USB_HOST_PSTATUSSET_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */
+#define USB_HOST_PSTATUSSET_DTGL (_U_(0x1) << USB_HOST_PSTATUSSET_DTGL_Pos)
+#define USB_HOST_PSTATUSSET_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */
+#define USB_HOST_PSTATUSSET_CURBK (_U_(0x1) << USB_HOST_PSTATUSSET_CURBK_Pos)
+#define USB_HOST_PSTATUSSET_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */
+#define USB_HOST_PSTATUSSET_PFREEZE (_U_(0x1) << USB_HOST_PSTATUSSET_PFREEZE_Pos)
+#define USB_HOST_PSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */
+#define USB_HOST_PSTATUSSET_BK0RDY (_U_(0x1) << USB_HOST_PSTATUSSET_BK0RDY_Pos)
+#define USB_HOST_PSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */
+#define USB_HOST_PSTATUSSET_BK1RDY (_U_(0x1) << USB_HOST_PSTATUSSET_BK1RDY_Pos)
+#define USB_HOST_PSTATUSSET_MASK _U_(0xD5) /**< \brief (USB_HOST_PSTATUSSET) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUS_OFFSET 0x106 /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */
+#define USB_DEVICE_EPSTATUS_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */
+
+#define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */
+#define USB_DEVICE_EPSTATUS_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */
+#define USB_DEVICE_EPSTATUS_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUS_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUS_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */
+#define USB_DEVICE_EPSTATUS_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUS_CURBK_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ(value) (USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */
+#define USB_DEVICE_EPSTATUS_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUS_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */
+#define USB_DEVICE_EPSTATUS_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUS_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUS_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */
+
+/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUS_OFFSET 0x106 /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */
+#define USB_HOST_PSTATUS_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */
+
+#define USB_HOST_PSTATUS_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUS) Data Toggle */
+#define USB_HOST_PSTATUS_DTGL (_U_(0x1) << USB_HOST_PSTATUS_DTGL_Pos)
+#define USB_HOST_PSTATUS_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUS) Current Bank */
+#define USB_HOST_PSTATUS_CURBK (_U_(0x1) << USB_HOST_PSTATUS_CURBK_Pos)
+#define USB_HOST_PSTATUS_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */
+#define USB_HOST_PSTATUS_PFREEZE (_U_(0x1) << USB_HOST_PSTATUS_PFREEZE_Pos)
+#define USB_HOST_PSTATUS_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */
+#define USB_HOST_PSTATUS_BK0RDY (_U_(0x1) << USB_HOST_PSTATUS_BK0RDY_Pos)
+#define USB_HOST_PSTATUS_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */
+#define USB_HOST_PSTATUS_BK1RDY (_U_(0x1) << USB_HOST_PSTATUS_BK1RDY_Pos)
+#define USB_HOST_PSTATUS_MASK _U_(0xD5) /**< \brief (USB_HOST_PSTATUS) MASK Register */
+
+/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
+ __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
+ __I uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
+ __I uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
+ __I uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
+ __I uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
+ __I uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
+ __I uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
+ __I uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
+ __I uint8_t :1; /*!< bit: 4 Reserved */
+ __I uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
+ __I uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTFLAG_OFFSET 0x107 /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */
+#define USB_DEVICE_EPINTFLAG_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */
+
+#define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */
+#define USB_DEVICE_EPINTFLAG_TRCPT0 (_U_(1) << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */
+#define USB_DEVICE_EPINTFLAG_TRCPT1 (_U_(1) << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */
+#define USB_DEVICE_EPINTFLAG_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT(value) (USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos))
+#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */
+#define USB_DEVICE_EPINTFLAG_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */
+#define USB_DEVICE_EPINTFLAG_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL(value) (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos))
+#define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */
+#define USB_DEVICE_EPINTFLAG_RXSTP (_U_(0x1) << USB_DEVICE_EPINTFLAG_RXSTP_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */
+#define USB_DEVICE_EPINTFLAG_STALL0 (_U_(1) << USB_DEVICE_EPINTFLAG_STALL0_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */
+#define USB_DEVICE_EPINTFLAG_STALL1 (_U_(1) << USB_DEVICE_EPINTFLAG_STALL1_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */
+#define USB_DEVICE_EPINTFLAG_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_STALL_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL(value) (USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos))
+#define USB_DEVICE_EPINTFLAG_MASK _U_(0x7F) /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */
+
+/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
+ __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
+ __I uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
+ __I uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
+ __I uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
+ __I uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
+ __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTFLAG_OFFSET 0x107 /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */
+#define USB_HOST_PINTFLAG_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */
+
+#define USB_HOST_PINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT0 (_U_(1) << USB_HOST_PINTFLAG_TRCPT0_Pos)
+#define USB_HOST_PINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT1 (_U_(1) << USB_HOST_PINTFLAG_TRCPT1_Pos)
+#define USB_HOST_PINTFLAG_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTFLAG_TRCPT_Pos)
+#define USB_HOST_PINTFLAG_TRCPT(value) (USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos))
+#define USB_HOST_PINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRFAIL (_U_(0x1) << USB_HOST_PINTFLAG_TRFAIL_Pos)
+#define USB_HOST_PINTFLAG_PERR_Pos 3 /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */
+#define USB_HOST_PINTFLAG_PERR (_U_(0x1) << USB_HOST_PINTFLAG_PERR_Pos)
+#define USB_HOST_PINTFLAG_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag */
+#define USB_HOST_PINTFLAG_TXSTP (_U_(0x1) << USB_HOST_PINTFLAG_TXSTP_Pos)
+#define USB_HOST_PINTFLAG_STALL_Pos 5 /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */
+#define USB_HOST_PINTFLAG_STALL (_U_(0x1) << USB_HOST_PINTFLAG_STALL_Pos)
+#define USB_HOST_PINTFLAG_MASK _U_(0x3F) /**< \brief (USB_HOST_PINTFLAG) MASK Register */
+
+/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTENCLR_OFFSET 0x108 /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+#define USB_DEVICE_EPINTENCLR_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+
+#define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT0 (_U_(1) << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT1 (_U_(1) << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT(value) (USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos))
+#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL(value) (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos))
+#define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_RXSTP (_U_(0x1) << USB_DEVICE_EPINTENCLR_RXSTP_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL0 (_U_(1) << USB_DEVICE_EPINTENCLR_STALL0_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL1 (_U_(1) << USB_DEVICE_EPINTENCLR_STALL1_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_STALL_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL(value) (USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos))
+#define USB_DEVICE_EPINTENCLR_MASK _U_(0x7F) /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */
+
+/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */
+ uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTENCLR_OFFSET 0x108 /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */
+#define USB_HOST_PINTENCLR_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */
+
+#define USB_HOST_PINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */
+#define USB_HOST_PINTENCLR_TRCPT0 (_U_(1) << USB_HOST_PINTENCLR_TRCPT0_Pos)
+#define USB_HOST_PINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */
+#define USB_HOST_PINTENCLR_TRCPT1 (_U_(1) << USB_HOST_PINTENCLR_TRCPT1_Pos)
+#define USB_HOST_PINTENCLR_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */
+#define USB_HOST_PINTENCLR_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTENCLR_TRCPT_Pos)
+#define USB_HOST_PINTENCLR_TRCPT(value) (USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos))
+#define USB_HOST_PINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */
+#define USB_HOST_PINTENCLR_TRFAIL (_U_(0x1) << USB_HOST_PINTENCLR_TRFAIL_Pos)
+#define USB_HOST_PINTENCLR_PERR_Pos 3 /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */
+#define USB_HOST_PINTENCLR_PERR (_U_(0x1) << USB_HOST_PINTENCLR_PERR_Pos)
+#define USB_HOST_PINTENCLR_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */
+#define USB_HOST_PINTENCLR_TXSTP (_U_(0x1) << USB_HOST_PINTENCLR_TXSTP_Pos)
+#define USB_HOST_PINTENCLR_STALL_Pos 5 /**< \brief (USB_HOST_PINTENCLR) Stall Inetrrupt Disable */
+#define USB_HOST_PINTENCLR_STALL (_U_(0x1) << USB_HOST_PINTENCLR_STALL_Pos)
+#define USB_HOST_PINTENCLR_MASK _U_(0x3F) /**< \brief (USB_HOST_PINTENCLR) MASK Register */
+
+/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTENSET_OFFSET 0x109 /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+#define USB_DEVICE_EPINTENSET_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+
+#define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT0 (_U_(1) << USB_DEVICE_EPINTENSET_TRCPT0_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT1 (_U_(1) << USB_DEVICE_EPINTENSET_TRCPT1_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_TRCPT_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT(value) (USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos))
+#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL(value) (USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos))
+#define USB_DEVICE_EPINTENSET_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_RXSTP (_U_(0x1) << USB_DEVICE_EPINTENSET_RXSTP_Pos)
+#define USB_DEVICE_EPINTENSET_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL0 (_U_(1) << USB_DEVICE_EPINTENSET_STALL0_Pos)
+#define USB_DEVICE_EPINTENSET_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL1 (_U_(1) << USB_DEVICE_EPINTENSET_STALL1_Pos)
+#define USB_DEVICE_EPINTENSET_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_STALL_Pos)
+#define USB_DEVICE_EPINTENSET_STALL(value) (USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos))
+#define USB_DEVICE_EPINTENSET_MASK _U_(0x7F) /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */
+
+/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */
+ uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTENSET_OFFSET 0x109 /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */
+#define USB_HOST_PINTENSET_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */
+
+#define USB_HOST_PINTENSET_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT0 (_U_(1) << USB_HOST_PINTENSET_TRCPT0_Pos)
+#define USB_HOST_PINTENSET_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT1 (_U_(1) << USB_HOST_PINTENSET_TRCPT1_Pos)
+#define USB_HOST_PINTENSET_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTENSET_TRCPT_Pos)
+#define USB_HOST_PINTENSET_TRCPT(value) (USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos))
+#define USB_HOST_PINTENSET_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */
+#define USB_HOST_PINTENSET_TRFAIL (_U_(0x1) << USB_HOST_PINTENSET_TRFAIL_Pos)
+#define USB_HOST_PINTENSET_PERR_Pos 3 /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */
+#define USB_HOST_PINTENSET_PERR (_U_(0x1) << USB_HOST_PINTENSET_PERR_Pos)
+#define USB_HOST_PINTENSET_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable */
+#define USB_HOST_PINTENSET_TXSTP (_U_(0x1) << USB_HOST_PINTENSET_TXSTP_Pos)
+#define USB_HOST_PINTENSET_STALL_Pos 5 /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */
+#define USB_HOST_PINTENSET_STALL (_U_(0x1) << USB_HOST_PINTENSET_STALL_Pos)
+#define USB_HOST_PINTENSET_MASK _U_(0x3F) /**< \brief (USB_HOST_PINTENSET) MASK Register */
+
+/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_DEVICE_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_ADDR_OFFSET 0x000 /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+
+#define USB_DEVICE_ADDR_ADDR_Pos 0 /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */
+#define USB_DEVICE_ADDR_ADDR_Msk (_U_(0xFFFFFFFF) << USB_DEVICE_ADDR_ADDR_Pos)
+#define USB_DEVICE_ADDR_ADDR(value) (USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos))
+#define USB_DEVICE_ADDR_MASK _U_(0xFFFFFFFF) /**< \brief (USB_DEVICE_ADDR) MASK Register */
+
+/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_HOST_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_ADDR_OFFSET 0x000 /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+
+#define USB_HOST_ADDR_ADDR_Pos 0 /**< \brief (USB_HOST_ADDR) Adress of data buffer */
+#define USB_HOST_ADDR_ADDR_Msk (_U_(0xFFFFFFFF) << USB_HOST_ADDR_ADDR_Pos)
+#define USB_HOST_ADDR_ADDR(value) (USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos))
+#define USB_HOST_ADDR_MASK _U_(0xFFFFFFFF) /**< \brief (USB_HOST_ADDR) MASK Register */
+
+/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
+ uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
+ uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */
+ uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_DEVICE_PCKSIZE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_PCKSIZE_OFFSET 0x004 /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (_U_(0x3FFF) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos))
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U_(0x3FFF) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos))
+#define USB_DEVICE_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */
+#define USB_DEVICE_PCKSIZE_SIZE_Msk (_U_(0x7) << USB_DEVICE_PCKSIZE_SIZE_Pos)
+#define USB_DEVICE_PCKSIZE_SIZE(value) (USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos))
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP (_U_(0x1) << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)
+#define USB_DEVICE_PCKSIZE_MASK _U_(0xFFFFFFFF) /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */
+
+/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
+ uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
+ uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */
+ uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_HOST_PCKSIZE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PCKSIZE_OFFSET 0x004 /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */
+
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_HOST_PCKSIZE) Byte Count */
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (_U_(0x3FFF) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)
+#define USB_HOST_PCKSIZE_BYTE_COUNT(value) (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos))
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U_(0x3FFF) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos))
+#define USB_HOST_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_HOST_PCKSIZE) Pipe size */
+#define USB_HOST_PCKSIZE_SIZE_Msk (_U_(0x7) << USB_HOST_PCKSIZE_SIZE_Pos)
+#define USB_HOST_PCKSIZE_SIZE(value) (USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos))
+#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */
+#define USB_HOST_PCKSIZE_AUTO_ZLP (_U_(0x1) << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)
+#define USB_HOST_PCKSIZE_MASK _U_(0xFFFFFFFF) /**< \brief (USB_HOST_PCKSIZE) MASK Register */
+
+/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
+ uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_EXTREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EXTREG_OFFSET 0x008 /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */
+
+#define USB_DEVICE_EXTREG_SUBPID_Pos 0 /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */
+#define USB_DEVICE_EXTREG_SUBPID_Msk (_U_(0xF) << USB_DEVICE_EXTREG_SUBPID_Pos)
+#define USB_DEVICE_EXTREG_SUBPID(value) (USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos))
+#define USB_DEVICE_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */
+#define USB_DEVICE_EXTREG_VARIABLE_Msk (_U_(0x7FF) << USB_DEVICE_EXTREG_VARIABLE_Pos)
+#define USB_DEVICE_EXTREG_VARIABLE(value) (USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos))
+#define USB_DEVICE_EXTREG_MASK _U_(0x7FFF) /**< \brief (USB_DEVICE_EXTREG) MASK Register */
+
+/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
+ uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_EXTREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_EXTREG_OFFSET 0x008 /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */
+
+#define USB_HOST_EXTREG_SUBPID_Pos 0 /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */
+#define USB_HOST_EXTREG_SUBPID_Msk (_U_(0xF) << USB_HOST_EXTREG_SUBPID_Pos)
+#define USB_HOST_EXTREG_SUBPID(value) (USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos))
+#define USB_HOST_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */
+#define USB_HOST_EXTREG_VARIABLE_Msk (_U_(0x7FF) << USB_HOST_EXTREG_VARIABLE_Pos)
+#define USB_HOST_EXTREG_VARIABLE(value) (USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos))
+#define USB_HOST_EXTREG_MASK _U_(0x7FFF) /**< \brief (USB_HOST_EXTREG) MASK Register */
+
+/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
+ uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_STATUS_BK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_STATUS_BK_OFFSET 0x00A /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+
+#define USB_DEVICE_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */
+#define USB_DEVICE_STATUS_BK_CRCERR (_U_(0x1) << USB_DEVICE_STATUS_BK_CRCERR_Pos)
+#define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */
+#define USB_DEVICE_STATUS_BK_ERRORFLOW (_U_(0x1) << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos)
+#define USB_DEVICE_STATUS_BK_MASK _U_(0x03) /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */
+
+/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
+ uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_STATUS_BK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_BK_OFFSET 0x00A /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */
+
+#define USB_HOST_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */
+#define USB_HOST_STATUS_BK_CRCERR (_U_(0x1) << USB_HOST_STATUS_BK_CRCERR_Pos)
+#define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */
+#define USB_HOST_STATUS_BK_ERRORFLOW (_U_(0x1) << USB_HOST_STATUS_BK_ERRORFLOW_Pos)
+#define USB_HOST_STATUS_BK_MASK _U_(0x03) /**< \brief (USB_HOST_STATUS_BK) MASK Register */
+
+/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */
+ uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_CTRL_PIPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_CTRL_PIPE_OFFSET 0x00C /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */
+#define USB_HOST_CTRL_PIPE_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */
+
+#define USB_HOST_CTRL_PIPE_PDADDR_Pos 0 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */
+#define USB_HOST_CTRL_PIPE_PDADDR_Msk (_U_(0x7F) << USB_HOST_CTRL_PIPE_PDADDR_Pos)
+#define USB_HOST_CTRL_PIPE_PDADDR(value) (USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos))
+#define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */
+#define USB_HOST_CTRL_PIPE_PEPNUM_Msk (_U_(0xF) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)
+#define USB_HOST_CTRL_PIPE_PEPNUM(value) (USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos))
+#define USB_HOST_CTRL_PIPE_PERMAX_Pos 12 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */
+#define USB_HOST_CTRL_PIPE_PERMAX_Msk (_U_(0xF) << USB_HOST_CTRL_PIPE_PERMAX_Pos)
+#define USB_HOST_CTRL_PIPE_PERMAX(value) (USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos))
+#define USB_HOST_CTRL_PIPE_MASK _U_(0xFF7F) /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */
+
+/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */
+ uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */
+ uint16_t PIDER:1; /*!< bit: 2 PID Error */
+ uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */
+ uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */
+ uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_STATUS_PIPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_PIPE_OFFSET 0x00E /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */
+
+#define USB_HOST_STATUS_PIPE_DTGLER_Pos 0 /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */
+#define USB_HOST_STATUS_PIPE_DTGLER (_U_(0x1) << USB_HOST_STATUS_PIPE_DTGLER_Pos)
+#define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1 /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */
+#define USB_HOST_STATUS_PIPE_DAPIDER (_U_(0x1) << USB_HOST_STATUS_PIPE_DAPIDER_Pos)
+#define USB_HOST_STATUS_PIPE_PIDER_Pos 2 /**< \brief (USB_HOST_STATUS_PIPE) PID Error */
+#define USB_HOST_STATUS_PIPE_PIDER (_U_(0x1) << USB_HOST_STATUS_PIPE_PIDER_Pos)
+#define USB_HOST_STATUS_PIPE_TOUTER_Pos 3 /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */
+#define USB_HOST_STATUS_PIPE_TOUTER (_U_(0x1) << USB_HOST_STATUS_PIPE_TOUTER_Pos)
+#define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4 /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */
+#define USB_HOST_STATUS_PIPE_CRC16ER (_U_(0x1) << USB_HOST_STATUS_PIPE_CRC16ER_Pos)
+#define USB_HOST_STATUS_PIPE_ERCNT_Pos 5 /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */
+#define USB_HOST_STATUS_PIPE_ERCNT_Msk (_U_(0x7) << USB_HOST_STATUS_PIPE_ERCNT_Pos)
+#define USB_HOST_STATUS_PIPE_ERCNT(value) (USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos))
+#define USB_HOST_STATUS_PIPE_MASK _U_(0x00FF) /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */
+
+/** \brief UsbDeviceDescBank SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+ __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+ __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
+ __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+ RoReg8 Reserved1[0x5];
+} UsbDeviceDescBank;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbHostDescBank SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+ __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
+ __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
+ __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */
+ RoReg8 Reserved1[0x1];
+ __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
+ __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
+} UsbHostDescBank;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbDeviceEndpoint hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */
+ RoReg8 Reserved1[0x3];
+ __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */
+ __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */
+ __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */
+ __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */
+ __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+ __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+ RoReg8 Reserved2[0x16];
+} UsbDeviceEndpoint;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbHostPipe hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */
+ RoReg8 Reserved1[0x2];
+ __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */
+ __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */
+ __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */
+ __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */
+ __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */
+ __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */
+ __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */
+ RoReg8 Reserved2[0x16];
+} UsbHostPipe;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_DEVICE APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Device */
+ __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ RoReg8 Reserved1[0x1];
+ __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
+ __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
+ RoReg8 Reserved2[0x4];
+ __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
+ __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */
+ RoReg8 Reserved3[0x1];
+ __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */
+ __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
+ RoReg8 Reserved4[0x2];
+ __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */
+ RoReg8 Reserved5[0x2];
+ __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
+ RoReg8 Reserved6[0x2];
+ __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
+ RoReg8 Reserved7[0x2];
+ __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
+ RoReg8 Reserved8[0x2];
+ __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */
+ RoReg8 Reserved9[0x2];
+ __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+ __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+ RoReg8 Reserved10[0xD6];
+ UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
+} UsbDevice;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_HOST hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Host */
+ __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ RoReg8 Reserved1[0x1];
+ __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
+ __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
+ RoReg8 Reserved2[0x4];
+ __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
+ __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */
+ RoReg8 Reserved3[0x1];
+ __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */
+ __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
+ RoReg8 Reserved4[0x2];
+ __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
+ __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */
+ RoReg8 Reserved5[0x1];
+ __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
+ RoReg8 Reserved6[0x2];
+ __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
+ RoReg8 Reserved7[0x2];
+ __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
+ RoReg8 Reserved8[0x2];
+ __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */
+ RoReg8 Reserved9[0x2];
+ __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+ __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+ RoReg8 Reserved10[0xD6];
+ UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [PIPE_NUM*HOST_IMPLEMENTED] */
+} UsbHost;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_DEVICE Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Device */
+ UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
+} UsbDeviceDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_HOST Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Host */
+ UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
+} UsbHostDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_USB_DESCRIPTOR
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */
+ UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */
+} Usb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_USB_COMPONENT_ */
diff --git a/sysmoOCTSIM/include/component/wdt.h b/sysmoOCTSIM/include/component/wdt.h
index d915474..08b2736 100644
--- a/sysmoOCTSIM/include/component/wdt.h
+++ b/sysmoOCTSIM/include/component/wdt.h
@@ -1,300 +1,300 @@
-/**
- * \file
- *
- * \brief Component description for WDT
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAME54_WDT_COMPONENT_
-#define _SAME54_WDT_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR WDT */
-/* ========================================================================== */
-/** \addtogroup SAME54_WDT Watchdog Timer */
-/*@{*/
-
-#define WDT_U2251
-#define REV_WDT 0x110
-
-/* -------- WDT_CTRLA : (WDT Offset: 0x0) (R/W 8) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t :1; /*!< bit: 0 Reserved */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} WDT_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_CTRLA_OFFSET 0x0 /**< \brief (WDT_CTRLA offset) Control */
-#define WDT_CTRLA_RESETVALUE _U_(0x00) /**< \brief (WDT_CTRLA reset_value) Control */
-
-#define WDT_CTRLA_ENABLE_Pos 1 /**< \brief (WDT_CTRLA) Enable */
-#define WDT_CTRLA_ENABLE (_U_(0x1) << WDT_CTRLA_ENABLE_Pos)
-#define WDT_CTRLA_WEN_Pos 2 /**< \brief (WDT_CTRLA) Watchdog Timer Window Mode Enable */
-#define WDT_CTRLA_WEN (_U_(0x1) << WDT_CTRLA_WEN_Pos)
-#define WDT_CTRLA_ALWAYSON_Pos 7 /**< \brief (WDT_CTRLA) Always-On */
-#define WDT_CTRLA_ALWAYSON (_U_(0x1) << WDT_CTRLA_ALWAYSON_Pos)
-#define WDT_CTRLA_MASK _U_(0x86) /**< \brief (WDT_CTRLA) MASK Register */
-
-/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
- uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} WDT_CONFIG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */
-#define WDT_CONFIG_RESETVALUE _U_(0xBB) /**< \brief (WDT_CONFIG reset_value) Configuration */
-
-#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */
-#define WDT_CONFIG_PER_Msk (_U_(0xF) << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
-#define WDT_CONFIG_PER_CYC8_Val _U_(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */
-#define WDT_CONFIG_PER_CYC16_Val _U_(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */
-#define WDT_CONFIG_PER_CYC32_Val _U_(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */
-#define WDT_CONFIG_PER_CYC64_Val _U_(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */
-#define WDT_CONFIG_PER_CYC128_Val _U_(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */
-#define WDT_CONFIG_PER_CYC256_Val _U_(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */
-#define WDT_CONFIG_PER_CYC512_Val _U_(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */
-#define WDT_CONFIG_PER_CYC1024_Val _U_(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */
-#define WDT_CONFIG_PER_CYC2048_Val _U_(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */
-#define WDT_CONFIG_PER_CYC4096_Val _U_(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */
-#define WDT_CONFIG_PER_CYC8192_Val _U_(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */
-#define WDT_CONFIG_PER_CYC16384_Val _U_(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */
-#define WDT_CONFIG_PER_CYC8 (WDT_CONFIG_PER_CYC8_Val << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC16 (WDT_CONFIG_PER_CYC16_Val << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC32 (WDT_CONFIG_PER_CYC32_Val << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC64 (WDT_CONFIG_PER_CYC64_Val << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC128 (WDT_CONFIG_PER_CYC128_Val << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC256 (WDT_CONFIG_PER_CYC256_Val << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC512 (WDT_CONFIG_PER_CYC512_Val << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC1024 (WDT_CONFIG_PER_CYC1024_Val << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC2048 (WDT_CONFIG_PER_CYC2048_Val << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC4096 (WDT_CONFIG_PER_CYC4096_Val << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC8192 (WDT_CONFIG_PER_CYC8192_Val << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC16384 (WDT_CONFIG_PER_CYC16384_Val << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
-#define WDT_CONFIG_WINDOW_Msk (_U_(0xF) << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
-#define WDT_CONFIG_WINDOW_CYC8_Val _U_(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */
-#define WDT_CONFIG_WINDOW_CYC16_Val _U_(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */
-#define WDT_CONFIG_WINDOW_CYC32_Val _U_(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */
-#define WDT_CONFIG_WINDOW_CYC64_Val _U_(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */
-#define WDT_CONFIG_WINDOW_CYC128_Val _U_(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */
-#define WDT_CONFIG_WINDOW_CYC256_Val _U_(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */
-#define WDT_CONFIG_WINDOW_CYC512_Val _U_(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */
-#define WDT_CONFIG_WINDOW_CYC1024_Val _U_(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */
-#define WDT_CONFIG_WINDOW_CYC2048_Val _U_(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */
-#define WDT_CONFIG_WINDOW_CYC4096_Val _U_(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */
-#define WDT_CONFIG_WINDOW_CYC8192_Val _U_(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */
-#define WDT_CONFIG_WINDOW_CYC16384_Val _U_(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */
-#define WDT_CONFIG_WINDOW_CYC8 (WDT_CONFIG_WINDOW_CYC8_Val << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC16 (WDT_CONFIG_WINDOW_CYC16_Val << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC32 (WDT_CONFIG_WINDOW_CYC32_Val << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC64 (WDT_CONFIG_WINDOW_CYC64_Val << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC128 (WDT_CONFIG_WINDOW_CYC128_Val << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC256 (WDT_CONFIG_WINDOW_CYC256_Val << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC512 (WDT_CONFIG_WINDOW_CYC512_Val << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC1024 (WDT_CONFIG_WINDOW_CYC1024_Val << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC2048 (WDT_CONFIG_WINDOW_CYC2048_Val << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC4096 (WDT_CONFIG_WINDOW_CYC4096_Val << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC8192 (WDT_CONFIG_WINDOW_CYC8192_Val << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC16384 (WDT_CONFIG_WINDOW_CYC16384_Val << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_MASK _U_(0xFF) /**< \brief (WDT_CONFIG) MASK Register */
-
-/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} WDT_EWCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
-#define WDT_EWCTRL_RESETVALUE _U_(0x0B) /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
-
-#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
-#define WDT_EWCTRL_EWOFFSET_Msk (_U_(0xF) << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
-#define WDT_EWCTRL_EWOFFSET_CYC8_Val _U_(0x0) /**< \brief (WDT_EWCTRL) 8 clock cycles */
-#define WDT_EWCTRL_EWOFFSET_CYC16_Val _U_(0x1) /**< \brief (WDT_EWCTRL) 16 clock cycles */
-#define WDT_EWCTRL_EWOFFSET_CYC32_Val _U_(0x2) /**< \brief (WDT_EWCTRL) 32 clock cycles */
-#define WDT_EWCTRL_EWOFFSET_CYC64_Val _U_(0x3) /**< \brief (WDT_EWCTRL) 64 clock cycles */
-#define WDT_EWCTRL_EWOFFSET_CYC128_Val _U_(0x4) /**< \brief (WDT_EWCTRL) 128 clock cycles */
-#define WDT_EWCTRL_EWOFFSET_CYC256_Val _U_(0x5) /**< \brief (WDT_EWCTRL) 256 clock cycles */
-#define WDT_EWCTRL_EWOFFSET_CYC512_Val _U_(0x6) /**< \brief (WDT_EWCTRL) 512 clock cycles */
-#define WDT_EWCTRL_EWOFFSET_CYC1024_Val _U_(0x7) /**< \brief (WDT_EWCTRL) 1024 clock cycles */
-#define WDT_EWCTRL_EWOFFSET_CYC2048_Val _U_(0x8) /**< \brief (WDT_EWCTRL) 2048 clock cycles */
-#define WDT_EWCTRL_EWOFFSET_CYC4096_Val _U_(0x9) /**< \brief (WDT_EWCTRL) 4096 clock cycles */
-#define WDT_EWCTRL_EWOFFSET_CYC8192_Val _U_(0xA) /**< \brief (WDT_EWCTRL) 8192 clock cycles */
-#define WDT_EWCTRL_EWOFFSET_CYC16384_Val _U_(0xB) /**< \brief (WDT_EWCTRL) 16384 clock cycles */
-#define WDT_EWCTRL_EWOFFSET_CYC8 (WDT_EWCTRL_EWOFFSET_CYC8_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC16 (WDT_EWCTRL_EWOFFSET_CYC16_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC32 (WDT_EWCTRL_EWOFFSET_CYC32_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC64 (WDT_EWCTRL_EWOFFSET_CYC64_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC128 (WDT_EWCTRL_EWOFFSET_CYC128_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC256 (WDT_EWCTRL_EWOFFSET_CYC256_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC512 (WDT_EWCTRL_EWOFFSET_CYC512_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC1024 (WDT_EWCTRL_EWOFFSET_CYC1024_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC2048 (WDT_EWCTRL_EWOFFSET_CYC2048_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC4096 (WDT_EWCTRL_EWOFFSET_CYC4096_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC8192 (WDT_EWCTRL_EWOFFSET_CYC8192_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC16384 (WDT_EWCTRL_EWOFFSET_CYC16384_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_MASK _U_(0x0F) /**< \brief (WDT_EWCTRL) MASK Register */
-
-/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} WDT_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
-#define WDT_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
-#define WDT_INTENCLR_EW (_U_(0x1) << WDT_INTENCLR_EW_Pos)
-#define WDT_INTENCLR_MASK _U_(0x01) /**< \brief (WDT_INTENCLR) MASK Register */
-
-/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} WDT_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
-#define WDT_INTENSET_RESETVALUE _U_(0x00) /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
-
-#define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
-#define WDT_INTENSET_EW (_U_(0x1) << WDT_INTENSET_EW_Pos)
-#define WDT_INTENSET_MASK _U_(0x01) /**< \brief (WDT_INTENSET) MASK Register */
-
-/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t EW:1; /*!< bit: 0 Early Warning */
- __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} WDT_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
-#define WDT_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */
-#define WDT_INTFLAG_EW (_U_(0x1) << WDT_INTFLAG_EW_Pos)
-#define WDT_INTFLAG_MASK _U_(0x01) /**< \brief (WDT_INTFLAG) MASK Register */
-
-/* -------- WDT_SYNCBUSY : (WDT Offset: 0x8) (R/ 32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
- uint32_t WEN:1; /*!< bit: 2 Window Enable Synchronization Busy */
- uint32_t ALWAYSON:1; /*!< bit: 3 Always-On Synchronization Busy */
- uint32_t CLEAR:1; /*!< bit: 4 Clear Synchronization Busy */
- uint32_t :27; /*!< bit: 5..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} WDT_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_SYNCBUSY_OFFSET 0x8 /**< \brief (WDT_SYNCBUSY offset) Synchronization Busy */
-#define WDT_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (WDT_SYNCBUSY reset_value) Synchronization Busy */
-
-#define WDT_SYNCBUSY_ENABLE_Pos 1 /**< \brief (WDT_SYNCBUSY) Enable Synchronization Busy */
-#define WDT_SYNCBUSY_ENABLE (_U_(0x1) << WDT_SYNCBUSY_ENABLE_Pos)
-#define WDT_SYNCBUSY_WEN_Pos 2 /**< \brief (WDT_SYNCBUSY) Window Enable Synchronization Busy */
-#define WDT_SYNCBUSY_WEN (_U_(0x1) << WDT_SYNCBUSY_WEN_Pos)
-#define WDT_SYNCBUSY_ALWAYSON_Pos 3 /**< \brief (WDT_SYNCBUSY) Always-On Synchronization Busy */
-#define WDT_SYNCBUSY_ALWAYSON (_U_(0x1) << WDT_SYNCBUSY_ALWAYSON_Pos)
-#define WDT_SYNCBUSY_CLEAR_Pos 4 /**< \brief (WDT_SYNCBUSY) Clear Synchronization Busy */
-#define WDT_SYNCBUSY_CLEAR (_U_(0x1) << WDT_SYNCBUSY_CLEAR_Pos)
-#define WDT_SYNCBUSY_MASK _U_(0x0000001E) /**< \brief (WDT_SYNCBUSY) MASK Register */
-
-/* -------- WDT_CLEAR : (WDT Offset: 0xC) ( /W 8) Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} WDT_CLEAR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_CLEAR_OFFSET 0xC /**< \brief (WDT_CLEAR offset) Clear */
-#define WDT_CLEAR_RESETVALUE _U_(0x00) /**< \brief (WDT_CLEAR reset_value) Clear */
-
-#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */
-#define WDT_CLEAR_CLEAR_Msk (_U_(0xFF) << WDT_CLEAR_CLEAR_Pos)
-#define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
-#define WDT_CLEAR_CLEAR_KEY_Val _U_(0xA5) /**< \brief (WDT_CLEAR) Clear Key */
-#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)
-#define WDT_CLEAR_MASK _U_(0xFF) /**< \brief (WDT_CLEAR) MASK Register */
-
-/** \brief WDT hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO WDT_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control */
- __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
- __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
- RoReg8 Reserved1[0x1];
- __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
- __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
- __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
- RoReg8 Reserved2[0x1];
- __I WDT_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x8 (R/ 32) Synchronization Busy */
- __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0xC ( /W 8) Clear */
-} Wdt;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAME54_WDT_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for WDT
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_WDT_COMPONENT_
+#define _SAME54_WDT_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR WDT */
+/* ========================================================================== */
+/** \addtogroup SAME54_WDT Watchdog Timer */
+/*@{*/
+
+#define WDT_U2251
+#define REV_WDT 0x110
+
+/* -------- WDT_CTRLA : (WDT Offset: 0x0) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CTRLA_OFFSET 0x0 /**< \brief (WDT_CTRLA offset) Control */
+#define WDT_CTRLA_RESETVALUE _U_(0x00) /**< \brief (WDT_CTRLA reset_value) Control */
+
+#define WDT_CTRLA_ENABLE_Pos 1 /**< \brief (WDT_CTRLA) Enable */
+#define WDT_CTRLA_ENABLE (_U_(0x1) << WDT_CTRLA_ENABLE_Pos)
+#define WDT_CTRLA_WEN_Pos 2 /**< \brief (WDT_CTRLA) Watchdog Timer Window Mode Enable */
+#define WDT_CTRLA_WEN (_U_(0x1) << WDT_CTRLA_WEN_Pos)
+#define WDT_CTRLA_ALWAYSON_Pos 7 /**< \brief (WDT_CTRLA) Always-On */
+#define WDT_CTRLA_ALWAYSON (_U_(0x1) << WDT_CTRLA_ALWAYSON_Pos)
+#define WDT_CTRLA_MASK _U_(0x86) /**< \brief (WDT_CTRLA) MASK Register */
+
+/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
+ uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */
+#define WDT_CONFIG_RESETVALUE _U_(0xBB) /**< \brief (WDT_CONFIG reset_value) Configuration */
+
+#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */
+#define WDT_CONFIG_PER_Msk (_U_(0xF) << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
+#define WDT_CONFIG_PER_CYC8_Val _U_(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define WDT_CONFIG_PER_CYC16_Val _U_(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define WDT_CONFIG_PER_CYC32_Val _U_(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define WDT_CONFIG_PER_CYC64_Val _U_(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define WDT_CONFIG_PER_CYC128_Val _U_(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define WDT_CONFIG_PER_CYC256_Val _U_(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define WDT_CONFIG_PER_CYC512_Val _U_(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define WDT_CONFIG_PER_CYC1024_Val _U_(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define WDT_CONFIG_PER_CYC2048_Val _U_(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define WDT_CONFIG_PER_CYC4096_Val _U_(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define WDT_CONFIG_PER_CYC8192_Val _U_(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define WDT_CONFIG_PER_CYC16384_Val _U_(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_PER_CYC8 (WDT_CONFIG_PER_CYC8_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC16 (WDT_CONFIG_PER_CYC16_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC32 (WDT_CONFIG_PER_CYC32_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC64 (WDT_CONFIG_PER_CYC64_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC128 (WDT_CONFIG_PER_CYC128_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC256 (WDT_CONFIG_PER_CYC256_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC512 (WDT_CONFIG_PER_CYC512_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC1024 (WDT_CONFIG_PER_CYC1024_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC2048 (WDT_CONFIG_PER_CYC2048_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC4096 (WDT_CONFIG_PER_CYC4096_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC8192 (WDT_CONFIG_PER_CYC8192_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC16384 (WDT_CONFIG_PER_CYC16384_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
+#define WDT_CONFIG_WINDOW_Msk (_U_(0xF) << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
+#define WDT_CONFIG_WINDOW_CYC8_Val _U_(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC16_Val _U_(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC32_Val _U_(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC64_Val _U_(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC128_Val _U_(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC256_Val _U_(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC512_Val _U_(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC1024_Val _U_(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC2048_Val _U_(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC4096_Val _U_(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC8192_Val _U_(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC16384_Val _U_(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC8 (WDT_CONFIG_WINDOW_CYC8_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC16 (WDT_CONFIG_WINDOW_CYC16_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC32 (WDT_CONFIG_WINDOW_CYC32_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC64 (WDT_CONFIG_WINDOW_CYC64_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC128 (WDT_CONFIG_WINDOW_CYC128_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC256 (WDT_CONFIG_WINDOW_CYC256_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC512 (WDT_CONFIG_WINDOW_CYC512_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC1024 (WDT_CONFIG_WINDOW_CYC1024_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC2048 (WDT_CONFIG_WINDOW_CYC2048_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC4096 (WDT_CONFIG_WINDOW_CYC4096_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC8192 (WDT_CONFIG_WINDOW_CYC8192_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC16384 (WDT_CONFIG_WINDOW_CYC16384_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_MASK _U_(0xFF) /**< \brief (WDT_CONFIG) MASK Register */
+
+/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_EWCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
+#define WDT_EWCTRL_RESETVALUE _U_(0x0B) /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
+
+#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
+#define WDT_EWCTRL_EWOFFSET_Msk (_U_(0xF) << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
+#define WDT_EWCTRL_EWOFFSET_CYC8_Val _U_(0x0) /**< \brief (WDT_EWCTRL) 8 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC16_Val _U_(0x1) /**< \brief (WDT_EWCTRL) 16 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC32_Val _U_(0x2) /**< \brief (WDT_EWCTRL) 32 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC64_Val _U_(0x3) /**< \brief (WDT_EWCTRL) 64 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC128_Val _U_(0x4) /**< \brief (WDT_EWCTRL) 128 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC256_Val _U_(0x5) /**< \brief (WDT_EWCTRL) 256 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC512_Val _U_(0x6) /**< \brief (WDT_EWCTRL) 512 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC1024_Val _U_(0x7) /**< \brief (WDT_EWCTRL) 1024 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC2048_Val _U_(0x8) /**< \brief (WDT_EWCTRL) 2048 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC4096_Val _U_(0x9) /**< \brief (WDT_EWCTRL) 4096 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC8192_Val _U_(0xA) /**< \brief (WDT_EWCTRL) 8192 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC16384_Val _U_(0xB) /**< \brief (WDT_EWCTRL) 16384 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC8 (WDT_EWCTRL_EWOFFSET_CYC8_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC16 (WDT_EWCTRL_EWOFFSET_CYC16_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC32 (WDT_EWCTRL_EWOFFSET_CYC32_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC64 (WDT_EWCTRL_EWOFFSET_CYC64_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC128 (WDT_EWCTRL_EWOFFSET_CYC128_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC256 (WDT_EWCTRL_EWOFFSET_CYC256_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC512 (WDT_EWCTRL_EWOFFSET_CYC512_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC1024 (WDT_EWCTRL_EWOFFSET_CYC1024_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC2048 (WDT_EWCTRL_EWOFFSET_CYC2048_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC4096 (WDT_EWCTRL_EWOFFSET_CYC4096_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC8192 (WDT_EWCTRL_EWOFFSET_CYC8192_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC16384 (WDT_EWCTRL_EWOFFSET_CYC16384_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_MASK _U_(0x0F) /**< \brief (WDT_EWCTRL) MASK Register */
+
+/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
+#define WDT_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
+#define WDT_INTENCLR_EW (_U_(0x1) << WDT_INTENCLR_EW_Pos)
+#define WDT_INTENCLR_MASK _U_(0x01) /**< \brief (WDT_INTENCLR) MASK Register */
+
+/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
+#define WDT_INTENSET_RESETVALUE _U_(0x00) /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
+
+#define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
+#define WDT_INTENSET_EW (_U_(0x1) << WDT_INTENSET_EW_Pos)
+#define WDT_INTENSET_MASK _U_(0x01) /**< \brief (WDT_INTENSET) MASK Register */
+
+/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t EW:1; /*!< bit: 0 Early Warning */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
+#define WDT_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */
+#define WDT_INTFLAG_EW (_U_(0x1) << WDT_INTFLAG_EW_Pos)
+#define WDT_INTFLAG_MASK _U_(0x01) /**< \brief (WDT_INTFLAG) MASK Register */
+
+/* -------- WDT_SYNCBUSY : (WDT Offset: 0x8) (R/ 32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
+ uint32_t WEN:1; /*!< bit: 2 Window Enable Synchronization Busy */
+ uint32_t ALWAYSON:1; /*!< bit: 3 Always-On Synchronization Busy */
+ uint32_t CLEAR:1; /*!< bit: 4 Clear Synchronization Busy */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} WDT_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_SYNCBUSY_OFFSET 0x8 /**< \brief (WDT_SYNCBUSY offset) Synchronization Busy */
+#define WDT_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (WDT_SYNCBUSY reset_value) Synchronization Busy */
+
+#define WDT_SYNCBUSY_ENABLE_Pos 1 /**< \brief (WDT_SYNCBUSY) Enable Synchronization Busy */
+#define WDT_SYNCBUSY_ENABLE (_U_(0x1) << WDT_SYNCBUSY_ENABLE_Pos)
+#define WDT_SYNCBUSY_WEN_Pos 2 /**< \brief (WDT_SYNCBUSY) Window Enable Synchronization Busy */
+#define WDT_SYNCBUSY_WEN (_U_(0x1) << WDT_SYNCBUSY_WEN_Pos)
+#define WDT_SYNCBUSY_ALWAYSON_Pos 3 /**< \brief (WDT_SYNCBUSY) Always-On Synchronization Busy */
+#define WDT_SYNCBUSY_ALWAYSON (_U_(0x1) << WDT_SYNCBUSY_ALWAYSON_Pos)
+#define WDT_SYNCBUSY_CLEAR_Pos 4 /**< \brief (WDT_SYNCBUSY) Clear Synchronization Busy */
+#define WDT_SYNCBUSY_CLEAR (_U_(0x1) << WDT_SYNCBUSY_CLEAR_Pos)
+#define WDT_SYNCBUSY_MASK _U_(0x0000001E) /**< \brief (WDT_SYNCBUSY) MASK Register */
+
+/* -------- WDT_CLEAR : (WDT Offset: 0xC) ( /W 8) Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_CLEAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CLEAR_OFFSET 0xC /**< \brief (WDT_CLEAR offset) Clear */
+#define WDT_CLEAR_RESETVALUE _U_(0x00) /**< \brief (WDT_CLEAR reset_value) Clear */
+
+#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */
+#define WDT_CLEAR_CLEAR_Msk (_U_(0xFF) << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
+#define WDT_CLEAR_CLEAR_KEY_Val _U_(0xA5) /**< \brief (WDT_CLEAR) Clear Key */
+#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_MASK _U_(0xFF) /**< \brief (WDT_CLEAR) MASK Register */
+
+/** \brief WDT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO WDT_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control */
+ __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
+ __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
+ RoReg8 Reserved1[0x1];
+ __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
+ __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
+ __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved2[0x1];
+ __I WDT_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x8 (R/ 32) Synchronization Busy */
+ __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0xC ( /W 8) Clear */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_WDT_COMPONENT_ */