Update from Atmel START 1.0.87 to 1.1.134
Change-Id: I095f2f3f4de8ebba154b7d8f9f763a2fa6472ebd
diff --git a/sysmoOCTSIM/include/instance/dsu.h b/sysmoOCTSIM/include/instance/dsu.h
index 3c7ae23..80c09e6 100644
--- a/sysmoOCTSIM/include/instance/dsu.h
+++ b/sysmoOCTSIM/include/instance/dsu.h
@@ -3,7 +3,7 @@
*
* \brief Instance description for DSU
*
- * Copyright (c) 2018 Microchip Technology Inc.
+ * Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
@@ -42,8 +42,6 @@
#define REG_DSU_DCC1 (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */
#define REG_DSU_DID (0x41002018) /**< \brief (DSU) Device Identification */
#define REG_DSU_CFG (0x4100201C) /**< \brief (DSU) Configuration */
-#define REG_DSU_DCFG0 (0x410020F0) /**< \brief (DSU) Device Configuration 0 */
-#define REG_DSU_DCFG1 (0x410020F4) /**< \brief (DSU) Device Configuration 1 */
#define REG_DSU_ENTRY0 (0x41003000) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
#define REG_DSU_ENTRY1 (0x41003004) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
#define REG_DSU_END (0x41003008) /**< \brief (DSU) CoreSight ROM Table End */
@@ -71,8 +69,6 @@
#define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */
#define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identification */
#define REG_DSU_CFG (*(RwReg *)0x4100201CUL) /**< \brief (DSU) Configuration */
-#define REG_DSU_DCFG0 (*(RwReg *)0x410020F0UL) /**< \brief (DSU) Device Configuration 0 */
-#define REG_DSU_DCFG1 (*(RwReg *)0x410020F4UL) /**< \brief (DSU) Device Configuration 1 */
#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
#define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) CoreSight ROM Table End */
diff --git a/sysmoOCTSIM/include/instance/evsys.h b/sysmoOCTSIM/include/instance/evsys.h
index 20d127f..0c25ff2 100644
--- a/sysmoOCTSIM/include/instance/evsys.h
+++ b/sysmoOCTSIM/include/instance/evsys.h
@@ -3,7 +3,7 @@
*
* \brief Instance description for EVSYS
*
- * Copyright (c) 2018 Microchip Technology Inc.
+ * Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
@@ -572,65 +572,65 @@
#define EVSYS_ID_GEN_TCC0_OVF 41
#define EVSYS_ID_GEN_TCC0_TRG 42
#define EVSYS_ID_GEN_TCC0_CNT 43
-#define EVSYS_ID_GEN_TCC0_MCX_0 44
-#define EVSYS_ID_GEN_TCC0_MCX_1 45
-#define EVSYS_ID_GEN_TCC0_MCX_2 46
-#define EVSYS_ID_GEN_TCC0_MCX_3 47
-#define EVSYS_ID_GEN_TCC0_MCX_4 48
-#define EVSYS_ID_GEN_TCC0_MCX_5 49
+#define EVSYS_ID_GEN_TCC0_MC_0 44
+#define EVSYS_ID_GEN_TCC0_MC_1 45
+#define EVSYS_ID_GEN_TCC0_MC_2 46
+#define EVSYS_ID_GEN_TCC0_MC_3 47
+#define EVSYS_ID_GEN_TCC0_MC_4 48
+#define EVSYS_ID_GEN_TCC0_MC_5 49
#define EVSYS_ID_GEN_TCC1_OVF 50
#define EVSYS_ID_GEN_TCC1_TRG 51
#define EVSYS_ID_GEN_TCC1_CNT 52
-#define EVSYS_ID_GEN_TCC1_MCX_0 53
-#define EVSYS_ID_GEN_TCC1_MCX_1 54
-#define EVSYS_ID_GEN_TCC1_MCX_2 55
-#define EVSYS_ID_GEN_TCC1_MCX_3 56
+#define EVSYS_ID_GEN_TCC1_MC_0 53
+#define EVSYS_ID_GEN_TCC1_MC_1 54
+#define EVSYS_ID_GEN_TCC1_MC_2 55
+#define EVSYS_ID_GEN_TCC1_MC_3 56
#define EVSYS_ID_GEN_TCC2_OVF 57
#define EVSYS_ID_GEN_TCC2_TRG 58
#define EVSYS_ID_GEN_TCC2_CNT 59
-#define EVSYS_ID_GEN_TCC2_MCX_0 60
-#define EVSYS_ID_GEN_TCC2_MCX_1 61
-#define EVSYS_ID_GEN_TCC2_MCX_2 62
+#define EVSYS_ID_GEN_TCC2_MC_0 60
+#define EVSYS_ID_GEN_TCC2_MC_1 61
+#define EVSYS_ID_GEN_TCC2_MC_2 62
#define EVSYS_ID_GEN_TCC3_OVF 63
#define EVSYS_ID_GEN_TCC3_TRG 64
#define EVSYS_ID_GEN_TCC3_CNT 65
-#define EVSYS_ID_GEN_TCC3_MCX_0 66
-#define EVSYS_ID_GEN_TCC3_MCX_1 67
+#define EVSYS_ID_GEN_TCC3_MC_0 66
+#define EVSYS_ID_GEN_TCC3_MC_1 67
#define EVSYS_ID_GEN_TCC4_OVF 68
#define EVSYS_ID_GEN_TCC4_TRG 69
#define EVSYS_ID_GEN_TCC4_CNT 70
-#define EVSYS_ID_GEN_TCC4_MCX_0 71
-#define EVSYS_ID_GEN_TCC4_MCX_1 72
+#define EVSYS_ID_GEN_TCC4_MC_0 71
+#define EVSYS_ID_GEN_TCC4_MC_1 72
#define EVSYS_ID_GEN_TC0_OVF 73
-#define EVSYS_ID_GEN_TC0_MCX_0 74
-#define EVSYS_ID_GEN_TC0_MCX_1 75
+#define EVSYS_ID_GEN_TC0_MC_0 74
+#define EVSYS_ID_GEN_TC0_MC_1 75
#define EVSYS_ID_GEN_TC1_OVF 76
-#define EVSYS_ID_GEN_TC1_MCX_0 77
-#define EVSYS_ID_GEN_TC1_MCX_1 78
+#define EVSYS_ID_GEN_TC1_MC_0 77
+#define EVSYS_ID_GEN_TC1_MC_1 78
#define EVSYS_ID_GEN_TC2_OVF 79
-#define EVSYS_ID_GEN_TC2_MCX_0 80
-#define EVSYS_ID_GEN_TC2_MCX_1 81
+#define EVSYS_ID_GEN_TC2_MC_0 80
+#define EVSYS_ID_GEN_TC2_MC_1 81
#define EVSYS_ID_GEN_TC3_OVF 82
-#define EVSYS_ID_GEN_TC3_MCX_0 83
-#define EVSYS_ID_GEN_TC3_MCX_1 84
+#define EVSYS_ID_GEN_TC3_MC_0 83
+#define EVSYS_ID_GEN_TC3_MC_1 84
#define EVSYS_ID_GEN_TC4_OVF 85
-#define EVSYS_ID_GEN_TC4_MCX_0 86
-#define EVSYS_ID_GEN_TC4_MCX_1 87
+#define EVSYS_ID_GEN_TC4_MC_0 86
+#define EVSYS_ID_GEN_TC4_MC_1 87
#define EVSYS_ID_GEN_TC5_OVF 88
-#define EVSYS_ID_GEN_TC5_MCX_0 89
-#define EVSYS_ID_GEN_TC5_MCX_1 90
+#define EVSYS_ID_GEN_TC5_MC_0 89
+#define EVSYS_ID_GEN_TC5_MC_1 90
#define EVSYS_ID_GEN_TC6_OVF 91
-#define EVSYS_ID_GEN_TC6_MCX_0 92
-#define EVSYS_ID_GEN_TC6_MCX_1 93
+#define EVSYS_ID_GEN_TC6_MC_0 92
+#define EVSYS_ID_GEN_TC6_MC_1 93
#define EVSYS_ID_GEN_TC7_OVF 94
-#define EVSYS_ID_GEN_TC7_MCX_0 95
-#define EVSYS_ID_GEN_TC7_MCX_1 96
+#define EVSYS_ID_GEN_TC7_MC_0 95
+#define EVSYS_ID_GEN_TC7_MC_1 96
#define EVSYS_ID_GEN_PDEC_OVF 97
#define EVSYS_ID_GEN_PDEC_ERR 98
#define EVSYS_ID_GEN_PDEC_DIR 99
#define EVSYS_ID_GEN_PDEC_VLC 100
-#define EVSYS_ID_GEN_PDEC_MCX_0 101
-#define EVSYS_ID_GEN_PDEC_MCX_1 102
+#define EVSYS_ID_GEN_PDEC_MC_0 101
+#define EVSYS_ID_GEN_PDEC_MC_1 102
#define EVSYS_ID_GEN_ADC0_RESRDY 103
#define EVSYS_ID_GEN_ADC0_WINMON 104
#define EVSYS_ID_GEN_ADC1_RESRDY 105
diff --git a/sysmoOCTSIM/include/instance/sercom0.h b/sysmoOCTSIM/include/instance/sercom0.h
index afe95e6..61dbab5 100644
--- a/sysmoOCTSIM/include/instance/sercom0.h
+++ b/sysmoOCTSIM/include/instance/sercom0.h
@@ -3,7 +3,7 @@
*
* \brief Instance description for SERCOM0
*
- * Copyright (c) 2018 Microchip Technology Inc.
+ * Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
@@ -145,6 +145,18 @@
#define SERCOM0_GCLK_ID_CORE 7
#define SERCOM0_GCLK_ID_SLOW 3
#define SERCOM0_INT_MSB 6
+#define SERCOM0_I2CM 1 // I2C Master mode implemented?
+#define SERCOM0_I2CS 1 // I2C Slave mode implemented?
+#define SERCOM0_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
+#define SERCOM0_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
+#define SERCOM0_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
+#define SERCOM0_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
+#define SERCOM0_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
+#define SERCOM0_I2C_FASTMP 1 // I2C fast mode plus implemented?
+#define SERCOM0_I2C_HSMODE 1 // USART mode implemented?
+#define SERCOM0_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
+#define SERCOM0_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
+#define SERCOM0_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
#define SERCOM0_PMSB 3
#define SERCOM0_RETENTION_SUPPORT 0 // Retention supported?
#define SERCOM0_SE_CNT 1 // SE counter included?
@@ -154,18 +166,6 @@
#define SERCOM0_SPI_OZMO 0 // OZMO features implemented?
#define SERCOM0_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
#define SERCOM0_TTBIT_EXTENSION 1 // 32-bit extension implemented?
-#define SERCOM0_TWIM 1 // TWI Master mode implemented?
-#define SERCOM0_TWIS 1 // TWI Slave mode implemented?
-#define SERCOM0_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
-#define SERCOM0_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
-#define SERCOM0_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
-#define SERCOM0_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
-#define SERCOM0_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
-#define SERCOM0_TWI_FASTMP 1 // TWI fast mode plus implemented?
-#define SERCOM0_TWI_HSMODE 1 // USART mode implemented?
-#define SERCOM0_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
-#define SERCOM0_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
-#define SERCOM0_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
#define SERCOM0_USART 1 // USART mode implemented?
#define SERCOM0_USART_AUTOBAUD 1 // USART autobaud implemented?
#define SERCOM0_USART_COLDET 1 // USART collision detection implemented?
diff --git a/sysmoOCTSIM/include/instance/sercom1.h b/sysmoOCTSIM/include/instance/sercom1.h
index 72c7bda..82a9084 100644
--- a/sysmoOCTSIM/include/instance/sercom1.h
+++ b/sysmoOCTSIM/include/instance/sercom1.h
@@ -3,7 +3,7 @@
*
* \brief Instance description for SERCOM1
*
- * Copyright (c) 2018 Microchip Technology Inc.
+ * Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
@@ -145,6 +145,18 @@
#define SERCOM1_GCLK_ID_CORE 8
#define SERCOM1_GCLK_ID_SLOW 3
#define SERCOM1_INT_MSB 6
+#define SERCOM1_I2CM 1 // I2C Master mode implemented?
+#define SERCOM1_I2CS 1 // I2C Slave mode implemented?
+#define SERCOM1_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
+#define SERCOM1_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
+#define SERCOM1_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
+#define SERCOM1_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
+#define SERCOM1_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
+#define SERCOM1_I2C_FASTMP 1 // I2C fast mode plus implemented?
+#define SERCOM1_I2C_HSMODE 1 // USART mode implemented?
+#define SERCOM1_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
+#define SERCOM1_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
+#define SERCOM1_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
#define SERCOM1_PMSB 3
#define SERCOM1_RETENTION_SUPPORT 0 // Retention supported?
#define SERCOM1_SE_CNT 1 // SE counter included?
@@ -154,18 +166,6 @@
#define SERCOM1_SPI_OZMO 0 // OZMO features implemented?
#define SERCOM1_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
#define SERCOM1_TTBIT_EXTENSION 1 // 32-bit extension implemented?
-#define SERCOM1_TWIM 1 // TWI Master mode implemented?
-#define SERCOM1_TWIS 1 // TWI Slave mode implemented?
-#define SERCOM1_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
-#define SERCOM1_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
-#define SERCOM1_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
-#define SERCOM1_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
-#define SERCOM1_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
-#define SERCOM1_TWI_FASTMP 1 // TWI fast mode plus implemented?
-#define SERCOM1_TWI_HSMODE 1 // USART mode implemented?
-#define SERCOM1_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
-#define SERCOM1_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
-#define SERCOM1_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
#define SERCOM1_USART 1 // USART mode implemented?
#define SERCOM1_USART_AUTOBAUD 1 // USART autobaud implemented?
#define SERCOM1_USART_COLDET 1 // USART collision detection implemented?
diff --git a/sysmoOCTSIM/include/instance/sercom2.h b/sysmoOCTSIM/include/instance/sercom2.h
index 852cd50..bd672b1 100644
--- a/sysmoOCTSIM/include/instance/sercom2.h
+++ b/sysmoOCTSIM/include/instance/sercom2.h
@@ -3,7 +3,7 @@
*
* \brief Instance description for SERCOM2
*
- * Copyright (c) 2018 Microchip Technology Inc.
+ * Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
@@ -145,6 +145,18 @@
#define SERCOM2_GCLK_ID_CORE 23
#define SERCOM2_GCLK_ID_SLOW 3
#define SERCOM2_INT_MSB 6
+#define SERCOM2_I2CM 1 // I2C Master mode implemented?
+#define SERCOM2_I2CS 1 // I2C Slave mode implemented?
+#define SERCOM2_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
+#define SERCOM2_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
+#define SERCOM2_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
+#define SERCOM2_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
+#define SERCOM2_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
+#define SERCOM2_I2C_FASTMP 1 // I2C fast mode plus implemented?
+#define SERCOM2_I2C_HSMODE 1 // USART mode implemented?
+#define SERCOM2_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
+#define SERCOM2_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
+#define SERCOM2_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
#define SERCOM2_PMSB 3
#define SERCOM2_RETENTION_SUPPORT 0 // Retention supported?
#define SERCOM2_SE_CNT 1 // SE counter included?
@@ -154,18 +166,6 @@
#define SERCOM2_SPI_OZMO 0 // OZMO features implemented?
#define SERCOM2_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
#define SERCOM2_TTBIT_EXTENSION 1 // 32-bit extension implemented?
-#define SERCOM2_TWIM 1 // TWI Master mode implemented?
-#define SERCOM2_TWIS 1 // TWI Slave mode implemented?
-#define SERCOM2_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
-#define SERCOM2_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
-#define SERCOM2_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
-#define SERCOM2_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
-#define SERCOM2_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
-#define SERCOM2_TWI_FASTMP 1 // TWI fast mode plus implemented?
-#define SERCOM2_TWI_HSMODE 1 // USART mode implemented?
-#define SERCOM2_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
-#define SERCOM2_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
-#define SERCOM2_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
#define SERCOM2_USART 1 // USART mode implemented?
#define SERCOM2_USART_AUTOBAUD 1 // USART autobaud implemented?
#define SERCOM2_USART_COLDET 1 // USART collision detection implemented?
diff --git a/sysmoOCTSIM/include/instance/sercom3.h b/sysmoOCTSIM/include/instance/sercom3.h
index 39ec12d..46cd992 100644
--- a/sysmoOCTSIM/include/instance/sercom3.h
+++ b/sysmoOCTSIM/include/instance/sercom3.h
@@ -3,7 +3,7 @@
*
* \brief Instance description for SERCOM3
*
- * Copyright (c) 2018 Microchip Technology Inc.
+ * Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
@@ -145,6 +145,18 @@
#define SERCOM3_GCLK_ID_CORE 24
#define SERCOM3_GCLK_ID_SLOW 3
#define SERCOM3_INT_MSB 6
+#define SERCOM3_I2CM 1 // I2C Master mode implemented?
+#define SERCOM3_I2CS 1 // I2C Slave mode implemented?
+#define SERCOM3_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
+#define SERCOM3_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
+#define SERCOM3_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
+#define SERCOM3_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
+#define SERCOM3_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
+#define SERCOM3_I2C_FASTMP 1 // I2C fast mode plus implemented?
+#define SERCOM3_I2C_HSMODE 1 // USART mode implemented?
+#define SERCOM3_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
+#define SERCOM3_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
+#define SERCOM3_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
#define SERCOM3_PMSB 3
#define SERCOM3_RETENTION_SUPPORT 0 // Retention supported?
#define SERCOM3_SE_CNT 1 // SE counter included?
@@ -154,18 +166,6 @@
#define SERCOM3_SPI_OZMO 0 // OZMO features implemented?
#define SERCOM3_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
#define SERCOM3_TTBIT_EXTENSION 1 // 32-bit extension implemented?
-#define SERCOM3_TWIM 1 // TWI Master mode implemented?
-#define SERCOM3_TWIS 1 // TWI Slave mode implemented?
-#define SERCOM3_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
-#define SERCOM3_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
-#define SERCOM3_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
-#define SERCOM3_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
-#define SERCOM3_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
-#define SERCOM3_TWI_FASTMP 1 // TWI fast mode plus implemented?
-#define SERCOM3_TWI_HSMODE 1 // USART mode implemented?
-#define SERCOM3_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
-#define SERCOM3_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
-#define SERCOM3_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
#define SERCOM3_USART 1 // USART mode implemented?
#define SERCOM3_USART_AUTOBAUD 1 // USART autobaud implemented?
#define SERCOM3_USART_COLDET 1 // USART collision detection implemented?
diff --git a/sysmoOCTSIM/include/instance/sercom4.h b/sysmoOCTSIM/include/instance/sercom4.h
index 8806404..b487a21 100644
--- a/sysmoOCTSIM/include/instance/sercom4.h
+++ b/sysmoOCTSIM/include/instance/sercom4.h
@@ -3,7 +3,7 @@
*
* \brief Instance description for SERCOM4
*
- * Copyright (c) 2018 Microchip Technology Inc.
+ * Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
@@ -145,6 +145,18 @@
#define SERCOM4_GCLK_ID_CORE 34
#define SERCOM4_GCLK_ID_SLOW 3
#define SERCOM4_INT_MSB 6
+#define SERCOM4_I2CM 1 // I2C Master mode implemented?
+#define SERCOM4_I2CS 1 // I2C Slave mode implemented?
+#define SERCOM4_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
+#define SERCOM4_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
+#define SERCOM4_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
+#define SERCOM4_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
+#define SERCOM4_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
+#define SERCOM4_I2C_FASTMP 1 // I2C fast mode plus implemented?
+#define SERCOM4_I2C_HSMODE 1 // USART mode implemented?
+#define SERCOM4_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
+#define SERCOM4_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
+#define SERCOM4_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
#define SERCOM4_PMSB 3
#define SERCOM4_RETENTION_SUPPORT 0 // Retention supported?
#define SERCOM4_SE_CNT 1 // SE counter included?
@@ -154,18 +166,6 @@
#define SERCOM4_SPI_OZMO 0 // OZMO features implemented?
#define SERCOM4_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
#define SERCOM4_TTBIT_EXTENSION 1 // 32-bit extension implemented?
-#define SERCOM4_TWIM 1 // TWI Master mode implemented?
-#define SERCOM4_TWIS 1 // TWI Slave mode implemented?
-#define SERCOM4_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
-#define SERCOM4_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
-#define SERCOM4_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
-#define SERCOM4_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
-#define SERCOM4_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
-#define SERCOM4_TWI_FASTMP 1 // TWI fast mode plus implemented?
-#define SERCOM4_TWI_HSMODE 1 // USART mode implemented?
-#define SERCOM4_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
-#define SERCOM4_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
-#define SERCOM4_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
#define SERCOM4_USART 1 // USART mode implemented?
#define SERCOM4_USART_AUTOBAUD 1 // USART autobaud implemented?
#define SERCOM4_USART_COLDET 1 // USART collision detection implemented?
diff --git a/sysmoOCTSIM/include/instance/sercom5.h b/sysmoOCTSIM/include/instance/sercom5.h
index a1fe75e..eaa937f 100644
--- a/sysmoOCTSIM/include/instance/sercom5.h
+++ b/sysmoOCTSIM/include/instance/sercom5.h
@@ -3,7 +3,7 @@
*
* \brief Instance description for SERCOM5
*
- * Copyright (c) 2018 Microchip Technology Inc.
+ * Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
@@ -145,6 +145,18 @@
#define SERCOM5_GCLK_ID_CORE 35
#define SERCOM5_GCLK_ID_SLOW 3
#define SERCOM5_INT_MSB 6
+#define SERCOM5_I2CM 1 // I2C Master mode implemented?
+#define SERCOM5_I2CS 1 // I2C Slave mode implemented?
+#define SERCOM5_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
+#define SERCOM5_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
+#define SERCOM5_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
+#define SERCOM5_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
+#define SERCOM5_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
+#define SERCOM5_I2C_FASTMP 1 // I2C fast mode plus implemented?
+#define SERCOM5_I2C_HSMODE 1 // USART mode implemented?
+#define SERCOM5_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
+#define SERCOM5_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
+#define SERCOM5_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
#define SERCOM5_PMSB 3
#define SERCOM5_RETENTION_SUPPORT 0 // Retention supported?
#define SERCOM5_SE_CNT 1 // SE counter included?
@@ -154,18 +166,6 @@
#define SERCOM5_SPI_OZMO 0 // OZMO features implemented?
#define SERCOM5_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
#define SERCOM5_TTBIT_EXTENSION 1 // 32-bit extension implemented?
-#define SERCOM5_TWIM 1 // TWI Master mode implemented?
-#define SERCOM5_TWIS 1 // TWI Slave mode implemented?
-#define SERCOM5_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
-#define SERCOM5_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
-#define SERCOM5_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
-#define SERCOM5_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
-#define SERCOM5_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
-#define SERCOM5_TWI_FASTMP 1 // TWI fast mode plus implemented?
-#define SERCOM5_TWI_HSMODE 1 // USART mode implemented?
-#define SERCOM5_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
-#define SERCOM5_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
-#define SERCOM5_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
#define SERCOM5_USART 1 // USART mode implemented?
#define SERCOM5_USART_AUTOBAUD 1 // USART autobaud implemented?
#define SERCOM5_USART_COLDET 1 // USART collision detection implemented?
diff --git a/sysmoOCTSIM/include/instance/sercom6.h b/sysmoOCTSIM/include/instance/sercom6.h
index b47957c..3f5a6c7 100644
--- a/sysmoOCTSIM/include/instance/sercom6.h
+++ b/sysmoOCTSIM/include/instance/sercom6.h
@@ -3,7 +3,7 @@
*
* \brief Instance description for SERCOM6
*
- * Copyright (c) 2018 Microchip Technology Inc.
+ * Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
@@ -145,6 +145,18 @@
#define SERCOM6_GCLK_ID_CORE 36
#define SERCOM6_GCLK_ID_SLOW 3
#define SERCOM6_INT_MSB 6
+#define SERCOM6_I2CM 1 // I2C Master mode implemented?
+#define SERCOM6_I2CS 1 // I2C Slave mode implemented?
+#define SERCOM6_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
+#define SERCOM6_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
+#define SERCOM6_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
+#define SERCOM6_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
+#define SERCOM6_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
+#define SERCOM6_I2C_FASTMP 1 // I2C fast mode plus implemented?
+#define SERCOM6_I2C_HSMODE 1 // USART mode implemented?
+#define SERCOM6_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
+#define SERCOM6_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
+#define SERCOM6_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
#define SERCOM6_PMSB 3
#define SERCOM6_RETENTION_SUPPORT 0 // Retention supported?
#define SERCOM6_SE_CNT 1 // SE counter included?
@@ -154,18 +166,6 @@
#define SERCOM6_SPI_OZMO 0 // OZMO features implemented?
#define SERCOM6_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
#define SERCOM6_TTBIT_EXTENSION 1 // 32-bit extension implemented?
-#define SERCOM6_TWIM 1 // TWI Master mode implemented?
-#define SERCOM6_TWIS 1 // TWI Slave mode implemented?
-#define SERCOM6_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
-#define SERCOM6_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
-#define SERCOM6_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
-#define SERCOM6_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
-#define SERCOM6_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
-#define SERCOM6_TWI_FASTMP 1 // TWI fast mode plus implemented?
-#define SERCOM6_TWI_HSMODE 1 // USART mode implemented?
-#define SERCOM6_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
-#define SERCOM6_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
-#define SERCOM6_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
#define SERCOM6_USART 1 // USART mode implemented?
#define SERCOM6_USART_AUTOBAUD 1 // USART autobaud implemented?
#define SERCOM6_USART_COLDET 1 // USART collision detection implemented?
diff --git a/sysmoOCTSIM/include/instance/sercom7.h b/sysmoOCTSIM/include/instance/sercom7.h
index 5bf5ae4..1118bca 100644
--- a/sysmoOCTSIM/include/instance/sercom7.h
+++ b/sysmoOCTSIM/include/instance/sercom7.h
@@ -3,7 +3,7 @@
*
* \brief Instance description for SERCOM7
*
- * Copyright (c) 2018 Microchip Technology Inc.
+ * Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
@@ -145,6 +145,18 @@
#define SERCOM7_GCLK_ID_CORE 37
#define SERCOM7_GCLK_ID_SLOW 3
#define SERCOM7_INT_MSB 6
+#define SERCOM7_I2CM 1 // I2C Master mode implemented?
+#define SERCOM7_I2CS 1 // I2C Slave mode implemented?
+#define SERCOM7_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
+#define SERCOM7_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
+#define SERCOM7_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
+#define SERCOM7_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
+#define SERCOM7_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
+#define SERCOM7_I2C_FASTMP 1 // I2C fast mode plus implemented?
+#define SERCOM7_I2C_HSMODE 1 // USART mode implemented?
+#define SERCOM7_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
+#define SERCOM7_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
+#define SERCOM7_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
#define SERCOM7_PMSB 3
#define SERCOM7_RETENTION_SUPPORT 0 // Retention supported?
#define SERCOM7_SE_CNT 1 // SE counter included?
@@ -154,18 +166,6 @@
#define SERCOM7_SPI_OZMO 0 // OZMO features implemented?
#define SERCOM7_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
#define SERCOM7_TTBIT_EXTENSION 1 // 32-bit extension implemented?
-#define SERCOM7_TWIM 1 // TWI Master mode implemented?
-#define SERCOM7_TWIS 1 // TWI Slave mode implemented?
-#define SERCOM7_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
-#define SERCOM7_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
-#define SERCOM7_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
-#define SERCOM7_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
-#define SERCOM7_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
-#define SERCOM7_TWI_FASTMP 1 // TWI fast mode plus implemented?
-#define SERCOM7_TWI_HSMODE 1 // USART mode implemented?
-#define SERCOM7_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
-#define SERCOM7_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
-#define SERCOM7_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
#define SERCOM7_USART 1 // USART mode implemented?
#define SERCOM7_USART_AUTOBAUD 1 // USART autobaud implemented?
#define SERCOM7_USART_COLDET 1 // USART collision detection implemented?
diff --git a/sysmoOCTSIM/include/instance/supc.h b/sysmoOCTSIM/include/instance/supc.h
index 734c682..4018344 100644
--- a/sysmoOCTSIM/include/instance/supc.h
+++ b/sysmoOCTSIM/include/instance/supc.h
@@ -3,7 +3,7 @@
*
* \brief Instance description for SUPC
*
- * Copyright (c) 2018 Microchip Technology Inc.
+ * Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
@@ -37,7 +37,6 @@
#define REG_SUPC_INTFLAG (0x40001808) /**< \brief (SUPC) Interrupt Flag Status and Clear */
#define REG_SUPC_STATUS (0x4000180C) /**< \brief (SUPC) Power and Clocks Status */
#define REG_SUPC_BOD33 (0x40001810) /**< \brief (SUPC) BOD33 Control */
-#define REG_SUPC_BOD12 (0x40001814) /**< \brief (SUPC) BOD12 Control */
#define REG_SUPC_VREG (0x40001818) /**< \brief (SUPC) VREG Control */
#define REG_SUPC_VREF (0x4000181C) /**< \brief (SUPC) VREF Control */
#define REG_SUPC_BBPS (0x40001820) /**< \brief (SUPC) Battery Backup Power Switch */
@@ -49,7 +48,6 @@
#define REG_SUPC_INTFLAG (*(RwReg *)0x40001808UL) /**< \brief (SUPC) Interrupt Flag Status and Clear */
#define REG_SUPC_STATUS (*(RoReg *)0x4000180CUL) /**< \brief (SUPC) Power and Clocks Status */
#define REG_SUPC_BOD33 (*(RwReg *)0x40001810UL) /**< \brief (SUPC) BOD33 Control */
-#define REG_SUPC_BOD12 (*(RwReg *)0x40001814UL) /**< \brief (SUPC) BOD12 Control */
#define REG_SUPC_VREG (*(RwReg *)0x40001818UL) /**< \brief (SUPC) VREG Control */
#define REG_SUPC_VREF (*(RwReg *)0x4000181CUL) /**< \brief (SUPC) VREF Control */
#define REG_SUPC_BBPS (*(RwReg *)0x40001820UL) /**< \brief (SUPC) Battery Backup Power Switch */