Update from Atmel START 1.0.87 to 1.1.134
Change-Id: I095f2f3f4de8ebba154b7d8f9f763a2fa6472ebd
diff --git a/sysmoOCTSIM/include/component/dsu.h b/sysmoOCTSIM/include/component/dsu.h
index feedfa9..043f4d8 100644
--- a/sysmoOCTSIM/include/component/dsu.h
+++ b/sysmoOCTSIM/include/component/dsu.h
@@ -3,7 +3,7 @@
*
* \brief Component description for DSU
*
- * Copyright (c) 2018 Microchip Technology Inc.
+ * Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
@@ -113,14 +113,12 @@
uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
uint8_t CELCK:1; /*!< bit: 5 Chip Erase Locked */
- uint8_t TDCCD0:1; /*!< bit: 6 Test Debug Communication Channel 0 Dirty */
- uint8_t TDCCD1:1; /*!< bit: 7 Test Debug Communication Channel 1 Dirty */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :2; /*!< bit: 0.. 1 Reserved */
uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
- uint8_t :2; /*!< bit: 4.. 5 Reserved */
- uint8_t TDCCD:2; /*!< bit: 6.. 7 Test Debug Communication Channel x Dirty */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} DSU_STATUSB_Type;
@@ -144,14 +142,7 @@
#define DSU_STATUSB_HPE (_U_(0x1) << DSU_STATUSB_HPE_Pos)
#define DSU_STATUSB_CELCK_Pos 5 /**< \brief (DSU_STATUSB) Chip Erase Locked */
#define DSU_STATUSB_CELCK (_U_(0x1) << DSU_STATUSB_CELCK_Pos)
-#define DSU_STATUSB_TDCCD0_Pos 6 /**< \brief (DSU_STATUSB) Test Debug Communication Channel 0 Dirty */
-#define DSU_STATUSB_TDCCD0 (_U_(1) << DSU_STATUSB_TDCCD0_Pos)
-#define DSU_STATUSB_TDCCD1_Pos 7 /**< \brief (DSU_STATUSB) Test Debug Communication Channel 1 Dirty */
-#define DSU_STATUSB_TDCCD1 (_U_(1) << DSU_STATUSB_TDCCD1_Pos)
-#define DSU_STATUSB_TDCCD_Pos 6 /**< \brief (DSU_STATUSB) Test Debug Communication Channel x Dirty */
-#define DSU_STATUSB_TDCCD_Msk (_U_(0x3) << DSU_STATUSB_TDCCD_Pos)
-#define DSU_STATUSB_TDCCD(value) (DSU_STATUSB_TDCCD_Msk & ((value) << DSU_STATUSB_TDCCD_Pos))
-#define DSU_STATUSB_MASK _U_(0xFF) /**< \brief (DSU_STATUSB) MASK Register */
+#define DSU_STATUSB_MASK _U_(0x3F) /**< \brief (DSU_STATUSB) MASK Register */
/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -318,24 +309,6 @@
#define DSU_CFG_ETBRAMEN (_U_(0x1) << DSU_CFG_ETBRAMEN_Pos)
#define DSU_CFG_MASK _U_(0x0000001F) /**< \brief (DSU_CFG) MASK Register */
-/* -------- DSU_DCFG : (DSU Offset: 0x00F0) (R/W 32) Device Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DCFG:32; /*!< bit: 0..31 Device Configuration */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} DSU_DCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_DCFG_OFFSET 0x00F0 /**< \brief (DSU_DCFG offset) Device Configuration */
-#define DSU_DCFG_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DCFG reset_value) Device Configuration */
-
-#define DSU_DCFG_DCFG_Pos 0 /**< \brief (DSU_DCFG) Device Configuration */
-#define DSU_DCFG_DCFG_Msk (_U_(0xFFFFFFFF) << DSU_DCFG_DCFG_Pos)
-#define DSU_DCFG_DCFG(value) (DSU_DCFG_DCFG_Msk & ((value) << DSU_DCFG_DCFG_Pos))
-#define DSU_DCFG_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DCFG) MASK Register */
-
/* -------- DSU_ENTRY0 : (DSU Offset: 0x1000) (R/ 32) CoreSight ROM Table Entry 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
@@ -648,13 +621,11 @@
__IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
__I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
__IO DSU_CFG_Type CFG; /**< \brief Offset: 0x001C (R/W 32) Configuration */
- RoReg8 Reserved2[0xD0];
- __IO DSU_DCFG_Type DCFG[2]; /**< \brief Offset: 0x00F0 (R/W 32) Device Configuration */
- RoReg8 Reserved3[0xF08];
+ RoReg8 Reserved2[0xFE0];
__I DSU_ENTRY0_Type ENTRY0; /**< \brief Offset: 0x1000 (R/ 32) CoreSight ROM Table Entry 0 */
__I DSU_ENTRY1_Type ENTRY1; /**< \brief Offset: 0x1004 (R/ 32) CoreSight ROM Table Entry 1 */
__I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) CoreSight ROM Table End */
- RoReg8 Reserved4[0xFC0];
+ RoReg8 Reserved3[0xFC0];
__I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) CoreSight ROM Table Memory Type */
__I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
__I DSU_PID5_Type PID5; /**< \brief Offset: 0x1FD4 (R/ 32) Peripheral Identification 5 */
diff --git a/sysmoOCTSIM/include/component/nvmctrl.h b/sysmoOCTSIM/include/component/nvmctrl.h
index e16038b..771f050 100644
--- a/sysmoOCTSIM/include/component/nvmctrl.h
+++ b/sysmoOCTSIM/include/component/nvmctrl.h
@@ -3,7 +3,7 @@
*
* \brief Component description for NVMCTRL
*
- * Copyright (c) 2018 Microchip Technology Inc.
+ * Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
@@ -647,24 +647,6 @@
#define ADC1_FUSES_BIASREFBUF_Msk (_U_(0x7) << ADC1_FUSES_BIASREFBUF_Pos)
#define ADC1_FUSES_BIASREFBUF(value) (ADC1_FUSES_BIASREFBUF_Msk & ((value) << ADC1_FUSES_BIASREFBUF_Pos))
-#define FUSES_BOD12USERLEVEL_ADDR NVMCTRL_USER
-#define FUSES_BOD12USERLEVEL_Pos 17 /**< \brief (NVMCTRL_USER) BOD12 User Level */
-#define FUSES_BOD12USERLEVEL_Msk (_U_(0x3F) << FUSES_BOD12USERLEVEL_Pos)
-#define FUSES_BOD12USERLEVEL(value) (FUSES_BOD12USERLEVEL_Msk & ((value) << FUSES_BOD12USERLEVEL_Pos))
-
-#define FUSES_BOD12_ACTION_ADDR NVMCTRL_USER
-#define FUSES_BOD12_ACTION_Pos 23 /**< \brief (NVMCTRL_USER) BOD12 Action */
-#define FUSES_BOD12_ACTION_Msk (_U_(0x3) << FUSES_BOD12_ACTION_Pos)
-#define FUSES_BOD12_ACTION(value) (FUSES_BOD12_ACTION_Msk & ((value) << FUSES_BOD12_ACTION_Pos))
-
-#define FUSES_BOD12_DIS_ADDR NVMCTRL_USER
-#define FUSES_BOD12_DIS_Pos 16 /**< \brief (NVMCTRL_USER) BOD12 Disable */
-#define FUSES_BOD12_DIS_Msk (_U_(0x1) << FUSES_BOD12_DIS_Pos)
-
-#define FUSES_BOD12_HYST_ADDR NVMCTRL_USER
-#define FUSES_BOD12_HYST_Pos 25 /**< \brief (NVMCTRL_USER) BOD12 Hysteresis */
-#define FUSES_BOD12_HYST_Msk (_U_(0x1) << FUSES_BOD12_HYST_Pos)
-
#define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
#define FUSES_BOD33USERLEVEL_Pos 1 /**< \brief (NVMCTRL_USER) BOD33 User Level */
#define FUSES_BOD33USERLEVEL_Msk (_U_(0xFF) << FUSES_BOD33USERLEVEL_Pos)
diff --git a/sysmoOCTSIM/include/component/supc.h b/sysmoOCTSIM/include/component/supc.h
index be1f48b..8967092 100644
--- a/sysmoOCTSIM/include/component/supc.h
+++ b/sysmoOCTSIM/include/component/supc.h
@@ -3,7 +3,7 @@
*
* \brief Component description for SUPC
*
- * Copyright (c) 2018 Microchip Technology Inc.
+ * Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
@@ -46,10 +46,7 @@
uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
- uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
- uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
- uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
- uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t :5; /*!< bit: 3.. 7 Reserved */
uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
uint32_t :1; /*!< bit: 9 Reserved */
uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
@@ -68,17 +65,11 @@
#define SUPC_INTENCLR_BOD33DET (_U_(0x1) << SUPC_INTENCLR_BOD33DET_Pos)
#define SUPC_INTENCLR_B33SRDY_Pos 2 /**< \brief (SUPC_INTENCLR) BOD33 Synchronization Ready */
#define SUPC_INTENCLR_B33SRDY (_U_(0x1) << SUPC_INTENCLR_B33SRDY_Pos)
-#define SUPC_INTENCLR_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENCLR) BOD12 Ready */
-#define SUPC_INTENCLR_BOD12RDY (_U_(0x1) << SUPC_INTENCLR_BOD12RDY_Pos)
-#define SUPC_INTENCLR_BOD12DET_Pos 4 /**< \brief (SUPC_INTENCLR) BOD12 Detection */
-#define SUPC_INTENCLR_BOD12DET (_U_(0x1) << SUPC_INTENCLR_BOD12DET_Pos)
-#define SUPC_INTENCLR_B12SRDY_Pos 5 /**< \brief (SUPC_INTENCLR) BOD12 Synchronization Ready */
-#define SUPC_INTENCLR_B12SRDY (_U_(0x1) << SUPC_INTENCLR_B12SRDY_Pos)
#define SUPC_INTENCLR_VREGRDY_Pos 8 /**< \brief (SUPC_INTENCLR) Voltage Regulator Ready */
#define SUPC_INTENCLR_VREGRDY (_U_(0x1) << SUPC_INTENCLR_VREGRDY_Pos)
#define SUPC_INTENCLR_VCORERDY_Pos 10 /**< \brief (SUPC_INTENCLR) VDDCORE Ready */
#define SUPC_INTENCLR_VCORERDY (_U_(0x1) << SUPC_INTENCLR_VCORERDY_Pos)
-#define SUPC_INTENCLR_MASK _U_(0x0000053F) /**< \brief (SUPC_INTENCLR) MASK Register */
+#define SUPC_INTENCLR_MASK _U_(0x00000507) /**< \brief (SUPC_INTENCLR) MASK Register */
/* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -87,10 +78,7 @@
uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
- uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
- uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
- uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
- uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t :5; /*!< bit: 3.. 7 Reserved */
uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
uint32_t :1; /*!< bit: 9 Reserved */
uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
@@ -109,17 +97,11 @@
#define SUPC_INTENSET_BOD33DET (_U_(0x1) << SUPC_INTENSET_BOD33DET_Pos)
#define SUPC_INTENSET_B33SRDY_Pos 2 /**< \brief (SUPC_INTENSET) BOD33 Synchronization Ready */
#define SUPC_INTENSET_B33SRDY (_U_(0x1) << SUPC_INTENSET_B33SRDY_Pos)
-#define SUPC_INTENSET_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENSET) BOD12 Ready */
-#define SUPC_INTENSET_BOD12RDY (_U_(0x1) << SUPC_INTENSET_BOD12RDY_Pos)
-#define SUPC_INTENSET_BOD12DET_Pos 4 /**< \brief (SUPC_INTENSET) BOD12 Detection */
-#define SUPC_INTENSET_BOD12DET (_U_(0x1) << SUPC_INTENSET_BOD12DET_Pos)
-#define SUPC_INTENSET_B12SRDY_Pos 5 /**< \brief (SUPC_INTENSET) BOD12 Synchronization Ready */
-#define SUPC_INTENSET_B12SRDY (_U_(0x1) << SUPC_INTENSET_B12SRDY_Pos)
#define SUPC_INTENSET_VREGRDY_Pos 8 /**< \brief (SUPC_INTENSET) Voltage Regulator Ready */
#define SUPC_INTENSET_VREGRDY (_U_(0x1) << SUPC_INTENSET_VREGRDY_Pos)
#define SUPC_INTENSET_VCORERDY_Pos 10 /**< \brief (SUPC_INTENSET) VDDCORE Ready */
#define SUPC_INTENSET_VCORERDY (_U_(0x1) << SUPC_INTENSET_VCORERDY_Pos)
-#define SUPC_INTENSET_MASK _U_(0x0000053F) /**< \brief (SUPC_INTENSET) MASK Register */
+#define SUPC_INTENSET_MASK _U_(0x00000507) /**< \brief (SUPC_INTENSET) MASK Register */
/* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -128,10 +110,7 @@
__I uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
__I uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
__I uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
- __I uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
- __I uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
- __I uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
- __I uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ __I uint32_t :5; /*!< bit: 3.. 7 Reserved */
__I uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
__I uint32_t :1; /*!< bit: 9 Reserved */
__I uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
@@ -150,17 +129,11 @@
#define SUPC_INTFLAG_BOD33DET (_U_(0x1) << SUPC_INTFLAG_BOD33DET_Pos)
#define SUPC_INTFLAG_B33SRDY_Pos 2 /**< \brief (SUPC_INTFLAG) BOD33 Synchronization Ready */
#define SUPC_INTFLAG_B33SRDY (_U_(0x1) << SUPC_INTFLAG_B33SRDY_Pos)
-#define SUPC_INTFLAG_BOD12RDY_Pos 3 /**< \brief (SUPC_INTFLAG) BOD12 Ready */
-#define SUPC_INTFLAG_BOD12RDY (_U_(0x1) << SUPC_INTFLAG_BOD12RDY_Pos)
-#define SUPC_INTFLAG_BOD12DET_Pos 4 /**< \brief (SUPC_INTFLAG) BOD12 Detection */
-#define SUPC_INTFLAG_BOD12DET (_U_(0x1) << SUPC_INTFLAG_BOD12DET_Pos)
-#define SUPC_INTFLAG_B12SRDY_Pos 5 /**< \brief (SUPC_INTFLAG) BOD12 Synchronization Ready */
-#define SUPC_INTFLAG_B12SRDY (_U_(0x1) << SUPC_INTFLAG_B12SRDY_Pos)
#define SUPC_INTFLAG_VREGRDY_Pos 8 /**< \brief (SUPC_INTFLAG) Voltage Regulator Ready */
#define SUPC_INTFLAG_VREGRDY (_U_(0x1) << SUPC_INTFLAG_VREGRDY_Pos)
#define SUPC_INTFLAG_VCORERDY_Pos 10 /**< \brief (SUPC_INTFLAG) VDDCORE Ready */
#define SUPC_INTFLAG_VCORERDY (_U_(0x1) << SUPC_INTFLAG_VCORERDY_Pos)
-#define SUPC_INTFLAG_MASK _U_(0x0000053F) /**< \brief (SUPC_INTFLAG) MASK Register */
+#define SUPC_INTFLAG_MASK _U_(0x00000507) /**< \brief (SUPC_INTFLAG) MASK Register */
/* -------- SUPC_STATUS : (SUPC Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -169,10 +142,7 @@
uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
- uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
- uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
- uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
- uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t :5; /*!< bit: 3.. 7 Reserved */
uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
uint32_t :1; /*!< bit: 9 Reserved */
uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
@@ -191,17 +161,11 @@
#define SUPC_STATUS_BOD33DET (_U_(0x1) << SUPC_STATUS_BOD33DET_Pos)
#define SUPC_STATUS_B33SRDY_Pos 2 /**< \brief (SUPC_STATUS) BOD33 Synchronization Ready */
#define SUPC_STATUS_B33SRDY (_U_(0x1) << SUPC_STATUS_B33SRDY_Pos)
-#define SUPC_STATUS_BOD12RDY_Pos 3 /**< \brief (SUPC_STATUS) BOD12 Ready */
-#define SUPC_STATUS_BOD12RDY (_U_(0x1) << SUPC_STATUS_BOD12RDY_Pos)
-#define SUPC_STATUS_BOD12DET_Pos 4 /**< \brief (SUPC_STATUS) BOD12 Detection */
-#define SUPC_STATUS_BOD12DET (_U_(0x1) << SUPC_STATUS_BOD12DET_Pos)
-#define SUPC_STATUS_B12SRDY_Pos 5 /**< \brief (SUPC_STATUS) BOD12 Synchronization Ready */
-#define SUPC_STATUS_B12SRDY (_U_(0x1) << SUPC_STATUS_B12SRDY_Pos)
#define SUPC_STATUS_VREGRDY_Pos 8 /**< \brief (SUPC_STATUS) Voltage Regulator Ready */
#define SUPC_STATUS_VREGRDY (_U_(0x1) << SUPC_STATUS_VREGRDY_Pos)
#define SUPC_STATUS_VCORERDY_Pos 10 /**< \brief (SUPC_STATUS) VDDCORE Ready */
#define SUPC_STATUS_VCORERDY (_U_(0x1) << SUPC_STATUS_VCORERDY_Pos)
-#define SUPC_STATUS_MASK _U_(0x0000053F) /**< \brief (SUPC_STATUS) MASK Register */
+#define SUPC_STATUS_MASK _U_(0x00000507) /**< \brief (SUPC_STATUS) MASK Register */
/* -------- SUPC_BOD33 : (SUPC Offset: 0x10) (R/W 32) BOD33 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -278,89 +242,6 @@
#define SUPC_BOD33_VBATLEVEL(value) (SUPC_BOD33_VBATLEVEL_Msk & ((value) << SUPC_BOD33_VBATLEVEL_Pos))
#define SUPC_BOD33_MASK _U_(0xFFFF7FFE) /**< \brief (SUPC_BOD33) MASK Register */
-/* -------- SUPC_BOD12 : (SUPC Offset: 0x14) (R/W 32) BOD12 Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */
- uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */
- uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */
- uint32_t :3; /*!< bit: 9..11 Reserved */
- uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
- uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} SUPC_BOD12_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SUPC_BOD12_OFFSET 0x14 /**< \brief (SUPC_BOD12 offset) BOD12 Control */
-#define SUPC_BOD12_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BOD12 reset_value) BOD12 Control */
-
-#define SUPC_BOD12_ENABLE_Pos 1 /**< \brief (SUPC_BOD12) Enable */
-#define SUPC_BOD12_ENABLE (_U_(0x1) << SUPC_BOD12_ENABLE_Pos)
-#define SUPC_BOD12_HYST_Pos 2 /**< \brief (SUPC_BOD12) Hysteresis Enable */
-#define SUPC_BOD12_HYST (_U_(0x1) << SUPC_BOD12_HYST_Pos)
-#define SUPC_BOD12_ACTION_Pos 3 /**< \brief (SUPC_BOD12) Action when Threshold Crossed */
-#define SUPC_BOD12_ACTION_Msk (_U_(0x3) << SUPC_BOD12_ACTION_Pos)
-#define SUPC_BOD12_ACTION(value) (SUPC_BOD12_ACTION_Msk & ((value) << SUPC_BOD12_ACTION_Pos))
-#define SUPC_BOD12_ACTION_NONE_Val _U_(0x0) /**< \brief (SUPC_BOD12) No action */
-#define SUPC_BOD12_ACTION_RESET_Val _U_(0x1) /**< \brief (SUPC_BOD12) The BOD12 generates a reset */
-#define SUPC_BOD12_ACTION_INT_Val _U_(0x2) /**< \brief (SUPC_BOD12) The BOD12 generates an interrupt */
-#define SUPC_BOD12_ACTION_NONE (SUPC_BOD12_ACTION_NONE_Val << SUPC_BOD12_ACTION_Pos)
-#define SUPC_BOD12_ACTION_RESET (SUPC_BOD12_ACTION_RESET_Val << SUPC_BOD12_ACTION_Pos)
-#define SUPC_BOD12_ACTION_INT (SUPC_BOD12_ACTION_INT_Val << SUPC_BOD12_ACTION_Pos)
-#define SUPC_BOD12_STDBYCFG_Pos 5 /**< \brief (SUPC_BOD12) Configuration in Standby mode */
-#define SUPC_BOD12_STDBYCFG (_U_(0x1) << SUPC_BOD12_STDBYCFG_Pos)
-#define SUPC_BOD12_RUNSTDBY_Pos 6 /**< \brief (SUPC_BOD12) Run during Standby */
-#define SUPC_BOD12_RUNSTDBY (_U_(0x1) << SUPC_BOD12_RUNSTDBY_Pos)
-#define SUPC_BOD12_ACTCFG_Pos 8 /**< \brief (SUPC_BOD12) Configuration in Active mode */
-#define SUPC_BOD12_ACTCFG (_U_(0x1) << SUPC_BOD12_ACTCFG_Pos)
-#define SUPC_BOD12_PSEL_Pos 12 /**< \brief (SUPC_BOD12) Prescaler Select */
-#define SUPC_BOD12_PSEL_Msk (_U_(0xF) << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL(value) (SUPC_BOD12_PSEL_Msk & ((value) << SUPC_BOD12_PSEL_Pos))
-#define SUPC_BOD12_PSEL_DIV2_Val _U_(0x0) /**< \brief (SUPC_BOD12) Divide clock by 2 */
-#define SUPC_BOD12_PSEL_DIV4_Val _U_(0x1) /**< \brief (SUPC_BOD12) Divide clock by 4 */
-#define SUPC_BOD12_PSEL_DIV8_Val _U_(0x2) /**< \brief (SUPC_BOD12) Divide clock by 8 */
-#define SUPC_BOD12_PSEL_DIV16_Val _U_(0x3) /**< \brief (SUPC_BOD12) Divide clock by 16 */
-#define SUPC_BOD12_PSEL_DIV32_Val _U_(0x4) /**< \brief (SUPC_BOD12) Divide clock by 32 */
-#define SUPC_BOD12_PSEL_DIV64_Val _U_(0x5) /**< \brief (SUPC_BOD12) Divide clock by 64 */
-#define SUPC_BOD12_PSEL_DIV128_Val _U_(0x6) /**< \brief (SUPC_BOD12) Divide clock by 128 */
-#define SUPC_BOD12_PSEL_DIV256_Val _U_(0x7) /**< \brief (SUPC_BOD12) Divide clock by 256 */
-#define SUPC_BOD12_PSEL_DIV512_Val _U_(0x8) /**< \brief (SUPC_BOD12) Divide clock by 512 */
-#define SUPC_BOD12_PSEL_DIV1024_Val _U_(0x9) /**< \brief (SUPC_BOD12) Divide clock by 1024 */
-#define SUPC_BOD12_PSEL_DIV2048_Val _U_(0xA) /**< \brief (SUPC_BOD12) Divide clock by 2048 */
-#define SUPC_BOD12_PSEL_DIV4096_Val _U_(0xB) /**< \brief (SUPC_BOD12) Divide clock by 4096 */
-#define SUPC_BOD12_PSEL_DIV8192_Val _U_(0xC) /**< \brief (SUPC_BOD12) Divide clock by 8192 */
-#define SUPC_BOD12_PSEL_DIV16384_Val _U_(0xD) /**< \brief (SUPC_BOD12) Divide clock by 16384 */
-#define SUPC_BOD12_PSEL_DIV32768_Val _U_(0xE) /**< \brief (SUPC_BOD12) Divide clock by 32768 */
-#define SUPC_BOD12_PSEL_DIV65536_Val _U_(0xF) /**< \brief (SUPC_BOD12) Divide clock by 65536 */
-#define SUPC_BOD12_PSEL_DIV2 (SUPC_BOD12_PSEL_DIV2_Val << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV4 (SUPC_BOD12_PSEL_DIV4_Val << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV8 (SUPC_BOD12_PSEL_DIV8_Val << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV16 (SUPC_BOD12_PSEL_DIV16_Val << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV32 (SUPC_BOD12_PSEL_DIV32_Val << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV64 (SUPC_BOD12_PSEL_DIV64_Val << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV128 (SUPC_BOD12_PSEL_DIV128_Val << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV256 (SUPC_BOD12_PSEL_DIV256_Val << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV512 (SUPC_BOD12_PSEL_DIV512_Val << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV1024 (SUPC_BOD12_PSEL_DIV1024_Val << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV2048 (SUPC_BOD12_PSEL_DIV2048_Val << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV4096 (SUPC_BOD12_PSEL_DIV4096_Val << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV8192 (SUPC_BOD12_PSEL_DIV8192_Val << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV16384 (SUPC_BOD12_PSEL_DIV16384_Val << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV32768 (SUPC_BOD12_PSEL_DIV32768_Val << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV65536 (SUPC_BOD12_PSEL_DIV65536_Val << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_LEVEL_Pos 16 /**< \brief (SUPC_BOD12) Threshold Level */
-#define SUPC_BOD12_LEVEL_Msk (_U_(0x3F) << SUPC_BOD12_LEVEL_Pos)
-#define SUPC_BOD12_LEVEL(value) (SUPC_BOD12_LEVEL_Msk & ((value) << SUPC_BOD12_LEVEL_Pos))
-#define SUPC_BOD12_MASK _U_(0x003FF17E) /**< \brief (SUPC_BOD12) MASK Register */
-
/* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
@@ -540,7 +421,7 @@
__IO SUPC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
__I SUPC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
__IO SUPC_BOD33_Type BOD33; /**< \brief Offset: 0x10 (R/W 32) BOD33 Control */
- __IO SUPC_BOD12_Type BOD12; /**< \brief Offset: 0x14 (R/W 32) BOD12 Control */
+ RoReg8 Reserved1[0x4];
__IO SUPC_VREG_Type VREG; /**< \brief Offset: 0x18 (R/W 32) VREG Control */
__IO SUPC_VREF_Type VREF; /**< \brief Offset: 0x1C (R/W 32) VREF Control */
__IO SUPC_BBPS_Type BBPS; /**< \brief Offset: 0x20 (R/W 32) Battery Backup Power Switch */