| commit | 986f06a6ca38085e5f39ba4d5df2e781d9f96202 | [log] [tgz] |
|---|---|---|
| author | Eric Wild <ewild@sysmocom.de> | Wed Oct 23 15:56:59 2019 +0200 |
| committer | Eric Wild <ewild@sysmocom.de> | Wed Oct 23 17:09:32 2019 +0200 |
| tree | a7d1d25d8e50108e0d49b170cbb34431809cb6f2 | |
| parent | 8ebd7d6d49a5bf203a705bc9ae30cbe9ddd4df52 [diff] [blame] |
debug for single slot v1 prototype, uart sync clock output Change-Id: Ie2b207c668ffd7352d2c57be8a8651c3ebbbba68
diff --git a/ccid_common/ccid_device.c b/ccid_common/ccid_device.c index 049b1cf..0a9b934 100644 --- a/ccid_common/ccid_device.c +++ b/ccid_common/ccid_device.c
@@ -877,7 +877,7 @@ ci->name = name; ci->priv = priv; - for (i = 0; i < ARRAY_SIZE(ci->slot); i++) { + for (i = 0; i < 1; i++) { struct ccid_slot *cs = &ci->slot[i]; cs->slot_nr = i; cs->ci = ci;