diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h
index 8d10f38..fbaa9b7 100644
--- a/sysmoOCTSIM/config/hpl_gclk_config.h
+++ b/sysmoOCTSIM/config/hpl_gclk_config.h
@@ -902,7 +902,7 @@
 // <i> Indicates whether Generic Clock Generator Enable is enabled or not
 // <id> gclk_arch_gen_11_enable
 #ifndef CONF_GCLK_GEN_11_GENEN
-#define CONF_GCLK_GEN_11_GENEN 1
+#define CONF_GCLK_GEN_11_GENEN 0
 #endif
 // </h>
 
diff --git a/sysmoOCTSIM/config/hpl_oscctrl_config.h b/sysmoOCTSIM/config/hpl_oscctrl_config.h
index d59ac43..6b3cc19 100644
--- a/sysmoOCTSIM/config/hpl_oscctrl_config.h
+++ b/sysmoOCTSIM/config/hpl_oscctrl_config.h
@@ -404,7 +404,7 @@
 // <i> Select the clock source.
 // <id> fdpll0_ref_clock
 #ifndef CONF_FDPLL0_GCLK
-#define CONF_FDPLL0_GCLK GCLK_PCHCTRL_GEN_GCLK11_Val
+#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC1
 #endif
 
 // <h> Digital Phase Locked Loop Control