switch from dev board to prototype
the SAM E54 Xplained Pro development board uses a SAM E54P20N
micro-controller.
the sysmocom sysmoOCTSIM prototype uses a SAM E54N19A
micro-controller.
the system LED and UART debug GPIO are different, else the code
is the same.
the Atmel START definitions have been updated accordingly.
Change-Id: Ifd15f6759c51b42a8d11b09f9f495d7e7a5b6afc
diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h
index 12c1539..d16af6f 100644
--- a/sysmoOCTSIM/config/hpl_gclk_config.h
+++ b/sysmoOCTSIM/config/hpl_gclk_config.h
@@ -328,7 +328,7 @@
// <i> This defines the clock source for generic clock generator 4
// <id> gclk_gen_4_oscillator
#ifndef CONF_GCLK_GEN_4_SOURCE
-#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC0
+#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
@@ -404,7 +404,7 @@
// <i> This defines the clock source for generic clock generator 5
// <id> gclk_gen_5_oscillator
#ifndef CONF_GCLK_GEN_5_SOURCE
-#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC0
+#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
@@ -480,7 +480,7 @@
// <i> This defines the clock source for generic clock generator 6
// <id> gclk_gen_6_oscillator
#ifndef CONF_GCLK_GEN_6_SOURCE
-#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC0
+#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
@@ -556,7 +556,7 @@
// <i> This defines the clock source for generic clock generator 7
// <id> gclk_gen_7_oscillator
#ifndef CONF_GCLK_GEN_7_SOURCE
-#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC0
+#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
@@ -632,7 +632,7 @@
// <i> This defines the clock source for generic clock generator 8
// <id> gclk_gen_8_oscillator
#ifndef CONF_GCLK_GEN_8_SOURCE
-#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC0
+#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
@@ -708,7 +708,7 @@
// <i> This defines the clock source for generic clock generator 9
// <id> gclk_gen_9_oscillator
#ifndef CONF_GCLK_GEN_9_SOURCE
-#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC0
+#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
@@ -784,7 +784,7 @@
// <i> This defines the clock source for generic clock generator 10
// <id> gclk_gen_10_oscillator
#ifndef CONF_GCLK_GEN_10_SOURCE
-#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC0
+#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
diff --git a/sysmoOCTSIM/config/hpl_port_config.h b/sysmoOCTSIM/config/hpl_port_config.h
index b5315f0..a7bd379 100644
--- a/sysmoOCTSIM/config/hpl_port_config.h
+++ b/sysmoOCTSIM/config/hpl_port_config.h
@@ -94,34 +94,6 @@
#endif
// </h>
-// <h> PORT Input Event 0 configuration on PORT D
-
-// <q> PORTD Input Event 0 Enable
-// <i> The event action will be triggered on any incoming event if PORT D Input Event 0 configuration is enabled
-// <id> portd_input_event_enable_0
-#ifndef CONF_PORTD_EVCTRL_PORTEI_0
-#define CONF_PORTD_EVCTRL_PORTEI_0 0x0
-#endif
-
-// <o> PORTD Event 0 Pin Identifier <0x00-0x1F>
-// <i> These bits define the I/O pin from port D on which the event action will be performed
-// <id> portd_event_pin_identifier_0
-#ifndef CONF_PORTD_EVCTRL_PID_0
-#define CONF_PORTD_EVCTRL_PID_0 0x0
-#endif
-
-// <o> PORTD Event 0 Action
-// <0=> Output register of pin will be set to level of event
-// <1=> Set output register of pin on event
-// <2=> Clear output register of pin on event
-// <3=> Toggle output register of pin on event
-// <i> These bits define the event action the PORT D will perform on event input 0
-// <id> portd_event_action_0
-#ifndef CONF_PORTD_EVCTRL_EVACT_0
-#define CONF_PORTD_EVCTRL_EVACT_0 0
-#endif
-
-// </h>
// </e>
@@ -215,34 +187,6 @@
#endif
// </h>
-// <h> PORT Input Event 1 configuration on PORT D
-
-// <q> PORTD Input Event 1 Enable
-// <i> The event action will be triggered on any incoming event if PORT D Input Event 1 configuration is enabled
-// <id> portd_input_event_enable_1
-#ifndef CONF_PORTD_EVCTRL_PORTEI_1
-#define CONF_PORTD_EVCTRL_PORTEI_1 0x0
-#endif
-
-// <o> PORTD Event 1 Pin Identifier <0x00-0x1F>
-// <i> These bits define the I/O pin from port D on which the event action will be performed
-// <id> portd_event_pin_identifier_1
-#ifndef CONF_PORTD_EVCTRL_PID_1
-#define CONF_PORTD_EVCTRL_PID_1 0x0
-#endif
-
-// <o> PORTD Event 1 Action
-// <0=> Output register of pin will be set to level of event
-// <1=> Set output register of pin on event
-// <2=> Clear output register of pin on event
-// <3=> Toggle output register of pin on event
-// <i> These bits define the event action the PORT D will perform on event input 1
-// <id> portd_event_action_1
-#ifndef CONF_PORTD_EVCTRL_EVACT_1
-#define CONF_PORTD_EVCTRL_EVACT_1 0
-#endif
-
-// </h>
// </e>
@@ -336,34 +280,6 @@
#endif
// </h>
-// <h> PORT Input Event 2 configuration on PORT D
-
-// <q> PORTD Input Event 2 Enable
-// <i> The event action will be triggered on any incoming event if PORT D Input Event 2 configuration is enabled
-// <id> portd_input_event_enable_2
-#ifndef CONF_PORTD_EVCTRL_PORTEI_2
-#define CONF_PORTD_EVCTRL_PORTEI_2 0x0
-#endif
-
-// <o> PORTD Event 2 Pin Identifier <0x00-0x1F>
-// <i> These bits define the I/O pin from port D on which the event action will be performed
-// <id> portd_event_pin_identifier_2
-#ifndef CONF_PORTD_EVCTRL_PID_2
-#define CONF_PORTD_EVCTRL_PID_2 0x0
-#endif
-
-// <o> PORTD Event 2 Action
-// <0=> Output register of pin will be set to level of event
-// <1=> Set output register of pin on event
-// <2=> Clear output register of pin on event
-// <3=> Toggle output register of pin on event
-// <i> These bits define the event action the PORT D will perform on event input 2
-// <id> portd_event_action_2
-#ifndef CONF_PORTD_EVCTRL_EVACT_2
-#define CONF_PORTD_EVCTRL_EVACT_2 0
-#endif
-
-// </h>
// </e>
@@ -457,34 +373,6 @@
#endif
// </h>
-// <h> PORT Input Event 3 configuration on PORT D
-
-// <q> PORTD Input Event 3 Enable
-// <i> The event action will be triggered on any incoming event if PORT D Input Event 3 configuration is enabled
-// <id> portd_input_event_enable_3
-#ifndef CONF_PORTD_EVCTRL_PORTEI_3
-#define CONF_PORTD_EVCTRL_PORTEI_3 0x0
-#endif
-
-// <o> PORTD Event 3 Pin Identifier <0x00-0x1F>
-// <i> These bits define the I/O pin from port D on which the event action will be performed
-// <id> portd_event_pin_identifier_3
-#ifndef CONF_PORTD_EVCTRL_PID_3
-#define CONF_PORTD_EVCTRL_PID_3 0x0
-#endif
-
-// <o> PORTD Event 3 Action
-// <0=> Output register of pin will be set to level of event
-// <1=> Set output register of pin on event
-// <2=> Clear output register of pin on event
-// <3=> Toggle output register of pin on event
-// <i> These bits define the event action the PORT D will perform on event input 3
-// <id> portd_event_action_3
-#ifndef CONF_PORTD_EVCTRL_EVACT_3
-#define CONF_PORTD_EVCTRL_EVACT_3 0
-#endif
-
-// </h>
// </e>
@@ -509,13 +397,6 @@
| PORT_EVCTRL_EVACT2(CONF_PORTC_EVCTRL_EVACT_2) | CONF_PORTC_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
| PORT_EVCTRL_PID2(CONF_PORTC_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTC_EVCTRL_EVACT_3) \
| CONF_PORTC_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTC_EVCTRL_PID_3))
-#define CONF_PORTD_EVCTRL \
- (0 | PORT_EVCTRL_EVACT0(CONF_PORTD_EVCTRL_EVACT_0) | CONF_PORTD_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
- | PORT_EVCTRL_PID0(CONF_PORTD_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTD_EVCTRL_EVACT_1) \
- | CONF_PORTD_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTD_EVCTRL_PID_1) \
- | PORT_EVCTRL_EVACT2(CONF_PORTD_EVCTRL_EVACT_2) | CONF_PORTD_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
- | PORT_EVCTRL_PID2(CONF_PORTD_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTD_EVCTRL_EVACT_3) \
- | CONF_PORTD_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTD_EVCTRL_PID_3))
// <<< end of configuration section >>>
diff --git a/sysmoOCTSIM/config/hpl_sercom_config.h b/sysmoOCTSIM/config/hpl_sercom_config.h
index e154ce2..2a8c023 100644
--- a/sysmoOCTSIM/config/hpl_sercom_config.h
+++ b/sysmoOCTSIM/config/hpl_sercom_config.h
@@ -6,8 +6,8 @@
#include <peripheral_clk_config.h>
-#ifndef CONF_SERCOM_2_USART_ENABLE
-#define CONF_SERCOM_2_USART_ENABLE 1
+#ifndef CONF_SERCOM_7_USART_ENABLE
+#define CONF_SERCOM_7_USART_ENABLE 1
#endif
// <h> Basic Configuration
@@ -15,15 +15,15 @@
// <q> Receive buffer enable
// <i> Enable input buffer in SERCOM module
// <id> usart_rx_enable
-#ifndef CONF_SERCOM_2_USART_RXEN
-#define CONF_SERCOM_2_USART_RXEN 1
+#ifndef CONF_SERCOM_7_USART_RXEN
+#define CONF_SERCOM_7_USART_RXEN 1
#endif
// <q> Transmitt buffer enable
// <i> Enable output buffer in SERCOM module
// <id> usart_tx_enable
-#ifndef CONF_SERCOM_2_USART_TXEN
-#define CONF_SERCOM_2_USART_TXEN 1
+#ifndef CONF_SERCOM_7_USART_TXEN
+#define CONF_SERCOM_7_USART_TXEN 1
#endif
// <o> Frame parity
@@ -32,8 +32,8 @@
// <0x2=>Odd parity
// <i> Parity bit mode for USART frame
// <id> usart_parity
-#ifndef CONF_SERCOM_2_USART_PARITY
-#define CONF_SERCOM_2_USART_PARITY 0x0
+#ifndef CONF_SERCOM_7_USART_PARITY
+#define CONF_SERCOM_7_USART_PARITY 0x0
#endif
// <o> Character Size
@@ -44,8 +44,8 @@
// <0x7=>7 bits
// <i> Data character size in USART frame
// <id> usart_character_size
-#ifndef CONF_SERCOM_2_USART_CHSIZE
-#define CONF_SERCOM_2_USART_CHSIZE 0x0
+#ifndef CONF_SERCOM_7_USART_CHSIZE
+#define CONF_SERCOM_7_USART_CHSIZE 0x0
#endif
// <o> Stop Bit
@@ -53,51 +53,51 @@
// <1=>Two stop bits
// <i> Number of stop bits in USART frame
// <id> usart_stop_bit
-#ifndef CONF_SERCOM_2_USART_SBMODE
-#define CONF_SERCOM_2_USART_SBMODE 0
+#ifndef CONF_SERCOM_7_USART_SBMODE
+#define CONF_SERCOM_7_USART_SBMODE 0
#endif
// <o> Baud rate <1-6250000>
// <i> USART baud rate setting
// <id> usart_baud_rate
-#ifndef CONF_SERCOM_2_USART_BAUD
-#define CONF_SERCOM_2_USART_BAUD 921600
+#ifndef CONF_SERCOM_7_USART_BAUD
+#define CONF_SERCOM_7_USART_BAUD 921600
#endif
// </h>
// <e> Advanced configuration
// <id> usart_advanced
-#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG
-#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0
+#ifndef CONF_SERCOM_7_USART_ADVANCED_CONFIG
+#define CONF_SERCOM_7_USART_ADVANCED_CONFIG 0
#endif
// <q> Run in stand-by
// <i> Keep the module running in standby sleep mode
// <id> usart_arch_runstdby
-#ifndef CONF_SERCOM_2_USART_RUNSTDBY
-#define CONF_SERCOM_2_USART_RUNSTDBY 0
+#ifndef CONF_SERCOM_7_USART_RUNSTDBY
+#define CONF_SERCOM_7_USART_RUNSTDBY 0
#endif
// <q> Immediate Buffer Overflow Notification
// <i> Controls when the BUFOVF status bit is asserted
// <id> usart_arch_ibon
-#ifndef CONF_SERCOM_2_USART_IBON
-#define CONF_SERCOM_2_USART_IBON 0
+#ifndef CONF_SERCOM_7_USART_IBON
+#define CONF_SERCOM_7_USART_IBON 0
#endif
// <q> Start of Frame Detection Enable
// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
// <id> usart_arch_sfde
-#ifndef CONF_SERCOM_2_USART_SFDE
-#define CONF_SERCOM_2_USART_SFDE 0
+#ifndef CONF_SERCOM_7_USART_SFDE
+#define CONF_SERCOM_7_USART_SFDE 0
#endif
// <q> Collision Detection Enable
// <i> Collision detection enable
// <id> usart_arch_cloden
-#ifndef CONF_SERCOM_2_USART_CLODEN
-#define CONF_SERCOM_2_USART_CLODEN 0
+#ifndef CONF_SERCOM_7_USART_CLODEN
+#define CONF_SERCOM_7_USART_CLODEN 0
#endif
// <o> Operating Mode
@@ -105,8 +105,8 @@
// <0x1=>USART with internal clock
// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin.
// <id> usart_arch_clock_mode
-#ifndef CONF_SERCOM_2_USART_MODE
-#define CONF_SERCOM_2_USART_MODE 0x1
+#ifndef CONF_SERCOM_7_USART_MODE
+#define CONF_SERCOM_7_USART_MODE 0x1
#endif
// <o> Sample Rate
@@ -117,8 +117,8 @@
// <0x4=>3x arithmetic
// <i> How many over-sampling bits used when sampling data state
// <id> usart_arch_sampr
-#ifndef CONF_SERCOM_2_USART_SAMPR
-#define CONF_SERCOM_2_USART_SAMPR 0x0
+#ifndef CONF_SERCOM_7_USART_SAMPR
+#define CONF_SERCOM_7_USART_SAMPR 0x0
#endif
// <o> Sample Adjustment
@@ -128,15 +128,15 @@
// <0x3=>13-14-15 (6-7-8 8-bit over-sampling)
// <i> Adjust which samples to use for data sampling in asynchronous mode
// <id> usart_arch_sampa
-#ifndef CONF_SERCOM_2_USART_SAMPA
-#define CONF_SERCOM_2_USART_SAMPA 0x0
+#ifndef CONF_SERCOM_7_USART_SAMPA
+#define CONF_SERCOM_7_USART_SAMPA 0x0
#endif
// <o> Fractional Part <0-7>
// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
// <id> usart_arch_fractional
-#ifndef CONF_SERCOM_2_USART_FRACTIONAL
-#define CONF_SERCOM_2_USART_FRACTIONAL 0x0
+#ifndef CONF_SERCOM_7_USART_FRACTIONAL
+#define CONF_SERCOM_7_USART_FRACTIONAL 0x0
#endif
// <o> Data Order
@@ -144,19 +144,19 @@
// <1=>LSB is transmitted first
// <i> Data order of the data bits in the frame
// <id> usart_arch_dord
-#ifndef CONF_SERCOM_2_USART_DORD
-#define CONF_SERCOM_2_USART_DORD 1
+#ifndef CONF_SERCOM_7_USART_DORD
+#define CONF_SERCOM_7_USART_DORD 1
#endif
// Does not do anything in UART mode
-#define CONF_SERCOM_2_USART_CPOL 0
+#define CONF_SERCOM_7_USART_CPOL 0
// <o> Encoding Format
// <0=>No encoding
// <1=>IrDA encoded
// <id> usart_arch_enc
-#ifndef CONF_SERCOM_2_USART_ENC
-#define CONF_SERCOM_2_USART_ENC 0
+#ifndef CONF_SERCOM_7_USART_ENC
+#define CONF_SERCOM_7_USART_ENC 0
#endif
// <o> LIN Slave Enable
@@ -165,8 +165,8 @@
// <0=>Disable
// <1=>Enable
// <id> usart_arch_lin_slave_enable
-#ifndef CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE
-#define CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE 0
+#ifndef CONF_SERCOM_7_USART_LIN_SLAVE_ENABLE
+#define CONF_SERCOM_7_USART_LIN_SLAVE_ENABLE 0
#endif
// <o> Debug Stop Mode
@@ -174,102 +174,102 @@
// <0=>Keep running
// <1=>Halt
// <id> usart_arch_dbgstop
-#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE
-#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0
+#ifndef CONF_SERCOM_7_USART_DEBUG_STOP_MODE
+#define CONF_SERCOM_7_USART_DEBUG_STOP_MODE 0
#endif
// </e>
-#ifndef CONF_SERCOM_2_USART_INACK
-#define CONF_SERCOM_2_USART_INACK 0x0
+#ifndef CONF_SERCOM_7_USART_INACK
+#define CONF_SERCOM_7_USART_INACK 0x0
#endif
-#ifndef CONF_SERCOM_2_USART_DSNACK
-#define CONF_SERCOM_2_USART_DSNACK 0x0
+#ifndef CONF_SERCOM_7_USART_DSNACK
+#define CONF_SERCOM_7_USART_DSNACK 0x0
#endif
-#ifndef CONF_SERCOM_2_USART_MAXITER
-#define CONF_SERCOM_2_USART_MAXITER 0x7
+#ifndef CONF_SERCOM_7_USART_MAXITER
+#define CONF_SERCOM_7_USART_MAXITER 0x7
#endif
-#ifndef CONF_SERCOM_2_USART_GTIME
-#define CONF_SERCOM_2_USART_GTIME 0x2
+#ifndef CONF_SERCOM_7_USART_GTIME
+#define CONF_SERCOM_7_USART_GTIME 0x2
#endif
-#define CONF_SERCOM_2_USART_RXINV 0x0
-#define CONF_SERCOM_2_USART_TXINV 0x0
+#define CONF_SERCOM_7_USART_RXINV 0x0
+#define CONF_SERCOM_7_USART_TXINV 0x0
-#ifndef CONF_SERCOM_2_USART_CMODE
-#define CONF_SERCOM_2_USART_CMODE 0
+#ifndef CONF_SERCOM_7_USART_CMODE
+#define CONF_SERCOM_7_USART_CMODE 0
#endif
-#ifndef CONF_SERCOM_2_USART_RXPO
-#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PB24 */
+#ifndef CONF_SERCOM_7_USART_RXPO
+#define CONF_SERCOM_7_USART_RXPO 1 /* RX is on PIN_PB31 */
#endif
-#ifndef CONF_SERCOM_2_USART_TXPO
-#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PB25 */
+#ifndef CONF_SERCOM_7_USART_TXPO
+#define CONF_SERCOM_7_USART_TXPO 0 /* TX is on PIN_PB30 */
#endif
/* Set correct parity settings in register interface based on PARITY setting */
-#if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 1
-#if CONF_SERCOM_2_USART_PARITY == 0
-#define CONF_SERCOM_2_USART_PMODE 0
-#define CONF_SERCOM_2_USART_FORM 4
+#if CONF_SERCOM_7_USART_LIN_SLAVE_ENABLE == 1
+#if CONF_SERCOM_7_USART_PARITY == 0
+#define CONF_SERCOM_7_USART_PMODE 0
+#define CONF_SERCOM_7_USART_FORM 4
#else
-#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
-#define CONF_SERCOM_2_USART_FORM 5
+#define CONF_SERCOM_7_USART_PMODE CONF_SERCOM_7_USART_PARITY - 1
+#define CONF_SERCOM_7_USART_FORM 5
#endif
-#else /* #if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 0 */
-#if CONF_SERCOM_2_USART_PARITY == 0
-#define CONF_SERCOM_2_USART_PMODE 0
-#define CONF_SERCOM_2_USART_FORM 0
+#else /* #if CONF_SERCOM_7_USART_LIN_SLAVE_ENABLE == 0 */
+#if CONF_SERCOM_7_USART_PARITY == 0
+#define CONF_SERCOM_7_USART_PMODE 0
+#define CONF_SERCOM_7_USART_FORM 0
#else
-#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
-#define CONF_SERCOM_2_USART_FORM 1
+#define CONF_SERCOM_7_USART_PMODE CONF_SERCOM_7_USART_PARITY - 1
+#define CONF_SERCOM_7_USART_FORM 1
#endif
#endif
// Calculate BAUD register value in UART mode
-#if CONF_SERCOM_2_USART_SAMPR == 0
-#ifndef CONF_SERCOM_2_USART_BAUD_RATE
-#define CONF_SERCOM_2_USART_BAUD_RATE \
- 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
+#if CONF_SERCOM_7_USART_SAMPR == 0
+#ifndef CONF_SERCOM_7_USART_BAUD_RATE
+#define CONF_SERCOM_7_USART_BAUD_RATE \
+ 65536 - ((65536 * 16.0f * CONF_SERCOM_7_USART_BAUD) / CONF_GCLK_SERCOM7_CORE_FREQUENCY)
#endif
-#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
-#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#ifndef CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH 0
#endif
-#elif CONF_SERCOM_2_USART_SAMPR == 1
-#ifndef CONF_SERCOM_2_USART_BAUD_RATE
-#define CONF_SERCOM_2_USART_BAUD_RATE \
- ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
+#elif CONF_SERCOM_7_USART_SAMPR == 1
+#ifndef CONF_SERCOM_7_USART_BAUD_RATE
+#define CONF_SERCOM_7_USART_BAUD_RATE \
+ ((CONF_GCLK_SERCOM7_CORE_FREQUENCY) / (CONF_SERCOM_7_USART_BAUD * 16)) - (CONF_SERCOM_7_USART_FRACTIONAL / 8)
#endif
-#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
-#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#ifndef CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH 0
#endif
-#elif CONF_SERCOM_2_USART_SAMPR == 2
-#ifndef CONF_SERCOM_2_USART_BAUD_RATE
-#define CONF_SERCOM_2_USART_BAUD_RATE \
- 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
+#elif CONF_SERCOM_7_USART_SAMPR == 2
+#ifndef CONF_SERCOM_7_USART_BAUD_RATE
+#define CONF_SERCOM_7_USART_BAUD_RATE \
+ 65536 - ((65536 * 8.0f * CONF_SERCOM_7_USART_BAUD) / CONF_GCLK_SERCOM7_CORE_FREQUENCY)
#endif
-#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
-#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#ifndef CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH 0
#endif
-#elif CONF_SERCOM_2_USART_SAMPR == 3
-#ifndef CONF_SERCOM_2_USART_BAUD_RATE
-#define CONF_SERCOM_2_USART_BAUD_RATE \
- ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
+#elif CONF_SERCOM_7_USART_SAMPR == 3
+#ifndef CONF_SERCOM_7_USART_BAUD_RATE
+#define CONF_SERCOM_7_USART_BAUD_RATE \
+ ((CONF_GCLK_SERCOM7_CORE_FREQUENCY) / (CONF_SERCOM_7_USART_BAUD * 8)) - (CONF_SERCOM_7_USART_FRACTIONAL / 8)
#endif
-#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
-#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#ifndef CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH 0
#endif
-#elif CONF_SERCOM_2_USART_SAMPR == 4
-#ifndef CONF_SERCOM_2_USART_BAUD_RATE
-#define CONF_SERCOM_2_USART_BAUD_RATE \
- 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
+#elif CONF_SERCOM_7_USART_SAMPR == 4
+#ifndef CONF_SERCOM_7_USART_BAUD_RATE
+#define CONF_SERCOM_7_USART_BAUD_RATE \
+ 65536 - ((65536 * 3.0f * CONF_SERCOM_7_USART_BAUD) / CONF_GCLK_SERCOM7_CORE_FREQUENCY)
#endif
-#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
-#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#ifndef CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH 0
#endif
#endif
diff --git a/sysmoOCTSIM/config/hpl_usb_config.h b/sysmoOCTSIM/config/hpl_usb_config.h
index 02439a3..73a9fea 100644
--- a/sysmoOCTSIM/config/hpl_usb_config.h
+++ b/sysmoOCTSIM/config/hpl_usb_config.h
@@ -39,7 +39,7 @@
// <CONF_USB_D_N_EP_MAX"> Max possible (by "Max Endpoint Number" config)
// <id> usbd_num_ep_sp
#ifndef CONF_USB_D_NUM_EP_SP
-#define CONF_USB_D_NUM_EP_SP CONF_USB_D_N_EP_MAX
+#define CONF_USB_D_NUM_EP_SP CONF_USB_N_4
#endif
// </h>
diff --git a/sysmoOCTSIM/config/peripheral_clk_config.h b/sysmoOCTSIM/config/peripheral_clk_config.h
index c9852b6..ce68abd 100644
--- a/sysmoOCTSIM/config/peripheral_clk_config.h
+++ b/sysmoOCTSIM/config/peripheral_clk_config.h
@@ -40,8 +40,8 @@
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for CORE.
-#ifndef CONF_GCLK_SERCOM2_CORE_SRC
-#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
+#ifndef CONF_GCLK_SERCOM7_CORE_SRC
+#define CONF_GCLK_SERCOM7_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
#endif
// <y> Slow Clock Source
@@ -72,24 +72,24 @@
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the slow clock source.
-#ifndef CONF_GCLK_SERCOM2_SLOW_SRC
-#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#ifndef CONF_GCLK_SERCOM7_SLOW_SRC
+#define CONF_GCLK_SERCOM7_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
- * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY
- * \brief SERCOM2's Core Clock frequency
+ * \def CONF_GCLK_SERCOM7_CORE_FREQUENCY
+ * \brief SERCOM7's Core Clock frequency
*/
-#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 100000000
+#ifndef CONF_GCLK_SERCOM7_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM7_CORE_FREQUENCY 100000000
#endif
/**
- * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY
- * \brief SERCOM2's Slow Clock frequency
+ * \def CONF_GCLK_SERCOM7_SLOW_FREQUENCY
+ * \brief SERCOM7's Slow Clock frequency
*/
-#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY
-#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768
+#ifndef CONF_GCLK_SERCOM7_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM7_SLOW_FREQUENCY 32768
#endif
// <y> USB Clock Source