add SERCOM peripheral for UART debug
currently only the SERCOM peripheral driver is added an configured,
but it is not being used.
UART debug will be done through the EDBG COM port, on PB24/PB25 of
SAM E54 Xplained Pro board
Change-Id: Id7af37ce1dd2d0a356e019c96bf6438ce459411b
diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h
index 0ad8ead..12c1539 100644
--- a/sysmoOCTSIM/config/hpl_gclk_config.h
+++ b/sysmoOCTSIM/config/hpl_gclk_config.h
@@ -218,7 +218,7 @@
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_2_enable
#ifndef CONF_GCLK_GEN_2_GENEN
-#define CONF_GCLK_GEN_2_GENEN 0
+#define CONF_GCLK_GEN_2_GENEN 1
#endif
// </h>
diff --git a/sysmoOCTSIM/config/hpl_sercom_config.h b/sysmoOCTSIM/config/hpl_sercom_config.h
new file mode 100644
index 0000000..e154ce2
--- /dev/null
+++ b/sysmoOCTSIM/config/hpl_sercom_config.h
@@ -0,0 +1,278 @@
+/* Auto-generated config file hpl_sercom_config.h */
+#ifndef HPL_SERCOM_CONFIG_H
+#define HPL_SERCOM_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+#ifndef CONF_SERCOM_2_USART_ENABLE
+#define CONF_SERCOM_2_USART_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable input buffer in SERCOM module
+// <id> usart_rx_enable
+#ifndef CONF_SERCOM_2_USART_RXEN
+#define CONF_SERCOM_2_USART_RXEN 1
+#endif
+
+// <q> Transmitt buffer enable
+// <i> Enable output buffer in SERCOM module
+// <id> usart_tx_enable
+#ifndef CONF_SERCOM_2_USART_TXEN
+#define CONF_SERCOM_2_USART_TXEN 1
+#endif
+
+// <o> Frame parity
+// <0x0=>No parity
+// <0x1=>Even parity
+// <0x2=>Odd parity
+// <i> Parity bit mode for USART frame
+// <id> usart_parity
+#ifndef CONF_SERCOM_2_USART_PARITY
+#define CONF_SERCOM_2_USART_PARITY 0x0
+#endif
+
+// <o> Character Size
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <0x5=>5 bits
+// <0x6=>6 bits
+// <0x7=>7 bits
+// <i> Data character size in USART frame
+// <id> usart_character_size
+#ifndef CONF_SERCOM_2_USART_CHSIZE
+#define CONF_SERCOM_2_USART_CHSIZE 0x0
+#endif
+
+// <o> Stop Bit
+// <0=>One stop bit
+// <1=>Two stop bits
+// <i> Number of stop bits in USART frame
+// <id> usart_stop_bit
+#ifndef CONF_SERCOM_2_USART_SBMODE
+#define CONF_SERCOM_2_USART_SBMODE 0
+#endif
+
+// <o> Baud rate <1-6250000>
+// <i> USART baud rate setting
+// <id> usart_baud_rate
+#ifndef CONF_SERCOM_2_USART_BAUD
+#define CONF_SERCOM_2_USART_BAUD 921600
+#endif
+
+// </h>
+
+// <e> Advanced configuration
+// <id> usart_advanced
+#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG
+#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0
+#endif
+
+// <q> Run in stand-by
+// <i> Keep the module running in standby sleep mode
+// <id> usart_arch_runstdby
+#ifndef CONF_SERCOM_2_USART_RUNSTDBY
+#define CONF_SERCOM_2_USART_RUNSTDBY 0
+#endif
+
+// <q> Immediate Buffer Overflow Notification
+// <i> Controls when the BUFOVF status bit is asserted
+// <id> usart_arch_ibon
+#ifndef CONF_SERCOM_2_USART_IBON
+#define CONF_SERCOM_2_USART_IBON 0
+#endif
+
+// <q> Start of Frame Detection Enable
+// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
+// <id> usart_arch_sfde
+#ifndef CONF_SERCOM_2_USART_SFDE
+#define CONF_SERCOM_2_USART_SFDE 0
+#endif
+
+// <q> Collision Detection Enable
+// <i> Collision detection enable
+// <id> usart_arch_cloden
+#ifndef CONF_SERCOM_2_USART_CLODEN
+#define CONF_SERCOM_2_USART_CLODEN 0
+#endif
+
+// <o> Operating Mode
+// <0x0=>USART with external clock
+// <0x1=>USART with internal clock
+// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin.
+// <id> usart_arch_clock_mode
+#ifndef CONF_SERCOM_2_USART_MODE
+#define CONF_SERCOM_2_USART_MODE 0x1
+#endif
+
+// <o> Sample Rate
+// <0x0=>16x arithmetic
+// <0x1=>16x fractional
+// <0x2=>8x arithmetic
+// <0x3=>8x fractional
+// <0x4=>3x arithmetic
+// <i> How many over-sampling bits used when sampling data state
+// <id> usart_arch_sampr
+#ifndef CONF_SERCOM_2_USART_SAMPR
+#define CONF_SERCOM_2_USART_SAMPR 0x0
+#endif
+
+// <o> Sample Adjustment
+// <0x0=>7-8-9 (3-4-5 8-bit over-sampling)
+// <0x1=>9-10-11 (4-5-6 8-bit over-sampling)
+// <0x2=>11-12-13 (5-6-7 8-bit over-sampling)
+// <0x3=>13-14-15 (6-7-8 8-bit over-sampling)
+// <i> Adjust which samples to use for data sampling in asynchronous mode
+// <id> usart_arch_sampa
+#ifndef CONF_SERCOM_2_USART_SAMPA
+#define CONF_SERCOM_2_USART_SAMPA 0x0
+#endif
+
+// <o> Fractional Part <0-7>
+// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
+// <id> usart_arch_fractional
+#ifndef CONF_SERCOM_2_USART_FRACTIONAL
+#define CONF_SERCOM_2_USART_FRACTIONAL 0x0
+#endif
+
+// <o> Data Order
+// <0=>MSB is transmitted first
+// <1=>LSB is transmitted first
+// <i> Data order of the data bits in the frame
+// <id> usart_arch_dord
+#ifndef CONF_SERCOM_2_USART_DORD
+#define CONF_SERCOM_2_USART_DORD 1
+#endif
+
+// Does not do anything in UART mode
+#define CONF_SERCOM_2_USART_CPOL 0
+
+// <o> Encoding Format
+// <0=>No encoding
+// <1=>IrDA encoded
+// <id> usart_arch_enc
+#ifndef CONF_SERCOM_2_USART_ENC
+#define CONF_SERCOM_2_USART_ENC 0
+#endif
+
+// <o> LIN Slave Enable
+// <i> Break Character Detection and Auto-Baud/LIN Slave Enable.
+// <i> Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1).
+// <0=>Disable
+// <1=>Enable
+// <id> usart_arch_lin_slave_enable
+#ifndef CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE
+#define CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE 0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
+// <0=>Keep running
+// <1=>Halt
+// <id> usart_arch_dbgstop
+#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE
+#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0
+#endif
+
+// </e>
+
+#ifndef CONF_SERCOM_2_USART_INACK
+#define CONF_SERCOM_2_USART_INACK 0x0
+#endif
+
+#ifndef CONF_SERCOM_2_USART_DSNACK
+#define CONF_SERCOM_2_USART_DSNACK 0x0
+#endif
+
+#ifndef CONF_SERCOM_2_USART_MAXITER
+#define CONF_SERCOM_2_USART_MAXITER 0x7
+#endif
+
+#ifndef CONF_SERCOM_2_USART_GTIME
+#define CONF_SERCOM_2_USART_GTIME 0x2
+#endif
+
+#define CONF_SERCOM_2_USART_RXINV 0x0
+#define CONF_SERCOM_2_USART_TXINV 0x0
+
+#ifndef CONF_SERCOM_2_USART_CMODE
+#define CONF_SERCOM_2_USART_CMODE 0
+#endif
+
+#ifndef CONF_SERCOM_2_USART_RXPO
+#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PB24 */
+#endif
+
+#ifndef CONF_SERCOM_2_USART_TXPO
+#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PB25 */
+#endif
+
+/* Set correct parity settings in register interface based on PARITY setting */
+#if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 1
+#if CONF_SERCOM_2_USART_PARITY == 0
+#define CONF_SERCOM_2_USART_PMODE 0
+#define CONF_SERCOM_2_USART_FORM 4
+#else
+#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
+#define CONF_SERCOM_2_USART_FORM 5
+#endif
+#else /* #if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 0 */
+#if CONF_SERCOM_2_USART_PARITY == 0
+#define CONF_SERCOM_2_USART_PMODE 0
+#define CONF_SERCOM_2_USART_FORM 0
+#else
+#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
+#define CONF_SERCOM_2_USART_FORM 1
+#endif
+#endif
+
+// Calculate BAUD register value in UART mode
+#if CONF_SERCOM_2_USART_SAMPR == 0
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE \
+ 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_2_USART_SAMPR == 1
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE \
+ ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
+#endif
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_2_USART_SAMPR == 2
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE \
+ 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_2_USART_SAMPR == 3
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE \
+ ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
+#endif
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_2_USART_SAMPR == 4
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE \
+ 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // HPL_SERCOM_CONFIG_H
diff --git a/sysmoOCTSIM/config/peripheral_clk_config.h b/sysmoOCTSIM/config/peripheral_clk_config.h
index 8078e4b..c9852b6 100644
--- a/sysmoOCTSIM/config/peripheral_clk_config.h
+++ b/sysmoOCTSIM/config/peripheral_clk_config.h
@@ -12,6 +12,86 @@
#define CONF_CPU_FREQUENCY 120000000
#endif
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM2_CORE_SRC
+#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM2_SLOW_SRC
+#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY
+ * \brief SERCOM2's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 100000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY
+ * \brief SERCOM2's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768
+#endif
+
// <y> USB Clock Source
// <id> usb_gclk_selection