diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h
index 398a617..0ad8ead 100644
--- a/sysmoOCTSIM/config/hpl_gclk_config.h
+++ b/sysmoOCTSIM/config/hpl_gclk_config.h
@@ -218,7 +218,7 @@
 // <i> Indicates whether Generic Clock Generator Enable is enabled or not
 // <id> gclk_arch_gen_2_enable
 #ifndef CONF_GCLK_GEN_2_GENEN
-#define CONF_GCLK_GEN_2_GENEN 1
+#define CONF_GCLK_GEN_2_GENEN 0
 #endif
 // </h>
 
@@ -843,7 +843,7 @@
 // <i> Indicates whether generic clock 11 configuration is enabled or not
 // <id> enable_gclk_gen_11
 #ifndef CONF_GCLK_GENERATOR_11_CONFIG
-#define CONF_GCLK_GENERATOR_11_CONFIG 1
+#define CONF_GCLK_GENERATOR_11_CONFIG 0
 #endif
 
 // <h> Generic Clock Generator Control
diff --git a/sysmoOCTSIM/config/hpl_oscctrl_config.h b/sysmoOCTSIM/config/hpl_oscctrl_config.h
index 06ee571..0676cb5 100644
--- a/sysmoOCTSIM/config/hpl_oscctrl_config.h
+++ b/sysmoOCTSIM/config/hpl_oscctrl_config.h
@@ -507,7 +507,7 @@
 // <i> Indicates whether configuration for FDPLL1 is enabled or not
 // <id> enable_fdpll1
 #ifndef CONF_FDPLL1_CONFIG
-#define CONF_FDPLL1_CONFIG 0
+#define CONF_FDPLL1_CONFIG 1
 #endif
 
 // <y> Reference Clock Source
@@ -529,7 +529,7 @@
 // <i> Select the clock source.
 // <id> fdpll1_ref_clock
 #ifndef CONF_FDPLL1_GCLK
-#define CONF_FDPLL1_GCLK GCLK_PCHCTRL_GEN_GCLK11_Val
+#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC1
 #endif
 
 // <h> Digital Phase Locked Loop Control