Fix SystemCoreClock for our use case (120 MHz)
With all the tons of ASF4 library code, ARM/Microchip couldn't even
bothered to implement the most basic CMSIS bits such as the
SystemCoreClockUpdate() function that would dynamically compute
the current SysTick rate at runtime.
To make things worse, they're also not using the #define they have
for the initial core clock rate that's set up at boot time but rather
have a hardcoded 48 MHz value as SystemCoreClock.
Without a correct SystemCoreClock, the jiffies rate is wrong, and
all related timing off.
Change-Id: I9966de4d9ad4e623893044fc341b9852659e8f39
diff --git a/sysmoOCTSIM/gcc/system_same54.c b/sysmoOCTSIM/gcc/system_same54.c
index 55a5fd2..9d17c8d 100644
--- a/sysmoOCTSIM/gcc/system_same54.c
+++ b/sysmoOCTSIM/gcc/system_same54.c
@@ -28,12 +28,13 @@
*/
#include "same54.h"
+#include "peripheral_clk_config.h"
/**
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
* the source for the main clock at chip startup.
*/
-#define __SYSTEM_CLOCK (48000000)
+#define __SYSTEM_CLOCK CONF_CPU_FREQUENCY
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/