set DPLL1 to 100 MHz
use GCLK11 to bring external crystal oscillator XOSC1 from 12 MHz
to 2MHz
use DPLL1 to multiply 2 MHz to 100 MHz.
the division is first needed because the DPLL0 maximum input
frequency is 3.2 MHz
100 MHz is the maximum input frequency for the SERCOM peripherals
Change-Id: I0482c39cc0db999904c585d21738dbce57ca3b55
diff --git a/sysmoOCTSIM/hpl/core/hpl_init.c b/sysmoOCTSIM/hpl/core/hpl_init.c
index 6f3dc20..bb8425c 100644
--- a/sysmoOCTSIM/hpl/core/hpl_init.c
+++ b/sysmoOCTSIM/hpl/core/hpl_init.c
@@ -42,6 +42,7 @@
#include <hal_cache.h>
/* Referenced GCLKs (out of 0~11), should be initialized firstly
+ * - GCLK 11 for FDPLL1
* - GCLK 11 for FDPLL0
*/
#define _GCLK_INIT_1ST 0x00000800