set DPLL1 to 100 MHz
use GCLK11 to bring external crystal oscillator XOSC1 from 12 MHz
to 2MHz
use DPLL1 to multiply 2 MHz to 100 MHz.
the division is first needed because the DPLL0 maximum input
frequency is 3.2 MHz
100 MHz is the maximum input frequency for the SERCOM peripherals
Change-Id: I0482c39cc0db999904c585d21738dbce57ca3b55
diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h
index fbaa9b7..398a617 100644
--- a/sysmoOCTSIM/config/hpl_gclk_config.h
+++ b/sysmoOCTSIM/config/hpl_gclk_config.h
@@ -159,7 +159,7 @@
// <i> Indicates whether generic clock 2 configuration is enabled or not
// <id> enable_gclk_gen_2
#ifndef CONF_GCLK_GENERATOR_2_CONFIG
-#define CONF_GCLK_GENERATOR_2_CONFIG 0
+#define CONF_GCLK_GENERATOR_2_CONFIG 1
#endif
// <h> Generic Clock Generator Control
@@ -176,7 +176,7 @@
// <i> This defines the clock source for generic clock generator 2
// <id> gclk_gen_2_oscillator
#ifndef CONF_GCLK_GEN_2_SOURCE
-#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC0
+#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_DPLL1
#endif
// <q> Run in Standby
@@ -190,7 +190,7 @@
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_2_div_sel
#ifndef CONF_GCLK_GEN_2_DIVSEL
-#define CONF_GCLK_GEN_2_DIVSEL 1
+#define CONF_GCLK_GEN_2_DIVSEL 0
#endif
// <q> Output Enable
@@ -218,7 +218,7 @@
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_2_enable
#ifndef CONF_GCLK_GEN_2_GENEN
-#define CONF_GCLK_GEN_2_GENEN 0
+#define CONF_GCLK_GEN_2_GENEN 1
#endif
// </h>
diff --git a/sysmoOCTSIM/config/hpl_oscctrl_config.h b/sysmoOCTSIM/config/hpl_oscctrl_config.h
index 6b3cc19..06ee571 100644
--- a/sysmoOCTSIM/config/hpl_oscctrl_config.h
+++ b/sysmoOCTSIM/config/hpl_oscctrl_config.h
@@ -529,7 +529,7 @@
// <i> Select the clock source.
// <id> fdpll1_ref_clock
#ifndef CONF_FDPLL1_GCLK
-#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K
+#define CONF_FDPLL1_GCLK GCLK_PCHCTRL_GEN_GCLK11_Val
#endif
// <h> Digital Phase Locked Loop Control
@@ -537,7 +537,7 @@
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
// <id> fdpll1_arch_enable
#ifndef CONF_FDPLL1_ENABLE
-#define CONF_FDPLL1_ENABLE 0
+#define CONF_FDPLL1_ENABLE 1
#endif
// <q> On Demand Control
@@ -557,19 +557,19 @@
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
// <id> fdpll1_ldrfrac
#ifndef CONF_FDPLL1_LDRFRAC
-#define CONF_FDPLL1_LDRFRAC 0xd
+#define CONF_FDPLL1_LDRFRAC 0x0
#endif
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
// <id> fdpll1_ldr
#ifndef CONF_FDPLL1_LDR
-#define CONF_FDPLL1_LDR 0x5b7
+#define CONF_FDPLL1_LDR 0x31
#endif
// <o> Clock Divider <0x0-0x7FF>
// <id> fdpll1_clock_div
#ifndef CONF_FDPLL1_DIV
-#define CONF_FDPLL1_DIV 0x0
+#define CONF_FDPLL1_DIV 0x6
#endif
// <q> DCO Filter Enable
@@ -610,7 +610,7 @@
// <0x3=>XOSC1 clock reference
// <id> fdpll1_arch_refclk
#ifndef CONF_FDPLL1_REFCLK
-#define CONF_FDPLL1_REFCLK 0x1
+#define CONF_FDPLL1_REFCLK 0x3
#endif
// <q> Wake Up Fast