gsm0808: add function to convert amr gsm0408 setings to gsm0808
Add a function to convert struct gsm48_multi_rate_conf, which holds the
codec settings for AMR, to S0-S15 bit representation as defined in
3GPP TS 48.008 3.2.2.49
This resurrects change-id I4e656731b16621736c7a2f4e64d9ce63b1064e98
which was reverted in I9e0d405e303ed86d23703ca6362e958dddb2f861
due to gsm0808_test failing.
The test failure is fixed by properly clearing the struct
gsm48_multirate_cfg prior to running tests (add memset(0)).
Change-Id: Ia782e21c206c15e840226d79b4209d13658ee916
Related: OS#3548
diff --git a/tests/gsm0808/gsm0808_test.c b/tests/gsm0808/gsm0808_test.c
index ae138be..6faa689 100644
--- a/tests/gsm0808/gsm0808_test.c
+++ b/tests/gsm0808/gsm0808_test.c
@@ -1444,6 +1444,202 @@
msgb_free(msg);
}
+static void test_gsm0808_sc_cfg_from_gsm48_mr_cfg_single(struct gsm48_multi_rate_conf *cfg)
+{
+ uint16_t s15_s0;
+
+ printf("Input:\n");
+ printf(" m4_75= %u smod= %u\n", cfg->m4_75, cfg->smod);
+ printf(" m5_15= %u spare= %u\n", cfg->m5_15, cfg->spare);
+ printf(" m5_90= %u icmi= %u\n", cfg->m5_90, cfg->icmi);
+ printf(" m6_70= %u nscb= %u\n", cfg->m6_70, cfg->nscb);
+ printf(" m7_40= %u ver= %u\n", cfg->m7_40, cfg->ver);
+ printf(" m7_95= %u\n", cfg->m7_95);
+ printf(" m10_2= %u\n", cfg->m10_2);
+ printf(" m12_2= %u\n", cfg->m12_2);
+
+ s15_s0 = gsm0808_sc_cfg_from_gsm48_mr_cfg(cfg, true);
+ printf("Result (fr):\n");
+ printf(" S15-S0 = %04x = 0b" OSMO_BIN_SPEC OSMO_BIN_SPEC "\n", s15_s0,
+ OSMO_BIN_PRINT(s15_s0 >> 8), OSMO_BIN_PRINT(s15_s0));
+
+ s15_s0 = gsm0808_sc_cfg_from_gsm48_mr_cfg(cfg, false);
+ printf("Result (hr):\n");
+ printf(" S15-S0 = %04x = 0b" OSMO_BIN_SPEC OSMO_BIN_SPEC "\n", s15_s0,
+ OSMO_BIN_PRINT(s15_s0 >> 8), OSMO_BIN_PRINT(s15_s0));
+
+ printf("\n");
+}
+
+static void test_gsm0808_sc_cfg_from_gsm48_mr_cfg(void)
+{
+ struct gsm48_multi_rate_conf cfg;
+
+ printf("Testing gsm0808_sc_cfg_from_gsm48_mr_cfg():\n");
+
+ memset(&cfg, 0, sizeof(cfg));
+
+ cfg.m4_75 = 0;
+ cfg.m5_15 = 0;
+ cfg.m5_90 = 0;
+ cfg.m6_70 = 0;
+ cfg.m7_40 = 0;
+ cfg.m7_95 = 0;
+ cfg.m10_2 = 0;
+ cfg.m12_2 = 0;
+ test_gsm0808_sc_cfg_from_gsm48_mr_cfg_single(&cfg);
+
+ cfg.m4_75 = 1;
+ cfg.m5_15 = 0;
+ cfg.m5_90 = 0;
+ cfg.m6_70 = 0;
+ cfg.m7_40 = 0;
+ cfg.m7_95 = 0;
+ cfg.m10_2 = 0;
+ cfg.m12_2 = 0;
+ test_gsm0808_sc_cfg_from_gsm48_mr_cfg_single(&cfg);
+
+ cfg.m4_75 = 0;
+ cfg.m5_15 = 1;
+ cfg.m5_90 = 0;
+ cfg.m6_70 = 0;
+ cfg.m7_40 = 0;
+ cfg.m7_95 = 0;
+ cfg.m10_2 = 0;
+ cfg.m12_2 = 0;
+ test_gsm0808_sc_cfg_from_gsm48_mr_cfg_single(&cfg);
+
+ cfg.m4_75 = 0;
+ cfg.m5_15 = 0;
+ cfg.m5_90 = 1;
+ cfg.m6_70 = 0;
+ cfg.m7_40 = 0;
+ cfg.m7_95 = 0;
+ cfg.m10_2 = 0;
+ cfg.m12_2 = 0;
+ test_gsm0808_sc_cfg_from_gsm48_mr_cfg_single(&cfg);
+
+ cfg.m4_75 = 0;
+ cfg.m5_15 = 0;
+ cfg.m5_90 = 0;
+ cfg.m6_70 = 1;
+ cfg.m7_40 = 0;
+ cfg.m7_95 = 0;
+ cfg.m10_2 = 0;
+ cfg.m12_2 = 0;
+ test_gsm0808_sc_cfg_from_gsm48_mr_cfg_single(&cfg);
+
+ cfg.m4_75 = 0;
+ cfg.m5_15 = 0;
+ cfg.m5_90 = 0;
+ cfg.m6_70 = 0;
+ cfg.m7_40 = 1;
+ cfg.m7_95 = 0;
+ cfg.m10_2 = 0;
+ cfg.m12_2 = 0;
+ test_gsm0808_sc_cfg_from_gsm48_mr_cfg_single(&cfg);
+
+ cfg.m4_75 = 0;
+ cfg.m5_15 = 0;
+ cfg.m5_90 = 0;
+ cfg.m6_70 = 0;
+ cfg.m7_40 = 0;
+ cfg.m7_95 = 1;
+ cfg.m10_2 = 0;
+ cfg.m12_2 = 0;
+ test_gsm0808_sc_cfg_from_gsm48_mr_cfg_single(&cfg);
+
+ cfg.m4_75 = 0;
+ cfg.m5_15 = 0;
+ cfg.m5_90 = 0;
+ cfg.m6_70 = 0;
+ cfg.m7_40 = 0;
+ cfg.m7_95 = 0;
+ cfg.m10_2 = 1;
+ cfg.m12_2 = 0;
+ test_gsm0808_sc_cfg_from_gsm48_mr_cfg_single(&cfg);
+
+ cfg.m4_75 = 0;
+ cfg.m5_15 = 0;
+ cfg.m5_90 = 0;
+ cfg.m6_70 = 0;
+ cfg.m7_40 = 0;
+ cfg.m7_95 = 0;
+ cfg.m10_2 = 0;
+ cfg.m12_2 = 1;
+ test_gsm0808_sc_cfg_from_gsm48_mr_cfg_single(&cfg);
+
+ cfg.m4_75 = 1;
+ cfg.m5_15 = 1;
+ cfg.m5_90 = 1;
+ cfg.m6_70 = 1;
+ cfg.m7_40 = 0;
+ cfg.m7_95 = 0;
+ cfg.m10_2 = 0;
+ cfg.m12_2 = 0;
+ test_gsm0808_sc_cfg_from_gsm48_mr_cfg_single(&cfg);
+
+ cfg.m4_75 = 0;
+ cfg.m5_15 = 0;
+ cfg.m5_90 = 0;
+ cfg.m6_70 = 0;
+ cfg.m7_40 = 1;
+ cfg.m7_95 = 1;
+ cfg.m10_2 = 1;
+ cfg.m12_2 = 1;
+ test_gsm0808_sc_cfg_from_gsm48_mr_cfg_single(&cfg);
+
+ cfg.m4_75 = 0;
+ cfg.m5_15 = 0;
+ cfg.m5_90 = 1;
+ cfg.m6_70 = 1;
+ cfg.m7_40 = 0;
+ cfg.m7_95 = 0;
+ cfg.m10_2 = 1;
+ cfg.m12_2 = 1;
+ test_gsm0808_sc_cfg_from_gsm48_mr_cfg_single(&cfg);
+
+ cfg.m4_75 = 1;
+ cfg.m5_15 = 1;
+ cfg.m5_90 = 0;
+ cfg.m6_70 = 0;
+ cfg.m7_40 = 1;
+ cfg.m7_95 = 1;
+ cfg.m10_2 = 0;
+ cfg.m12_2 = 0;
+ test_gsm0808_sc_cfg_from_gsm48_mr_cfg_single(&cfg);
+
+ cfg.m4_75 = 0;
+ cfg.m5_15 = 1;
+ cfg.m5_90 = 0;
+ cfg.m6_70 = 1;
+ cfg.m7_40 = 0;
+ cfg.m7_95 = 1;
+ cfg.m10_2 = 0;
+ cfg.m12_2 = 1;
+ test_gsm0808_sc_cfg_from_gsm48_mr_cfg_single(&cfg);
+
+ cfg.m4_75 = 1;
+ cfg.m5_15 = 0;
+ cfg.m5_90 = 1;
+ cfg.m6_70 = 0;
+ cfg.m7_40 = 1;
+ cfg.m7_95 = 0;
+ cfg.m10_2 = 1;
+ cfg.m12_2 = 0;
+ test_gsm0808_sc_cfg_from_gsm48_mr_cfg_single(&cfg);
+
+ cfg.m4_75 = 1;
+ cfg.m5_15 = 1;
+ cfg.m5_90 = 1;
+ cfg.m6_70 = 1;
+ cfg.m7_40 = 1;
+ cfg.m7_95 = 1;
+ cfg.m10_2 = 1;
+ cfg.m12_2 = 1;
+ test_gsm0808_sc_cfg_from_gsm48_mr_cfg_single(&cfg);
+}
+
int main(int argc, char **argv)
{
printf("Testing generation of GSM0808 messages\n");
@@ -1495,6 +1691,8 @@
test_gsm0808_enc_dec_cell_id_lac_and_ci();
test_gsm0808_enc_dec_cell_id_global();
+ test_gsm0808_sc_cfg_from_gsm48_mr_cfg();
+
printf("Done\n");
return EXIT_SUCCESS;
}
diff --git a/tests/gsm0808/gsm0808_test.ok b/tests/gsm0808/gsm0808_test.ok
index 6cd7982..dc1deba 100644
--- a/tests/gsm0808/gsm0808_test.ok
+++ b/tests/gsm0808/gsm0808_test.ok
@@ -74,4 +74,229 @@
test_gsm0808_enc_dec_cell_id_ci: encoded: 05 03 02 04 23 (rc = 5)
test_gsm0808_enc_dec_cell_id_lac_and_ci: encoded: 05 05 01 04 23 02 35 (rc = 7)
test_gsm0808_enc_dec_cell_id_global: encoded: 05 08 00 21 63 54 23 42 04 23 (rc = 10)
+Testing gsm0808_sc_cfg_from_gsm48_mr_cfg():
+Input:
+ m4_75= 0 smod= 0
+ m5_15= 0 spare= 0
+ m5_90= 0 icmi= 0
+ m6_70= 0 nscb= 0
+ m7_40= 0 ver= 0
+ m7_95= 0
+ m10_2= 0
+ m12_2= 0
+Result (fr):
+ S15-S0 = 0000 = 0b0000000000000000
+Result (hr):
+ S15-S0 = 0000 = 0b0000000000000000
+
+Input:
+ m4_75= 1 smod= 0
+ m5_15= 0 spare= 0
+ m5_90= 0 icmi= 0
+ m6_70= 0 nscb= 0
+ m7_40= 0 ver= 0
+ m7_95= 0
+ m10_2= 0
+ m12_2= 0
+Result (fr):
+ S15-S0 = 5703 = 0b0101011100000011
+Result (hr):
+ S15-S0 = 0703 = 0b0000011100000011
+
+Input:
+ m4_75= 0 smod= 0
+ m5_15= 1 spare= 0
+ m5_90= 0 icmi= 0
+ m6_70= 0 nscb= 0
+ m7_40= 0 ver= 0
+ m7_95= 0
+ m10_2= 0
+ m12_2= 0
+Result (fr):
+ S15-S0 = 0000 = 0b0000000000000000
+Result (hr):
+ S15-S0 = 0000 = 0b0000000000000000
+
+Input:
+ m4_75= 0 smod= 0
+ m5_15= 0 spare= 0
+ m5_90= 1 icmi= 0
+ m6_70= 0 nscb= 0
+ m7_40= 0 ver= 0
+ m7_95= 0
+ m10_2= 0
+ m12_2= 0
+Result (fr):
+ S15-S0 = 5706 = 0b0101011100000110
+Result (hr):
+ S15-S0 = 0706 = 0b0000011100000110
+
+Input:
+ m4_75= 0 smod= 0
+ m5_15= 0 spare= 0
+ m5_90= 0 icmi= 0
+ m6_70= 1 nscb= 0
+ m7_40= 0 ver= 0
+ m7_95= 0
+ m10_2= 0
+ m12_2= 0
+Result (fr):
+ S15-S0 = 1608 = 0b0001011000001000
+Result (hr):
+ S15-S0 = 0608 = 0b0000011000001000
+
+Input:
+ m4_75= 0 smod= 0
+ m5_15= 0 spare= 0
+ m5_90= 0 icmi= 0
+ m6_70= 0 nscb= 0
+ m7_40= 1 ver= 0
+ m7_95= 0
+ m10_2= 0
+ m12_2= 0
+Result (fr):
+ S15-S0 = 0412 = 0b0000010000010010
+Result (hr):
+ S15-S0 = 0412 = 0b0000010000010010
+
+Input:
+ m4_75= 0 smod= 0
+ m5_15= 0 spare= 0
+ m5_90= 0 icmi= 0
+ m6_70= 0 nscb= 0
+ m7_40= 0 ver= 0
+ m7_95= 1
+ m10_2= 0
+ m12_2= 0
+Result (fr):
+ S15-S0 = 4020 = 0b0100000000100000
+Result (hr):
+ S15-S0 = 0020 = 0b0000000000100000
+
+Input:
+ m4_75= 0 smod= 0
+ m5_15= 0 spare= 0
+ m5_90= 0 icmi= 0
+ m6_70= 0 nscb= 0
+ m7_40= 0 ver= 0
+ m7_95= 0
+ m10_2= 1
+ m12_2= 0
+Result (fr):
+ S15-S0 = 1040 = 0b0001000001000000
+Result (hr):
+ S15-S0 = 0000 = 0b0000000000000000
+
+Input:
+ m4_75= 0 smod= 0
+ m5_15= 0 spare= 0
+ m5_90= 0 icmi= 0
+ m6_70= 0 nscb= 0
+ m7_40= 0 ver= 0
+ m7_95= 0
+ m10_2= 0
+ m12_2= 1
+Result (fr):
+ S15-S0 = 4082 = 0b0100000010000010
+Result (hr):
+ S15-S0 = 0002 = 0b0000000000000010
+
+Input:
+ m4_75= 1 smod= 0
+ m5_15= 1 spare= 0
+ m5_90= 1 icmi= 0
+ m6_70= 1 nscb= 0
+ m7_40= 0 ver= 0
+ m7_95= 0
+ m10_2= 0
+ m12_2= 0
+Result (fr):
+ S15-S0 = 570f = 0b0101011100001111
+Result (hr):
+ S15-S0 = 070f = 0b0000011100001111
+
+Input:
+ m4_75= 0 smod= 0
+ m5_15= 0 spare= 0
+ m5_90= 0 icmi= 0
+ m6_70= 0 nscb= 0
+ m7_40= 1 ver= 0
+ m7_95= 1
+ m10_2= 1
+ m12_2= 1
+Result (fr):
+ S15-S0 = 54f2 = 0b0101010011110010
+Result (hr):
+ S15-S0 = 0432 = 0b0000010000110010
+
+Input:
+ m4_75= 0 smod= 0
+ m5_15= 0 spare= 0
+ m5_90= 1 icmi= 0
+ m6_70= 1 nscb= 0
+ m7_40= 0 ver= 0
+ m7_95= 0
+ m10_2= 1
+ m12_2= 1
+Result (fr):
+ S15-S0 = 57ce = 0b0101011111001110
+Result (hr):
+ S15-S0 = 070e = 0b0000011100001110
+
+Input:
+ m4_75= 1 smod= 0
+ m5_15= 1 spare= 0
+ m5_90= 0 icmi= 0
+ m6_70= 0 nscb= 0
+ m7_40= 1 ver= 0
+ m7_95= 1
+ m10_2= 0
+ m12_2= 0
+Result (fr):
+ S15-S0 = 5733 = 0b0101011100110011
+Result (hr):
+ S15-S0 = 0733 = 0b0000011100110011
+
+Input:
+ m4_75= 0 smod= 0
+ m5_15= 1 spare= 0
+ m5_90= 0 icmi= 0
+ m6_70= 1 nscb= 0
+ m7_40= 0 ver= 0
+ m7_95= 1
+ m10_2= 0
+ m12_2= 1
+Result (fr):
+ S15-S0 = 56aa = 0b0101011010101010
+Result (hr):
+ S15-S0 = 062a = 0b0000011000101010
+
+Input:
+ m4_75= 1 smod= 0
+ m5_15= 0 spare= 0
+ m5_90= 1 icmi= 0
+ m6_70= 0 nscb= 0
+ m7_40= 1 ver= 0
+ m7_95= 0
+ m10_2= 1
+ m12_2= 0
+Result (fr):
+ S15-S0 = 5757 = 0b0101011101010111
+Result (hr):
+ S15-S0 = 0717 = 0b0000011100010111
+
+Input:
+ m4_75= 1 smod= 0
+ m5_15= 1 spare= 0
+ m5_90= 1 icmi= 0
+ m6_70= 1 nscb= 0
+ m7_40= 1 ver= 0
+ m7_95= 1
+ m10_2= 1
+ m12_2= 1
+Result (fr):
+ S15-S0 = 57ff = 0b0101011111111111
+Result (hr):
+ S15-S0 = 073f = 0b0000011100111111
+
Done